rigless 0.0.5

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model, and unit of virtual time in Rust; a fork of QEMU is built in and executes the instructions
Documentation 
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// Copyright (c) 2026 Rigless Labs.
// SPDX-License-Identifier: MIT OR Apache-2.0
//! The chip end of an inter-integrated-circuit bus.

use crate::device::DeviceContext;

/// An integrated circuit on an I²C bus: what a controller, on a part or inside another chip, addresses.
///
/// A transaction is a start carrying an address and a direction, bytes one way, and a stop; a restart is
/// another start without the stop. The controller calls this and never learns what is behind it; a chip
/// implements it and never learns there is a controller. A chip that is not at the address does not
/// acknowledge the start, and the controller reads nothing from it.
pub trait Peer: std::fmt::Debug + Send {
    /// A start condition carrying `address` and whether the controller will read; the acknowledge.
    fn start(&mut self, address: u8, read: bool, context: &DeviceContext<'_>) -> bool;

    /// One byte from the controller, after a start it acknowledged for a write; the acknowledge.
    fn write(&mut self, byte: u8, context: &DeviceContext<'_>) -> bool;

    /// One byte to the controller, after a start it acknowledged for a read; `last` is the controller's
    /// not-acknowledge, which says the stop is next.
    fn read(&mut self, last: bool, context: &DeviceContext<'_>) -> u8;

    /// The stop condition.
    fn stop(&mut self, context: &DeviceContext<'_>);
}