redfish_codegen/models/processor/v1_18_0/
processor_memory_type.rs

1// Generated by redfish-codegen. Do not modify.
2
3
4#[derive(Clone, Debug, serde::Deserialize, serde::Serialize)]
5pub enum ProcessorMemoryType {
6    /// Processor cache, but no level is determined. Added in version v1_17_0.
7    Cache,
8    /// L1 cache.
9    #[serde(rename = "L1Cache")]
10    L1C,
11    /// L2 cache.
12    #[serde(rename = "L2Cache")]
13    L2C,
14    /// L3 cache.
15    #[serde(rename = "L3Cache")]
16    L3C,
17    /// L4 cache.
18    #[serde(rename = "L4Cache")]
19    L4C,
20    /// L5 cache.
21    #[serde(rename = "L5Cache")]
22    L5C,
23    /// L6 cache.
24    #[serde(rename = "L6Cache")]
25    L6C,
26    /// L7 cache.
27    #[serde(rename = "L7Cache")]
28    L7C,
29    /// High Bandwidth Memory.
30    HBM1,
31    /// The second generation of High Bandwidth Memory.
32    HBM2,
33    /// An updated version of the second generation of High Bandwidth Memory. Added in version v1_17_0.
34    HBM2E,
35    /// The third generation of High Bandwidth Memory.
36    HBM3,
37    /// Synchronous graphics RAM.
38    SGRAM,
39    /// Synchronous graphics random-access memory.
40    GDDR,
41    /// Double data rate type two synchronous graphics random-access memory.
42    GDDR2,
43    /// Double data rate type three synchronous graphics random-access memory.
44    GDDR3,
45    /// Double data rate type four synchronous graphics random-access memory.
46    GDDR4,
47    /// Double data rate type five synchronous graphics random-access memory.
48    GDDR5,
49    /// Double data rate type five X synchronous graphics random-access memory.
50    GDDR5X,
51    /// Double data rate type six synchronous graphics random-access memory.
52    GDDR6,
53    /// Double data rate synchronous dynamic random-access memory.
54    DDR,
55    /// Double data rate type two synchronous dynamic random-access memory.
56    DDR2,
57    /// Double data rate type three synchronous dynamic random-access memory.
58    DDR3,
59    /// Double data rate type four synchronous dynamic random-access memory.
60    DDR4,
61    /// Double data rate type five synchronous dynamic random-access memory.
62    DDR5,
63    /// Synchronous dynamic random-access memory.
64    SDRAM,
65    /// Static random-access memory.
66    SRAM,
67    /// Flash memory.
68    Flash,
69    /// OEM-defined.
70    OEM,
71}
72
73#[allow(clippy::derivable_impls)]
74impl Default for ProcessorMemoryType {
75     fn default() -> ProcessorMemoryType {
76        ProcessorMemoryType::Cache
77     }
78}
79
80impl crate::Metadata<'static> for ProcessorMemoryType {
81    const JSON_SCHEMA: &'static str = "Processor.v1_18_0.json";
82}
redfish_codegen/models/processor/v1_18_0/processor_memory_type.rs

redfish_codegen/models/processor/v1_18_0/
processor_memory_type.rs
