raw_acpi/madt/
mod.rs

1pub mod interrupt_source_override;
2pub mod ioapic;
3pub mod local_apic_nmi;
4pub mod nmi_source;
5pub mod proc_local_apic;
6pub mod bridge_io_pic;
7pub mod core_pic;
8pub mod extend_io_pic;
9pub mod gic_distributor;
10pub mod gic_interrupt_translation_service;
11pub mod gic_msi_frame;
12pub mod gic_redistributor;
13pub mod giccpu_interface;
14pub mod hyper_transport_pic;
15pub mod iosapic;
16pub mod legacy_io_pic;
17pub mod local_api_address_override;
18pub mod local_sapic;
19pub mod local_x2apic_nmi;
20pub mod lpc_pic;
21pub mod msi_pic;
22pub mod multiprocessor_wakeup;
23pub mod platform_interrupt_source;
24pub mod processor_local_x2apic;
25
26use crate::SDTHeader;
27
28#[derive(Copy, Clone)]
29/// ## Local (S)APIC Flags
30pub struct LocalAPICFlags(u32);
31impl LocalAPICFlags {
32    /// If this bit is set the processor is ready for use. If this bit is clear and the Online Capable bit is set,
33    /// system hardware supports enabling this processor during OS runtime.<br>
34    /// If this bit is clear and the Online Capable bit is also clear, this processor is unusable,
35    /// and OSPM shall ignore the contents of the Processor Local APIC Structure.
36    pub const fn enabled(&self) -> bool {
37        self.0 & 0b01 != 0
38    }
39    /// The information conveyed by this bit depends on the value of the Enabled bit.
40    /// If the Enabled bit is set, this bit is reserved and must be zero.
41    /// Otherwise, if this this bit is set, system hardware supports enabling this processor during OS runtime.
42    pub const fn online_capable(&self) -> bool {
43        self.0 & 0b10 != 0
44    }
45    // JJ here, the rest of the bits are reserved; no need to implement.
46}
47
48#[derive(Copy, Clone)]
49/// ## Multiple APIC Flags
50pub struct MADTFlags(u32);
51impl MADTFlags {
52    /// A one indicates that the system also has a PC-AT-compatible dual-8259 setup.
53    ///
54    /// The 8259 vectors must be disabled (that is, masked) when enabling the ACPI APIC operation.
55    pub const fn pcat_compat(&self) -> bool {
56        self.0 & 0b1 != 0
57    }
58    // JJ here, the rest of the bits are reserved; no need to implement.
59}
60
61#[derive(Copy, Clone)]
62#[repr(C, packed)]
63/// ## Multiple APIC Description Table
64///
65/// The ACPI interrupt model describes all interrupts for the entire system in a uniform interrupt model implementation. Supported interrupt models include:
66///
67/// - The PC-AT-compatible dual 8259 interrupt controller.
68/// - **Intel processor-based systems** - The Intel Advanced Programmable Interrupt Controller (APIC) and Intel Streamlined Advanced Programmable Interrupt.
69/// - **ARM processor-based systems** - The Generic Interrupt Controller (GIC).
70/// - **LoongArch processor-based systems** - the LoongArch Programmable Interrupt Controller (LPIC).
71///
72/// The choice of interrupt model(s) to support is up to the platform designer.
73/// The interrupt model cannot be dynamically changed by system firmware; OSPM will choose which model to use and install support for that model at the time of installation.
74/// If a platform supports multiple models, an OS will install support for only one of the models and will not mix models.
75/// Multi-boot capability is a feature in many modern operating systems.
76/// This means that a system may have multiple operating systems or multiple instances of an OS installed at any one time. Platform designers must allow for this.
77///
78/// This provides OSPM with information necessary for operation on systems with APIC, SAPIC, GIC, or LPIC implementations.
79///
80/// ACPI represents all interrupts as "flat" values known as global system interrupts.
81/// Therefore to support APICs, SAPICs, GICs, or LPICs on an ACPI-enabled system, each used interrupt input must be mapped to the global system interrupt value used by ACPI. See Global System Interrupts for more details.
82///
83/// Additional support is required to handle various multi-processor functions that implementations might support (for example, identifying each processor's local interrupt controller ID).
84///
85/// All addresses in the MADT are processor-relative physical addresses.
86///
87/// Starting with ACPI Specification 6.3, the use of the Processor() object was deprecated.
88/// Only legacy systems should continue with this usage. On the Itanium architecture only, a _UID is provided for the Processor() that is a string object.
89/// This usage of _UID is also deprecated since it can preclude an OSPM from being able to match a processor to a non-enumerable device, such as those defined in the MADT.
90/// From ACPI Specification 6.3 onward, all processor objects for all architectures except Itanium must now use Device() objects with an _HID of ACPI0007, and use only integer _UID values.
91pub struct MADT {
92    /// - **Signature** - "APIC"
93    pub header: SDTHeader,
94    /// The 32-bit physical address at which each processor can access its local interrupt controller.
95    pub local_interrupt_controller_address: u32,
96    /// Multiple APIC flags.
97    pub flags: MADTFlags,
98    /// A list of interrupt controller structures for this implementation.
99    ///
100    /// This list will contain all of the structures from Interrupt Controller Structure Types needed to support this platform. These structures are described in the following sections.
101    pub interrupt_controller_structure: [u8; 0],
102}
raw_acpi/madt/mod.rs

raw_acpi/madt/
mod.rs
