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/* SPDX-FileCopyrightText: © 2022-2023 Decompollaborate */
/* SPDX-License-Identifier: MIT */

/* Automatically generated. DO NOT MODIFY */

#[repr(u32)]
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
#[allow(non_camel_case_types)]
pub enum InstrIdType {
    ALL_INVALID,
    CPU_INVALID,
    CPU_NORMAL,
    CPU_SPECIAL,
    CPU_REGIMM,
    CPU_COP0,
    CPU_COP0_BC0,
    CPU_COP0_TLB,
    CPU_COP1,
    CPU_COP1_BC1,
    CPU_COP1_FPUS,
    CPU_COP1_FPUD,
    CPU_COP1_FPUW,
    CPU_COP1_FPUL,
    CPU_COP2,
    RSP_INVALID,
    RSP_NORMAL,
    RSP_NORMAL_LWC2,
    RSP_NORMAL_SWC2,
    RSP_SPECIAL,
    RSP_REGIMM,
    RSP_COP0,
    RSP_COP1,
    RSP_COP2,
    RSP_COP2_VU,
    R3000GTE_INVALID,
    R3000GTE_NORMAL,
    R3000GTE_SPECIAL,
    R3000GTE_REGIMM,
    R3000GTE_COP0,
    R3000GTE_COP1,
    R3000GTE_COP2,
    R3000GTE_COP2_GTE,
    R5900_INVALID,
    R5900_NORMAL,
    R5900_SPECIAL,
    R5900_REGIMM,
    R5900_COP0,
    R5900_COP0_TLB,
    R5900_COP1,
    R5900_COP1_FPUS,
    R5900_COP2,
    R5900_COP2_BC2,
    R5900_COP2_SPECIAL1,
    R5900_COP2_SPECIAL2,
    R5900_MMI,
    R5900_MMI_0,
    R5900_MMI_1,
    R5900_MMI_2,
    R5900_MMI_3,
    ALL_MAX,
}