#ifndef InstrIdType_enum_h_automatic
#define InstrIdType_enum_h_automatic
typedef enum RabInstrIdType {
RAB_INSTR_ID_TYPE_ALL_INVALID,
RAB_INSTR_ID_TYPE_CPU_INVALID,
RAB_INSTR_ID_TYPE_CPU_NORMAL,
RAB_INSTR_ID_TYPE_CPU_SPECIAL,
RAB_INSTR_ID_TYPE_CPU_REGIMM,
RAB_INSTR_ID_TYPE_CPU_COP0,
RAB_INSTR_ID_TYPE_CPU_COP0_BC0,
RAB_INSTR_ID_TYPE_CPU_COP0_TLB,
RAB_INSTR_ID_TYPE_CPU_COP1,
RAB_INSTR_ID_TYPE_CPU_COP1_BC1,
RAB_INSTR_ID_TYPE_CPU_COP1_FPUS,
RAB_INSTR_ID_TYPE_CPU_COP1_FPUD,
RAB_INSTR_ID_TYPE_CPU_COP1_FPUW,
RAB_INSTR_ID_TYPE_CPU_COP1_FPUL,
RAB_INSTR_ID_TYPE_CPU_COP2,
RAB_INSTR_ID_TYPE_RSP_INVALID,
RAB_INSTR_ID_TYPE_RSP_NORMAL,
RAB_INSTR_ID_TYPE_RSP_NORMAL_LWC2,
RAB_INSTR_ID_TYPE_RSP_NORMAL_SWC2,
RAB_INSTR_ID_TYPE_RSP_SPECIAL,
RAB_INSTR_ID_TYPE_RSP_REGIMM,
RAB_INSTR_ID_TYPE_RSP_COP0,
RAB_INSTR_ID_TYPE_RSP_COP1,
RAB_INSTR_ID_TYPE_RSP_COP2,
RAB_INSTR_ID_TYPE_RSP_COP2_VU,
RAB_INSTR_ID_TYPE_R3000GTE_INVALID,
RAB_INSTR_ID_TYPE_R3000GTE_NORMAL,
RAB_INSTR_ID_TYPE_R3000GTE_SPECIAL,
RAB_INSTR_ID_TYPE_R3000GTE_REGIMM,
RAB_INSTR_ID_TYPE_R3000GTE_COP0,
RAB_INSTR_ID_TYPE_R3000GTE_COP1,
RAB_INSTR_ID_TYPE_R3000GTE_COP2,
RAB_INSTR_ID_TYPE_R3000GTE_COP2_GTE,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_INVALID,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_NORMAL,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL_RS,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL_SA,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_REGIMM,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL2,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL3,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL3_BSHFL,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP0,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP0_BC0,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP0_TLB,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1_BC1,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1_FPUS,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1_FPUW,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_BC2,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MFHC2,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MFHC2_P,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MFHC2_P_S,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MTHC2,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU0,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU1,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU3,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT0,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT2,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT3,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_RND,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CVTFLT,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CVTINT,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT8,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT9,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CONTROL,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_COLOR,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CST,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT2,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT2_CNDMOVE,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU5,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU6,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU6_FMT7,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU6_FMT7_FMT0,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU7,
RAB_INSTR_ID_TYPE_R4000ALLEGREX_QUADLR,
RAB_INSTR_ID_TYPE_R5900_INVALID,
RAB_INSTR_ID_TYPE_R5900_NORMAL,
RAB_INSTR_ID_TYPE_R5900_SPECIAL,
RAB_INSTR_ID_TYPE_R5900_REGIMM,
RAB_INSTR_ID_TYPE_R5900_COP0,
RAB_INSTR_ID_TYPE_R5900_COP0_TLB,
RAB_INSTR_ID_TYPE_R5900_COP1,
RAB_INSTR_ID_TYPE_R5900_COP1_FPUS,
RAB_INSTR_ID_TYPE_R5900_COP2,
RAB_INSTR_ID_TYPE_R5900_COP2_NOHIGHBIT,
RAB_INSTR_ID_TYPE_R5900_COP2_BC2,
RAB_INSTR_ID_TYPE_R5900_COP2_SPECIAL1,
RAB_INSTR_ID_TYPE_R5900_COP2_SPECIAL2,
RAB_INSTR_ID_TYPE_R5900_COP2_VIWR,
RAB_INSTR_ID_TYPE_R5900_MMI,
RAB_INSTR_ID_TYPE_R5900_MMI_0,
RAB_INSTR_ID_TYPE_R5900_MMI_1,
RAB_INSTR_ID_TYPE_R5900_MMI_2,
RAB_INSTR_ID_TYPE_R5900_MMI_3,
RAB_INSTR_ID_TYPE_R5900_MMI_PMFHL,
RAB_INSTR_ID_TYPE_R5900_MMI_PMTHL,
RAB_INSTR_ID_TYPE_ALL_MAX,
} RabInstrIdType;
#endif