ra8e2_pac/
bus_ns.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.00.01, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:54:26 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Bus Control"]
28unsafe impl ::core::marker::Send for super::BusNs {}
29unsafe impl ::core::marker::Sync for super::BusNs {}
30impl super::BusNs {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "CS%s Mode Register (n = 0 to 7)"]
38    #[inline(always)]
39    pub const fn csmod(
40        &self,
41    ) -> &'static crate::common::ClusterRegisterArray<
42        crate::common::Reg<self::Csmod_SPEC, crate::common::RW>,
43        8,
44        0x10,
45    > {
46        unsafe {
47            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x2usize))
48        }
49    }
50    #[inline(always)]
51    pub const fn cs0mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
52        unsafe {
53            crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
54                self._svd2pac_as_ptr().add(0x2usize),
55            )
56        }
57    }
58    #[inline(always)]
59    pub const fn cs1mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(0x12usize),
63            )
64        }
65    }
66    #[inline(always)]
67    pub const fn cs2mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
68        unsafe {
69            crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
70                self._svd2pac_as_ptr().add(0x22usize),
71            )
72        }
73    }
74    #[inline(always)]
75    pub const fn cs3mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
76        unsafe {
77            crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
78                self._svd2pac_as_ptr().add(0x32usize),
79            )
80        }
81    }
82    #[inline(always)]
83    pub const fn cs4mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
84        unsafe {
85            crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
86                self._svd2pac_as_ptr().add(0x42usize),
87            )
88        }
89    }
90    #[inline(always)]
91    pub const fn cs5mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
92        unsafe {
93            crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
94                self._svd2pac_as_ptr().add(0x52usize),
95            )
96        }
97    }
98    #[inline(always)]
99    pub const fn cs6mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(0x62usize),
103            )
104        }
105    }
106    #[inline(always)]
107    pub const fn cs7mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
108        unsafe {
109            crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
110                self._svd2pac_as_ptr().add(0x72usize),
111            )
112        }
113    }
114
115    #[doc = "CS%s Wait Control Register 1 (n = 0 to 7)"]
116    #[inline(always)]
117    pub const fn cswcr1(
118        &self,
119    ) -> &'static crate::common::ClusterRegisterArray<
120        crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW>,
121        8,
122        0x10,
123    > {
124        unsafe {
125            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x4usize))
126        }
127    }
128    #[inline(always)]
129    pub const fn cs0wcr1(
130        &self,
131    ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
132        unsafe {
133            crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
134                self._svd2pac_as_ptr().add(0x4usize),
135            )
136        }
137    }
138    #[inline(always)]
139    pub const fn cs1wcr1(
140        &self,
141    ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
142        unsafe {
143            crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
144                self._svd2pac_as_ptr().add(0x14usize),
145            )
146        }
147    }
148    #[inline(always)]
149    pub const fn cs2wcr1(
150        &self,
151    ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
152        unsafe {
153            crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
154                self._svd2pac_as_ptr().add(0x24usize),
155            )
156        }
157    }
158    #[inline(always)]
159    pub const fn cs3wcr1(
160        &self,
161    ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
162        unsafe {
163            crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
164                self._svd2pac_as_ptr().add(0x34usize),
165            )
166        }
167    }
168    #[inline(always)]
169    pub const fn cs4wcr1(
170        &self,
171    ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
172        unsafe {
173            crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
174                self._svd2pac_as_ptr().add(0x44usize),
175            )
176        }
177    }
178    #[inline(always)]
179    pub const fn cs5wcr1(
180        &self,
181    ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
182        unsafe {
183            crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
184                self._svd2pac_as_ptr().add(0x54usize),
185            )
186        }
187    }
188    #[inline(always)]
189    pub const fn cs6wcr1(
190        &self,
191    ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
192        unsafe {
193            crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
194                self._svd2pac_as_ptr().add(0x64usize),
195            )
196        }
197    }
198    #[inline(always)]
199    pub const fn cs7wcr1(
200        &self,
201    ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
202        unsafe {
203            crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
204                self._svd2pac_as_ptr().add(0x74usize),
205            )
206        }
207    }
208
209    #[doc = "CS%s Wait Control Register 2 (n = 0 to 7)"]
210    #[inline(always)]
211    pub const fn cswcr2(
212        &self,
213    ) -> &'static crate::common::ClusterRegisterArray<
214        crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW>,
215        8,
216        0x10,
217    > {
218        unsafe {
219            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x8usize))
220        }
221    }
222    #[inline(always)]
223    pub const fn cs0wcr2(
224        &self,
225    ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
226        unsafe {
227            crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
228                self._svd2pac_as_ptr().add(0x8usize),
229            )
230        }
231    }
232    #[inline(always)]
233    pub const fn cs1wcr2(
234        &self,
235    ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
236        unsafe {
237            crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
238                self._svd2pac_as_ptr().add(0x18usize),
239            )
240        }
241    }
242    #[inline(always)]
243    pub const fn cs2wcr2(
244        &self,
245    ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
246        unsafe {
247            crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
248                self._svd2pac_as_ptr().add(0x28usize),
249            )
250        }
251    }
252    #[inline(always)]
253    pub const fn cs3wcr2(
254        &self,
255    ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
256        unsafe {
257            crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
258                self._svd2pac_as_ptr().add(0x38usize),
259            )
260        }
261    }
262    #[inline(always)]
263    pub const fn cs4wcr2(
264        &self,
265    ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
266        unsafe {
267            crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
268                self._svd2pac_as_ptr().add(0x48usize),
269            )
270        }
271    }
272    #[inline(always)]
273    pub const fn cs5wcr2(
274        &self,
275    ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
276        unsafe {
277            crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
278                self._svd2pac_as_ptr().add(0x58usize),
279            )
280        }
281    }
282    #[inline(always)]
283    pub const fn cs6wcr2(
284        &self,
285    ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
286        unsafe {
287            crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
288                self._svd2pac_as_ptr().add(0x68usize),
289            )
290        }
291    }
292    #[inline(always)]
293    pub const fn cs7wcr2(
294        &self,
295    ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
296        unsafe {
297            crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
298                self._svd2pac_as_ptr().add(0x78usize),
299            )
300        }
301    }
302
303    #[doc = "CS0 Control Register"]
304    #[inline(always)]
305    pub const fn cs0cr(&self) -> &'static crate::common::Reg<self::Cs0Cr_SPEC, crate::common::RW> {
306        unsafe {
307            crate::common::Reg::<self::Cs0Cr_SPEC, crate::common::RW>::from_ptr(
308                self._svd2pac_as_ptr().add(2050usize),
309            )
310        }
311    }
312
313    #[doc = "CS%s Recovery Cycle Register (n = 0 to 7)"]
314    #[inline(always)]
315    pub const fn csrec(
316        &self,
317    ) -> &'static crate::common::ClusterRegisterArray<
318        crate::common::Reg<self::Csrec_SPEC, crate::common::RW>,
319        8,
320        0x10,
321    > {
322        unsafe {
323            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x80ausize))
324        }
325    }
326    #[inline(always)]
327    pub const fn cs0rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
328        unsafe {
329            crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
330                self._svd2pac_as_ptr().add(0x80ausize),
331            )
332        }
333    }
334    #[inline(always)]
335    pub const fn cs1rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
336        unsafe {
337            crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
338                self._svd2pac_as_ptr().add(0x81ausize),
339            )
340        }
341    }
342    #[inline(always)]
343    pub const fn cs2rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
344        unsafe {
345            crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
346                self._svd2pac_as_ptr().add(0x82ausize),
347            )
348        }
349    }
350    #[inline(always)]
351    pub const fn cs3rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
352        unsafe {
353            crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
354                self._svd2pac_as_ptr().add(0x83ausize),
355            )
356        }
357    }
358    #[inline(always)]
359    pub const fn cs4rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
360        unsafe {
361            crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
362                self._svd2pac_as_ptr().add(0x84ausize),
363            )
364        }
365    }
366    #[inline(always)]
367    pub const fn cs5rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
368        unsafe {
369            crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
370                self._svd2pac_as_ptr().add(0x85ausize),
371            )
372        }
373    }
374    #[inline(always)]
375    pub const fn cs6rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
376        unsafe {
377            crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
378                self._svd2pac_as_ptr().add(0x86ausize),
379            )
380        }
381    }
382    #[inline(always)]
383    pub const fn cs7rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
384        unsafe {
385            crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
386                self._svd2pac_as_ptr().add(0x87ausize),
387            )
388        }
389    }
390
391    #[doc = "CS%s Control Register"]
392    #[inline(always)]
393    pub const fn cscr(
394        &self,
395    ) -> &'static crate::common::ClusterRegisterArray<
396        crate::common::Reg<self::Cscr_SPEC, crate::common::RW>,
397        7,
398        0x10,
399    > {
400        unsafe {
401            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x812usize))
402        }
403    }
404    #[inline(always)]
405    pub const fn cs1cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
406        unsafe {
407            crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
408                self._svd2pac_as_ptr().add(0x812usize),
409            )
410        }
411    }
412    #[inline(always)]
413    pub const fn cs2cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
414        unsafe {
415            crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
416                self._svd2pac_as_ptr().add(0x822usize),
417            )
418        }
419    }
420    #[inline(always)]
421    pub const fn cs3cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
422        unsafe {
423            crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
424                self._svd2pac_as_ptr().add(0x832usize),
425            )
426        }
427    }
428    #[inline(always)]
429    pub const fn cs4cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
430        unsafe {
431            crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
432                self._svd2pac_as_ptr().add(0x842usize),
433            )
434        }
435    }
436    #[inline(always)]
437    pub const fn cs5cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
438        unsafe {
439            crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
440                self._svd2pac_as_ptr().add(0x852usize),
441            )
442        }
443    }
444    #[inline(always)]
445    pub const fn cs6cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
446        unsafe {
447            crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
448                self._svd2pac_as_ptr().add(0x862usize),
449            )
450        }
451    }
452    #[inline(always)]
453    pub const fn cs7cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
454        unsafe {
455            crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
456                self._svd2pac_as_ptr().add(0x872usize),
457            )
458        }
459    }
460
461    #[doc = "CS Recovery Cycle Insertion Enable Register"]
462    #[inline(always)]
463    pub const fn csrecen(
464        &self,
465    ) -> &'static crate::common::Reg<self::Csrecen_SPEC, crate::common::RW> {
466        unsafe {
467            crate::common::Reg::<self::Csrecen_SPEC, crate::common::RW>::from_ptr(
468                self._svd2pac_as_ptr().add(2176usize),
469            )
470        }
471    }
472
473    #[doc = "SDC Control Register"]
474    #[inline(always)]
475    pub const fn sdccr(&self) -> &'static crate::common::Reg<self::Sdccr_SPEC, crate::common::RW> {
476        unsafe {
477            crate::common::Reg::<self::Sdccr_SPEC, crate::common::RW>::from_ptr(
478                self._svd2pac_as_ptr().add(3072usize),
479            )
480        }
481    }
482
483    #[doc = "SDC Mode Register"]
484    #[inline(always)]
485    pub const fn sdcmod(
486        &self,
487    ) -> &'static crate::common::Reg<self::Sdcmod_SPEC, crate::common::RW> {
488        unsafe {
489            crate::common::Reg::<self::Sdcmod_SPEC, crate::common::RW>::from_ptr(
490                self._svd2pac_as_ptr().add(3073usize),
491            )
492        }
493    }
494
495    #[doc = "SDRAM Access Mode Register"]
496    #[inline(always)]
497    pub const fn sdamod(
498        &self,
499    ) -> &'static crate::common::Reg<self::Sdamod_SPEC, crate::common::RW> {
500        unsafe {
501            crate::common::Reg::<self::Sdamod_SPEC, crate::common::RW>::from_ptr(
502                self._svd2pac_as_ptr().add(3074usize),
503            )
504        }
505    }
506
507    #[doc = "SDRAM Self-Refresh Control Register"]
508    #[inline(always)]
509    pub const fn sdself(
510        &self,
511    ) -> &'static crate::common::Reg<self::Sdself_SPEC, crate::common::RW> {
512        unsafe {
513            crate::common::Reg::<self::Sdself_SPEC, crate::common::RW>::from_ptr(
514                self._svd2pac_as_ptr().add(3088usize),
515            )
516        }
517    }
518
519    #[doc = "SDRAM Refresh Control Register"]
520    #[inline(always)]
521    pub const fn sdrfcr(
522        &self,
523    ) -> &'static crate::common::Reg<self::Sdrfcr_SPEC, crate::common::RW> {
524        unsafe {
525            crate::common::Reg::<self::Sdrfcr_SPEC, crate::common::RW>::from_ptr(
526                self._svd2pac_as_ptr().add(3092usize),
527            )
528        }
529    }
530
531    #[doc = "SDRAM Auto-Refresh Control Register"]
532    #[inline(always)]
533    pub const fn sdrfen(
534        &self,
535    ) -> &'static crate::common::Reg<self::Sdrfen_SPEC, crate::common::RW> {
536        unsafe {
537            crate::common::Reg::<self::Sdrfen_SPEC, crate::common::RW>::from_ptr(
538                self._svd2pac_as_ptr().add(3094usize),
539            )
540        }
541    }
542
543    #[doc = "SDRAM Initialization Sequence Control Register"]
544    #[inline(always)]
545    pub const fn sdicr(&self) -> &'static crate::common::Reg<self::Sdicr_SPEC, crate::common::RW> {
546        unsafe {
547            crate::common::Reg::<self::Sdicr_SPEC, crate::common::RW>::from_ptr(
548                self._svd2pac_as_ptr().add(3104usize),
549            )
550        }
551    }
552
553    #[doc = "SDRAM Initialization Register"]
554    #[inline(always)]
555    pub const fn sdir(&self) -> &'static crate::common::Reg<self::Sdir_SPEC, crate::common::RW> {
556        unsafe {
557            crate::common::Reg::<self::Sdir_SPEC, crate::common::RW>::from_ptr(
558                self._svd2pac_as_ptr().add(3108usize),
559            )
560        }
561    }
562
563    #[doc = "SDRAM Address Register"]
564    #[inline(always)]
565    pub const fn sdadr(&self) -> &'static crate::common::Reg<self::Sdadr_SPEC, crate::common::RW> {
566        unsafe {
567            crate::common::Reg::<self::Sdadr_SPEC, crate::common::RW>::from_ptr(
568                self._svd2pac_as_ptr().add(3136usize),
569            )
570        }
571    }
572
573    #[doc = "SDRAM Timing Register"]
574    #[inline(always)]
575    pub const fn sdtr(&self) -> &'static crate::common::Reg<self::Sdtr_SPEC, crate::common::RW> {
576        unsafe {
577            crate::common::Reg::<self::Sdtr_SPEC, crate::common::RW>::from_ptr(
578                self._svd2pac_as_ptr().add(3140usize),
579            )
580        }
581    }
582
583    #[doc = "SDRAM Mode Register"]
584    #[inline(always)]
585    pub const fn sdmod(&self) -> &'static crate::common::Reg<self::Sdmod_SPEC, crate::common::RW> {
586        unsafe {
587            crate::common::Reg::<self::Sdmod_SPEC, crate::common::RW>::from_ptr(
588                self._svd2pac_as_ptr().add(3144usize),
589            )
590        }
591    }
592
593    #[doc = "SDRAM Status Register"]
594    #[inline(always)]
595    pub const fn sdsr(&self) -> &'static crate::common::Reg<self::Sdsr_SPEC, crate::common::R> {
596        unsafe {
597            crate::common::Reg::<self::Sdsr_SPEC, crate::common::R>::from_ptr(
598                self._svd2pac_as_ptr().add(3152usize),
599            )
600        }
601    }
602
603    #[doc = "BUS Operation After Detection Register"]
604    #[inline(always)]
605    pub const fn busoad(
606        &self,
607    ) -> &'static crate::common::Reg<self::Busoad_SPEC, crate::common::RW> {
608        unsafe {
609            crate::common::Reg::<self::Busoad_SPEC, crate::common::RW>::from_ptr(
610                self._svd2pac_as_ptr().add(4096usize),
611            )
612        }
613    }
614
615    #[doc = "BUS Operation After Detection Protect Register"]
616    #[inline(always)]
617    pub const fn busoadpt(
618        &self,
619    ) -> &'static crate::common::Reg<self::Busoadpt_SPEC, crate::common::RW> {
620        unsafe {
621            crate::common::Reg::<self::Busoadpt_SPEC, crate::common::RW>::from_ptr(
622                self._svd2pac_as_ptr().add(4100usize),
623            )
624        }
625    }
626
627    #[doc = "Bus Master Arbitration Control Register"]
628    #[inline(always)]
629    pub const fn busmabt(
630        &self,
631    ) -> &'static crate::common::Reg<self::Busmabt_SPEC, crate::common::RW> {
632        unsafe {
633            crate::common::Reg::<self::Busmabt_SPEC, crate::common::RW>::from_ptr(
634                self._svd2pac_as_ptr().add(4352usize),
635            )
636        }
637    }
638
639    #[doc = "Bus Slave Arbitration Control Register 1(x = FHBI, S0BI, S1BI)"]
640    #[inline(always)]
641    pub const fn bussabt1fhbi(
642        &self,
643    ) -> &'static crate::common::Reg<self::Bussabt1Fhbi_SPEC, crate::common::RW> {
644        unsafe {
645            crate::common::Reg::<self::Bussabt1Fhbi_SPEC, crate::common::RW>::from_ptr(
646                self._svd2pac_as_ptr().add(4608usize),
647            )
648        }
649    }
650
651    #[doc = "Bus Slave Arbitration Control Register 0"]
652    #[inline(always)]
653    pub const fn bussabt0flbi(
654        &self,
655    ) -> &'static crate::common::Reg<self::Bussabt0Flbi_SPEC, crate::common::RW> {
656        unsafe {
657            crate::common::Reg::<self::Bussabt0Flbi_SPEC, crate::common::RW>::from_ptr(
658                self._svd2pac_as_ptr().add(4624usize),
659            )
660        }
661    }
662
663    #[doc = "Bus Slave Arbitration Control Register 1(x = FHBI, S0BI, S1BI)"]
664    #[inline(always)]
665    pub const fn bussabt1s0bi(
666        &self,
667    ) -> &'static crate::common::Reg<self::Bussabt1S0Bi_SPEC, crate::common::RW> {
668        unsafe {
669            crate::common::Reg::<self::Bussabt1S0Bi_SPEC, crate::common::RW>::from_ptr(
670                self._svd2pac_as_ptr().add(4632usize),
671            )
672        }
673    }
674
675    #[doc = "Bus Slave Arbitration Control Register 1(x = FHBI, S0BI, S1BI)"]
676    #[inline(always)]
677    pub const fn bussabt1s1bi(
678        &self,
679    ) -> &'static crate::common::Reg<self::Bussabt1S1Bi_SPEC, crate::common::RW> {
680        unsafe {
681            crate::common::Reg::<self::Bussabt1S1Bi_SPEC, crate::common::RW>::from_ptr(
682                self._svd2pac_as_ptr().add(4640usize),
683            )
684        }
685    }
686
687    #[doc = "Bus Slave Arbitration Control Register 0"]
688    #[inline(always)]
689    pub const fn bussabt0stbysbi(
690        &self,
691    ) -> &'static crate::common::Reg<self::Bussabt0Stbysbi_SPEC, crate::common::RW> {
692        unsafe {
693            crate::common::Reg::<self::Bussabt0Stbysbi_SPEC, crate::common::RW>::from_ptr(
694                self._svd2pac_as_ptr().add(4680usize),
695            )
696        }
697    }
698
699    #[doc = "Bus Slave Arbitration Control Register 0"]
700    #[inline(always)]
701    pub const fn bussabt0ecbi(
702        &self,
703    ) -> &'static crate::common::Reg<self::Bussabt0Ecbi_SPEC, crate::common::RW> {
704        unsafe {
705            crate::common::Reg::<self::Bussabt0Ecbi_SPEC, crate::common::RW>::from_ptr(
706                self._svd2pac_as_ptr().add(4688usize),
707            )
708        }
709    }
710
711    #[doc = "Bus Slave Arbitration Control Register 0"]
712    #[inline(always)]
713    pub const fn bussabt0eobi(
714        &self,
715    ) -> &'static crate::common::Reg<self::Bussabt0Eobi_SPEC, crate::common::RW> {
716        unsafe {
717            crate::common::Reg::<self::Bussabt0Eobi_SPEC, crate::common::RW>::from_ptr(
718                self._svd2pac_as_ptr().add(4696usize),
719            )
720        }
721    }
722
723    #[doc = "Bus Slave Arbitration Control Register 0"]
724    #[inline(always)]
725    pub const fn bussabt0pbbi(
726        &self,
727    ) -> &'static crate::common::Reg<self::Bussabt0Pbbi_SPEC, crate::common::RW> {
728        unsafe {
729            crate::common::Reg::<self::Bussabt0Pbbi_SPEC, crate::common::RW>::from_ptr(
730                self._svd2pac_as_ptr().add(4704usize),
731            )
732        }
733    }
734
735    #[doc = "Bus Slave Arbitration Control Register 0"]
736    #[inline(always)]
737    pub const fn bussabt0pabi(
738        &self,
739    ) -> &'static crate::common::Reg<self::Bussabt0Pabi_SPEC, crate::common::RW> {
740        unsafe {
741            crate::common::Reg::<self::Bussabt0Pabi_SPEC, crate::common::RW>::from_ptr(
742                self._svd2pac_as_ptr().add(4712usize),
743            )
744        }
745    }
746
747    #[doc = "Bus Slave Arbitration Control Register 0"]
748    #[inline(always)]
749    pub const fn bussabt0pibi(
750        &self,
751    ) -> &'static crate::common::Reg<self::Bussabt0Pibi_SPEC, crate::common::RW> {
752        unsafe {
753            crate::common::Reg::<self::Bussabt0Pibi_SPEC, crate::common::RW>::from_ptr(
754                self._svd2pac_as_ptr().add(4720usize),
755            )
756        }
757    }
758
759    #[doc = "Bus Slave Arbitration Control Register 0"]
760    #[inline(always)]
761    pub const fn bussabt0psbi(
762        &self,
763    ) -> &'static crate::common::Reg<self::Bussabt0Psbi_SPEC, crate::common::RW> {
764        unsafe {
765            crate::common::Reg::<self::Bussabt0Psbi_SPEC, crate::common::RW>::from_ptr(
766                self._svd2pac_as_ptr().add(4728usize),
767            )
768        }
769    }
770
771    #[doc = "Bus Divider Bypass Register"]
772    #[inline(always)]
773    pub const fn busdivbyp(
774        &self,
775    ) -> &'static crate::common::Reg<self::Busdivbyp_SPEC, crate::common::RW> {
776        unsafe {
777            crate::common::Reg::<self::Busdivbyp_SPEC, crate::common::RW>::from_ptr(
778                self._svd2pac_as_ptr().add(4864usize),
779            )
780        }
781    }
782
783    #[doc = "BUS Error Read Write (n = 6 to 9)"]
784    #[inline(always)]
785    pub const fn buserrrw(
786        &self,
787    ) -> &'static crate::common::ClusterRegisterArray<
788        crate::common::Reg<self::Buserrrw_SPEC, crate::common::R>,
789        4,
790        0x10,
791    > {
792        unsafe {
793            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1824usize))
794        }
795    }
796    #[inline(always)]
797    pub const fn bus6errrw(
798        &self,
799    ) -> &'static crate::common::Reg<self::Buserrrw_SPEC, crate::common::R> {
800        unsafe {
801            crate::common::Reg::<self::Buserrrw_SPEC, crate::common::R>::from_ptr(
802                self._svd2pac_as_ptr().add(0x1824usize),
803            )
804        }
805    }
806    #[inline(always)]
807    pub const fn bus7errrw(
808        &self,
809    ) -> &'static crate::common::Reg<self::Buserrrw_SPEC, crate::common::R> {
810        unsafe {
811            crate::common::Reg::<self::Buserrrw_SPEC, crate::common::R>::from_ptr(
812                self._svd2pac_as_ptr().add(0x1834usize),
813            )
814        }
815    }
816    #[inline(always)]
817    pub const fn bus8errrw(
818        &self,
819    ) -> &'static crate::common::Reg<self::Buserrrw_SPEC, crate::common::R> {
820        unsafe {
821            crate::common::Reg::<self::Buserrrw_SPEC, crate::common::R>::from_ptr(
822                self._svd2pac_as_ptr().add(0x1844usize),
823            )
824        }
825    }
826    #[inline(always)]
827    pub const fn bus9errrw(
828        &self,
829    ) -> &'static crate::common::Reg<self::Buserrrw_SPEC, crate::common::R> {
830        unsafe {
831            crate::common::Reg::<self::Buserrrw_SPEC, crate::common::R>::from_ptr(
832                self._svd2pac_as_ptr().add(0x1854usize),
833            )
834        }
835    }
836
837    #[doc = "BUS Error Address Register (n = 6 to 9)"]
838    #[inline(always)]
839    pub const fn buserradd(
840        &self,
841    ) -> &'static crate::common::ClusterRegisterArray<
842        crate::common::Reg<self::Buserradd_SPEC, crate::common::R>,
843        4,
844        0x10,
845    > {
846        unsafe {
847            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1850usize))
848        }
849    }
850    #[inline(always)]
851    pub const fn bus6erradd(
852        &self,
853    ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
854        unsafe {
855            crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
856                self._svd2pac_as_ptr().add(0x1850usize),
857            )
858        }
859    }
860    #[inline(always)]
861    pub const fn bus7erradd(
862        &self,
863    ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
864        unsafe {
865            crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
866                self._svd2pac_as_ptr().add(0x1860usize),
867            )
868        }
869    }
870    #[inline(always)]
871    pub const fn bus8erradd(
872        &self,
873    ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
874        unsafe {
875            crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
876                self._svd2pac_as_ptr().add(0x1870usize),
877            )
878        }
879    }
880    #[inline(always)]
881    pub const fn bus9erradd(
882        &self,
883    ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
884        unsafe {
885            crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
886                self._svd2pac_as_ptr().add(0x1880usize),
887            )
888        }
889    }
890
891    #[doc = "Bus Master Security Attribution Unit Error Address"]
892    #[inline(always)]
893    pub const fn bmsaerradd(
894        &self,
895    ) -> &'static crate::common::ClusterRegisterArray<
896        crate::common::Reg<self::Bmsaerradd_SPEC, crate::common::R>,
897        4,
898        0x10,
899    > {
900        unsafe {
901            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1920usize))
902        }
903    }
904    #[inline(always)]
905    pub const fn bmsa6erradd(
906        &self,
907    ) -> &'static crate::common::Reg<self::Bmsaerradd_SPEC, crate::common::R> {
908        unsafe {
909            crate::common::Reg::<self::Bmsaerradd_SPEC, crate::common::R>::from_ptr(
910                self._svd2pac_as_ptr().add(0x1920usize),
911            )
912        }
913    }
914    #[inline(always)]
915    pub const fn bmsa7erradd(
916        &self,
917    ) -> &'static crate::common::Reg<self::Bmsaerradd_SPEC, crate::common::R> {
918        unsafe {
919            crate::common::Reg::<self::Bmsaerradd_SPEC, crate::common::R>::from_ptr(
920                self._svd2pac_as_ptr().add(0x1930usize),
921            )
922        }
923    }
924    #[inline(always)]
925    pub const fn bmsa8erradd(
926        &self,
927    ) -> &'static crate::common::Reg<self::Bmsaerradd_SPEC, crate::common::R> {
928        unsafe {
929            crate::common::Reg::<self::Bmsaerradd_SPEC, crate::common::R>::from_ptr(
930                self._svd2pac_as_ptr().add(0x1940usize),
931            )
932        }
933    }
934    #[inline(always)]
935    pub const fn bmsa9erradd(
936        &self,
937    ) -> &'static crate::common::Reg<self::Bmsaerradd_SPEC, crate::common::R> {
938        unsafe {
939            crate::common::Reg::<self::Bmsaerradd_SPEC, crate::common::R>::from_ptr(
940                self._svd2pac_as_ptr().add(0x1950usize),
941            )
942        }
943    }
944
945    #[doc = "BUS Master Security Attribution Unit Error Read Write (n = 6 to 9)"]
946    #[inline(always)]
947    pub const fn bmsaerrrw(
948        &self,
949    ) -> &'static crate::common::ClusterRegisterArray<
950        crate::common::Reg<self::Bmsaerrrw_SPEC, crate::common::R>,
951        4,
952        0x10,
953    > {
954        unsafe {
955            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1924usize))
956        }
957    }
958    #[inline(always)]
959    pub const fn bmsa6errrw(
960        &self,
961    ) -> &'static crate::common::Reg<self::Bmsaerrrw_SPEC, crate::common::R> {
962        unsafe {
963            crate::common::Reg::<self::Bmsaerrrw_SPEC, crate::common::R>::from_ptr(
964                self._svd2pac_as_ptr().add(0x1924usize),
965            )
966        }
967    }
968    #[inline(always)]
969    pub const fn bmsa7errrw(
970        &self,
971    ) -> &'static crate::common::Reg<self::Bmsaerrrw_SPEC, crate::common::R> {
972        unsafe {
973            crate::common::Reg::<self::Bmsaerrrw_SPEC, crate::common::R>::from_ptr(
974                self._svd2pac_as_ptr().add(0x1934usize),
975            )
976        }
977    }
978    #[inline(always)]
979    pub const fn bmsa8errrw(
980        &self,
981    ) -> &'static crate::common::Reg<self::Bmsaerrrw_SPEC, crate::common::R> {
982        unsafe {
983            crate::common::Reg::<self::Bmsaerrrw_SPEC, crate::common::R>::from_ptr(
984                self._svd2pac_as_ptr().add(0x1944usize),
985            )
986        }
987    }
988    #[inline(always)]
989    pub const fn bmsa9errrw(
990        &self,
991    ) -> &'static crate::common::Reg<self::Bmsaerrrw_SPEC, crate::common::R> {
992        unsafe {
993            crate::common::Reg::<self::Bmsaerrrw_SPEC, crate::common::R>::from_ptr(
994                self._svd2pac_as_ptr().add(0x1954usize),
995            )
996        }
997    }
998
999    #[doc = "BUS Error Status Register"]
1000    #[inline(always)]
1001    pub const fn buserrstat(
1002        &self,
1003    ) -> &'static crate::common::ClusterRegisterArray<
1004        crate::common::Reg<self::Buserrstat_SPEC, crate::common::R>,
1005        4,
1006        0x10,
1007    > {
1008        unsafe {
1009            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1a50usize))
1010        }
1011    }
1012    #[inline(always)]
1013    pub const fn bus6errstat(
1014        &self,
1015    ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
1016        unsafe {
1017            crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
1018                self._svd2pac_as_ptr().add(0x1a50usize),
1019            )
1020        }
1021    }
1022    #[inline(always)]
1023    pub const fn bus7errstat(
1024        &self,
1025    ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
1026        unsafe {
1027            crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
1028                self._svd2pac_as_ptr().add(0x1a60usize),
1029            )
1030        }
1031    }
1032    #[inline(always)]
1033    pub const fn bus8errstat(
1034        &self,
1035    ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
1036        unsafe {
1037            crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
1038                self._svd2pac_as_ptr().add(0x1a70usize),
1039            )
1040        }
1041    }
1042    #[inline(always)]
1043    pub const fn bus9errstat(
1044        &self,
1045    ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
1046        unsafe {
1047            crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
1048                self._svd2pac_as_ptr().add(0x1a80usize),
1049            )
1050        }
1051    }
1052
1053    #[doc = "BUS Error Clear Register"]
1054    #[inline(always)]
1055    pub const fn buserrclr(
1056        &self,
1057    ) -> &'static crate::common::ClusterRegisterArray<
1058        crate::common::Reg<self::Buserrclr_SPEC, crate::common::RW>,
1059        4,
1060        0x10,
1061    > {
1062        unsafe {
1063            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1a58usize))
1064        }
1065    }
1066    #[inline(always)]
1067    pub const fn bus6errclr(
1068        &self,
1069    ) -> &'static crate::common::Reg<self::Buserrclr_SPEC, crate::common::RW> {
1070        unsafe {
1071            crate::common::Reg::<self::Buserrclr_SPEC, crate::common::RW>::from_ptr(
1072                self._svd2pac_as_ptr().add(0x1a58usize),
1073            )
1074        }
1075    }
1076    #[inline(always)]
1077    pub const fn bus7errclr(
1078        &self,
1079    ) -> &'static crate::common::Reg<self::Buserrclr_SPEC, crate::common::RW> {
1080        unsafe {
1081            crate::common::Reg::<self::Buserrclr_SPEC, crate::common::RW>::from_ptr(
1082                self._svd2pac_as_ptr().add(0x1a68usize),
1083            )
1084        }
1085    }
1086    #[inline(always)]
1087    pub const fn bus8errclr(
1088        &self,
1089    ) -> &'static crate::common::Reg<self::Buserrclr_SPEC, crate::common::RW> {
1090        unsafe {
1091            crate::common::Reg::<self::Buserrclr_SPEC, crate::common::RW>::from_ptr(
1092                self._svd2pac_as_ptr().add(0x1a78usize),
1093            )
1094        }
1095    }
1096    #[inline(always)]
1097    pub const fn bus9errclr(
1098        &self,
1099    ) -> &'static crate::common::Reg<self::Buserrclr_SPEC, crate::common::RW> {
1100        unsafe {
1101            crate::common::Reg::<self::Buserrclr_SPEC, crate::common::RW>::from_ptr(
1102                self._svd2pac_as_ptr().add(0x1a88usize),
1103            )
1104        }
1105    }
1106
1107    #[doc = "Master Bufferable Write Error Status Register"]
1108    #[inline(always)]
1109    pub const fn mbwerrstat(
1110        &self,
1111    ) -> &'static crate::common::Reg<self::Mbwerrstat_SPEC, crate::common::R> {
1112        unsafe {
1113            crate::common::Reg::<self::Mbwerrstat_SPEC, crate::common::R>::from_ptr(
1114                self._svd2pac_as_ptr().add(6912usize),
1115            )
1116        }
1117    }
1118
1119    #[doc = "Master Bufferable Write Error Clear Register"]
1120    #[inline(always)]
1121    pub const fn mbwerrclr(
1122        &self,
1123    ) -> &'static crate::common::Reg<self::Mbwerrclr_SPEC, crate::common::RW> {
1124        unsafe {
1125            crate::common::Reg::<self::Mbwerrclr_SPEC, crate::common::RW>::from_ptr(
1126                self._svd2pac_as_ptr().add(6920usize),
1127            )
1128        }
1129    }
1130
1131    #[doc = "Slave Bufferable Write Error Status Register"]
1132    #[inline(always)]
1133    pub const fn sbwerrstat(
1134        &self,
1135    ) -> &'static crate::common::Reg<self::Sbwerrstat_SPEC, crate::common::R> {
1136        unsafe {
1137            crate::common::Reg::<self::Sbwerrstat_SPEC, crate::common::R>::from_ptr(
1138                self._svd2pac_as_ptr().add(6944usize),
1139            )
1140        }
1141    }
1142
1143    #[doc = "Slave Bufferable Write Error Clear Register"]
1144    #[inline(always)]
1145    pub const fn sbwerrclr(
1146        &self,
1147    ) -> &'static crate::common::Reg<self::Sbwerrclr_SPEC, crate::common::RW> {
1148        unsafe {
1149            crate::common::Reg::<self::Sbwerrclr_SPEC, crate::common::RW>::from_ptr(
1150                self._svd2pac_as_ptr().add(6952usize),
1151            )
1152        }
1153    }
1154}
1155#[doc(hidden)]
1156#[derive(Copy, Clone, Eq, PartialEq)]
1157pub struct Csmod_SPEC;
1158impl crate::sealed::RegSpec for Csmod_SPEC {
1159    type DataType = u16;
1160}
1161
1162#[doc = "CS%s Mode Register (n = 0 to 7)"]
1163pub type Csmod = crate::RegValueT<Csmod_SPEC>;
1164
1165impl Csmod {
1166    #[doc = "Write Access Mode Select"]
1167    #[inline(always)]
1168    pub fn wrmod(
1169        self,
1170    ) -> crate::common::RegisterField<
1171        0,
1172        0x1,
1173        1,
1174        0,
1175        csmod::Wrmod,
1176        csmod::Wrmod,
1177        Csmod_SPEC,
1178        crate::common::RW,
1179    > {
1180        crate::common::RegisterField::<
1181            0,
1182            0x1,
1183            1,
1184            0,
1185            csmod::Wrmod,
1186            csmod::Wrmod,
1187            Csmod_SPEC,
1188            crate::common::RW,
1189        >::from_register(self, 0)
1190    }
1191
1192    #[doc = "External Wait Enable"]
1193    #[inline(always)]
1194    pub fn ewenb(
1195        self,
1196    ) -> crate::common::RegisterField<
1197        3,
1198        0x1,
1199        1,
1200        0,
1201        csmod::Ewenb,
1202        csmod::Ewenb,
1203        Csmod_SPEC,
1204        crate::common::RW,
1205    > {
1206        crate::common::RegisterField::<
1207            3,
1208            0x1,
1209            1,
1210            0,
1211            csmod::Ewenb,
1212            csmod::Ewenb,
1213            Csmod_SPEC,
1214            crate::common::RW,
1215        >::from_register(self, 0)
1216    }
1217
1218    #[doc = "Page Read Access Enable"]
1219    #[inline(always)]
1220    pub fn prenb(
1221        self,
1222    ) -> crate::common::RegisterField<
1223        8,
1224        0x1,
1225        1,
1226        0,
1227        csmod::Prenb,
1228        csmod::Prenb,
1229        Csmod_SPEC,
1230        crate::common::RW,
1231    > {
1232        crate::common::RegisterField::<
1233            8,
1234            0x1,
1235            1,
1236            0,
1237            csmod::Prenb,
1238            csmod::Prenb,
1239            Csmod_SPEC,
1240            crate::common::RW,
1241        >::from_register(self, 0)
1242    }
1243
1244    #[doc = "Page Write Access Enable"]
1245    #[inline(always)]
1246    pub fn pwenb(
1247        self,
1248    ) -> crate::common::RegisterField<
1249        9,
1250        0x1,
1251        1,
1252        0,
1253        csmod::Pwenb,
1254        csmod::Pwenb,
1255        Csmod_SPEC,
1256        crate::common::RW,
1257    > {
1258        crate::common::RegisterField::<
1259            9,
1260            0x1,
1261            1,
1262            0,
1263            csmod::Pwenb,
1264            csmod::Pwenb,
1265            Csmod_SPEC,
1266            crate::common::RW,
1267        >::from_register(self, 0)
1268    }
1269
1270    #[doc = "Page Read Access Mode Select"]
1271    #[inline(always)]
1272    pub fn prmod(
1273        self,
1274    ) -> crate::common::RegisterField<
1275        15,
1276        0x1,
1277        1,
1278        0,
1279        csmod::Prmod,
1280        csmod::Prmod,
1281        Csmod_SPEC,
1282        crate::common::RW,
1283    > {
1284        crate::common::RegisterField::<
1285            15,
1286            0x1,
1287            1,
1288            0,
1289            csmod::Prmod,
1290            csmod::Prmod,
1291            Csmod_SPEC,
1292            crate::common::RW,
1293        >::from_register(self, 0)
1294    }
1295}
1296impl ::core::default::Default for Csmod {
1297    #[inline(always)]
1298    fn default() -> Csmod {
1299        <crate::RegValueT<Csmod_SPEC> as RegisterValue<_>>::new(0)
1300    }
1301}
1302pub mod csmod {
1303
1304    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1305    pub struct Wrmod_SPEC;
1306    pub type Wrmod = crate::EnumBitfieldStruct<u8, Wrmod_SPEC>;
1307    impl Wrmod {
1308        #[doc = "Byte strobe mode"]
1309        pub const _0: Self = Self::new(0);
1310
1311        #[doc = "Single-write strobe mode"]
1312        pub const _1: Self = Self::new(1);
1313    }
1314    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1315    pub struct Ewenb_SPEC;
1316    pub type Ewenb = crate::EnumBitfieldStruct<u8, Ewenb_SPEC>;
1317    impl Ewenb {
1318        #[doc = "Disabled"]
1319        pub const _0: Self = Self::new(0);
1320
1321        #[doc = "Enabled"]
1322        pub const _1: Self = Self::new(1);
1323    }
1324    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1325    pub struct Prenb_SPEC;
1326    pub type Prenb = crate::EnumBitfieldStruct<u8, Prenb_SPEC>;
1327    impl Prenb {
1328        #[doc = "Disabled"]
1329        pub const _0: Self = Self::new(0);
1330
1331        #[doc = "Enabled"]
1332        pub const _1: Self = Self::new(1);
1333    }
1334    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1335    pub struct Pwenb_SPEC;
1336    pub type Pwenb = crate::EnumBitfieldStruct<u8, Pwenb_SPEC>;
1337    impl Pwenb {
1338        #[doc = "Disabled"]
1339        pub const _0: Self = Self::new(0);
1340
1341        #[doc = "Enabled"]
1342        pub const _1: Self = Self::new(1);
1343    }
1344    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1345    pub struct Prmod_SPEC;
1346    pub type Prmod = crate::EnumBitfieldStruct<u8, Prmod_SPEC>;
1347    impl Prmod {
1348        #[doc = "Normal access compatible mode"]
1349        pub const _0: Self = Self::new(0);
1350
1351        #[doc = "External data read continuous assertion mode"]
1352        pub const _1: Self = Self::new(1);
1353    }
1354}
1355#[doc(hidden)]
1356#[derive(Copy, Clone, Eq, PartialEq)]
1357pub struct Cswcr1_SPEC;
1358impl crate::sealed::RegSpec for Cswcr1_SPEC {
1359    type DataType = u32;
1360}
1361
1362#[doc = "CS%s Wait Control Register 1 (n = 0 to 7)"]
1363pub type Cswcr1 = crate::RegValueT<Cswcr1_SPEC>;
1364
1365impl Cswcr1 {
1366    #[doc = "Page Write Cycle Wait Select"]
1367    #[inline(always)]
1368    pub fn cspwwait(
1369        self,
1370    ) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, Cswcr1_SPEC, crate::common::RW> {
1371        crate::common::RegisterField::<0,0x7,1,0,u8,u8,Cswcr1_SPEC,crate::common::RW>::from_register(self,0)
1372    }
1373
1374    #[doc = "Page Read Cycle Wait Select"]
1375    #[inline(always)]
1376    pub fn csprwait(
1377        self,
1378    ) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, Cswcr1_SPEC, crate::common::RW> {
1379        crate::common::RegisterField::<8,0x7,1,0,u8,u8,Cswcr1_SPEC,crate::common::RW>::from_register(self,0)
1380    }
1381
1382    #[doc = "Normal Write Cycle Wait Select"]
1383    #[inline(always)]
1384    pub fn cswwait(
1385        self,
1386    ) -> crate::common::RegisterField<16, 0x1f, 1, 0, u8, u8, Cswcr1_SPEC, crate::common::RW> {
1387        crate::common::RegisterField::<16,0x1f,1,0,u8,u8,Cswcr1_SPEC,crate::common::RW>::from_register(self,0)
1388    }
1389
1390    #[doc = "Normal Read Cycle Wait Select"]
1391    #[inline(always)]
1392    pub fn csrwait(
1393        self,
1394    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, Cswcr1_SPEC, crate::common::RW> {
1395        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,Cswcr1_SPEC,crate::common::RW>::from_register(self,0)
1396    }
1397}
1398impl ::core::default::Default for Cswcr1 {
1399    #[inline(always)]
1400    fn default() -> Cswcr1 {
1401        <crate::RegValueT<Cswcr1_SPEC> as RegisterValue<_>>::new(117901063)
1402    }
1403}
1404
1405#[doc(hidden)]
1406#[derive(Copy, Clone, Eq, PartialEq)]
1407pub struct Cswcr2_SPEC;
1408impl crate::sealed::RegSpec for Cswcr2_SPEC {
1409    type DataType = u32;
1410}
1411
1412#[doc = "CS%s Wait Control Register 2 (n = 0 to 7)"]
1413pub type Cswcr2 = crate::RegValueT<Cswcr2_SPEC>;
1414
1415impl Cswcr2 {
1416    #[doc = "Read Access CS Extension Cycle Select"]
1417    #[inline(always)]
1418    pub fn csroff(
1419        self,
1420    ) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, Cswcr2_SPEC, crate::common::RW> {
1421        crate::common::RegisterField::<0,0x7,1,0,u8,u8,Cswcr2_SPEC,crate::common::RW>::from_register(self,0)
1422    }
1423
1424    #[doc = "Write Access CS Extension Cycle Select"]
1425    #[inline(always)]
1426    pub fn cswoff(
1427        self,
1428    ) -> crate::common::RegisterField<4, 0x7, 1, 0, u8, u8, Cswcr2_SPEC, crate::common::RW> {
1429        crate::common::RegisterField::<4,0x7,1,0,u8,u8,Cswcr2_SPEC,crate::common::RW>::from_register(self,0)
1430    }
1431
1432    #[doc = "Write Data Output Extension Cycle Select"]
1433    #[inline(always)]
1434    pub fn wdoff(
1435        self,
1436    ) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, Cswcr2_SPEC, crate::common::RW> {
1437        crate::common::RegisterField::<8,0x7,1,0,u8,u8,Cswcr2_SPEC,crate::common::RW>::from_register(self,0)
1438    }
1439
1440    #[doc = "Address Cycle Wait Select"]
1441    #[inline(always)]
1442    pub fn r#await(
1443        self,
1444    ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, Cswcr2_SPEC, crate::common::RW> {
1445        crate::common::RegisterField::<12,0x3,1,0,u8,u8,Cswcr2_SPEC,crate::common::RW>::from_register(self,0)
1446    }
1447
1448    #[doc = "RD Assert Wait Select"]
1449    #[inline(always)]
1450    pub fn rdon(
1451        self,
1452    ) -> crate::common::RegisterField<16, 0x7, 1, 0, u8, u8, Cswcr2_SPEC, crate::common::RW> {
1453        crate::common::RegisterField::<16,0x7,1,0,u8,u8,Cswcr2_SPEC,crate::common::RW>::from_register(self,0)
1454    }
1455
1456    #[doc = "WR Assert Wait Select"]
1457    #[inline(always)]
1458    pub fn wron(
1459        self,
1460    ) -> crate::common::RegisterField<20, 0x7, 1, 0, u8, u8, Cswcr2_SPEC, crate::common::RW> {
1461        crate::common::RegisterField::<20,0x7,1,0,u8,u8,Cswcr2_SPEC,crate::common::RW>::from_register(self,0)
1462    }
1463
1464    #[doc = "Write Data Output Wait Select"]
1465    #[inline(always)]
1466    pub fn wdon(
1467        self,
1468    ) -> crate::common::RegisterField<24, 0x7, 1, 0, u8, u8, Cswcr2_SPEC, crate::common::RW> {
1469        crate::common::RegisterField::<24,0x7,1,0,u8,u8,Cswcr2_SPEC,crate::common::RW>::from_register(self,0)
1470    }
1471
1472    #[doc = "CS Assert Wait Select"]
1473    #[inline(always)]
1474    pub fn cson(
1475        self,
1476    ) -> crate::common::RegisterField<28, 0x7, 1, 0, u8, u8, Cswcr2_SPEC, crate::common::RW> {
1477        crate::common::RegisterField::<28,0x7,1,0,u8,u8,Cswcr2_SPEC,crate::common::RW>::from_register(self,0)
1478    }
1479}
1480impl ::core::default::Default for Cswcr2 {
1481    #[inline(always)]
1482    fn default() -> Cswcr2 {
1483        <crate::RegValueT<Cswcr2_SPEC> as RegisterValue<_>>::new(7)
1484    }
1485}
1486
1487#[doc(hidden)]
1488#[derive(Copy, Clone, Eq, PartialEq)]
1489pub struct Cs0Cr_SPEC;
1490impl crate::sealed::RegSpec for Cs0Cr_SPEC {
1491    type DataType = u16;
1492}
1493
1494#[doc = "CS0 Control Register"]
1495pub type Cs0Cr = crate::RegValueT<Cs0Cr_SPEC>;
1496
1497impl Cs0Cr {
1498    #[doc = "Operation Enable"]
1499    #[inline(always)]
1500    pub fn exenb(
1501        self,
1502    ) -> crate::common::RegisterField<
1503        0,
1504        0x1,
1505        1,
1506        0,
1507        cs0cr::Exenb,
1508        cs0cr::Exenb,
1509        Cs0Cr_SPEC,
1510        crate::common::RW,
1511    > {
1512        crate::common::RegisterField::<
1513            0,
1514            0x1,
1515            1,
1516            0,
1517            cs0cr::Exenb,
1518            cs0cr::Exenb,
1519            Cs0Cr_SPEC,
1520            crate::common::RW,
1521        >::from_register(self, 0)
1522    }
1523
1524    #[doc = "External Bus Width Select"]
1525    #[inline(always)]
1526    pub fn bsize(
1527        self,
1528    ) -> crate::common::RegisterField<
1529        4,
1530        0x3,
1531        1,
1532        0,
1533        cs0cr::Bsize,
1534        cs0cr::Bsize,
1535        Cs0Cr_SPEC,
1536        crate::common::RW,
1537    > {
1538        crate::common::RegisterField::<
1539            4,
1540            0x3,
1541            1,
1542            0,
1543            cs0cr::Bsize,
1544            cs0cr::Bsize,
1545            Cs0Cr_SPEC,
1546            crate::common::RW,
1547        >::from_register(self, 0)
1548    }
1549
1550    #[doc = "Endian Mode"]
1551    #[inline(always)]
1552    pub fn emode(
1553        self,
1554    ) -> crate::common::RegisterField<
1555        8,
1556        0x1,
1557        1,
1558        0,
1559        cs0cr::Emode,
1560        cs0cr::Emode,
1561        Cs0Cr_SPEC,
1562        crate::common::RW,
1563    > {
1564        crate::common::RegisterField::<
1565            8,
1566            0x1,
1567            1,
1568            0,
1569            cs0cr::Emode,
1570            cs0cr::Emode,
1571            Cs0Cr_SPEC,
1572            crate::common::RW,
1573        >::from_register(self, 0)
1574    }
1575
1576    #[doc = "Address/Data Multiplexed I/O Interface Select"]
1577    #[inline(always)]
1578    pub fn mpxen(
1579        self,
1580    ) -> crate::common::RegisterField<
1581        12,
1582        0x1,
1583        1,
1584        0,
1585        cs0cr::Mpxen,
1586        cs0cr::Mpxen,
1587        Cs0Cr_SPEC,
1588        crate::common::RW,
1589    > {
1590        crate::common::RegisterField::<
1591            12,
1592            0x1,
1593            1,
1594            0,
1595            cs0cr::Mpxen,
1596            cs0cr::Mpxen,
1597            Cs0Cr_SPEC,
1598            crate::common::RW,
1599        >::from_register(self, 0)
1600    }
1601}
1602impl ::core::default::Default for Cs0Cr {
1603    #[inline(always)]
1604    fn default() -> Cs0Cr {
1605        <crate::RegValueT<Cs0Cr_SPEC> as RegisterValue<_>>::new(1)
1606    }
1607}
1608pub mod cs0cr {
1609
1610    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1611    pub struct Exenb_SPEC;
1612    pub type Exenb = crate::EnumBitfieldStruct<u8, Exenb_SPEC>;
1613    impl Exenb {
1614        #[doc = "Disable operation"]
1615        pub const _0: Self = Self::new(0);
1616
1617        #[doc = "Enable operation"]
1618        pub const _1: Self = Self::new(1);
1619    }
1620    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1621    pub struct Bsize_SPEC;
1622    pub type Bsize = crate::EnumBitfieldStruct<u8, Bsize_SPEC>;
1623    impl Bsize {
1624        #[doc = "16-bit bus space"]
1625        pub const _00: Self = Self::new(0);
1626
1627        #[doc = "8-bit bus space"]
1628        pub const _10: Self = Self::new(2);
1629
1630        #[doc = "Setting prohibited"]
1631        pub const OTHERS: Self = Self::new(0);
1632    }
1633    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1634    pub struct Emode_SPEC;
1635    pub type Emode = crate::EnumBitfieldStruct<u8, Emode_SPEC>;
1636    impl Emode {
1637        #[doc = "Little endian"]
1638        pub const _0: Self = Self::new(0);
1639
1640        #[doc = "Big endian"]
1641        pub const _1: Self = Self::new(1);
1642    }
1643    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1644    pub struct Mpxen_SPEC;
1645    pub type Mpxen = crate::EnumBitfieldStruct<u8, Mpxen_SPEC>;
1646    impl Mpxen {
1647        #[doc = "Separate bus interface is selected for area n."]
1648        pub const _0: Self = Self::new(0);
1649
1650        #[doc = "Address/data multiplexed I/O interface is selected for area n."]
1651        pub const _1: Self = Self::new(1);
1652    }
1653}
1654#[doc(hidden)]
1655#[derive(Copy, Clone, Eq, PartialEq)]
1656pub struct Csrec_SPEC;
1657impl crate::sealed::RegSpec for Csrec_SPEC {
1658    type DataType = u16;
1659}
1660
1661#[doc = "CS%s Recovery Cycle Register (n = 0 to 7)"]
1662pub type Csrec = crate::RegValueT<Csrec_SPEC>;
1663
1664impl Csrec {
1665    #[doc = "Read Recovery"]
1666    #[inline(always)]
1667    pub fn rrcv(
1668        self,
1669    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, Csrec_SPEC, crate::common::RW> {
1670        crate::common::RegisterField::<0,0xf,1,0,u8,u8,Csrec_SPEC,crate::common::RW>::from_register(self,0)
1671    }
1672
1673    #[doc = "Write Recovery"]
1674    #[inline(always)]
1675    pub fn wrcv(
1676        self,
1677    ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, Csrec_SPEC, crate::common::RW> {
1678        crate::common::RegisterField::<8,0xf,1,0,u8,u8,Csrec_SPEC,crate::common::RW>::from_register(self,0)
1679    }
1680}
1681impl ::core::default::Default for Csrec {
1682    #[inline(always)]
1683    fn default() -> Csrec {
1684        <crate::RegValueT<Csrec_SPEC> as RegisterValue<_>>::new(0)
1685    }
1686}
1687
1688#[doc(hidden)]
1689#[derive(Copy, Clone, Eq, PartialEq)]
1690pub struct Cscr_SPEC;
1691impl crate::sealed::RegSpec for Cscr_SPEC {
1692    type DataType = u16;
1693}
1694
1695#[doc = "CS%s Control Register"]
1696pub type Cscr = crate::RegValueT<Cscr_SPEC>;
1697
1698impl Cscr {
1699    #[doc = "Operation Enable"]
1700    #[inline(always)]
1701    pub fn exenb(
1702        self,
1703    ) -> crate::common::RegisterField<
1704        0,
1705        0x1,
1706        1,
1707        0,
1708        cscr::Exenb,
1709        cscr::Exenb,
1710        Cscr_SPEC,
1711        crate::common::RW,
1712    > {
1713        crate::common::RegisterField::<
1714            0,
1715            0x1,
1716            1,
1717            0,
1718            cscr::Exenb,
1719            cscr::Exenb,
1720            Cscr_SPEC,
1721            crate::common::RW,
1722        >::from_register(self, 0)
1723    }
1724
1725    #[doc = "External Bus Width Select"]
1726    #[inline(always)]
1727    pub fn bsize(
1728        self,
1729    ) -> crate::common::RegisterField<
1730        4,
1731        0x3,
1732        1,
1733        0,
1734        cscr::Bsize,
1735        cscr::Bsize,
1736        Cscr_SPEC,
1737        crate::common::RW,
1738    > {
1739        crate::common::RegisterField::<
1740            4,
1741            0x3,
1742            1,
1743            0,
1744            cscr::Bsize,
1745            cscr::Bsize,
1746            Cscr_SPEC,
1747            crate::common::RW,
1748        >::from_register(self, 0)
1749    }
1750
1751    #[doc = "Endian Mode"]
1752    #[inline(always)]
1753    pub fn emode(
1754        self,
1755    ) -> crate::common::RegisterField<
1756        8,
1757        0x1,
1758        1,
1759        0,
1760        cscr::Emode,
1761        cscr::Emode,
1762        Cscr_SPEC,
1763        crate::common::RW,
1764    > {
1765        crate::common::RegisterField::<
1766            8,
1767            0x1,
1768            1,
1769            0,
1770            cscr::Emode,
1771            cscr::Emode,
1772            Cscr_SPEC,
1773            crate::common::RW,
1774        >::from_register(self, 0)
1775    }
1776
1777    #[doc = "Address/Data Multiplexed I/O Interface Select"]
1778    #[inline(always)]
1779    pub fn mpxen(
1780        self,
1781    ) -> crate::common::RegisterField<
1782        12,
1783        0x1,
1784        1,
1785        0,
1786        cscr::Mpxen,
1787        cscr::Mpxen,
1788        Cscr_SPEC,
1789        crate::common::RW,
1790    > {
1791        crate::common::RegisterField::<
1792            12,
1793            0x1,
1794            1,
1795            0,
1796            cscr::Mpxen,
1797            cscr::Mpxen,
1798            Cscr_SPEC,
1799            crate::common::RW,
1800        >::from_register(self, 0)
1801    }
1802}
1803impl ::core::default::Default for Cscr {
1804    #[inline(always)]
1805    fn default() -> Cscr {
1806        <crate::RegValueT<Cscr_SPEC> as RegisterValue<_>>::new(0)
1807    }
1808}
1809pub mod cscr {
1810
1811    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1812    pub struct Exenb_SPEC;
1813    pub type Exenb = crate::EnumBitfieldStruct<u8, Exenb_SPEC>;
1814    impl Exenb {
1815        #[doc = "Disable operation"]
1816        pub const _0: Self = Self::new(0);
1817
1818        #[doc = "Enable operation"]
1819        pub const _1: Self = Self::new(1);
1820    }
1821    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1822    pub struct Bsize_SPEC;
1823    pub type Bsize = crate::EnumBitfieldStruct<u8, Bsize_SPEC>;
1824    impl Bsize {
1825        #[doc = "16-bit bus space"]
1826        pub const _00: Self = Self::new(0);
1827
1828        #[doc = "8-bit bus space"]
1829        pub const _10: Self = Self::new(2);
1830
1831        #[doc = "Setting prohibited"]
1832        pub const OTHERS: Self = Self::new(0);
1833    }
1834    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1835    pub struct Emode_SPEC;
1836    pub type Emode = crate::EnumBitfieldStruct<u8, Emode_SPEC>;
1837    impl Emode {
1838        #[doc = "Little endian"]
1839        pub const _0: Self = Self::new(0);
1840
1841        #[doc = "Big endian"]
1842        pub const _1: Self = Self::new(1);
1843    }
1844    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1845    pub struct Mpxen_SPEC;
1846    pub type Mpxen = crate::EnumBitfieldStruct<u8, Mpxen_SPEC>;
1847    impl Mpxen {
1848        #[doc = "Separate bus interface is selected for area n."]
1849        pub const _0: Self = Self::new(0);
1850
1851        #[doc = "Address/data multiplexed I/O interface is selected for area n."]
1852        pub const _1: Self = Self::new(1);
1853    }
1854}
1855#[doc(hidden)]
1856#[derive(Copy, Clone, Eq, PartialEq)]
1857pub struct Csrecen_SPEC;
1858impl crate::sealed::RegSpec for Csrecen_SPEC {
1859    type DataType = u16;
1860}
1861
1862#[doc = "CS Recovery Cycle Insertion Enable Register"]
1863pub type Csrecen = crate::RegValueT<Csrecen_SPEC>;
1864
1865impl Csrecen {
1866    #[doc = "Separate Bus Recovery Cycle Insertion Enable 0"]
1867    #[inline(always)]
1868    pub fn rcven0(
1869        self,
1870    ) -> crate::common::RegisterField<
1871        0,
1872        0x1,
1873        1,
1874        0,
1875        csrecen::Rcven0,
1876        csrecen::Rcven0,
1877        Csrecen_SPEC,
1878        crate::common::RW,
1879    > {
1880        crate::common::RegisterField::<
1881            0,
1882            0x1,
1883            1,
1884            0,
1885            csrecen::Rcven0,
1886            csrecen::Rcven0,
1887            Csrecen_SPEC,
1888            crate::common::RW,
1889        >::from_register(self, 0)
1890    }
1891
1892    #[doc = "Separate Bus Recovery Cycle Insertion Enable 1"]
1893    #[inline(always)]
1894    pub fn rcven1(
1895        self,
1896    ) -> crate::common::RegisterField<
1897        1,
1898        0x1,
1899        1,
1900        0,
1901        csrecen::Rcven1,
1902        csrecen::Rcven1,
1903        Csrecen_SPEC,
1904        crate::common::RW,
1905    > {
1906        crate::common::RegisterField::<
1907            1,
1908            0x1,
1909            1,
1910            0,
1911            csrecen::Rcven1,
1912            csrecen::Rcven1,
1913            Csrecen_SPEC,
1914            crate::common::RW,
1915        >::from_register(self, 0)
1916    }
1917
1918    #[doc = "Separate Bus Recovery Cycle Insertion Enable 2"]
1919    #[inline(always)]
1920    pub fn rcven2(
1921        self,
1922    ) -> crate::common::RegisterField<
1923        2,
1924        0x1,
1925        1,
1926        0,
1927        csrecen::Rcven2,
1928        csrecen::Rcven2,
1929        Csrecen_SPEC,
1930        crate::common::RW,
1931    > {
1932        crate::common::RegisterField::<
1933            2,
1934            0x1,
1935            1,
1936            0,
1937            csrecen::Rcven2,
1938            csrecen::Rcven2,
1939            Csrecen_SPEC,
1940            crate::common::RW,
1941        >::from_register(self, 0)
1942    }
1943
1944    #[doc = "Separate Bus Recovery Cycle Insertion Enable 3"]
1945    #[inline(always)]
1946    pub fn rcven3(
1947        self,
1948    ) -> crate::common::RegisterField<
1949        3,
1950        0x1,
1951        1,
1952        0,
1953        csrecen::Rcven3,
1954        csrecen::Rcven3,
1955        Csrecen_SPEC,
1956        crate::common::RW,
1957    > {
1958        crate::common::RegisterField::<
1959            3,
1960            0x1,
1961            1,
1962            0,
1963            csrecen::Rcven3,
1964            csrecen::Rcven3,
1965            Csrecen_SPEC,
1966            crate::common::RW,
1967        >::from_register(self, 0)
1968    }
1969
1970    #[doc = "Separate Bus Recovery Cycle Insertion Enable 4"]
1971    #[inline(always)]
1972    pub fn rcven4(
1973        self,
1974    ) -> crate::common::RegisterField<
1975        4,
1976        0x1,
1977        1,
1978        0,
1979        csrecen::Rcven4,
1980        csrecen::Rcven4,
1981        Csrecen_SPEC,
1982        crate::common::RW,
1983    > {
1984        crate::common::RegisterField::<
1985            4,
1986            0x1,
1987            1,
1988            0,
1989            csrecen::Rcven4,
1990            csrecen::Rcven4,
1991            Csrecen_SPEC,
1992            crate::common::RW,
1993        >::from_register(self, 0)
1994    }
1995
1996    #[doc = "Separate Bus Recovery Cycle Insertion Enable 5"]
1997    #[inline(always)]
1998    pub fn rcven5(
1999        self,
2000    ) -> crate::common::RegisterField<
2001        5,
2002        0x1,
2003        1,
2004        0,
2005        csrecen::Rcven5,
2006        csrecen::Rcven5,
2007        Csrecen_SPEC,
2008        crate::common::RW,
2009    > {
2010        crate::common::RegisterField::<
2011            5,
2012            0x1,
2013            1,
2014            0,
2015            csrecen::Rcven5,
2016            csrecen::Rcven5,
2017            Csrecen_SPEC,
2018            crate::common::RW,
2019        >::from_register(self, 0)
2020    }
2021
2022    #[doc = "Separate Bus Recovery Cycle Insertion Enable 6"]
2023    #[inline(always)]
2024    pub fn rcven6(
2025        self,
2026    ) -> crate::common::RegisterField<
2027        6,
2028        0x1,
2029        1,
2030        0,
2031        csrecen::Rcven6,
2032        csrecen::Rcven6,
2033        Csrecen_SPEC,
2034        crate::common::RW,
2035    > {
2036        crate::common::RegisterField::<
2037            6,
2038            0x1,
2039            1,
2040            0,
2041            csrecen::Rcven6,
2042            csrecen::Rcven6,
2043            Csrecen_SPEC,
2044            crate::common::RW,
2045        >::from_register(self, 0)
2046    }
2047
2048    #[doc = "Separate Bus Recovery Cycle Insertion Enable 7"]
2049    #[inline(always)]
2050    pub fn rcven7(
2051        self,
2052    ) -> crate::common::RegisterField<
2053        7,
2054        0x1,
2055        1,
2056        0,
2057        csrecen::Rcven7,
2058        csrecen::Rcven7,
2059        Csrecen_SPEC,
2060        crate::common::RW,
2061    > {
2062        crate::common::RegisterField::<
2063            7,
2064            0x1,
2065            1,
2066            0,
2067            csrecen::Rcven7,
2068            csrecen::Rcven7,
2069            Csrecen_SPEC,
2070            crate::common::RW,
2071        >::from_register(self, 0)
2072    }
2073
2074    #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 0"]
2075    #[inline(always)]
2076    pub fn rcvenm0(
2077        self,
2078    ) -> crate::common::RegisterField<
2079        8,
2080        0x1,
2081        1,
2082        0,
2083        csrecen::Rcvenm0,
2084        csrecen::Rcvenm0,
2085        Csrecen_SPEC,
2086        crate::common::RW,
2087    > {
2088        crate::common::RegisterField::<
2089            8,
2090            0x1,
2091            1,
2092            0,
2093            csrecen::Rcvenm0,
2094            csrecen::Rcvenm0,
2095            Csrecen_SPEC,
2096            crate::common::RW,
2097        >::from_register(self, 0)
2098    }
2099
2100    #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 1"]
2101    #[inline(always)]
2102    pub fn rcvenm1(
2103        self,
2104    ) -> crate::common::RegisterField<
2105        9,
2106        0x1,
2107        1,
2108        0,
2109        csrecen::Rcvenm1,
2110        csrecen::Rcvenm1,
2111        Csrecen_SPEC,
2112        crate::common::RW,
2113    > {
2114        crate::common::RegisterField::<
2115            9,
2116            0x1,
2117            1,
2118            0,
2119            csrecen::Rcvenm1,
2120            csrecen::Rcvenm1,
2121            Csrecen_SPEC,
2122            crate::common::RW,
2123        >::from_register(self, 0)
2124    }
2125
2126    #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 2"]
2127    #[inline(always)]
2128    pub fn rcvenm2(
2129        self,
2130    ) -> crate::common::RegisterField<
2131        10,
2132        0x1,
2133        1,
2134        0,
2135        csrecen::Rcvenm2,
2136        csrecen::Rcvenm2,
2137        Csrecen_SPEC,
2138        crate::common::RW,
2139    > {
2140        crate::common::RegisterField::<
2141            10,
2142            0x1,
2143            1,
2144            0,
2145            csrecen::Rcvenm2,
2146            csrecen::Rcvenm2,
2147            Csrecen_SPEC,
2148            crate::common::RW,
2149        >::from_register(self, 0)
2150    }
2151
2152    #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 3"]
2153    #[inline(always)]
2154    pub fn rcvenm3(
2155        self,
2156    ) -> crate::common::RegisterField<
2157        11,
2158        0x1,
2159        1,
2160        0,
2161        csrecen::Rcvenm3,
2162        csrecen::Rcvenm3,
2163        Csrecen_SPEC,
2164        crate::common::RW,
2165    > {
2166        crate::common::RegisterField::<
2167            11,
2168            0x1,
2169            1,
2170            0,
2171            csrecen::Rcvenm3,
2172            csrecen::Rcvenm3,
2173            Csrecen_SPEC,
2174            crate::common::RW,
2175        >::from_register(self, 0)
2176    }
2177
2178    #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 4"]
2179    #[inline(always)]
2180    pub fn rcvenm4(
2181        self,
2182    ) -> crate::common::RegisterField<
2183        12,
2184        0x1,
2185        1,
2186        0,
2187        csrecen::Rcvenm4,
2188        csrecen::Rcvenm4,
2189        Csrecen_SPEC,
2190        crate::common::RW,
2191    > {
2192        crate::common::RegisterField::<
2193            12,
2194            0x1,
2195            1,
2196            0,
2197            csrecen::Rcvenm4,
2198            csrecen::Rcvenm4,
2199            Csrecen_SPEC,
2200            crate::common::RW,
2201        >::from_register(self, 0)
2202    }
2203
2204    #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 5"]
2205    #[inline(always)]
2206    pub fn rcvenm5(
2207        self,
2208    ) -> crate::common::RegisterField<
2209        13,
2210        0x1,
2211        1,
2212        0,
2213        csrecen::Rcvenm5,
2214        csrecen::Rcvenm5,
2215        Csrecen_SPEC,
2216        crate::common::RW,
2217    > {
2218        crate::common::RegisterField::<
2219            13,
2220            0x1,
2221            1,
2222            0,
2223            csrecen::Rcvenm5,
2224            csrecen::Rcvenm5,
2225            Csrecen_SPEC,
2226            crate::common::RW,
2227        >::from_register(self, 0)
2228    }
2229
2230    #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 6"]
2231    #[inline(always)]
2232    pub fn rcvenm6(
2233        self,
2234    ) -> crate::common::RegisterField<
2235        14,
2236        0x1,
2237        1,
2238        0,
2239        csrecen::Rcvenm6,
2240        csrecen::Rcvenm6,
2241        Csrecen_SPEC,
2242        crate::common::RW,
2243    > {
2244        crate::common::RegisterField::<
2245            14,
2246            0x1,
2247            1,
2248            0,
2249            csrecen::Rcvenm6,
2250            csrecen::Rcvenm6,
2251            Csrecen_SPEC,
2252            crate::common::RW,
2253        >::from_register(self, 0)
2254    }
2255
2256    #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 7"]
2257    #[inline(always)]
2258    pub fn rcvenm7(
2259        self,
2260    ) -> crate::common::RegisterField<
2261        15,
2262        0x1,
2263        1,
2264        0,
2265        csrecen::Rcvenm7,
2266        csrecen::Rcvenm7,
2267        Csrecen_SPEC,
2268        crate::common::RW,
2269    > {
2270        crate::common::RegisterField::<
2271            15,
2272            0x1,
2273            1,
2274            0,
2275            csrecen::Rcvenm7,
2276            csrecen::Rcvenm7,
2277            Csrecen_SPEC,
2278            crate::common::RW,
2279        >::from_register(self, 0)
2280    }
2281}
2282impl ::core::default::Default for Csrecen {
2283    #[inline(always)]
2284    fn default() -> Csrecen {
2285        <crate::RegValueT<Csrecen_SPEC> as RegisterValue<_>>::new(15934)
2286    }
2287}
2288pub mod csrecen {
2289
2290    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2291    pub struct Rcven0_SPEC;
2292    pub type Rcven0 = crate::EnumBitfieldStruct<u8, Rcven0_SPEC>;
2293    impl Rcven0 {
2294        #[doc = "Disabled"]
2295        pub const _0: Self = Self::new(0);
2296
2297        #[doc = "Enabled"]
2298        pub const _1: Self = Self::new(1);
2299    }
2300    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2301    pub struct Rcven1_SPEC;
2302    pub type Rcven1 = crate::EnumBitfieldStruct<u8, Rcven1_SPEC>;
2303    impl Rcven1 {
2304        #[doc = "Disabled"]
2305        pub const _0: Self = Self::new(0);
2306
2307        #[doc = "Enabled"]
2308        pub const _1: Self = Self::new(1);
2309    }
2310    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2311    pub struct Rcven2_SPEC;
2312    pub type Rcven2 = crate::EnumBitfieldStruct<u8, Rcven2_SPEC>;
2313    impl Rcven2 {
2314        #[doc = "Disabled"]
2315        pub const _0: Self = Self::new(0);
2316
2317        #[doc = "Enabled"]
2318        pub const _1: Self = Self::new(1);
2319    }
2320    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2321    pub struct Rcven3_SPEC;
2322    pub type Rcven3 = crate::EnumBitfieldStruct<u8, Rcven3_SPEC>;
2323    impl Rcven3 {
2324        #[doc = "Disabled"]
2325        pub const _0: Self = Self::new(0);
2326
2327        #[doc = "Enabled"]
2328        pub const _1: Self = Self::new(1);
2329    }
2330    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2331    pub struct Rcven4_SPEC;
2332    pub type Rcven4 = crate::EnumBitfieldStruct<u8, Rcven4_SPEC>;
2333    impl Rcven4 {
2334        #[doc = "Disabled"]
2335        pub const _0: Self = Self::new(0);
2336
2337        #[doc = "Enabled"]
2338        pub const _1: Self = Self::new(1);
2339    }
2340    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2341    pub struct Rcven5_SPEC;
2342    pub type Rcven5 = crate::EnumBitfieldStruct<u8, Rcven5_SPEC>;
2343    impl Rcven5 {
2344        #[doc = "Disabled"]
2345        pub const _0: Self = Self::new(0);
2346
2347        #[doc = "Enabled"]
2348        pub const _1: Self = Self::new(1);
2349    }
2350    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2351    pub struct Rcven6_SPEC;
2352    pub type Rcven6 = crate::EnumBitfieldStruct<u8, Rcven6_SPEC>;
2353    impl Rcven6 {
2354        #[doc = "Disabled"]
2355        pub const _0: Self = Self::new(0);
2356
2357        #[doc = "Enabled"]
2358        pub const _1: Self = Self::new(1);
2359    }
2360    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2361    pub struct Rcven7_SPEC;
2362    pub type Rcven7 = crate::EnumBitfieldStruct<u8, Rcven7_SPEC>;
2363    impl Rcven7 {
2364        #[doc = "Disabled"]
2365        pub const _0: Self = Self::new(0);
2366
2367        #[doc = "Enabled"]
2368        pub const _1: Self = Self::new(1);
2369    }
2370    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2371    pub struct Rcvenm0_SPEC;
2372    pub type Rcvenm0 = crate::EnumBitfieldStruct<u8, Rcvenm0_SPEC>;
2373    impl Rcvenm0 {
2374        #[doc = "Disabled"]
2375        pub const _0: Self = Self::new(0);
2376
2377        #[doc = "Enabled"]
2378        pub const _1: Self = Self::new(1);
2379    }
2380    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2381    pub struct Rcvenm1_SPEC;
2382    pub type Rcvenm1 = crate::EnumBitfieldStruct<u8, Rcvenm1_SPEC>;
2383    impl Rcvenm1 {
2384        #[doc = "Disabled"]
2385        pub const _0: Self = Self::new(0);
2386
2387        #[doc = "Enabled"]
2388        pub const _1: Self = Self::new(1);
2389    }
2390    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2391    pub struct Rcvenm2_SPEC;
2392    pub type Rcvenm2 = crate::EnumBitfieldStruct<u8, Rcvenm2_SPEC>;
2393    impl Rcvenm2 {
2394        #[doc = "Disabled"]
2395        pub const _0: Self = Self::new(0);
2396
2397        #[doc = "Enabled"]
2398        pub const _1: Self = Self::new(1);
2399    }
2400    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2401    pub struct Rcvenm3_SPEC;
2402    pub type Rcvenm3 = crate::EnumBitfieldStruct<u8, Rcvenm3_SPEC>;
2403    impl Rcvenm3 {
2404        #[doc = "Disabled"]
2405        pub const _0: Self = Self::new(0);
2406
2407        #[doc = "Enabled"]
2408        pub const _1: Self = Self::new(1);
2409    }
2410    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2411    pub struct Rcvenm4_SPEC;
2412    pub type Rcvenm4 = crate::EnumBitfieldStruct<u8, Rcvenm4_SPEC>;
2413    impl Rcvenm4 {
2414        #[doc = "Disabled"]
2415        pub const _0: Self = Self::new(0);
2416
2417        #[doc = "Enabled"]
2418        pub const _1: Self = Self::new(1);
2419    }
2420    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2421    pub struct Rcvenm5_SPEC;
2422    pub type Rcvenm5 = crate::EnumBitfieldStruct<u8, Rcvenm5_SPEC>;
2423    impl Rcvenm5 {
2424        #[doc = "Disabled"]
2425        pub const _0: Self = Self::new(0);
2426
2427        #[doc = "Enabled"]
2428        pub const _1: Self = Self::new(1);
2429    }
2430    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2431    pub struct Rcvenm6_SPEC;
2432    pub type Rcvenm6 = crate::EnumBitfieldStruct<u8, Rcvenm6_SPEC>;
2433    impl Rcvenm6 {
2434        #[doc = "Disabled"]
2435        pub const _0: Self = Self::new(0);
2436
2437        #[doc = "Enabled"]
2438        pub const _1: Self = Self::new(1);
2439    }
2440    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2441    pub struct Rcvenm7_SPEC;
2442    pub type Rcvenm7 = crate::EnumBitfieldStruct<u8, Rcvenm7_SPEC>;
2443    impl Rcvenm7 {
2444        #[doc = "Disabled"]
2445        pub const _0: Self = Self::new(0);
2446
2447        #[doc = "Enabled"]
2448        pub const _1: Self = Self::new(1);
2449    }
2450}
2451#[doc(hidden)]
2452#[derive(Copy, Clone, Eq, PartialEq)]
2453pub struct Sdccr_SPEC;
2454impl crate::sealed::RegSpec for Sdccr_SPEC {
2455    type DataType = u8;
2456}
2457
2458#[doc = "SDC Control Register"]
2459pub type Sdccr = crate::RegValueT<Sdccr_SPEC>;
2460
2461impl Sdccr {
2462    #[doc = "Operation Enable"]
2463    #[inline(always)]
2464    pub fn exenb(
2465        self,
2466    ) -> crate::common::RegisterField<
2467        0,
2468        0x1,
2469        1,
2470        0,
2471        sdccr::Exenb,
2472        sdccr::Exenb,
2473        Sdccr_SPEC,
2474        crate::common::RW,
2475    > {
2476        crate::common::RegisterField::<
2477            0,
2478            0x1,
2479            1,
2480            0,
2481            sdccr::Exenb,
2482            sdccr::Exenb,
2483            Sdccr_SPEC,
2484            crate::common::RW,
2485        >::from_register(self, 0)
2486    }
2487
2488    #[doc = "SDRAM Bus Width Select"]
2489    #[inline(always)]
2490    pub fn bsize(
2491        self,
2492    ) -> crate::common::RegisterField<
2493        4,
2494        0x3,
2495        1,
2496        0,
2497        sdccr::Bsize,
2498        sdccr::Bsize,
2499        Sdccr_SPEC,
2500        crate::common::RW,
2501    > {
2502        crate::common::RegisterField::<
2503            4,
2504            0x3,
2505            1,
2506            0,
2507            sdccr::Bsize,
2508            sdccr::Bsize,
2509            Sdccr_SPEC,
2510            crate::common::RW,
2511        >::from_register(self, 0)
2512    }
2513}
2514impl ::core::default::Default for Sdccr {
2515    #[inline(always)]
2516    fn default() -> Sdccr {
2517        <crate::RegValueT<Sdccr_SPEC> as RegisterValue<_>>::new(0)
2518    }
2519}
2520pub mod sdccr {
2521
2522    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2523    pub struct Exenb_SPEC;
2524    pub type Exenb = crate::EnumBitfieldStruct<u8, Exenb_SPEC>;
2525    impl Exenb {
2526        #[doc = "Disable"]
2527        pub const _0: Self = Self::new(0);
2528
2529        #[doc = "Enable"]
2530        pub const _1: Self = Self::new(1);
2531    }
2532    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2533    pub struct Bsize_SPEC;
2534    pub type Bsize = crate::EnumBitfieldStruct<u8, Bsize_SPEC>;
2535    impl Bsize {
2536        #[doc = "16-bit bus space"]
2537        pub const _00: Self = Self::new(0);
2538
2539        #[doc = "8-bit bus space"]
2540        pub const _10: Self = Self::new(2);
2541
2542        #[doc = "Setting prohibited"]
2543        pub const OTHERS: Self = Self::new(0);
2544    }
2545}
2546#[doc(hidden)]
2547#[derive(Copy, Clone, Eq, PartialEq)]
2548pub struct Sdcmod_SPEC;
2549impl crate::sealed::RegSpec for Sdcmod_SPEC {
2550    type DataType = u8;
2551}
2552
2553#[doc = "SDC Mode Register"]
2554pub type Sdcmod = crate::RegValueT<Sdcmod_SPEC>;
2555
2556impl Sdcmod {
2557    #[doc = "Endian Mode"]
2558    #[inline(always)]
2559    pub fn emode(
2560        self,
2561    ) -> crate::common::RegisterField<
2562        0,
2563        0x1,
2564        1,
2565        0,
2566        sdcmod::Emode,
2567        sdcmod::Emode,
2568        Sdcmod_SPEC,
2569        crate::common::RW,
2570    > {
2571        crate::common::RegisterField::<
2572            0,
2573            0x1,
2574            1,
2575            0,
2576            sdcmod::Emode,
2577            sdcmod::Emode,
2578            Sdcmod_SPEC,
2579            crate::common::RW,
2580        >::from_register(self, 0)
2581    }
2582}
2583impl ::core::default::Default for Sdcmod {
2584    #[inline(always)]
2585    fn default() -> Sdcmod {
2586        <crate::RegValueT<Sdcmod_SPEC> as RegisterValue<_>>::new(0)
2587    }
2588}
2589pub mod sdcmod {
2590
2591    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2592    pub struct Emode_SPEC;
2593    pub type Emode = crate::EnumBitfieldStruct<u8, Emode_SPEC>;
2594    impl Emode {
2595        #[doc = "Endian order of SDRAM address space is the same as the endian order of the operating mode."]
2596        pub const _0: Self = Self::new(0);
2597
2598        #[doc = "Endian order of SDRAM address space is not the endian order of the operating mode."]
2599        pub const _1: Self = Self::new(1);
2600    }
2601}
2602#[doc(hidden)]
2603#[derive(Copy, Clone, Eq, PartialEq)]
2604pub struct Sdamod_SPEC;
2605impl crate::sealed::RegSpec for Sdamod_SPEC {
2606    type DataType = u8;
2607}
2608
2609#[doc = "SDRAM Access Mode Register"]
2610pub type Sdamod = crate::RegValueT<Sdamod_SPEC>;
2611
2612impl Sdamod {
2613    #[doc = "Continuous Access Enable"]
2614    #[inline(always)]
2615    pub fn be(
2616        self,
2617    ) -> crate::common::RegisterField<
2618        0,
2619        0x1,
2620        1,
2621        0,
2622        sdamod::Be,
2623        sdamod::Be,
2624        Sdamod_SPEC,
2625        crate::common::RW,
2626    > {
2627        crate::common::RegisterField::<
2628            0,
2629            0x1,
2630            1,
2631            0,
2632            sdamod::Be,
2633            sdamod::Be,
2634            Sdamod_SPEC,
2635            crate::common::RW,
2636        >::from_register(self, 0)
2637    }
2638}
2639impl ::core::default::Default for Sdamod {
2640    #[inline(always)]
2641    fn default() -> Sdamod {
2642        <crate::RegValueT<Sdamod_SPEC> as RegisterValue<_>>::new(0)
2643    }
2644}
2645pub mod sdamod {
2646
2647    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2648    pub struct Be_SPEC;
2649    pub type Be = crate::EnumBitfieldStruct<u8, Be_SPEC>;
2650    impl Be {
2651        #[doc = "Continuous access is disabled"]
2652        pub const _0: Self = Self::new(0);
2653
2654        #[doc = "Continuous access is enabled"]
2655        pub const _1: Self = Self::new(1);
2656    }
2657}
2658#[doc(hidden)]
2659#[derive(Copy, Clone, Eq, PartialEq)]
2660pub struct Sdself_SPEC;
2661impl crate::sealed::RegSpec for Sdself_SPEC {
2662    type DataType = u8;
2663}
2664
2665#[doc = "SDRAM Self-Refresh Control Register"]
2666pub type Sdself = crate::RegValueT<Sdself_SPEC>;
2667
2668impl Sdself {
2669    #[doc = "SDRAM Self-Refresh Enable"]
2670    #[inline(always)]
2671    pub fn sfen(
2672        self,
2673    ) -> crate::common::RegisterField<
2674        0,
2675        0x1,
2676        1,
2677        0,
2678        sdself::Sfen,
2679        sdself::Sfen,
2680        Sdself_SPEC,
2681        crate::common::RW,
2682    > {
2683        crate::common::RegisterField::<
2684            0,
2685            0x1,
2686            1,
2687            0,
2688            sdself::Sfen,
2689            sdself::Sfen,
2690            Sdself_SPEC,
2691            crate::common::RW,
2692        >::from_register(self, 0)
2693    }
2694}
2695impl ::core::default::Default for Sdself {
2696    #[inline(always)]
2697    fn default() -> Sdself {
2698        <crate::RegValueT<Sdself_SPEC> as RegisterValue<_>>::new(0)
2699    }
2700}
2701pub mod sdself {
2702
2703    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2704    pub struct Sfen_SPEC;
2705    pub type Sfen = crate::EnumBitfieldStruct<u8, Sfen_SPEC>;
2706    impl Sfen {
2707        #[doc = "Disable"]
2708        pub const _0: Self = Self::new(0);
2709
2710        #[doc = "Enable"]
2711        pub const _1: Self = Self::new(1);
2712    }
2713}
2714#[doc(hidden)]
2715#[derive(Copy, Clone, Eq, PartialEq)]
2716pub struct Sdrfcr_SPEC;
2717impl crate::sealed::RegSpec for Sdrfcr_SPEC {
2718    type DataType = u16;
2719}
2720
2721#[doc = "SDRAM Refresh Control Register"]
2722pub type Sdrfcr = crate::RegValueT<Sdrfcr_SPEC>;
2723
2724impl Sdrfcr {
2725    #[doc = "Auto-Refresh Request Interval Setting"]
2726    #[inline(always)]
2727    pub fn rfc(
2728        self,
2729    ) -> crate::common::RegisterField<0, 0xfff, 1, 0, u16, u16, Sdrfcr_SPEC, crate::common::RW>
2730    {
2731        crate::common::RegisterField::<0,0xfff,1,0,u16,u16,Sdrfcr_SPEC,crate::common::RW>::from_register(self,0)
2732    }
2733
2734    #[doc = "Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting"]
2735    #[inline(always)]
2736    pub fn refw(
2737        self,
2738    ) -> crate::common::RegisterField<12, 0xf, 1, 0, u8, u8, Sdrfcr_SPEC, crate::common::RW> {
2739        crate::common::RegisterField::<12,0xf,1,0,u8,u8,Sdrfcr_SPEC,crate::common::RW>::from_register(self,0)
2740    }
2741}
2742impl ::core::default::Default for Sdrfcr {
2743    #[inline(always)]
2744    fn default() -> Sdrfcr {
2745        <crate::RegValueT<Sdrfcr_SPEC> as RegisterValue<_>>::new(1)
2746    }
2747}
2748
2749#[doc(hidden)]
2750#[derive(Copy, Clone, Eq, PartialEq)]
2751pub struct Sdrfen_SPEC;
2752impl crate::sealed::RegSpec for Sdrfen_SPEC {
2753    type DataType = u8;
2754}
2755
2756#[doc = "SDRAM Auto-Refresh Control Register"]
2757pub type Sdrfen = crate::RegValueT<Sdrfen_SPEC>;
2758
2759impl Sdrfen {
2760    #[doc = "Auto-Refresh Operation Enable"]
2761    #[inline(always)]
2762    pub fn rfen(
2763        self,
2764    ) -> crate::common::RegisterField<
2765        0,
2766        0x1,
2767        1,
2768        0,
2769        sdrfen::Rfen,
2770        sdrfen::Rfen,
2771        Sdrfen_SPEC,
2772        crate::common::RW,
2773    > {
2774        crate::common::RegisterField::<
2775            0,
2776            0x1,
2777            1,
2778            0,
2779            sdrfen::Rfen,
2780            sdrfen::Rfen,
2781            Sdrfen_SPEC,
2782            crate::common::RW,
2783        >::from_register(self, 0)
2784    }
2785}
2786impl ::core::default::Default for Sdrfen {
2787    #[inline(always)]
2788    fn default() -> Sdrfen {
2789        <crate::RegValueT<Sdrfen_SPEC> as RegisterValue<_>>::new(0)
2790    }
2791}
2792pub mod sdrfen {
2793
2794    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2795    pub struct Rfen_SPEC;
2796    pub type Rfen = crate::EnumBitfieldStruct<u8, Rfen_SPEC>;
2797    impl Rfen {
2798        #[doc = "Disable"]
2799        pub const _0: Self = Self::new(0);
2800
2801        #[doc = "Enable"]
2802        pub const _1: Self = Self::new(1);
2803    }
2804}
2805#[doc(hidden)]
2806#[derive(Copy, Clone, Eq, PartialEq)]
2807pub struct Sdicr_SPEC;
2808impl crate::sealed::RegSpec for Sdicr_SPEC {
2809    type DataType = u8;
2810}
2811
2812#[doc = "SDRAM Initialization Sequence Control Register"]
2813pub type Sdicr = crate::RegValueT<Sdicr_SPEC>;
2814
2815impl Sdicr {
2816    #[doc = "Initialization Sequence Start"]
2817    #[inline(always)]
2818    pub fn inirq(
2819        self,
2820    ) -> crate::common::RegisterField<
2821        0,
2822        0x1,
2823        1,
2824        0,
2825        sdicr::Inirq,
2826        sdicr::Inirq,
2827        Sdicr_SPEC,
2828        crate::common::RW,
2829    > {
2830        crate::common::RegisterField::<
2831            0,
2832            0x1,
2833            1,
2834            0,
2835            sdicr::Inirq,
2836            sdicr::Inirq,
2837            Sdicr_SPEC,
2838            crate::common::RW,
2839        >::from_register(self, 0)
2840    }
2841}
2842impl ::core::default::Default for Sdicr {
2843    #[inline(always)]
2844    fn default() -> Sdicr {
2845        <crate::RegValueT<Sdicr_SPEC> as RegisterValue<_>>::new(0)
2846    }
2847}
2848pub mod sdicr {
2849
2850    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2851    pub struct Inirq_SPEC;
2852    pub type Inirq = crate::EnumBitfieldStruct<u8, Inirq_SPEC>;
2853    impl Inirq {
2854        #[doc = "Invalid"]
2855        pub const _0: Self = Self::new(0);
2856
2857        #[doc = "Start initialization sequence"]
2858        pub const _1: Self = Self::new(1);
2859    }
2860}
2861#[doc(hidden)]
2862#[derive(Copy, Clone, Eq, PartialEq)]
2863pub struct Sdir_SPEC;
2864impl crate::sealed::RegSpec for Sdir_SPEC {
2865    type DataType = u16;
2866}
2867
2868#[doc = "SDRAM Initialization Register"]
2869pub type Sdir = crate::RegValueT<Sdir_SPEC>;
2870
2871impl Sdir {
2872    #[doc = "Initialization Auto-Refresh Interval"]
2873    #[inline(always)]
2874    pub fn arfi(
2875        self,
2876    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, Sdir_SPEC, crate::common::RW> {
2877        crate::common::RegisterField::<0,0xf,1,0,u8,u8,Sdir_SPEC,crate::common::RW>::from_register(self,0)
2878    }
2879
2880    #[doc = "Initialization Auto-Refresh Count"]
2881    #[inline(always)]
2882    pub fn arfc(
2883        self,
2884    ) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, Sdir_SPEC, crate::common::RW> {
2885        crate::common::RegisterField::<4,0xf,1,0,u8,u8,Sdir_SPEC,crate::common::RW>::from_register(self,0)
2886    }
2887
2888    #[doc = "Initialization Precharge Cycle Count"]
2889    #[inline(always)]
2890    pub fn prc(
2891        self,
2892    ) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, Sdir_SPEC, crate::common::RW> {
2893        crate::common::RegisterField::<8,0x7,1,0,u8,u8,Sdir_SPEC,crate::common::RW>::from_register(self,0)
2894    }
2895}
2896impl ::core::default::Default for Sdir {
2897    #[inline(always)]
2898    fn default() -> Sdir {
2899        <crate::RegValueT<Sdir_SPEC> as RegisterValue<_>>::new(16)
2900    }
2901}
2902
2903#[doc(hidden)]
2904#[derive(Copy, Clone, Eq, PartialEq)]
2905pub struct Sdadr_SPEC;
2906impl crate::sealed::RegSpec for Sdadr_SPEC {
2907    type DataType = u8;
2908}
2909
2910#[doc = "SDRAM Address Register"]
2911pub type Sdadr = crate::RegValueT<Sdadr_SPEC>;
2912
2913impl Sdadr {
2914    #[doc = "Address Multiplex Select"]
2915    #[inline(always)]
2916    pub fn mxc(
2917        self,
2918    ) -> crate::common::RegisterField<
2919        0,
2920        0x3,
2921        1,
2922        0,
2923        sdadr::Mxc,
2924        sdadr::Mxc,
2925        Sdadr_SPEC,
2926        crate::common::RW,
2927    > {
2928        crate::common::RegisterField::<
2929            0,
2930            0x3,
2931            1,
2932            0,
2933            sdadr::Mxc,
2934            sdadr::Mxc,
2935            Sdadr_SPEC,
2936            crate::common::RW,
2937        >::from_register(self, 0)
2938    }
2939}
2940impl ::core::default::Default for Sdadr {
2941    #[inline(always)]
2942    fn default() -> Sdadr {
2943        <crate::RegValueT<Sdadr_SPEC> as RegisterValue<_>>::new(0)
2944    }
2945}
2946pub mod sdadr {
2947
2948    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2949    pub struct Mxc_SPEC;
2950    pub type Mxc = crate::EnumBitfieldStruct<u8, Mxc_SPEC>;
2951    impl Mxc {
2952        #[doc = "8-bit shift"]
2953        pub const _00: Self = Self::new(0);
2954
2955        #[doc = "9-bit shift"]
2956        pub const _01: Self = Self::new(1);
2957
2958        #[doc = "10-bit shift"]
2959        pub const _10: Self = Self::new(2);
2960
2961        #[doc = "11-bit shift"]
2962        pub const _11: Self = Self::new(3);
2963    }
2964}
2965#[doc(hidden)]
2966#[derive(Copy, Clone, Eq, PartialEq)]
2967pub struct Sdtr_SPEC;
2968impl crate::sealed::RegSpec for Sdtr_SPEC {
2969    type DataType = u32;
2970}
2971
2972#[doc = "SDRAM Timing Register"]
2973pub type Sdtr = crate::RegValueT<Sdtr_SPEC>;
2974
2975impl Sdtr {
2976    #[doc = "SDRAMC Column Latency"]
2977    #[inline(always)]
2978    pub fn cl(
2979        self,
2980    ) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, Sdtr_SPEC, crate::common::RW> {
2981        crate::common::RegisterField::<0,0x7,1,0,u8,u8,Sdtr_SPEC,crate::common::RW>::from_register(self,0)
2982    }
2983
2984    #[doc = "Write Recovery Interval"]
2985    #[inline(always)]
2986    pub fn wr(
2987        self,
2988    ) -> crate::common::RegisterField<8, 0x1, 1, 0, sdtr::Wr, sdtr::Wr, Sdtr_SPEC, crate::common::RW>
2989    {
2990        crate::common::RegisterField::<8,0x1,1,0,sdtr::Wr,sdtr::Wr,Sdtr_SPEC,crate::common::RW>::from_register(self,0)
2991    }
2992
2993    #[doc = "Row Precharge Interval"]
2994    #[inline(always)]
2995    pub fn rp(
2996        self,
2997    ) -> crate::common::RegisterField<9, 0x7, 1, 0, u8, u8, Sdtr_SPEC, crate::common::RW> {
2998        crate::common::RegisterField::<9,0x7,1,0,u8,u8,Sdtr_SPEC,crate::common::RW>::from_register(self,0)
2999    }
3000
3001    #[doc = "Row Column Latency"]
3002    #[inline(always)]
3003    pub fn rcd(
3004        self,
3005    ) -> crate::common::RegisterField<
3006        12,
3007        0x3,
3008        1,
3009        0,
3010        sdtr::Rcd,
3011        sdtr::Rcd,
3012        Sdtr_SPEC,
3013        crate::common::RW,
3014    > {
3015        crate::common::RegisterField::<
3016            12,
3017            0x3,
3018            1,
3019            0,
3020            sdtr::Rcd,
3021            sdtr::Rcd,
3022            Sdtr_SPEC,
3023            crate::common::RW,
3024        >::from_register(self, 0)
3025    }
3026
3027    #[doc = "Row Active Interval"]
3028    #[inline(always)]
3029    pub fn rai(
3030        self,
3031    ) -> crate::common::RegisterField<16, 0x7, 1, 0, u8, u8, Sdtr_SPEC, crate::common::RW> {
3032        crate::common::RegisterField::<16,0x7,1,0,u8,u8,Sdtr_SPEC,crate::common::RW>::from_register(self,0)
3033    }
3034}
3035impl ::core::default::Default for Sdtr {
3036    #[inline(always)]
3037    fn default() -> Sdtr {
3038        <crate::RegValueT<Sdtr_SPEC> as RegisterValue<_>>::new(2)
3039    }
3040}
3041pub mod sdtr {
3042
3043    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3044    pub struct Wr_SPEC;
3045    pub type Wr = crate::EnumBitfieldStruct<u8, Wr_SPEC>;
3046    impl Wr {
3047        #[doc = "1 cycle"]
3048        pub const _0: Self = Self::new(0);
3049
3050        #[doc = "2 cycles"]
3051        pub const _1: Self = Self::new(1);
3052    }
3053    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3054    pub struct Rcd_SPEC;
3055    pub type Rcd = crate::EnumBitfieldStruct<u8, Rcd_SPEC>;
3056    impl Rcd {
3057        #[doc = "1 cycle"]
3058        pub const _00: Self = Self::new(0);
3059
3060        #[doc = "2 cycles"]
3061        pub const _01: Self = Self::new(1);
3062
3063        #[doc = "3 cycles"]
3064        pub const _10: Self = Self::new(2);
3065
3066        #[doc = "4 cycles"]
3067        pub const _11: Self = Self::new(3);
3068    }
3069}
3070#[doc(hidden)]
3071#[derive(Copy, Clone, Eq, PartialEq)]
3072pub struct Sdmod_SPEC;
3073impl crate::sealed::RegSpec for Sdmod_SPEC {
3074    type DataType = u16;
3075}
3076
3077#[doc = "SDRAM Mode Register"]
3078pub type Sdmod = crate::RegValueT<Sdmod_SPEC>;
3079
3080impl Sdmod {
3081    #[doc = "Mode Register Setting"]
3082    #[inline(always)]
3083    pub fn mr(
3084        self,
3085    ) -> crate::common::RegisterField<0, 0x7fff, 1, 0, u16, u16, Sdmod_SPEC, crate::common::RW>
3086    {
3087        crate::common::RegisterField::<0,0x7fff,1,0,u16,u16,Sdmod_SPEC,crate::common::RW>::from_register(self,0)
3088    }
3089}
3090impl ::core::default::Default for Sdmod {
3091    #[inline(always)]
3092    fn default() -> Sdmod {
3093        <crate::RegValueT<Sdmod_SPEC> as RegisterValue<_>>::new(0)
3094    }
3095}
3096
3097#[doc(hidden)]
3098#[derive(Copy, Clone, Eq, PartialEq)]
3099pub struct Sdsr_SPEC;
3100impl crate::sealed::RegSpec for Sdsr_SPEC {
3101    type DataType = u8;
3102}
3103
3104#[doc = "SDRAM Status Register"]
3105pub type Sdsr = crate::RegValueT<Sdsr_SPEC>;
3106
3107impl Sdsr {
3108    #[doc = "Mode Register Setting Status"]
3109    #[inline(always)]
3110    pub fn mrsst(
3111        self,
3112    ) -> crate::common::RegisterField<
3113        0,
3114        0x1,
3115        1,
3116        0,
3117        sdsr::Mrsst,
3118        sdsr::Mrsst,
3119        Sdsr_SPEC,
3120        crate::common::R,
3121    > {
3122        crate::common::RegisterField::<
3123            0,
3124            0x1,
3125            1,
3126            0,
3127            sdsr::Mrsst,
3128            sdsr::Mrsst,
3129            Sdsr_SPEC,
3130            crate::common::R,
3131        >::from_register(self, 0)
3132    }
3133
3134    #[doc = "Initialization Status"]
3135    #[inline(always)]
3136    pub fn inist(
3137        self,
3138    ) -> crate::common::RegisterField<
3139        3,
3140        0x1,
3141        1,
3142        0,
3143        sdsr::Inist,
3144        sdsr::Inist,
3145        Sdsr_SPEC,
3146        crate::common::R,
3147    > {
3148        crate::common::RegisterField::<
3149            3,
3150            0x1,
3151            1,
3152            0,
3153            sdsr::Inist,
3154            sdsr::Inist,
3155            Sdsr_SPEC,
3156            crate::common::R,
3157        >::from_register(self, 0)
3158    }
3159
3160    #[doc = "Self-Refresh Transition/Recovery Status"]
3161    #[inline(always)]
3162    pub fn srfst(
3163        self,
3164    ) -> crate::common::RegisterField<
3165        4,
3166        0x1,
3167        1,
3168        0,
3169        sdsr::Srfst,
3170        sdsr::Srfst,
3171        Sdsr_SPEC,
3172        crate::common::R,
3173    > {
3174        crate::common::RegisterField::<
3175            4,
3176            0x1,
3177            1,
3178            0,
3179            sdsr::Srfst,
3180            sdsr::Srfst,
3181            Sdsr_SPEC,
3182            crate::common::R,
3183        >::from_register(self, 0)
3184    }
3185}
3186impl ::core::default::Default for Sdsr {
3187    #[inline(always)]
3188    fn default() -> Sdsr {
3189        <crate::RegValueT<Sdsr_SPEC> as RegisterValue<_>>::new(0)
3190    }
3191}
3192pub mod sdsr {
3193
3194    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3195    pub struct Mrsst_SPEC;
3196    pub type Mrsst = crate::EnumBitfieldStruct<u8, Mrsst_SPEC>;
3197    impl Mrsst {
3198        #[doc = "Mode register setting not in progress"]
3199        pub const _0: Self = Self::new(0);
3200
3201        #[doc = "Mode register setting in progress"]
3202        pub const _1: Self = Self::new(1);
3203    }
3204    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3205    pub struct Inist_SPEC;
3206    pub type Inist = crate::EnumBitfieldStruct<u8, Inist_SPEC>;
3207    impl Inist {
3208        #[doc = "Initialization sequence not in progress"]
3209        pub const _0: Self = Self::new(0);
3210
3211        #[doc = "Initialization sequence in progress"]
3212        pub const _1: Self = Self::new(1);
3213    }
3214    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3215    pub struct Srfst_SPEC;
3216    pub type Srfst = crate::EnumBitfieldStruct<u8, Srfst_SPEC>;
3217    impl Srfst {
3218        #[doc = "Transition/recovery not in progress"]
3219        pub const _0: Self = Self::new(0);
3220
3221        #[doc = "Transition/recovery in progress"]
3222        pub const _1: Self = Self::new(1);
3223    }
3224}
3225#[doc(hidden)]
3226#[derive(Copy, Clone, Eq, PartialEq)]
3227pub struct Busoad_SPEC;
3228impl crate::sealed::RegSpec for Busoad_SPEC {
3229    type DataType = u16;
3230}
3231
3232#[doc = "BUS Operation After Detection Register"]
3233pub type Busoad = crate::RegValueT<Busoad_SPEC>;
3234
3235impl Busoad {
3236    #[doc = "Illegal address access error operation after detection"]
3237    #[inline(always)]
3238    pub fn ilerroad(
3239        self,
3240    ) -> crate::common::RegisterFieldBool<0, 1, 0, Busoad_SPEC, crate::common::RW> {
3241        crate::common::RegisterFieldBool::<0, 1, 0, Busoad_SPEC, crate::common::RW>::from_register(
3242            self, 0,
3243        )
3244    }
3245
3246    #[doc = "Slave bus error operation after detection"]
3247    #[inline(always)]
3248    pub fn slerroad(
3249        self,
3250    ) -> crate::common::RegisterFieldBool<1, 1, 0, Busoad_SPEC, crate::common::RW> {
3251        crate::common::RegisterFieldBool::<1, 1, 0, Busoad_SPEC, crate::common::RW>::from_register(
3252            self, 0,
3253        )
3254    }
3255
3256    #[doc = "Bufferable write error operation after detection"]
3257    #[inline(always)]
3258    pub fn bwerroad(
3259        self,
3260    ) -> crate::common::RegisterFieldBool<2, 1, 0, Busoad_SPEC, crate::common::RW> {
3261        crate::common::RegisterFieldBool::<2, 1, 0, Busoad_SPEC, crate::common::RW>::from_register(
3262            self, 0,
3263        )
3264    }
3265}
3266impl ::core::default::Default for Busoad {
3267    #[inline(always)]
3268    fn default() -> Busoad {
3269        <crate::RegValueT<Busoad_SPEC> as RegisterValue<_>>::new(0)
3270    }
3271}
3272
3273#[doc(hidden)]
3274#[derive(Copy, Clone, Eq, PartialEq)]
3275pub struct Busoadpt_SPEC;
3276impl crate::sealed::RegSpec for Busoadpt_SPEC {
3277    type DataType = u16;
3278}
3279
3280#[doc = "BUS Operation After Detection Protect Register"]
3281pub type Busoadpt = crate::RegValueT<Busoadpt_SPEC>;
3282
3283impl Busoadpt {
3284    #[doc = "Protection of register"]
3285    #[inline(always)]
3286    pub fn protect(
3287        self,
3288    ) -> crate::common::RegisterField<
3289        0,
3290        0x1,
3291        1,
3292        0,
3293        busoadpt::Protect,
3294        busoadpt::Protect,
3295        Busoadpt_SPEC,
3296        crate::common::RW,
3297    > {
3298        crate::common::RegisterField::<
3299            0,
3300            0x1,
3301            1,
3302            0,
3303            busoadpt::Protect,
3304            busoadpt::Protect,
3305            Busoadpt_SPEC,
3306            crate::common::RW,
3307        >::from_register(self, 0)
3308    }
3309
3310    #[doc = "Key code"]
3311    #[inline(always)]
3312    pub fn key(
3313        self,
3314    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Busoadpt_SPEC, crate::common::W> {
3315        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Busoadpt_SPEC,crate::common::W>::from_register(self,0)
3316    }
3317}
3318impl ::core::default::Default for Busoadpt {
3319    #[inline(always)]
3320    fn default() -> Busoadpt {
3321        <crate::RegValueT<Busoadpt_SPEC> as RegisterValue<_>>::new(0)
3322    }
3323}
3324pub mod busoadpt {
3325
3326    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3327    pub struct Protect_SPEC;
3328    pub type Protect = crate::EnumBitfieldStruct<u8, Protect_SPEC>;
3329    impl Protect {
3330        #[doc = "BUSOAD register writing is possible."]
3331        pub const _0: Self = Self::new(0);
3332
3333        #[doc = "BUSOAD register writing is protected. Read is possible."]
3334        pub const _1: Self = Self::new(1);
3335    }
3336}
3337#[doc(hidden)]
3338#[derive(Copy, Clone, Eq, PartialEq)]
3339pub struct Busmabt_SPEC;
3340impl crate::sealed::RegSpec for Busmabt_SPEC {
3341    type DataType = u32;
3342}
3343
3344#[doc = "Bus Master Arbitration Control Register"]
3345pub type Busmabt = crate::RegValueT<Busmabt_SPEC>;
3346
3347impl Busmabt {
3348    #[doc = "Arbitration Select for GDSSBI"]
3349    #[inline(always)]
3350    pub fn arbs(
3351        self,
3352    ) -> crate::common::RegisterField<
3353        0,
3354        0x1,
3355        1,
3356        0,
3357        busmabt::Arbs,
3358        busmabt::Arbs,
3359        Busmabt_SPEC,
3360        crate::common::RW,
3361    > {
3362        crate::common::RegisterField::<
3363            0,
3364            0x1,
3365            1,
3366            0,
3367            busmabt::Arbs,
3368            busmabt::Arbs,
3369            Busmabt_SPEC,
3370            crate::common::RW,
3371        >::from_register(self, 0)
3372    }
3373}
3374impl ::core::default::Default for Busmabt {
3375    #[inline(always)]
3376    fn default() -> Busmabt {
3377        <crate::RegValueT<Busmabt_SPEC> as RegisterValue<_>>::new(0)
3378    }
3379}
3380pub mod busmabt {
3381
3382    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3383    pub struct Arbs_SPEC;
3384    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
3385    impl Arbs {
3386        #[doc = "Fixed priority"]
3387        pub const _0: Self = Self::new(0);
3388
3389        #[doc = "Round-robin"]
3390        pub const _1: Self = Self::new(1);
3391    }
3392}
3393#[doc(hidden)]
3394#[derive(Copy, Clone, Eq, PartialEq)]
3395pub struct Bussabt1Fhbi_SPEC;
3396impl crate::sealed::RegSpec for Bussabt1Fhbi_SPEC {
3397    type DataType = u32;
3398}
3399
3400#[doc = "Bus Slave Arbitration Control Register 1(x = FHBI, S0BI, S1BI)"]
3401pub type Bussabt1Fhbi = crate::RegValueT<Bussabt1Fhbi_SPEC>;
3402
3403impl Bussabt1Fhbi {
3404    #[doc = "Arbitration Select for <slave>"]
3405    #[inline(always)]
3406    pub fn arbs(
3407        self,
3408    ) -> crate::common::RegisterField<
3409        0,
3410        0x3,
3411        1,
3412        0,
3413        bussabt1fhbi::Arbs,
3414        bussabt1fhbi::Arbs,
3415        Bussabt1Fhbi_SPEC,
3416        crate::common::RW,
3417    > {
3418        crate::common::RegisterField::<
3419            0,
3420            0x3,
3421            1,
3422            0,
3423            bussabt1fhbi::Arbs,
3424            bussabt1fhbi::Arbs,
3425            Bussabt1Fhbi_SPEC,
3426            crate::common::RW,
3427        >::from_register(self, 0)
3428    }
3429}
3430impl ::core::default::Default for Bussabt1Fhbi {
3431    #[inline(always)]
3432    fn default() -> Bussabt1Fhbi {
3433        <crate::RegValueT<Bussabt1Fhbi_SPEC> as RegisterValue<_>>::new(0)
3434    }
3435}
3436pub mod bussabt1fhbi {
3437
3438    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3439    pub struct Arbs_SPEC;
3440    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
3441    impl Arbs {
3442        #[doc = "Fixed priority"]
3443        pub const _00: Self = Self::new(0);
3444
3445        #[doc = "Setting prohibited"]
3446        pub const _01: Self = Self::new(1);
3447
3448        #[doc = "Combination of round-robin and fixed priority"]
3449        pub const _10: Self = Self::new(2);
3450
3451        #[doc = "Round-robin"]
3452        pub const _11: Self = Self::new(3);
3453    }
3454}
3455#[doc(hidden)]
3456#[derive(Copy, Clone, Eq, PartialEq)]
3457pub struct Bussabt0Flbi_SPEC;
3458impl crate::sealed::RegSpec for Bussabt0Flbi_SPEC {
3459    type DataType = u32;
3460}
3461
3462#[doc = "Bus Slave Arbitration Control Register 0"]
3463pub type Bussabt0Flbi = crate::RegValueT<Bussabt0Flbi_SPEC>;
3464
3465impl Bussabt0Flbi {
3466    #[doc = "Arbitration Select for <slave>"]
3467    #[inline(always)]
3468    pub fn arbs(
3469        self,
3470    ) -> crate::common::RegisterField<
3471        0,
3472        0x1,
3473        1,
3474        0,
3475        bussabt0flbi::Arbs,
3476        bussabt0flbi::Arbs,
3477        Bussabt0Flbi_SPEC,
3478        crate::common::RW,
3479    > {
3480        crate::common::RegisterField::<
3481            0,
3482            0x1,
3483            1,
3484            0,
3485            bussabt0flbi::Arbs,
3486            bussabt0flbi::Arbs,
3487            Bussabt0Flbi_SPEC,
3488            crate::common::RW,
3489        >::from_register(self, 0)
3490    }
3491}
3492impl ::core::default::Default for Bussabt0Flbi {
3493    #[inline(always)]
3494    fn default() -> Bussabt0Flbi {
3495        <crate::RegValueT<Bussabt0Flbi_SPEC> as RegisterValue<_>>::new(0)
3496    }
3497}
3498pub mod bussabt0flbi {
3499
3500    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3501    pub struct Arbs_SPEC;
3502    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
3503    impl Arbs {
3504        #[doc = "Fixed priority"]
3505        pub const _0: Self = Self::new(0);
3506
3507        #[doc = "Round-robin"]
3508        pub const _1: Self = Self::new(1);
3509    }
3510}
3511#[doc(hidden)]
3512#[derive(Copy, Clone, Eq, PartialEq)]
3513pub struct Bussabt1S0Bi_SPEC;
3514impl crate::sealed::RegSpec for Bussabt1S0Bi_SPEC {
3515    type DataType = u32;
3516}
3517
3518#[doc = "Bus Slave Arbitration Control Register 1(x = FHBI, S0BI, S1BI)"]
3519pub type Bussabt1S0Bi = crate::RegValueT<Bussabt1S0Bi_SPEC>;
3520
3521impl Bussabt1S0Bi {
3522    #[doc = "Arbitration Select for <slave>"]
3523    #[inline(always)]
3524    pub fn arbs(
3525        self,
3526    ) -> crate::common::RegisterField<
3527        0,
3528        0x3,
3529        1,
3530        0,
3531        bussabt1s0bi::Arbs,
3532        bussabt1s0bi::Arbs,
3533        Bussabt1S0Bi_SPEC,
3534        crate::common::RW,
3535    > {
3536        crate::common::RegisterField::<
3537            0,
3538            0x3,
3539            1,
3540            0,
3541            bussabt1s0bi::Arbs,
3542            bussabt1s0bi::Arbs,
3543            Bussabt1S0Bi_SPEC,
3544            crate::common::RW,
3545        >::from_register(self, 0)
3546    }
3547}
3548impl ::core::default::Default for Bussabt1S0Bi {
3549    #[inline(always)]
3550    fn default() -> Bussabt1S0Bi {
3551        <crate::RegValueT<Bussabt1S0Bi_SPEC> as RegisterValue<_>>::new(0)
3552    }
3553}
3554pub mod bussabt1s0bi {
3555
3556    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3557    pub struct Arbs_SPEC;
3558    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
3559    impl Arbs {
3560        #[doc = "Fixed priority"]
3561        pub const _00: Self = Self::new(0);
3562
3563        #[doc = "Setting prohibited"]
3564        pub const _01: Self = Self::new(1);
3565
3566        #[doc = "Combination of round-robin and fixed priority"]
3567        pub const _10: Self = Self::new(2);
3568
3569        #[doc = "Round-robin"]
3570        pub const _11: Self = Self::new(3);
3571    }
3572}
3573#[doc(hidden)]
3574#[derive(Copy, Clone, Eq, PartialEq)]
3575pub struct Bussabt1S1Bi_SPEC;
3576impl crate::sealed::RegSpec for Bussabt1S1Bi_SPEC {
3577    type DataType = u32;
3578}
3579
3580#[doc = "Bus Slave Arbitration Control Register 1(x = FHBI, S0BI, S1BI)"]
3581pub type Bussabt1S1Bi = crate::RegValueT<Bussabt1S1Bi_SPEC>;
3582
3583impl Bussabt1S1Bi {
3584    #[doc = "Arbitration Select for <slave>"]
3585    #[inline(always)]
3586    pub fn arbs(
3587        self,
3588    ) -> crate::common::RegisterField<
3589        0,
3590        0x3,
3591        1,
3592        0,
3593        bussabt1s1bi::Arbs,
3594        bussabt1s1bi::Arbs,
3595        Bussabt1S1Bi_SPEC,
3596        crate::common::RW,
3597    > {
3598        crate::common::RegisterField::<
3599            0,
3600            0x3,
3601            1,
3602            0,
3603            bussabt1s1bi::Arbs,
3604            bussabt1s1bi::Arbs,
3605            Bussabt1S1Bi_SPEC,
3606            crate::common::RW,
3607        >::from_register(self, 0)
3608    }
3609}
3610impl ::core::default::Default for Bussabt1S1Bi {
3611    #[inline(always)]
3612    fn default() -> Bussabt1S1Bi {
3613        <crate::RegValueT<Bussabt1S1Bi_SPEC> as RegisterValue<_>>::new(0)
3614    }
3615}
3616pub mod bussabt1s1bi {
3617
3618    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3619    pub struct Arbs_SPEC;
3620    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
3621    impl Arbs {
3622        #[doc = "Fixed priority"]
3623        pub const _00: Self = Self::new(0);
3624
3625        #[doc = "Setting prohibited"]
3626        pub const _01: Self = Self::new(1);
3627
3628        #[doc = "Combination of round-robin and fixed priority"]
3629        pub const _10: Self = Self::new(2);
3630
3631        #[doc = "Round-robin"]
3632        pub const _11: Self = Self::new(3);
3633    }
3634}
3635#[doc(hidden)]
3636#[derive(Copy, Clone, Eq, PartialEq)]
3637pub struct Bussabt0Stbysbi_SPEC;
3638impl crate::sealed::RegSpec for Bussabt0Stbysbi_SPEC {
3639    type DataType = u32;
3640}
3641
3642#[doc = "Bus Slave Arbitration Control Register 0"]
3643pub type Bussabt0Stbysbi = crate::RegValueT<Bussabt0Stbysbi_SPEC>;
3644
3645impl Bussabt0Stbysbi {
3646    #[doc = "Arbitration Select for <slave>"]
3647    #[inline(always)]
3648    pub fn arbs(
3649        self,
3650    ) -> crate::common::RegisterField<
3651        0,
3652        0x1,
3653        1,
3654        0,
3655        bussabt0stbysbi::Arbs,
3656        bussabt0stbysbi::Arbs,
3657        Bussabt0Stbysbi_SPEC,
3658        crate::common::RW,
3659    > {
3660        crate::common::RegisterField::<
3661            0,
3662            0x1,
3663            1,
3664            0,
3665            bussabt0stbysbi::Arbs,
3666            bussabt0stbysbi::Arbs,
3667            Bussabt0Stbysbi_SPEC,
3668            crate::common::RW,
3669        >::from_register(self, 0)
3670    }
3671}
3672impl ::core::default::Default for Bussabt0Stbysbi {
3673    #[inline(always)]
3674    fn default() -> Bussabt0Stbysbi {
3675        <crate::RegValueT<Bussabt0Stbysbi_SPEC> as RegisterValue<_>>::new(0)
3676    }
3677}
3678pub mod bussabt0stbysbi {
3679
3680    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3681    pub struct Arbs_SPEC;
3682    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
3683    impl Arbs {
3684        #[doc = "Fixed priority"]
3685        pub const _0: Self = Self::new(0);
3686
3687        #[doc = "Round-robin"]
3688        pub const _1: Self = Self::new(1);
3689    }
3690}
3691#[doc(hidden)]
3692#[derive(Copy, Clone, Eq, PartialEq)]
3693pub struct Bussabt0Ecbi_SPEC;
3694impl crate::sealed::RegSpec for Bussabt0Ecbi_SPEC {
3695    type DataType = u32;
3696}
3697
3698#[doc = "Bus Slave Arbitration Control Register 0"]
3699pub type Bussabt0Ecbi = crate::RegValueT<Bussabt0Ecbi_SPEC>;
3700
3701impl Bussabt0Ecbi {
3702    #[doc = "Arbitration Select for <slave>"]
3703    #[inline(always)]
3704    pub fn arbs(
3705        self,
3706    ) -> crate::common::RegisterField<
3707        0,
3708        0x1,
3709        1,
3710        0,
3711        bussabt0ecbi::Arbs,
3712        bussabt0ecbi::Arbs,
3713        Bussabt0Ecbi_SPEC,
3714        crate::common::RW,
3715    > {
3716        crate::common::RegisterField::<
3717            0,
3718            0x1,
3719            1,
3720            0,
3721            bussabt0ecbi::Arbs,
3722            bussabt0ecbi::Arbs,
3723            Bussabt0Ecbi_SPEC,
3724            crate::common::RW,
3725        >::from_register(self, 0)
3726    }
3727}
3728impl ::core::default::Default for Bussabt0Ecbi {
3729    #[inline(always)]
3730    fn default() -> Bussabt0Ecbi {
3731        <crate::RegValueT<Bussabt0Ecbi_SPEC> as RegisterValue<_>>::new(0)
3732    }
3733}
3734pub mod bussabt0ecbi {
3735
3736    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3737    pub struct Arbs_SPEC;
3738    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
3739    impl Arbs {
3740        #[doc = "Fixed priority"]
3741        pub const _0: Self = Self::new(0);
3742
3743        #[doc = "Round-robin"]
3744        pub const _1: Self = Self::new(1);
3745    }
3746}
3747#[doc(hidden)]
3748#[derive(Copy, Clone, Eq, PartialEq)]
3749pub struct Bussabt0Eobi_SPEC;
3750impl crate::sealed::RegSpec for Bussabt0Eobi_SPEC {
3751    type DataType = u32;
3752}
3753
3754#[doc = "Bus Slave Arbitration Control Register 0"]
3755pub type Bussabt0Eobi = crate::RegValueT<Bussabt0Eobi_SPEC>;
3756
3757impl Bussabt0Eobi {
3758    #[doc = "Arbitration Select for <slave>"]
3759    #[inline(always)]
3760    pub fn arbs(
3761        self,
3762    ) -> crate::common::RegisterField<
3763        0,
3764        0x1,
3765        1,
3766        0,
3767        bussabt0eobi::Arbs,
3768        bussabt0eobi::Arbs,
3769        Bussabt0Eobi_SPEC,
3770        crate::common::RW,
3771    > {
3772        crate::common::RegisterField::<
3773            0,
3774            0x1,
3775            1,
3776            0,
3777            bussabt0eobi::Arbs,
3778            bussabt0eobi::Arbs,
3779            Bussabt0Eobi_SPEC,
3780            crate::common::RW,
3781        >::from_register(self, 0)
3782    }
3783}
3784impl ::core::default::Default for Bussabt0Eobi {
3785    #[inline(always)]
3786    fn default() -> Bussabt0Eobi {
3787        <crate::RegValueT<Bussabt0Eobi_SPEC> as RegisterValue<_>>::new(0)
3788    }
3789}
3790pub mod bussabt0eobi {
3791
3792    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3793    pub struct Arbs_SPEC;
3794    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
3795    impl Arbs {
3796        #[doc = "Fixed priority"]
3797        pub const _0: Self = Self::new(0);
3798
3799        #[doc = "Round-robin"]
3800        pub const _1: Self = Self::new(1);
3801    }
3802}
3803#[doc(hidden)]
3804#[derive(Copy, Clone, Eq, PartialEq)]
3805pub struct Bussabt0Pbbi_SPEC;
3806impl crate::sealed::RegSpec for Bussabt0Pbbi_SPEC {
3807    type DataType = u32;
3808}
3809
3810#[doc = "Bus Slave Arbitration Control Register 0"]
3811pub type Bussabt0Pbbi = crate::RegValueT<Bussabt0Pbbi_SPEC>;
3812
3813impl Bussabt0Pbbi {
3814    #[doc = "Arbitration Select for <slave>"]
3815    #[inline(always)]
3816    pub fn arbs(
3817        self,
3818    ) -> crate::common::RegisterField<
3819        0,
3820        0x1,
3821        1,
3822        0,
3823        bussabt0pbbi::Arbs,
3824        bussabt0pbbi::Arbs,
3825        Bussabt0Pbbi_SPEC,
3826        crate::common::RW,
3827    > {
3828        crate::common::RegisterField::<
3829            0,
3830            0x1,
3831            1,
3832            0,
3833            bussabt0pbbi::Arbs,
3834            bussabt0pbbi::Arbs,
3835            Bussabt0Pbbi_SPEC,
3836            crate::common::RW,
3837        >::from_register(self, 0)
3838    }
3839}
3840impl ::core::default::Default for Bussabt0Pbbi {
3841    #[inline(always)]
3842    fn default() -> Bussabt0Pbbi {
3843        <crate::RegValueT<Bussabt0Pbbi_SPEC> as RegisterValue<_>>::new(0)
3844    }
3845}
3846pub mod bussabt0pbbi {
3847
3848    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3849    pub struct Arbs_SPEC;
3850    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
3851    impl Arbs {
3852        #[doc = "Fixed priority"]
3853        pub const _0: Self = Self::new(0);
3854
3855        #[doc = "Round-robin"]
3856        pub const _1: Self = Self::new(1);
3857    }
3858}
3859#[doc(hidden)]
3860#[derive(Copy, Clone, Eq, PartialEq)]
3861pub struct Bussabt0Pabi_SPEC;
3862impl crate::sealed::RegSpec for Bussabt0Pabi_SPEC {
3863    type DataType = u32;
3864}
3865
3866#[doc = "Bus Slave Arbitration Control Register 0"]
3867pub type Bussabt0Pabi = crate::RegValueT<Bussabt0Pabi_SPEC>;
3868
3869impl Bussabt0Pabi {
3870    #[doc = "Arbitration Select for <slave>"]
3871    #[inline(always)]
3872    pub fn arbs(
3873        self,
3874    ) -> crate::common::RegisterField<
3875        0,
3876        0x1,
3877        1,
3878        0,
3879        bussabt0pabi::Arbs,
3880        bussabt0pabi::Arbs,
3881        Bussabt0Pabi_SPEC,
3882        crate::common::RW,
3883    > {
3884        crate::common::RegisterField::<
3885            0,
3886            0x1,
3887            1,
3888            0,
3889            bussabt0pabi::Arbs,
3890            bussabt0pabi::Arbs,
3891            Bussabt0Pabi_SPEC,
3892            crate::common::RW,
3893        >::from_register(self, 0)
3894    }
3895}
3896impl ::core::default::Default for Bussabt0Pabi {
3897    #[inline(always)]
3898    fn default() -> Bussabt0Pabi {
3899        <crate::RegValueT<Bussabt0Pabi_SPEC> as RegisterValue<_>>::new(0)
3900    }
3901}
3902pub mod bussabt0pabi {
3903
3904    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3905    pub struct Arbs_SPEC;
3906    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
3907    impl Arbs {
3908        #[doc = "Fixed priority"]
3909        pub const _0: Self = Self::new(0);
3910
3911        #[doc = "Round-robin"]
3912        pub const _1: Self = Self::new(1);
3913    }
3914}
3915#[doc(hidden)]
3916#[derive(Copy, Clone, Eq, PartialEq)]
3917pub struct Bussabt0Pibi_SPEC;
3918impl crate::sealed::RegSpec for Bussabt0Pibi_SPEC {
3919    type DataType = u32;
3920}
3921
3922#[doc = "Bus Slave Arbitration Control Register 0"]
3923pub type Bussabt0Pibi = crate::RegValueT<Bussabt0Pibi_SPEC>;
3924
3925impl Bussabt0Pibi {
3926    #[doc = "Arbitration Select for <slave>"]
3927    #[inline(always)]
3928    pub fn arbs(
3929        self,
3930    ) -> crate::common::RegisterField<
3931        0,
3932        0x1,
3933        1,
3934        0,
3935        bussabt0pibi::Arbs,
3936        bussabt0pibi::Arbs,
3937        Bussabt0Pibi_SPEC,
3938        crate::common::RW,
3939    > {
3940        crate::common::RegisterField::<
3941            0,
3942            0x1,
3943            1,
3944            0,
3945            bussabt0pibi::Arbs,
3946            bussabt0pibi::Arbs,
3947            Bussabt0Pibi_SPEC,
3948            crate::common::RW,
3949        >::from_register(self, 0)
3950    }
3951}
3952impl ::core::default::Default for Bussabt0Pibi {
3953    #[inline(always)]
3954    fn default() -> Bussabt0Pibi {
3955        <crate::RegValueT<Bussabt0Pibi_SPEC> as RegisterValue<_>>::new(0)
3956    }
3957}
3958pub mod bussabt0pibi {
3959
3960    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3961    pub struct Arbs_SPEC;
3962    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
3963    impl Arbs {
3964        #[doc = "Fixed priority"]
3965        pub const _0: Self = Self::new(0);
3966
3967        #[doc = "Round-robin"]
3968        pub const _1: Self = Self::new(1);
3969    }
3970}
3971#[doc(hidden)]
3972#[derive(Copy, Clone, Eq, PartialEq)]
3973pub struct Bussabt0Psbi_SPEC;
3974impl crate::sealed::RegSpec for Bussabt0Psbi_SPEC {
3975    type DataType = u32;
3976}
3977
3978#[doc = "Bus Slave Arbitration Control Register 0"]
3979pub type Bussabt0Psbi = crate::RegValueT<Bussabt0Psbi_SPEC>;
3980
3981impl Bussabt0Psbi {
3982    #[doc = "Arbitration Select for <slave>"]
3983    #[inline(always)]
3984    pub fn arbs(
3985        self,
3986    ) -> crate::common::RegisterField<
3987        0,
3988        0x1,
3989        1,
3990        0,
3991        bussabt0psbi::Arbs,
3992        bussabt0psbi::Arbs,
3993        Bussabt0Psbi_SPEC,
3994        crate::common::RW,
3995    > {
3996        crate::common::RegisterField::<
3997            0,
3998            0x1,
3999            1,
4000            0,
4001            bussabt0psbi::Arbs,
4002            bussabt0psbi::Arbs,
4003            Bussabt0Psbi_SPEC,
4004            crate::common::RW,
4005        >::from_register(self, 0)
4006    }
4007}
4008impl ::core::default::Default for Bussabt0Psbi {
4009    #[inline(always)]
4010    fn default() -> Bussabt0Psbi {
4011        <crate::RegValueT<Bussabt0Psbi_SPEC> as RegisterValue<_>>::new(0)
4012    }
4013}
4014pub mod bussabt0psbi {
4015
4016    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4017    pub struct Arbs_SPEC;
4018    pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
4019    impl Arbs {
4020        #[doc = "Fixed priority"]
4021        pub const _0: Self = Self::new(0);
4022
4023        #[doc = "Round-robin"]
4024        pub const _1: Self = Self::new(1);
4025    }
4026}
4027#[doc(hidden)]
4028#[derive(Copy, Clone, Eq, PartialEq)]
4029pub struct Busdivbyp_SPEC;
4030impl crate::sealed::RegSpec for Busdivbyp_SPEC {
4031    type DataType = u32;
4032}
4033
4034#[doc = "Bus Divider Bypass Register"]
4035pub type Busdivbyp = crate::RegValueT<Busdivbyp_SPEC>;
4036
4037impl Busdivbyp {
4038    #[doc = "Divider for GDSSBI bypass enable"]
4039    #[inline(always)]
4040    pub fn gdssbpe(
4041        self,
4042    ) -> crate::common::RegisterField<
4043        3,
4044        0x1,
4045        1,
4046        0,
4047        busdivbyp::Gdssbpe,
4048        busdivbyp::Gdssbpe,
4049        Busdivbyp_SPEC,
4050        crate::common::RW,
4051    > {
4052        crate::common::RegisterField::<
4053            3,
4054            0x1,
4055            1,
4056            0,
4057            busdivbyp::Gdssbpe,
4058            busdivbyp::Gdssbpe,
4059            Busdivbyp_SPEC,
4060            crate::common::RW,
4061        >::from_register(self, 0)
4062    }
4063
4064    #[doc = "Divider for CPUSAHBI bypass enable"]
4065    #[inline(always)]
4066    pub fn cpu0sbpe(
4067        self,
4068    ) -> crate::common::RegisterField<
4069        16,
4070        0x1,
4071        1,
4072        0,
4073        busdivbyp::Cpu0Sbpe,
4074        busdivbyp::Cpu0Sbpe,
4075        Busdivbyp_SPEC,
4076        crate::common::RW,
4077    > {
4078        crate::common::RegisterField::<
4079            16,
4080            0x1,
4081            1,
4082            0,
4083            busdivbyp::Cpu0Sbpe,
4084            busdivbyp::Cpu0Sbpe,
4085            Busdivbyp_SPEC,
4086            crate::common::RW,
4087        >::from_register(self, 0)
4088    }
4089}
4090impl ::core::default::Default for Busdivbyp {
4091    #[inline(always)]
4092    fn default() -> Busdivbyp {
4093        <crate::RegValueT<Busdivbyp_SPEC> as RegisterValue<_>>::new(0)
4094    }
4095}
4096pub mod busdivbyp {
4097
4098    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4099    pub struct Gdssbpe_SPEC;
4100    pub type Gdssbpe = crate::EnumBitfieldStruct<u8, Gdssbpe_SPEC>;
4101    impl Gdssbpe {
4102        #[doc = "Disable"]
4103        pub const _0: Self = Self::new(0);
4104
4105        #[doc = "Enable"]
4106        pub const _1: Self = Self::new(1);
4107    }
4108    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4109    pub struct Cpu0Sbpe_SPEC;
4110    pub type Cpu0Sbpe = crate::EnumBitfieldStruct<u8, Cpu0Sbpe_SPEC>;
4111    impl Cpu0Sbpe {
4112        #[doc = "Disable"]
4113        pub const _0: Self = Self::new(0);
4114
4115        #[doc = "Enable"]
4116        pub const _1: Self = Self::new(1);
4117    }
4118}
4119#[doc(hidden)]
4120#[derive(Copy, Clone, Eq, PartialEq)]
4121pub struct Buserrrw_SPEC;
4122impl crate::sealed::RegSpec for Buserrrw_SPEC {
4123    type DataType = u8;
4124}
4125
4126#[doc = "BUS Error Read Write (n = 6 to 9)"]
4127pub type Buserrrw = crate::RegValueT<Buserrrw_SPEC>;
4128
4129impl Buserrrw {
4130    #[doc = "Error access Read/Write Status"]
4131    #[inline(always)]
4132    pub fn rwstat(
4133        self,
4134    ) -> crate::common::RegisterField<
4135        0,
4136        0x1,
4137        1,
4138        0,
4139        buserrrw::Rwstat,
4140        buserrrw::Rwstat,
4141        Buserrrw_SPEC,
4142        crate::common::R,
4143    > {
4144        crate::common::RegisterField::<
4145            0,
4146            0x1,
4147            1,
4148            0,
4149            buserrrw::Rwstat,
4150            buserrrw::Rwstat,
4151            Buserrrw_SPEC,
4152            crate::common::R,
4153        >::from_register(self, 0)
4154    }
4155}
4156impl ::core::default::Default for Buserrrw {
4157    #[inline(always)]
4158    fn default() -> Buserrrw {
4159        <crate::RegValueT<Buserrrw_SPEC> as RegisterValue<_>>::new(0)
4160    }
4161}
4162pub mod buserrrw {
4163
4164    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4165    pub struct Rwstat_SPEC;
4166    pub type Rwstat = crate::EnumBitfieldStruct<u8, Rwstat_SPEC>;
4167    impl Rwstat {
4168        #[doc = "Read access"]
4169        pub const _0: Self = Self::new(0);
4170
4171        #[doc = "Write access"]
4172        pub const _1: Self = Self::new(1);
4173    }
4174}
4175#[doc(hidden)]
4176#[derive(Copy, Clone, Eq, PartialEq)]
4177pub struct Buserradd_SPEC;
4178impl crate::sealed::RegSpec for Buserradd_SPEC {
4179    type DataType = u32;
4180}
4181
4182#[doc = "BUS Error Address Register (n = 6 to 9)"]
4183pub type Buserradd = crate::RegValueT<Buserradd_SPEC>;
4184
4185impl Buserradd {
4186    #[doc = "Bus Error Address"]
4187    #[inline(always)]
4188    pub fn berad(
4189        self,
4190    ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Buserradd_SPEC, crate::common::R>
4191    {
4192        crate::common::RegisterField::<
4193            0,
4194            0xffffffff,
4195            1,
4196            0,
4197            u32,
4198            u32,
4199            Buserradd_SPEC,
4200            crate::common::R,
4201        >::from_register(self, 0)
4202    }
4203}
4204impl ::core::default::Default for Buserradd {
4205    #[inline(always)]
4206    fn default() -> Buserradd {
4207        <crate::RegValueT<Buserradd_SPEC> as RegisterValue<_>>::new(0)
4208    }
4209}
4210
4211#[doc(hidden)]
4212#[derive(Copy, Clone, Eq, PartialEq)]
4213pub struct Bmsaerradd_SPEC;
4214impl crate::sealed::RegSpec for Bmsaerradd_SPEC {
4215    type DataType = u32;
4216}
4217
4218#[doc = "Bus Master Security Attribution Unit Error Address"]
4219pub type Bmsaerradd = crate::RegValueT<Bmsaerradd_SPEC>;
4220
4221impl Bmsaerradd {
4222    #[doc = "Bus Master Security Attribution Unit Error Address"]
4223    #[inline(always)]
4224    pub fn mserad(
4225        self,
4226    ) -> crate::common::RegisterField<
4227        0,
4228        0xffffffff,
4229        1,
4230        0,
4231        u32,
4232        u32,
4233        Bmsaerradd_SPEC,
4234        crate::common::R,
4235    > {
4236        crate::common::RegisterField::<
4237            0,
4238            0xffffffff,
4239            1,
4240            0,
4241            u32,
4242            u32,
4243            Bmsaerradd_SPEC,
4244            crate::common::R,
4245        >::from_register(self, 0)
4246    }
4247}
4248impl ::core::default::Default for Bmsaerradd {
4249    #[inline(always)]
4250    fn default() -> Bmsaerradd {
4251        <crate::RegValueT<Bmsaerradd_SPEC> as RegisterValue<_>>::new(0)
4252    }
4253}
4254
4255#[doc(hidden)]
4256#[derive(Copy, Clone, Eq, PartialEq)]
4257pub struct Bmsaerrrw_SPEC;
4258impl crate::sealed::RegSpec for Bmsaerrrw_SPEC {
4259    type DataType = u8;
4260}
4261
4262#[doc = "BUS Master Security Attribution Unit Error Read Write (n = 6 to 9)"]
4263pub type Bmsaerrrw = crate::RegValueT<Bmsaerrrw_SPEC>;
4264
4265impl Bmsaerrrw {
4266    #[doc = "Master Security Attribution Unit error access Read/Write Status"]
4267    #[inline(always)]
4268    pub fn msarwstat(
4269        self,
4270    ) -> crate::common::RegisterField<
4271        0,
4272        0x1,
4273        1,
4274        0,
4275        bmsaerrrw::Msarwstat,
4276        bmsaerrrw::Msarwstat,
4277        Bmsaerrrw_SPEC,
4278        crate::common::R,
4279    > {
4280        crate::common::RegisterField::<
4281            0,
4282            0x1,
4283            1,
4284            0,
4285            bmsaerrrw::Msarwstat,
4286            bmsaerrrw::Msarwstat,
4287            Bmsaerrrw_SPEC,
4288            crate::common::R,
4289        >::from_register(self, 0)
4290    }
4291}
4292impl ::core::default::Default for Bmsaerrrw {
4293    #[inline(always)]
4294    fn default() -> Bmsaerrrw {
4295        <crate::RegValueT<Bmsaerrrw_SPEC> as RegisterValue<_>>::new(0)
4296    }
4297}
4298pub mod bmsaerrrw {
4299
4300    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4301    pub struct Msarwstat_SPEC;
4302    pub type Msarwstat = crate::EnumBitfieldStruct<u8, Msarwstat_SPEC>;
4303    impl Msarwstat {
4304        #[doc = "Read access"]
4305        pub const _0: Self = Self::new(0);
4306
4307        #[doc = "Write access"]
4308        pub const _1: Self = Self::new(1);
4309    }
4310}
4311#[doc(hidden)]
4312#[derive(Copy, Clone, Eq, PartialEq)]
4313pub struct Buserrstat_SPEC;
4314impl crate::sealed::RegSpec for Buserrstat_SPEC {
4315    type DataType = u8;
4316}
4317
4318#[doc = "BUS Error Status Register"]
4319pub type Buserrstat = crate::RegValueT<Buserrstat_SPEC>;
4320
4321impl Buserrstat {
4322    #[doc = "Slave Bus Error Status"]
4323    #[inline(always)]
4324    pub fn slerrstat(
4325        self,
4326    ) -> crate::common::RegisterField<
4327        0,
4328        0x1,
4329        1,
4330        0,
4331        buserrstat::Slerrstat,
4332        buserrstat::Slerrstat,
4333        Buserrstat_SPEC,
4334        crate::common::R,
4335    > {
4336        crate::common::RegisterField::<
4337            0,
4338            0x1,
4339            1,
4340            0,
4341            buserrstat::Slerrstat,
4342            buserrstat::Slerrstat,
4343            Buserrstat_SPEC,
4344            crate::common::R,
4345        >::from_register(self, 0)
4346    }
4347
4348    #[doc = "Master MPU Error Status"]
4349    #[inline(always)]
4350    pub fn mmerrstat(
4351        self,
4352    ) -> crate::common::RegisterField<
4353        3,
4354        0x1,
4355        1,
4356        0,
4357        buserrstat::Mmerrstat,
4358        buserrstat::Mmerrstat,
4359        Buserrstat_SPEC,
4360        crate::common::R,
4361    > {
4362        crate::common::RegisterField::<
4363            3,
4364            0x1,
4365            1,
4366            0,
4367            buserrstat::Mmerrstat,
4368            buserrstat::Mmerrstat,
4369            Buserrstat_SPEC,
4370            crate::common::R,
4371        >::from_register(self, 0)
4372    }
4373
4374    #[doc = "Illegal Address Access Error Status"]
4375    #[inline(always)]
4376    pub fn ilerrstat(
4377        self,
4378    ) -> crate::common::RegisterField<
4379        4,
4380        0x1,
4381        1,
4382        0,
4383        buserrstat::Ilerrstat,
4384        buserrstat::Ilerrstat,
4385        Buserrstat_SPEC,
4386        crate::common::R,
4387    > {
4388        crate::common::RegisterField::<
4389            4,
4390            0x1,
4391            1,
4392            0,
4393            buserrstat::Ilerrstat,
4394            buserrstat::Ilerrstat,
4395            Buserrstat_SPEC,
4396            crate::common::R,
4397        >::from_register(self, 0)
4398    }
4399
4400    #[doc = "Master Security Attribution Unit Error Status"]
4401    #[inline(always)]
4402    pub fn mserrstat(
4403        self,
4404    ) -> crate::common::RegisterField<
4405        5,
4406        0x1,
4407        1,
4408        0,
4409        buserrstat::Mserrstat,
4410        buserrstat::Mserrstat,
4411        Buserrstat_SPEC,
4412        crate::common::R,
4413    > {
4414        crate::common::RegisterField::<
4415            5,
4416            0x1,
4417            1,
4418            0,
4419            buserrstat::Mserrstat,
4420            buserrstat::Mserrstat,
4421            Buserrstat_SPEC,
4422            crate::common::R,
4423        >::from_register(self, 0)
4424    }
4425}
4426impl ::core::default::Default for Buserrstat {
4427    #[inline(always)]
4428    fn default() -> Buserrstat {
4429        <crate::RegValueT<Buserrstat_SPEC> as RegisterValue<_>>::new(0)
4430    }
4431}
4432pub mod buserrstat {
4433
4434    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4435    pub struct Slerrstat_SPEC;
4436    pub type Slerrstat = crate::EnumBitfieldStruct<u8, Slerrstat_SPEC>;
4437    impl Slerrstat {
4438        #[doc = "No error occurred"]
4439        pub const _0: Self = Self::new(0);
4440
4441        #[doc = "Error occurred"]
4442        pub const _1: Self = Self::new(1);
4443    }
4444    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4445    pub struct Mmerrstat_SPEC;
4446    pub type Mmerrstat = crate::EnumBitfieldStruct<u8, Mmerrstat_SPEC>;
4447    impl Mmerrstat {
4448        #[doc = "No error occurred"]
4449        pub const _0: Self = Self::new(0);
4450
4451        #[doc = "Error occurred"]
4452        pub const _1: Self = Self::new(1);
4453    }
4454    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4455    pub struct Ilerrstat_SPEC;
4456    pub type Ilerrstat = crate::EnumBitfieldStruct<u8, Ilerrstat_SPEC>;
4457    impl Ilerrstat {
4458        #[doc = "No error occurred"]
4459        pub const _0: Self = Self::new(0);
4460
4461        #[doc = "Error occurred"]
4462        pub const _1: Self = Self::new(1);
4463    }
4464    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4465    pub struct Mserrstat_SPEC;
4466    pub type Mserrstat = crate::EnumBitfieldStruct<u8, Mserrstat_SPEC>;
4467    impl Mserrstat {
4468        #[doc = "No error occurred"]
4469        pub const _0: Self = Self::new(0);
4470
4471        #[doc = "Error occurred"]
4472        pub const _1: Self = Self::new(1);
4473    }
4474}
4475#[doc(hidden)]
4476#[derive(Copy, Clone, Eq, PartialEq)]
4477pub struct Buserrclr_SPEC;
4478impl crate::sealed::RegSpec for Buserrclr_SPEC {
4479    type DataType = u8;
4480}
4481
4482#[doc = "BUS Error Clear Register"]
4483pub type Buserrclr = crate::RegValueT<Buserrclr_SPEC>;
4484
4485impl Buserrclr {
4486    #[doc = "Slave Bus Error Clear"]
4487    #[inline(always)]
4488    pub fn slerrclr(
4489        self,
4490    ) -> crate::common::RegisterFieldBool<0, 1, 0, Buserrclr_SPEC, crate::common::RW> {
4491        crate::common::RegisterFieldBool::<0,1,0,Buserrclr_SPEC,crate::common::RW>::from_register(self,0)
4492    }
4493
4494    #[doc = "Master MPU Error Clear"]
4495    #[inline(always)]
4496    pub fn mmerrclr(
4497        self,
4498    ) -> crate::common::RegisterFieldBool<3, 1, 0, Buserrclr_SPEC, crate::common::RW> {
4499        crate::common::RegisterFieldBool::<3,1,0,Buserrclr_SPEC,crate::common::RW>::from_register(self,0)
4500    }
4501
4502    #[doc = "Illegal Address Access Error Clear"]
4503    #[inline(always)]
4504    pub fn ilerrclr(
4505        self,
4506    ) -> crate::common::RegisterFieldBool<4, 1, 0, Buserrclr_SPEC, crate::common::RW> {
4507        crate::common::RegisterFieldBool::<4,1,0,Buserrclr_SPEC,crate::common::RW>::from_register(self,0)
4508    }
4509
4510    #[doc = "Master Security Attribution Unit Error Clear"]
4511    #[inline(always)]
4512    pub fn mserrclr(
4513        self,
4514    ) -> crate::common::RegisterFieldBool<5, 1, 0, Buserrclr_SPEC, crate::common::RW> {
4515        crate::common::RegisterFieldBool::<5,1,0,Buserrclr_SPEC,crate::common::RW>::from_register(self,0)
4516    }
4517}
4518impl ::core::default::Default for Buserrclr {
4519    #[inline(always)]
4520    fn default() -> Buserrclr {
4521        <crate::RegValueT<Buserrclr_SPEC> as RegisterValue<_>>::new(0)
4522    }
4523}
4524
4525#[doc(hidden)]
4526#[derive(Copy, Clone, Eq, PartialEq)]
4527pub struct Mbwerrstat_SPEC;
4528impl crate::sealed::RegSpec for Mbwerrstat_SPEC {
4529    type DataType = u32;
4530}
4531
4532#[doc = "Master Bufferable Write Error Status Register"]
4533pub type Mbwerrstat = crate::RegValueT<Mbwerrstat_SPEC>;
4534
4535impl Mbwerrstat {
4536    #[doc = "Master Bufferable Write Error"]
4537    #[inline(always)]
4538    pub fn mbwerr0(
4539        self,
4540    ) -> crate::common::RegisterField<
4541        0,
4542        0x1,
4543        1,
4544        0,
4545        mbwerrstat::Mbwerr0,
4546        mbwerrstat::Mbwerr0,
4547        Mbwerrstat_SPEC,
4548        crate::common::R,
4549    > {
4550        crate::common::RegisterField::<
4551            0,
4552            0x1,
4553            1,
4554            0,
4555            mbwerrstat::Mbwerr0,
4556            mbwerrstat::Mbwerr0,
4557            Mbwerrstat_SPEC,
4558            crate::common::R,
4559        >::from_register(self, 0)
4560    }
4561
4562    #[doc = "Master Bufferable Write Error"]
4563    #[inline(always)]
4564    pub fn mbwerr1(
4565        self,
4566    ) -> crate::common::RegisterField<
4567        1,
4568        0x1,
4569        1,
4570        0,
4571        mbwerrstat::Mbwerr1,
4572        mbwerrstat::Mbwerr1,
4573        Mbwerrstat_SPEC,
4574        crate::common::R,
4575    > {
4576        crate::common::RegisterField::<
4577            1,
4578            0x1,
4579            1,
4580            0,
4581            mbwerrstat::Mbwerr1,
4582            mbwerrstat::Mbwerr1,
4583            Mbwerrstat_SPEC,
4584            crate::common::R,
4585        >::from_register(self, 0)
4586    }
4587
4588    #[doc = "Master Bufferable Write Error"]
4589    #[inline(always)]
4590    pub fn mbwerr8(
4591        self,
4592    ) -> crate::common::RegisterField<
4593        8,
4594        0x1,
4595        1,
4596        0,
4597        mbwerrstat::Mbwerr8,
4598        mbwerrstat::Mbwerr8,
4599        Mbwerrstat_SPEC,
4600        crate::common::R,
4601    > {
4602        crate::common::RegisterField::<
4603            8,
4604            0x1,
4605            1,
4606            0,
4607            mbwerrstat::Mbwerr8,
4608            mbwerrstat::Mbwerr8,
4609            Mbwerrstat_SPEC,
4610            crate::common::R,
4611        >::from_register(self, 0)
4612    }
4613
4614    #[doc = "Master Bufferable Write Error"]
4615    #[inline(always)]
4616    pub fn mbwerr17(
4617        self,
4618    ) -> crate::common::RegisterField<
4619        17,
4620        0x1,
4621        1,
4622        0,
4623        mbwerrstat::Mbwerr17,
4624        mbwerrstat::Mbwerr17,
4625        Mbwerrstat_SPEC,
4626        crate::common::R,
4627    > {
4628        crate::common::RegisterField::<
4629            17,
4630            0x1,
4631            1,
4632            0,
4633            mbwerrstat::Mbwerr17,
4634            mbwerrstat::Mbwerr17,
4635            Mbwerrstat_SPEC,
4636            crate::common::R,
4637        >::from_register(self, 0)
4638    }
4639
4640    #[doc = "Master Bufferable Write Error"]
4641    #[inline(always)]
4642    pub fn mbwerr18(
4643        self,
4644    ) -> crate::common::RegisterField<
4645        18,
4646        0x1,
4647        1,
4648        0,
4649        mbwerrstat::Mbwerr18,
4650        mbwerrstat::Mbwerr18,
4651        Mbwerrstat_SPEC,
4652        crate::common::R,
4653    > {
4654        crate::common::RegisterField::<
4655            18,
4656            0x1,
4657            1,
4658            0,
4659            mbwerrstat::Mbwerr18,
4660            mbwerrstat::Mbwerr18,
4661            Mbwerrstat_SPEC,
4662            crate::common::R,
4663        >::from_register(self, 0)
4664    }
4665
4666    #[doc = "Master Bufferable Write Error"]
4667    #[inline(always)]
4668    pub fn mbwerr19(
4669        self,
4670    ) -> crate::common::RegisterField<
4671        19,
4672        0x1,
4673        1,
4674        0,
4675        mbwerrstat::Mbwerr19,
4676        mbwerrstat::Mbwerr19,
4677        Mbwerrstat_SPEC,
4678        crate::common::R,
4679    > {
4680        crate::common::RegisterField::<
4681            19,
4682            0x1,
4683            1,
4684            0,
4685            mbwerrstat::Mbwerr19,
4686            mbwerrstat::Mbwerr19,
4687            Mbwerrstat_SPEC,
4688            crate::common::R,
4689        >::from_register(self, 0)
4690    }
4691
4692    #[doc = "Master Bufferable Write Error"]
4693    #[inline(always)]
4694    pub fn mbwerr20(
4695        self,
4696    ) -> crate::common::RegisterField<
4697        20,
4698        0x1,
4699        1,
4700        0,
4701        mbwerrstat::Mbwerr20,
4702        mbwerrstat::Mbwerr20,
4703        Mbwerrstat_SPEC,
4704        crate::common::R,
4705    > {
4706        crate::common::RegisterField::<
4707            20,
4708            0x1,
4709            1,
4710            0,
4711            mbwerrstat::Mbwerr20,
4712            mbwerrstat::Mbwerr20,
4713            Mbwerrstat_SPEC,
4714            crate::common::R,
4715        >::from_register(self, 0)
4716    }
4717
4718    #[doc = "Master Bufferable Write Error"]
4719    #[inline(always)]
4720    pub fn mbwerr23(
4721        self,
4722    ) -> crate::common::RegisterField<
4723        23,
4724        0x1,
4725        1,
4726        0,
4727        mbwerrstat::Mbwerr23,
4728        mbwerrstat::Mbwerr23,
4729        Mbwerrstat_SPEC,
4730        crate::common::R,
4731    > {
4732        crate::common::RegisterField::<
4733            23,
4734            0x1,
4735            1,
4736            0,
4737            mbwerrstat::Mbwerr23,
4738            mbwerrstat::Mbwerr23,
4739            Mbwerrstat_SPEC,
4740            crate::common::R,
4741        >::from_register(self, 0)
4742    }
4743}
4744impl ::core::default::Default for Mbwerrstat {
4745    #[inline(always)]
4746    fn default() -> Mbwerrstat {
4747        <crate::RegValueT<Mbwerrstat_SPEC> as RegisterValue<_>>::new(0)
4748    }
4749}
4750pub mod mbwerrstat {
4751
4752    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4753    pub struct Mbwerr0_SPEC;
4754    pub type Mbwerr0 = crate::EnumBitfieldStruct<u8, Mbwerr0_SPEC>;
4755    impl Mbwerr0 {
4756        #[doc = "No bufferable write error in Master #0"]
4757        pub const _0: Self = Self::new(0);
4758
4759        #[doc = "Bufferable write error occurs in Master #0"]
4760        pub const _1: Self = Self::new(1);
4761    }
4762    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4763    pub struct Mbwerr1_SPEC;
4764    pub type Mbwerr1 = crate::EnumBitfieldStruct<u8, Mbwerr1_SPEC>;
4765    impl Mbwerr1 {
4766        #[doc = "No bufferable write error in Master #1"]
4767        pub const _0: Self = Self::new(0);
4768
4769        #[doc = "Bufferable write error occurs in Master #1"]
4770        pub const _1: Self = Self::new(1);
4771    }
4772    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4773    pub struct Mbwerr8_SPEC;
4774    pub type Mbwerr8 = crate::EnumBitfieldStruct<u8, Mbwerr8_SPEC>;
4775    impl Mbwerr8 {
4776        #[doc = "No bufferable write error in Master #8"]
4777        pub const _0: Self = Self::new(0);
4778
4779        #[doc = "Bufferable write error occurs in Master #8"]
4780        pub const _1: Self = Self::new(1);
4781    }
4782    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4783    pub struct Mbwerr17_SPEC;
4784    pub type Mbwerr17 = crate::EnumBitfieldStruct<u8, Mbwerr17_SPEC>;
4785    impl Mbwerr17 {
4786        #[doc = "No bufferable write error in Master #17"]
4787        pub const _0: Self = Self::new(0);
4788
4789        #[doc = "Bufferable write error occurs in Master #17"]
4790        pub const _1: Self = Self::new(1);
4791    }
4792    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4793    pub struct Mbwerr18_SPEC;
4794    pub type Mbwerr18 = crate::EnumBitfieldStruct<u8, Mbwerr18_SPEC>;
4795    impl Mbwerr18 {
4796        #[doc = "No bufferable write error in Master #18"]
4797        pub const _0: Self = Self::new(0);
4798
4799        #[doc = "Bufferable write error occurs in Master #18"]
4800        pub const _1: Self = Self::new(1);
4801    }
4802    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4803    pub struct Mbwerr19_SPEC;
4804    pub type Mbwerr19 = crate::EnumBitfieldStruct<u8, Mbwerr19_SPEC>;
4805    impl Mbwerr19 {
4806        #[doc = "No bufferable write error in Master #19"]
4807        pub const _0: Self = Self::new(0);
4808
4809        #[doc = "Bufferable write error occurs in Master #19"]
4810        pub const _1: Self = Self::new(1);
4811    }
4812    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4813    pub struct Mbwerr20_SPEC;
4814    pub type Mbwerr20 = crate::EnumBitfieldStruct<u8, Mbwerr20_SPEC>;
4815    impl Mbwerr20 {
4816        #[doc = "No bufferable write error in Master #20"]
4817        pub const _0: Self = Self::new(0);
4818
4819        #[doc = "Bufferable write error occurs in Master #20"]
4820        pub const _1: Self = Self::new(1);
4821    }
4822    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4823    pub struct Mbwerr23_SPEC;
4824    pub type Mbwerr23 = crate::EnumBitfieldStruct<u8, Mbwerr23_SPEC>;
4825    impl Mbwerr23 {
4826        #[doc = "No bufferable write error in Master #23"]
4827        pub const _0: Self = Self::new(0);
4828
4829        #[doc = "Bufferable write error occurs in Master #23"]
4830        pub const _1: Self = Self::new(1);
4831    }
4832}
4833#[doc(hidden)]
4834#[derive(Copy, Clone, Eq, PartialEq)]
4835pub struct Mbwerrclr_SPEC;
4836impl crate::sealed::RegSpec for Mbwerrclr_SPEC {
4837    type DataType = u32;
4838}
4839
4840#[doc = "Master Bufferable Write Error Clear Register"]
4841pub type Mbwerrclr = crate::RegValueT<Mbwerrclr_SPEC>;
4842
4843impl Mbwerrclr {
4844    #[doc = "Master Bufferable Write Error Clear"]
4845    #[inline(always)]
4846    pub fn mbweclr0(
4847        self,
4848    ) -> crate::common::RegisterFieldBool<0, 1, 0, Mbwerrclr_SPEC, crate::common::RW> {
4849        crate::common::RegisterFieldBool::<0,1,0,Mbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
4850    }
4851
4852    #[doc = "Master Bufferable Write Error Clear"]
4853    #[inline(always)]
4854    pub fn mbweclr1(
4855        self,
4856    ) -> crate::common::RegisterFieldBool<1, 1, 0, Mbwerrclr_SPEC, crate::common::RW> {
4857        crate::common::RegisterFieldBool::<1,1,0,Mbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
4858    }
4859
4860    #[doc = "Master Bufferable Write Error Clear"]
4861    #[inline(always)]
4862    pub fn mbweclr8(
4863        self,
4864    ) -> crate::common::RegisterFieldBool<8, 1, 0, Mbwerrclr_SPEC, crate::common::RW> {
4865        crate::common::RegisterFieldBool::<8,1,0,Mbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
4866    }
4867
4868    #[doc = "Master Bufferable Write Error Clear"]
4869    #[inline(always)]
4870    pub fn mbweclr17(
4871        self,
4872    ) -> crate::common::RegisterFieldBool<17, 1, 0, Mbwerrclr_SPEC, crate::common::RW> {
4873        crate::common::RegisterFieldBool::<17,1,0,Mbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
4874    }
4875
4876    #[doc = "Master Bufferable Write Error Clear"]
4877    #[inline(always)]
4878    pub fn mbweclr18(
4879        self,
4880    ) -> crate::common::RegisterFieldBool<18, 1, 0, Mbwerrclr_SPEC, crate::common::RW> {
4881        crate::common::RegisterFieldBool::<18,1,0,Mbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
4882    }
4883
4884    #[doc = "Master Bufferable Write Error Clear"]
4885    #[inline(always)]
4886    pub fn mbweclr19(
4887        self,
4888    ) -> crate::common::RegisterFieldBool<19, 1, 0, Mbwerrclr_SPEC, crate::common::RW> {
4889        crate::common::RegisterFieldBool::<19,1,0,Mbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
4890    }
4891
4892    #[doc = "Master Bufferable Write Error Clear"]
4893    #[inline(always)]
4894    pub fn mbweclr20(
4895        self,
4896    ) -> crate::common::RegisterFieldBool<20, 1, 0, Mbwerrclr_SPEC, crate::common::RW> {
4897        crate::common::RegisterFieldBool::<20,1,0,Mbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
4898    }
4899
4900    #[doc = "Master Bufferable Write Error Clear"]
4901    #[inline(always)]
4902    pub fn mbweclr23(
4903        self,
4904    ) -> crate::common::RegisterFieldBool<23, 1, 0, Mbwerrclr_SPEC, crate::common::RW> {
4905        crate::common::RegisterFieldBool::<23,1,0,Mbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
4906    }
4907}
4908impl ::core::default::Default for Mbwerrclr {
4909    #[inline(always)]
4910    fn default() -> Mbwerrclr {
4911        <crate::RegValueT<Mbwerrclr_SPEC> as RegisterValue<_>>::new(0)
4912    }
4913}
4914
4915#[doc(hidden)]
4916#[derive(Copy, Clone, Eq, PartialEq)]
4917pub struct Sbwerrstat_SPEC;
4918impl crate::sealed::RegSpec for Sbwerrstat_SPEC {
4919    type DataType = u32;
4920}
4921
4922#[doc = "Slave Bufferable Write Error Status Register"]
4923pub type Sbwerrstat = crate::RegValueT<Sbwerrstat_SPEC>;
4924
4925impl Sbwerrstat {
4926    #[doc = "Slave Bufferable Write Error"]
4927    #[inline(always)]
4928    pub fn sbwerr0(
4929        self,
4930    ) -> crate::common::RegisterField<
4931        0,
4932        0x1,
4933        1,
4934        0,
4935        sbwerrstat::Sbwerr0,
4936        sbwerrstat::Sbwerr0,
4937        Sbwerrstat_SPEC,
4938        crate::common::R,
4939    > {
4940        crate::common::RegisterField::<
4941            0,
4942            0x1,
4943            1,
4944            0,
4945            sbwerrstat::Sbwerr0,
4946            sbwerrstat::Sbwerr0,
4947            Sbwerrstat_SPEC,
4948            crate::common::R,
4949        >::from_register(self, 0)
4950    }
4951
4952    #[doc = "Slave Bufferable Write Error"]
4953    #[inline(always)]
4954    pub fn sbwerr1(
4955        self,
4956    ) -> crate::common::RegisterField<
4957        1,
4958        0x1,
4959        1,
4960        0,
4961        sbwerrstat::Sbwerr1,
4962        sbwerrstat::Sbwerr1,
4963        Sbwerrstat_SPEC,
4964        crate::common::R,
4965    > {
4966        crate::common::RegisterField::<
4967            1,
4968            0x1,
4969            1,
4970            0,
4971            sbwerrstat::Sbwerr1,
4972            sbwerrstat::Sbwerr1,
4973            Sbwerrstat_SPEC,
4974            crate::common::R,
4975        >::from_register(self, 0)
4976    }
4977
4978    #[doc = "Slave Bufferable Write Error"]
4979    #[inline(always)]
4980    pub fn sbwerr2(
4981        self,
4982    ) -> crate::common::RegisterField<
4983        2,
4984        0x1,
4985        1,
4986        0,
4987        sbwerrstat::Sbwerr2,
4988        sbwerrstat::Sbwerr2,
4989        Sbwerrstat_SPEC,
4990        crate::common::R,
4991    > {
4992        crate::common::RegisterField::<
4993            2,
4994            0x1,
4995            1,
4996            0,
4997            sbwerrstat::Sbwerr2,
4998            sbwerrstat::Sbwerr2,
4999            Sbwerrstat_SPEC,
5000            crate::common::R,
5001        >::from_register(self, 0)
5002    }
5003
5004    #[doc = "Slave Bufferable Write Error"]
5005    #[inline(always)]
5006    pub fn sbwerr3(
5007        self,
5008    ) -> crate::common::RegisterField<
5009        3,
5010        0x1,
5011        1,
5012        0,
5013        sbwerrstat::Sbwerr3,
5014        sbwerrstat::Sbwerr3,
5015        Sbwerrstat_SPEC,
5016        crate::common::R,
5017    > {
5018        crate::common::RegisterField::<
5019            3,
5020            0x1,
5021            1,
5022            0,
5023            sbwerrstat::Sbwerr3,
5024            sbwerrstat::Sbwerr3,
5025            Sbwerrstat_SPEC,
5026            crate::common::R,
5027        >::from_register(self, 0)
5028    }
5029
5030    #[doc = "Slave Bufferable Write Error"]
5031    #[inline(always)]
5032    pub fn sbwerr4(
5033        self,
5034    ) -> crate::common::RegisterField<
5035        4,
5036        0x1,
5037        1,
5038        0,
5039        sbwerrstat::Sbwerr4,
5040        sbwerrstat::Sbwerr4,
5041        Sbwerrstat_SPEC,
5042        crate::common::R,
5043    > {
5044        crate::common::RegisterField::<
5045            4,
5046            0x1,
5047            1,
5048            0,
5049            sbwerrstat::Sbwerr4,
5050            sbwerrstat::Sbwerr4,
5051            Sbwerrstat_SPEC,
5052            crate::common::R,
5053        >::from_register(self, 0)
5054    }
5055
5056    #[doc = "Slave Bufferable Write Error"]
5057    #[inline(always)]
5058    pub fn sbwerr5(
5059        self,
5060    ) -> crate::common::RegisterField<
5061        5,
5062        0x1,
5063        1,
5064        0,
5065        sbwerrstat::Sbwerr5,
5066        sbwerrstat::Sbwerr5,
5067        Sbwerrstat_SPEC,
5068        crate::common::R,
5069    > {
5070        crate::common::RegisterField::<
5071            5,
5072            0x1,
5073            1,
5074            0,
5075            sbwerrstat::Sbwerr5,
5076            sbwerrstat::Sbwerr5,
5077            Sbwerrstat_SPEC,
5078            crate::common::R,
5079        >::from_register(self, 0)
5080    }
5081
5082    #[doc = "Slave Bufferable Write Error"]
5083    #[inline(always)]
5084    pub fn sbwerr6(
5085        self,
5086    ) -> crate::common::RegisterField<
5087        6,
5088        0x1,
5089        1,
5090        0,
5091        sbwerrstat::Sbwerr6,
5092        sbwerrstat::Sbwerr6,
5093        Sbwerrstat_SPEC,
5094        crate::common::R,
5095    > {
5096        crate::common::RegisterField::<
5097            6,
5098            0x1,
5099            1,
5100            0,
5101            sbwerrstat::Sbwerr6,
5102            sbwerrstat::Sbwerr6,
5103            Sbwerrstat_SPEC,
5104            crate::common::R,
5105        >::from_register(self, 0)
5106    }
5107
5108    #[doc = "Slave Bufferable Write Error"]
5109    #[inline(always)]
5110    pub fn sbwerr7(
5111        self,
5112    ) -> crate::common::RegisterField<
5113        7,
5114        0x1,
5115        1,
5116        0,
5117        sbwerrstat::Sbwerr7,
5118        sbwerrstat::Sbwerr7,
5119        Sbwerrstat_SPEC,
5120        crate::common::R,
5121    > {
5122        crate::common::RegisterField::<
5123            7,
5124            0x1,
5125            1,
5126            0,
5127            sbwerrstat::Sbwerr7,
5128            sbwerrstat::Sbwerr7,
5129            Sbwerrstat_SPEC,
5130            crate::common::R,
5131        >::from_register(self, 0)
5132    }
5133
5134    #[doc = "Slave Bufferable Write Error"]
5135    #[inline(always)]
5136    pub fn sbwerr8(
5137        self,
5138    ) -> crate::common::RegisterField<
5139        8,
5140        0x1,
5141        1,
5142        0,
5143        sbwerrstat::Sbwerr8,
5144        sbwerrstat::Sbwerr8,
5145        Sbwerrstat_SPEC,
5146        crate::common::R,
5147    > {
5148        crate::common::RegisterField::<
5149            8,
5150            0x1,
5151            1,
5152            0,
5153            sbwerrstat::Sbwerr8,
5154            sbwerrstat::Sbwerr8,
5155            Sbwerrstat_SPEC,
5156            crate::common::R,
5157        >::from_register(self, 0)
5158    }
5159
5160    #[doc = "Slave Bufferable Write Error"]
5161    #[inline(always)]
5162    pub fn sbwerr9(
5163        self,
5164    ) -> crate::common::RegisterField<
5165        9,
5166        0x1,
5167        1,
5168        0,
5169        sbwerrstat::Sbwerr9,
5170        sbwerrstat::Sbwerr9,
5171        Sbwerrstat_SPEC,
5172        crate::common::R,
5173    > {
5174        crate::common::RegisterField::<
5175            9,
5176            0x1,
5177            1,
5178            0,
5179            sbwerrstat::Sbwerr9,
5180            sbwerrstat::Sbwerr9,
5181            Sbwerrstat_SPEC,
5182            crate::common::R,
5183        >::from_register(self, 0)
5184    }
5185
5186    #[doc = "Slave Bufferable Write Error"]
5187    #[inline(always)]
5188    pub fn sbwerr10(
5189        self,
5190    ) -> crate::common::RegisterField<
5191        10,
5192        0x1,
5193        1,
5194        0,
5195        sbwerrstat::Sbwerr10,
5196        sbwerrstat::Sbwerr10,
5197        Sbwerrstat_SPEC,
5198        crate::common::R,
5199    > {
5200        crate::common::RegisterField::<
5201            10,
5202            0x1,
5203            1,
5204            0,
5205            sbwerrstat::Sbwerr10,
5206            sbwerrstat::Sbwerr10,
5207            Sbwerrstat_SPEC,
5208            crate::common::R,
5209        >::from_register(self, 0)
5210    }
5211
5212    #[doc = "Slave Bufferable Write Error"]
5213    #[inline(always)]
5214    pub fn sbwerr11(
5215        self,
5216    ) -> crate::common::RegisterField<
5217        11,
5218        0x1,
5219        1,
5220        0,
5221        sbwerrstat::Sbwerr11,
5222        sbwerrstat::Sbwerr11,
5223        Sbwerrstat_SPEC,
5224        crate::common::R,
5225    > {
5226        crate::common::RegisterField::<
5227            11,
5228            0x1,
5229            1,
5230            0,
5231            sbwerrstat::Sbwerr11,
5232            sbwerrstat::Sbwerr11,
5233            Sbwerrstat_SPEC,
5234            crate::common::R,
5235        >::from_register(self, 0)
5236    }
5237
5238    #[doc = "Slave Bufferable Write Error"]
5239    #[inline(always)]
5240    pub fn sbwerr12(
5241        self,
5242    ) -> crate::common::RegisterField<
5243        12,
5244        0x1,
5245        1,
5246        0,
5247        sbwerrstat::Sbwerr12,
5248        sbwerrstat::Sbwerr12,
5249        Sbwerrstat_SPEC,
5250        crate::common::R,
5251    > {
5252        crate::common::RegisterField::<
5253            12,
5254            0x1,
5255            1,
5256            0,
5257            sbwerrstat::Sbwerr12,
5258            sbwerrstat::Sbwerr12,
5259            Sbwerrstat_SPEC,
5260            crate::common::R,
5261        >::from_register(self, 0)
5262    }
5263}
5264impl ::core::default::Default for Sbwerrstat {
5265    #[inline(always)]
5266    fn default() -> Sbwerrstat {
5267        <crate::RegValueT<Sbwerrstat_SPEC> as RegisterValue<_>>::new(0)
5268    }
5269}
5270pub mod sbwerrstat {
5271
5272    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5273    pub struct Sbwerr0_SPEC;
5274    pub type Sbwerr0 = crate::EnumBitfieldStruct<u8, Sbwerr0_SPEC>;
5275    impl Sbwerr0 {
5276        #[doc = "No bufferable write error in Slave #0"]
5277        pub const _0: Self = Self::new(0);
5278
5279        #[doc = "Bufferable write error occurs in Slave #0"]
5280        pub const _1: Self = Self::new(1);
5281    }
5282    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5283    pub struct Sbwerr1_SPEC;
5284    pub type Sbwerr1 = crate::EnumBitfieldStruct<u8, Sbwerr1_SPEC>;
5285    impl Sbwerr1 {
5286        #[doc = "No bufferable write error in Slave #1"]
5287        pub const _0: Self = Self::new(0);
5288
5289        #[doc = "Bufferable write error occurs in Slave #1"]
5290        pub const _1: Self = Self::new(1);
5291    }
5292    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5293    pub struct Sbwerr2_SPEC;
5294    pub type Sbwerr2 = crate::EnumBitfieldStruct<u8, Sbwerr2_SPEC>;
5295    impl Sbwerr2 {
5296        #[doc = "No bufferable write error in Slave #2"]
5297        pub const _0: Self = Self::new(0);
5298
5299        #[doc = "Bufferable write error occurs in Slave #2"]
5300        pub const _1: Self = Self::new(1);
5301    }
5302    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5303    pub struct Sbwerr3_SPEC;
5304    pub type Sbwerr3 = crate::EnumBitfieldStruct<u8, Sbwerr3_SPEC>;
5305    impl Sbwerr3 {
5306        #[doc = "No bufferable write error in Slave #3"]
5307        pub const _0: Self = Self::new(0);
5308
5309        #[doc = "Bufferable write error occurs in Slave #3"]
5310        pub const _1: Self = Self::new(1);
5311    }
5312    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5313    pub struct Sbwerr4_SPEC;
5314    pub type Sbwerr4 = crate::EnumBitfieldStruct<u8, Sbwerr4_SPEC>;
5315    impl Sbwerr4 {
5316        #[doc = "No bufferable write error in Slave #4"]
5317        pub const _0: Self = Self::new(0);
5318
5319        #[doc = "Bufferable write error occurs in Slave #4"]
5320        pub const _1: Self = Self::new(1);
5321    }
5322    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5323    pub struct Sbwerr5_SPEC;
5324    pub type Sbwerr5 = crate::EnumBitfieldStruct<u8, Sbwerr5_SPEC>;
5325    impl Sbwerr5 {
5326        #[doc = "No bufferable write error in Slave #5"]
5327        pub const _0: Self = Self::new(0);
5328
5329        #[doc = "Bufferable write error occurs in Slave #5"]
5330        pub const _1: Self = Self::new(1);
5331    }
5332    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5333    pub struct Sbwerr6_SPEC;
5334    pub type Sbwerr6 = crate::EnumBitfieldStruct<u8, Sbwerr6_SPEC>;
5335    impl Sbwerr6 {
5336        #[doc = "No bufferable write error in Slave #6"]
5337        pub const _0: Self = Self::new(0);
5338
5339        #[doc = "Bufferable write error occurs in Slave #6"]
5340        pub const _1: Self = Self::new(1);
5341    }
5342    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5343    pub struct Sbwerr7_SPEC;
5344    pub type Sbwerr7 = crate::EnumBitfieldStruct<u8, Sbwerr7_SPEC>;
5345    impl Sbwerr7 {
5346        #[doc = "No bufferable write error in Slave #7"]
5347        pub const _0: Self = Self::new(0);
5348
5349        #[doc = "Bufferable write error occurs in Slave #7"]
5350        pub const _1: Self = Self::new(1);
5351    }
5352    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5353    pub struct Sbwerr8_SPEC;
5354    pub type Sbwerr8 = crate::EnumBitfieldStruct<u8, Sbwerr8_SPEC>;
5355    impl Sbwerr8 {
5356        #[doc = "No bufferable write error in Slave #8"]
5357        pub const _0: Self = Self::new(0);
5358
5359        #[doc = "Bufferable write error occurs in Slave #8"]
5360        pub const _1: Self = Self::new(1);
5361    }
5362    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5363    pub struct Sbwerr9_SPEC;
5364    pub type Sbwerr9 = crate::EnumBitfieldStruct<u8, Sbwerr9_SPEC>;
5365    impl Sbwerr9 {
5366        #[doc = "No bufferable write error in Slave #9"]
5367        pub const _0: Self = Self::new(0);
5368
5369        #[doc = "Bufferable write error occurs in Slave #9"]
5370        pub const _1: Self = Self::new(1);
5371    }
5372    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5373    pub struct Sbwerr10_SPEC;
5374    pub type Sbwerr10 = crate::EnumBitfieldStruct<u8, Sbwerr10_SPEC>;
5375    impl Sbwerr10 {
5376        #[doc = "No bufferable write error in Slave #10"]
5377        pub const _0: Self = Self::new(0);
5378
5379        #[doc = "Bufferable write error occurs in Slave #10"]
5380        pub const _1: Self = Self::new(1);
5381    }
5382    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5383    pub struct Sbwerr11_SPEC;
5384    pub type Sbwerr11 = crate::EnumBitfieldStruct<u8, Sbwerr11_SPEC>;
5385    impl Sbwerr11 {
5386        #[doc = "No bufferable write error in Slave #11"]
5387        pub const _0: Self = Self::new(0);
5388
5389        #[doc = "Bufferable write error occurs in Slave #11"]
5390        pub const _1: Self = Self::new(1);
5391    }
5392    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5393    pub struct Sbwerr12_SPEC;
5394    pub type Sbwerr12 = crate::EnumBitfieldStruct<u8, Sbwerr12_SPEC>;
5395    impl Sbwerr12 {
5396        #[doc = "No bufferable write error in Slave #12"]
5397        pub const _0: Self = Self::new(0);
5398
5399        #[doc = "Bufferable write error occurs in Slave #12"]
5400        pub const _1: Self = Self::new(1);
5401    }
5402}
5403#[doc(hidden)]
5404#[derive(Copy, Clone, Eq, PartialEq)]
5405pub struct Sbwerrclr_SPEC;
5406impl crate::sealed::RegSpec for Sbwerrclr_SPEC {
5407    type DataType = u32;
5408}
5409
5410#[doc = "Slave Bufferable Write Error Clear Register"]
5411pub type Sbwerrclr = crate::RegValueT<Sbwerrclr_SPEC>;
5412
5413impl Sbwerrclr {
5414    #[doc = "Slave Bufferable Write Error Clear"]
5415    #[inline(always)]
5416    pub fn sbweclr0(
5417        self,
5418    ) -> crate::common::RegisterFieldBool<0, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5419        crate::common::RegisterFieldBool::<0,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5420    }
5421
5422    #[doc = "Slave Bufferable Write Error Clear"]
5423    #[inline(always)]
5424    pub fn sbweclr1(
5425        self,
5426    ) -> crate::common::RegisterFieldBool<1, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5427        crate::common::RegisterFieldBool::<1,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5428    }
5429
5430    #[doc = "Slave Bufferable Write Error Clear"]
5431    #[inline(always)]
5432    pub fn sbweclr2(
5433        self,
5434    ) -> crate::common::RegisterFieldBool<2, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5435        crate::common::RegisterFieldBool::<2,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5436    }
5437
5438    #[doc = "Slave Bufferable Write Error Clear"]
5439    #[inline(always)]
5440    pub fn sbweclr3(
5441        self,
5442    ) -> crate::common::RegisterFieldBool<3, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5443        crate::common::RegisterFieldBool::<3,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5444    }
5445
5446    #[doc = "Slave Bufferable Write Error Clear"]
5447    #[inline(always)]
5448    pub fn sbweclr4(
5449        self,
5450    ) -> crate::common::RegisterFieldBool<4, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5451        crate::common::RegisterFieldBool::<4,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5452    }
5453
5454    #[doc = "Slave Bufferable Write Error Clear"]
5455    #[inline(always)]
5456    pub fn sbweclr5(
5457        self,
5458    ) -> crate::common::RegisterFieldBool<5, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5459        crate::common::RegisterFieldBool::<5,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5460    }
5461
5462    #[doc = "Slave Bufferable Write Error Clear"]
5463    #[inline(always)]
5464    pub fn sbweclr6(
5465        self,
5466    ) -> crate::common::RegisterFieldBool<6, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5467        crate::common::RegisterFieldBool::<6,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5468    }
5469
5470    #[doc = "Slave Bufferable Write Error Clear"]
5471    #[inline(always)]
5472    pub fn sbweclr7(
5473        self,
5474    ) -> crate::common::RegisterFieldBool<7, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5475        crate::common::RegisterFieldBool::<7,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5476    }
5477
5478    #[doc = "Slave Bufferable Write Error Clear"]
5479    #[inline(always)]
5480    pub fn sbweclr8(
5481        self,
5482    ) -> crate::common::RegisterFieldBool<8, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5483        crate::common::RegisterFieldBool::<8,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5484    }
5485
5486    #[doc = "Slave Bufferable Write Error Clear"]
5487    #[inline(always)]
5488    pub fn sbweclr9(
5489        self,
5490    ) -> crate::common::RegisterFieldBool<9, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5491        crate::common::RegisterFieldBool::<9,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5492    }
5493
5494    #[doc = "Slave Bufferable Write Error Clear"]
5495    #[inline(always)]
5496    pub fn sbweclr10(
5497        self,
5498    ) -> crate::common::RegisterFieldBool<10, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5499        crate::common::RegisterFieldBool::<10,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5500    }
5501
5502    #[doc = "Slave Bufferable Write Error Clear"]
5503    #[inline(always)]
5504    pub fn sbweclr11(
5505        self,
5506    ) -> crate::common::RegisterFieldBool<11, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5507        crate::common::RegisterFieldBool::<11,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5508    }
5509
5510    #[doc = "Slave Bufferable Write Error Clear"]
5511    #[inline(always)]
5512    pub fn sbweclr12(
5513        self,
5514    ) -> crate::common::RegisterFieldBool<12, 1, 0, Sbwerrclr_SPEC, crate::common::RW> {
5515        crate::common::RegisterFieldBool::<12,1,0,Sbwerrclr_SPEC,crate::common::RW>::from_register(self,0)
5516    }
5517}
5518impl ::core::default::Default for Sbwerrclr {
5519    #[inline(always)]
5520    fn default() -> Sbwerrclr {
5521        <crate::RegValueT<Sbwerrclr_SPEC> as RegisterValue<_>>::new(0)
5522    }
5523}