ra6t1/system/
lvdcr0.rs

1#[doc = "Register `LVD%sCR0` reader"]
2pub struct R(crate::R<LVDCR0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<LVDCR0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<LVDCR0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<LVDCR0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `LVD%sCR0` writer"]
17pub struct W(crate::W<LVDCR0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<LVDCR0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<LVDCR0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<LVDCR0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RIE` reader - Voltage Monitor Interrupt/Reset Enable"]
38pub type RIE_R = crate::BitReader<RIE_A>;
39#[doc = "Voltage Monitor Interrupt/Reset Enable\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum RIE_A {
42    #[doc = "0: Disable"]
43    _0 = 0,
44    #[doc = "1: Enable"]
45    _1 = 1,
46}
47impl From<RIE_A> for bool {
48    #[inline(always)]
49    fn from(variant: RIE_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl RIE_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> RIE_A {
57        match self.bits {
58            false => RIE_A::_0,
59            true => RIE_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == RIE_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == RIE_A::_1
71    }
72}
73#[doc = "Field `RIE` writer - Voltage Monitor Interrupt/Reset Enable"]
74pub type RIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, LVDCR0_SPEC, RIE_A, O>;
75impl<'a, const O: u8> RIE_W<'a, O> {
76    #[doc = "Disable"]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(RIE_A::_0)
80    }
81    #[doc = "Enable"]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(RIE_A::_1)
85    }
86}
87#[doc = "Field `DFDIS` reader - Voltage Monitor Digital Filter Disable Mode Select"]
88pub type DFDIS_R = crate::BitReader<DFDIS_A>;
89#[doc = "Voltage Monitor Digital Filter Disable Mode Select\n\nValue on reset: 1"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum DFDIS_A {
92    #[doc = "0: Enable digital filter"]
93    _0 = 0,
94    #[doc = "1: Disable digital filter"]
95    _1 = 1,
96}
97impl From<DFDIS_A> for bool {
98    #[inline(always)]
99    fn from(variant: DFDIS_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl DFDIS_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> DFDIS_A {
107        match self.bits {
108            false => DFDIS_A::_0,
109            true => DFDIS_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == DFDIS_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == DFDIS_A::_1
121    }
122}
123#[doc = "Field `DFDIS` writer - Voltage Monitor Digital Filter Disable Mode Select"]
124pub type DFDIS_W<'a, const O: u8> = crate::BitWriter<'a, u8, LVDCR0_SPEC, DFDIS_A, O>;
125impl<'a, const O: u8> DFDIS_W<'a, O> {
126    #[doc = "Enable digital filter"]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(DFDIS_A::_0)
130    }
131    #[doc = "Disable digital filter"]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(DFDIS_A::_1)
135    }
136}
137#[doc = "Field `CMPE` reader - Voltage Monitor Circuit Comparison Result Output Enable"]
138pub type CMPE_R = crate::BitReader<CMPE_A>;
139#[doc = "Voltage Monitor Circuit Comparison Result Output Enable\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum CMPE_A {
142    #[doc = "0: Disable voltage monitor 1 circuit comparison result output"]
143    _0 = 0,
144    #[doc = "1: Enable voltage monitor 1 circuit comparison result output."]
145    _1 = 1,
146}
147impl From<CMPE_A> for bool {
148    #[inline(always)]
149    fn from(variant: CMPE_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl CMPE_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> CMPE_A {
157        match self.bits {
158            false => CMPE_A::_0,
159            true => CMPE_A::_1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `_0`"]
163    #[inline(always)]
164    pub fn is_0(&self) -> bool {
165        *self == CMPE_A::_0
166    }
167    #[doc = "Checks if the value of the field is `_1`"]
168    #[inline(always)]
169    pub fn is_1(&self) -> bool {
170        *self == CMPE_A::_1
171    }
172}
173#[doc = "Field `CMPE` writer - Voltage Monitor Circuit Comparison Result Output Enable"]
174pub type CMPE_W<'a, const O: u8> = crate::BitWriter<'a, u8, LVDCR0_SPEC, CMPE_A, O>;
175impl<'a, const O: u8> CMPE_W<'a, O> {
176    #[doc = "Disable voltage monitor 1 circuit comparison result output"]
177    #[inline(always)]
178    pub fn _0(self) -> &'a mut W {
179        self.variant(CMPE_A::_0)
180    }
181    #[doc = "Enable voltage monitor 1 circuit comparison result output."]
182    #[inline(always)]
183    pub fn _1(self) -> &'a mut W {
184        self.variant(CMPE_A::_1)
185    }
186}
187#[doc = "Field `FSAMP` reader - Sampling Clock Select"]
188pub type FSAMP_R = crate::FieldReader<u8, FSAMP_A>;
189#[doc = "Sampling Clock Select\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191#[repr(u8)]
192pub enum FSAMP_A {
193    #[doc = "0: 1/2 LOCO frequency"]
194    _00 = 0,
195    #[doc = "1: 1/4 LOCO frequency"]
196    _01 = 1,
197    #[doc = "2: 1/8 LOCO frequency"]
198    _10 = 2,
199    #[doc = "3: 1/16 LOCO frequency"]
200    _11 = 3,
201}
202impl From<FSAMP_A> for u8 {
203    #[inline(always)]
204    fn from(variant: FSAMP_A) -> Self {
205        variant as _
206    }
207}
208impl FSAMP_R {
209    #[doc = "Get enumerated values variant"]
210    #[inline(always)]
211    pub fn variant(&self) -> FSAMP_A {
212        match self.bits {
213            0 => FSAMP_A::_00,
214            1 => FSAMP_A::_01,
215            2 => FSAMP_A::_10,
216            3 => FSAMP_A::_11,
217            _ => unreachable!(),
218        }
219    }
220    #[doc = "Checks if the value of the field is `_00`"]
221    #[inline(always)]
222    pub fn is_00(&self) -> bool {
223        *self == FSAMP_A::_00
224    }
225    #[doc = "Checks if the value of the field is `_01`"]
226    #[inline(always)]
227    pub fn is_01(&self) -> bool {
228        *self == FSAMP_A::_01
229    }
230    #[doc = "Checks if the value of the field is `_10`"]
231    #[inline(always)]
232    pub fn is_10(&self) -> bool {
233        *self == FSAMP_A::_10
234    }
235    #[doc = "Checks if the value of the field is `_11`"]
236    #[inline(always)]
237    pub fn is_11(&self) -> bool {
238        *self == FSAMP_A::_11
239    }
240}
241#[doc = "Field `FSAMP` writer - Sampling Clock Select"]
242pub type FSAMP_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, LVDCR0_SPEC, u8, FSAMP_A, 2, O>;
243impl<'a, const O: u8> FSAMP_W<'a, O> {
244    #[doc = "1/2 LOCO frequency"]
245    #[inline(always)]
246    pub fn _00(self) -> &'a mut W {
247        self.variant(FSAMP_A::_00)
248    }
249    #[doc = "1/4 LOCO frequency"]
250    #[inline(always)]
251    pub fn _01(self) -> &'a mut W {
252        self.variant(FSAMP_A::_01)
253    }
254    #[doc = "1/8 LOCO frequency"]
255    #[inline(always)]
256    pub fn _10(self) -> &'a mut W {
257        self.variant(FSAMP_A::_10)
258    }
259    #[doc = "1/16 LOCO frequency"]
260    #[inline(always)]
261    pub fn _11(self) -> &'a mut W {
262        self.variant(FSAMP_A::_11)
263    }
264}
265#[doc = "Field `RI` reader - Voltage Monitor Circuit Mode Select"]
266pub type RI_R = crate::BitReader<RI_A>;
267#[doc = "Voltage Monitor Circuit Mode Select\n\nValue on reset: 0"]
268#[derive(Clone, Copy, Debug, PartialEq, Eq)]
269pub enum RI_A {
270    #[doc = "0: Voltage Monitor interrupt during Vdet1 passage"]
271    _0 = 0,
272    #[doc = "1: Voltage Monitor reset enabled when the voltage falls to and below Vdet1"]
273    _1 = 1,
274}
275impl From<RI_A> for bool {
276    #[inline(always)]
277    fn from(variant: RI_A) -> Self {
278        variant as u8 != 0
279    }
280}
281impl RI_R {
282    #[doc = "Get enumerated values variant"]
283    #[inline(always)]
284    pub fn variant(&self) -> RI_A {
285        match self.bits {
286            false => RI_A::_0,
287            true => RI_A::_1,
288        }
289    }
290    #[doc = "Checks if the value of the field is `_0`"]
291    #[inline(always)]
292    pub fn is_0(&self) -> bool {
293        *self == RI_A::_0
294    }
295    #[doc = "Checks if the value of the field is `_1`"]
296    #[inline(always)]
297    pub fn is_1(&self) -> bool {
298        *self == RI_A::_1
299    }
300}
301#[doc = "Field `RI` writer - Voltage Monitor Circuit Mode Select"]
302pub type RI_W<'a, const O: u8> = crate::BitWriter<'a, u8, LVDCR0_SPEC, RI_A, O>;
303impl<'a, const O: u8> RI_W<'a, O> {
304    #[doc = "Voltage Monitor interrupt during Vdet1 passage"]
305    #[inline(always)]
306    pub fn _0(self) -> &'a mut W {
307        self.variant(RI_A::_0)
308    }
309    #[doc = "Voltage Monitor reset enabled when the voltage falls to and below Vdet1"]
310    #[inline(always)]
311    pub fn _1(self) -> &'a mut W {
312        self.variant(RI_A::_1)
313    }
314}
315#[doc = "Field `RN` reader - Voltage Monitor Reset Negate Select"]
316pub type RN_R = crate::BitReader<RN_A>;
317#[doc = "Voltage Monitor Reset Negate Select\n\nValue on reset: 1"]
318#[derive(Clone, Copy, Debug, PartialEq, Eq)]
319pub enum RN_A {
320    #[doc = "0: Negation follows a stabilization time (tLVD) after VCC > Vdet is detected."]
321    _0 = 0,
322    #[doc = "1: Negation follows a stabilization time (tLVD) after assertion of the LVD reset."]
323    _1 = 1,
324}
325impl From<RN_A> for bool {
326    #[inline(always)]
327    fn from(variant: RN_A) -> Self {
328        variant as u8 != 0
329    }
330}
331impl RN_R {
332    #[doc = "Get enumerated values variant"]
333    #[inline(always)]
334    pub fn variant(&self) -> RN_A {
335        match self.bits {
336            false => RN_A::_0,
337            true => RN_A::_1,
338        }
339    }
340    #[doc = "Checks if the value of the field is `_0`"]
341    #[inline(always)]
342    pub fn is_0(&self) -> bool {
343        *self == RN_A::_0
344    }
345    #[doc = "Checks if the value of the field is `_1`"]
346    #[inline(always)]
347    pub fn is_1(&self) -> bool {
348        *self == RN_A::_1
349    }
350}
351#[doc = "Field `RN` writer - Voltage Monitor Reset Negate Select"]
352pub type RN_W<'a, const O: u8> = crate::BitWriter<'a, u8, LVDCR0_SPEC, RN_A, O>;
353impl<'a, const O: u8> RN_W<'a, O> {
354    #[doc = "Negation follows a stabilization time (tLVD) after VCC > Vdet is detected."]
355    #[inline(always)]
356    pub fn _0(self) -> &'a mut W {
357        self.variant(RN_A::_0)
358    }
359    #[doc = "Negation follows a stabilization time (tLVD) after assertion of the LVD reset."]
360    #[inline(always)]
361    pub fn _1(self) -> &'a mut W {
362        self.variant(RN_A::_1)
363    }
364}
365impl R {
366    #[doc = "Bit 0 - Voltage Monitor Interrupt/Reset Enable"]
367    #[inline(always)]
368    pub fn rie(&self) -> RIE_R {
369        RIE_R::new((self.bits & 1) != 0)
370    }
371    #[doc = "Bit 1 - Voltage Monitor Digital Filter Disable Mode Select"]
372    #[inline(always)]
373    pub fn dfdis(&self) -> DFDIS_R {
374        DFDIS_R::new(((self.bits >> 1) & 1) != 0)
375    }
376    #[doc = "Bit 2 - Voltage Monitor Circuit Comparison Result Output Enable"]
377    #[inline(always)]
378    pub fn cmpe(&self) -> CMPE_R {
379        CMPE_R::new(((self.bits >> 2) & 1) != 0)
380    }
381    #[doc = "Bits 4:5 - Sampling Clock Select"]
382    #[inline(always)]
383    pub fn fsamp(&self) -> FSAMP_R {
384        FSAMP_R::new((self.bits >> 4) & 3)
385    }
386    #[doc = "Bit 6 - Voltage Monitor Circuit Mode Select"]
387    #[inline(always)]
388    pub fn ri(&self) -> RI_R {
389        RI_R::new(((self.bits >> 6) & 1) != 0)
390    }
391    #[doc = "Bit 7 - Voltage Monitor Reset Negate Select"]
392    #[inline(always)]
393    pub fn rn(&self) -> RN_R {
394        RN_R::new(((self.bits >> 7) & 1) != 0)
395    }
396}
397impl W {
398    #[doc = "Bit 0 - Voltage Monitor Interrupt/Reset Enable"]
399    #[inline(always)]
400    #[must_use]
401    pub fn rie(&mut self) -> RIE_W<0> {
402        RIE_W::new(self)
403    }
404    #[doc = "Bit 1 - Voltage Monitor Digital Filter Disable Mode Select"]
405    #[inline(always)]
406    #[must_use]
407    pub fn dfdis(&mut self) -> DFDIS_W<1> {
408        DFDIS_W::new(self)
409    }
410    #[doc = "Bit 2 - Voltage Monitor Circuit Comparison Result Output Enable"]
411    #[inline(always)]
412    #[must_use]
413    pub fn cmpe(&mut self) -> CMPE_W<2> {
414        CMPE_W::new(self)
415    }
416    #[doc = "Bits 4:5 - Sampling Clock Select"]
417    #[inline(always)]
418    #[must_use]
419    pub fn fsamp(&mut self) -> FSAMP_W<4> {
420        FSAMP_W::new(self)
421    }
422    #[doc = "Bit 6 - Voltage Monitor Circuit Mode Select"]
423    #[inline(always)]
424    #[must_use]
425    pub fn ri(&mut self) -> RI_W<6> {
426        RI_W::new(self)
427    }
428    #[doc = "Bit 7 - Voltage Monitor Reset Negate Select"]
429    #[inline(always)]
430    #[must_use]
431    pub fn rn(&mut self) -> RN_W<7> {
432        RN_W::new(self)
433    }
434    #[doc = "Writes raw bits to the register."]
435    #[inline(always)]
436    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
437        self.0.bits(bits);
438        self
439    }
440}
441#[doc = "Voltage Monitor %s Circuit Control Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lvdcr0](index.html) module"]
442pub struct LVDCR0_SPEC;
443impl crate::RegisterSpec for LVDCR0_SPEC {
444    type Ux = u8;
445}
446#[doc = "`read()` method returns [lvdcr0::R](R) reader structure"]
447impl crate::Readable for LVDCR0_SPEC {
448    type Reader = R;
449}
450#[doc = "`write(|w| ..)` method takes [lvdcr0::W](W) writer structure"]
451impl crate::Writable for LVDCR0_SPEC {
452    type Writer = W;
453    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
454    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
455}
456#[doc = "`reset()` method sets LVD%sCR0 to value 0x8a"]
457impl crate::Resettable for LVDCR0_SPEC {
458    const RESET_VALUE: Self::Ux = 0x8a;
459}
ra6t1/system/lvdcr0.rs

ra6t1/system/
lvdcr0.rs
