ra6t1/sci0/
semr.rs

1#[doc = "Register `SEMR` reader"]
2pub struct R(crate::R<SEMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SEMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SEMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SEMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SEMR` writer"]
17pub struct W(crate::W<SEMR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SEMR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SEMR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SEMR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `BRME` reader - Bit Modulation Enable"]
38pub type BRME_R = crate::BitReader<BRME_A>;
39#[doc = "Bit Modulation Enable\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum BRME_A {
42    #[doc = "0: Bit rate modulation function is disabled."]
43    _0 = 0,
44    #[doc = "1: Bit rate modulation function is enabled."]
45    _1 = 1,
46}
47impl From<BRME_A> for bool {
48    #[inline(always)]
49    fn from(variant: BRME_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl BRME_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> BRME_A {
57        match self.bits {
58            false => BRME_A::_0,
59            true => BRME_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == BRME_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == BRME_A::_1
71    }
72}
73#[doc = "Field `BRME` writer - Bit Modulation Enable"]
74pub type BRME_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, BRME_A, O>;
75impl<'a, const O: u8> BRME_W<'a, O> {
76    #[doc = "Bit rate modulation function is disabled."]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(BRME_A::_0)
80    }
81    #[doc = "Bit rate modulation function is enabled."]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(BRME_A::_1)
85    }
86}
87#[doc = "Field `ABCSE` reader - Asynchronous Mode Extended Base Clock Select1 (Valid only in asynchronous mode and SCR.CKE\\[1\\]=0)"]
88pub type ABCSE_R = crate::BitReader<ABCSE_A>;
89#[doc = "Asynchronous Mode Extended Base Clock Select1 (Valid only in asynchronous mode and SCR.CKE\\[1\\]=0)\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum ABCSE_A {
92    #[doc = "0: Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR."]
93    _0 = 0,
94    #[doc = "1: Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator."]
95    _1 = 1,
96}
97impl From<ABCSE_A> for bool {
98    #[inline(always)]
99    fn from(variant: ABCSE_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl ABCSE_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> ABCSE_A {
107        match self.bits {
108            false => ABCSE_A::_0,
109            true => ABCSE_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == ABCSE_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == ABCSE_A::_1
121    }
122}
123#[doc = "Field `ABCSE` writer - Asynchronous Mode Extended Base Clock Select1 (Valid only in asynchronous mode and SCR.CKE\\[1\\]=0)"]
124pub type ABCSE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, ABCSE_A, O>;
125impl<'a, const O: u8> ABCSE_W<'a, O> {
126    #[doc = "Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR."]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(ABCSE_A::_0)
130    }
131    #[doc = "Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator."]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(ABCSE_A::_1)
135    }
136}
137#[doc = "Field `ABCS` reader - Asynchronous Mode Base Clock Select (Valid only in asynchronous mode)"]
138pub type ABCS_R = crate::BitReader<ABCS_A>;
139#[doc = "Asynchronous Mode Base Clock Select (Valid only in asynchronous mode)\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum ABCS_A {
142    #[doc = "0: Selects 16 base clock cycles for 1-bit period."]
143    _0 = 0,
144    #[doc = "1: Selects 8 base clock cycles for 1-bit period."]
145    _1 = 1,
146}
147impl From<ABCS_A> for bool {
148    #[inline(always)]
149    fn from(variant: ABCS_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl ABCS_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> ABCS_A {
157        match self.bits {
158            false => ABCS_A::_0,
159            true => ABCS_A::_1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `_0`"]
163    #[inline(always)]
164    pub fn is_0(&self) -> bool {
165        *self == ABCS_A::_0
166    }
167    #[doc = "Checks if the value of the field is `_1`"]
168    #[inline(always)]
169    pub fn is_1(&self) -> bool {
170        *self == ABCS_A::_1
171    }
172}
173#[doc = "Field `ABCS` writer - Asynchronous Mode Base Clock Select (Valid only in asynchronous mode)"]
174pub type ABCS_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, ABCS_A, O>;
175impl<'a, const O: u8> ABCS_W<'a, O> {
176    #[doc = "Selects 16 base clock cycles for 1-bit period."]
177    #[inline(always)]
178    pub fn _0(self) -> &'a mut W {
179        self.variant(ABCS_A::_0)
180    }
181    #[doc = "Selects 8 base clock cycles for 1-bit period."]
182    #[inline(always)]
183    pub fn _1(self) -> &'a mut W {
184        self.variant(ABCS_A::_1)
185    }
186}
187#[doc = "Field `NFEN` reader - Digital Noise Filter Function Enable (The NFEN bit should be 0 without simple I2C mode and asynchronous mode.) In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input."]
188pub type NFEN_R = crate::BitReader<NFEN_A>;
189#[doc = "Digital Noise Filter Function Enable (The NFEN bit should be 0 without simple I2C mode and asynchronous mode.) In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input.\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum NFEN_A {
192    #[doc = "0: Noise cancellation function for the RXDn/TXDn input signal is disabled."]
193    _0 = 0,
194    #[doc = "1: Noise cancellation function for the RXDn/TXDn input signal is enabled."]
195    _1 = 1,
196}
197impl From<NFEN_A> for bool {
198    #[inline(always)]
199    fn from(variant: NFEN_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl NFEN_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> NFEN_A {
207        match self.bits {
208            false => NFEN_A::_0,
209            true => NFEN_A::_1,
210        }
211    }
212    #[doc = "Checks if the value of the field is `_0`"]
213    #[inline(always)]
214    pub fn is_0(&self) -> bool {
215        *self == NFEN_A::_0
216    }
217    #[doc = "Checks if the value of the field is `_1`"]
218    #[inline(always)]
219    pub fn is_1(&self) -> bool {
220        *self == NFEN_A::_1
221    }
222}
223#[doc = "Field `NFEN` writer - Digital Noise Filter Function Enable (The NFEN bit should be 0 without simple I2C mode and asynchronous mode.) In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input."]
224pub type NFEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, NFEN_A, O>;
225impl<'a, const O: u8> NFEN_W<'a, O> {
226    #[doc = "Noise cancellation function for the RXDn/TXDn input signal is disabled."]
227    #[inline(always)]
228    pub fn _0(self) -> &'a mut W {
229        self.variant(NFEN_A::_0)
230    }
231    #[doc = "Noise cancellation function for the RXDn/TXDn input signal is enabled."]
232    #[inline(always)]
233    pub fn _1(self) -> &'a mut W {
234        self.variant(NFEN_A::_1)
235    }
236}
237#[doc = "Field `BGDM` reader - Baud Rate Generator Double-Speed Mode Select (Only valid the CKE\\[1\\]
238bit in SCR is 0 in asynchronous mode)."]
239pub type BGDM_R = crate::BitReader<BGDM_A>;
240#[doc = "Baud Rate Generator Double-Speed Mode Select (Only valid the CKE\\[1\\]
241bit in SCR is 0 in asynchronous mode).\n\nValue on reset: 0"]
242#[derive(Clone, Copy, Debug, PartialEq, Eq)]
243pub enum BGDM_A {
244    #[doc = "0: Baud rate generator outputs the clock with normal frequency."]
245    _0 = 0,
246    #[doc = "1: Baud rate generator outputs the clock with doubled frequency."]
247    _1 = 1,
248}
249impl From<BGDM_A> for bool {
250    #[inline(always)]
251    fn from(variant: BGDM_A) -> Self {
252        variant as u8 != 0
253    }
254}
255impl BGDM_R {
256    #[doc = "Get enumerated values variant"]
257    #[inline(always)]
258    pub fn variant(&self) -> BGDM_A {
259        match self.bits {
260            false => BGDM_A::_0,
261            true => BGDM_A::_1,
262        }
263    }
264    #[doc = "Checks if the value of the field is `_0`"]
265    #[inline(always)]
266    pub fn is_0(&self) -> bool {
267        *self == BGDM_A::_0
268    }
269    #[doc = "Checks if the value of the field is `_1`"]
270    #[inline(always)]
271    pub fn is_1(&self) -> bool {
272        *self == BGDM_A::_1
273    }
274}
275#[doc = "Field `BGDM` writer - Baud Rate Generator Double-Speed Mode Select (Only valid the CKE\\[1\\]
276bit in SCR is 0 in asynchronous mode)."]
277pub type BGDM_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, BGDM_A, O>;
278impl<'a, const O: u8> BGDM_W<'a, O> {
279    #[doc = "Baud rate generator outputs the clock with normal frequency."]
280    #[inline(always)]
281    pub fn _0(self) -> &'a mut W {
282        self.variant(BGDM_A::_0)
283    }
284    #[doc = "Baud rate generator outputs the clock with doubled frequency."]
285    #[inline(always)]
286    pub fn _1(self) -> &'a mut W {
287        self.variant(BGDM_A::_1)
288    }
289}
290#[doc = "Field `RXDESEL` reader - Asynchronous Start Bit Edge Detection Select (Valid only in asynchronous mode)"]
291pub type RXDESEL_R = crate::BitReader<RXDESEL_A>;
292#[doc = "Asynchronous Start Bit Edge Detection Select (Valid only in asynchronous mode)\n\nValue on reset: 0"]
293#[derive(Clone, Copy, Debug, PartialEq, Eq)]
294pub enum RXDESEL_A {
295    #[doc = "0: The low level on the RXDn pin is detected as the start bit."]
296    _0 = 0,
297    #[doc = "1: A falling edge on the RXDn pin is detected as the start bit."]
298    _1 = 1,
299}
300impl From<RXDESEL_A> for bool {
301    #[inline(always)]
302    fn from(variant: RXDESEL_A) -> Self {
303        variant as u8 != 0
304    }
305}
306impl RXDESEL_R {
307    #[doc = "Get enumerated values variant"]
308    #[inline(always)]
309    pub fn variant(&self) -> RXDESEL_A {
310        match self.bits {
311            false => RXDESEL_A::_0,
312            true => RXDESEL_A::_1,
313        }
314    }
315    #[doc = "Checks if the value of the field is `_0`"]
316    #[inline(always)]
317    pub fn is_0(&self) -> bool {
318        *self == RXDESEL_A::_0
319    }
320    #[doc = "Checks if the value of the field is `_1`"]
321    #[inline(always)]
322    pub fn is_1(&self) -> bool {
323        *self == RXDESEL_A::_1
324    }
325}
326#[doc = "Field `RXDESEL` writer - Asynchronous Start Bit Edge Detection Select (Valid only in asynchronous mode)"]
327pub type RXDESEL_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, RXDESEL_A, O>;
328impl<'a, const O: u8> RXDESEL_W<'a, O> {
329    #[doc = "The low level on the RXDn pin is detected as the start bit."]
330    #[inline(always)]
331    pub fn _0(self) -> &'a mut W {
332        self.variant(RXDESEL_A::_0)
333    }
334    #[doc = "A falling edge on the RXDn pin is detected as the start bit."]
335    #[inline(always)]
336    pub fn _1(self) -> &'a mut W {
337        self.variant(RXDESEL_A::_1)
338    }
339}
340impl R {
341    #[doc = "Bit 2 - Bit Modulation Enable"]
342    #[inline(always)]
343    pub fn brme(&self) -> BRME_R {
344        BRME_R::new(((self.bits >> 2) & 1) != 0)
345    }
346    #[doc = "Bit 3 - Asynchronous Mode Extended Base Clock Select1 (Valid only in asynchronous mode and SCR.CKE\\[1\\]=0)"]
347    #[inline(always)]
348    pub fn abcse(&self) -> ABCSE_R {
349        ABCSE_R::new(((self.bits >> 3) & 1) != 0)
350    }
351    #[doc = "Bit 4 - Asynchronous Mode Base Clock Select (Valid only in asynchronous mode)"]
352    #[inline(always)]
353    pub fn abcs(&self) -> ABCS_R {
354        ABCS_R::new(((self.bits >> 4) & 1) != 0)
355    }
356    #[doc = "Bit 5 - Digital Noise Filter Function Enable (The NFEN bit should be 0 without simple I2C mode and asynchronous mode.) In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input."]
357    #[inline(always)]
358    pub fn nfen(&self) -> NFEN_R {
359        NFEN_R::new(((self.bits >> 5) & 1) != 0)
360    }
361    #[doc = "Bit 6 - Baud Rate Generator Double-Speed Mode Select (Only valid the CKE\\[1\\]
362bit in SCR is 0 in asynchronous mode)."]
363    #[inline(always)]
364    pub fn bgdm(&self) -> BGDM_R {
365        BGDM_R::new(((self.bits >> 6) & 1) != 0)
366    }
367    #[doc = "Bit 7 - Asynchronous Start Bit Edge Detection Select (Valid only in asynchronous mode)"]
368    #[inline(always)]
369    pub fn rxdesel(&self) -> RXDESEL_R {
370        RXDESEL_R::new(((self.bits >> 7) & 1) != 0)
371    }
372}
373impl W {
374    #[doc = "Bit 2 - Bit Modulation Enable"]
375    #[inline(always)]
376    #[must_use]
377    pub fn brme(&mut self) -> BRME_W<2> {
378        BRME_W::new(self)
379    }
380    #[doc = "Bit 3 - Asynchronous Mode Extended Base Clock Select1 (Valid only in asynchronous mode and SCR.CKE\\[1\\]=0)"]
381    #[inline(always)]
382    #[must_use]
383    pub fn abcse(&mut self) -> ABCSE_W<3> {
384        ABCSE_W::new(self)
385    }
386    #[doc = "Bit 4 - Asynchronous Mode Base Clock Select (Valid only in asynchronous mode)"]
387    #[inline(always)]
388    #[must_use]
389    pub fn abcs(&mut self) -> ABCS_W<4> {
390        ABCS_W::new(self)
391    }
392    #[doc = "Bit 5 - Digital Noise Filter Function Enable (The NFEN bit should be 0 without simple I2C mode and asynchronous mode.) In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input."]
393    #[inline(always)]
394    #[must_use]
395    pub fn nfen(&mut self) -> NFEN_W<5> {
396        NFEN_W::new(self)
397    }
398    #[doc = "Bit 6 - Baud Rate Generator Double-Speed Mode Select (Only valid the CKE\\[1\\]
399bit in SCR is 0 in asynchronous mode)."]
400    #[inline(always)]
401    #[must_use]
402    pub fn bgdm(&mut self) -> BGDM_W<6> {
403        BGDM_W::new(self)
404    }
405    #[doc = "Bit 7 - Asynchronous Start Bit Edge Detection Select (Valid only in asynchronous mode)"]
406    #[inline(always)]
407    #[must_use]
408    pub fn rxdesel(&mut self) -> RXDESEL_W<7> {
409        RXDESEL_W::new(self)
410    }
411    #[doc = "Writes raw bits to the register."]
412    #[inline(always)]
413    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
414        self.0.bits(bits);
415        self
416    }
417}
418#[doc = "Serial Extended Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [semr](index.html) module"]
419pub struct SEMR_SPEC;
420impl crate::RegisterSpec for SEMR_SPEC {
421    type Ux = u8;
422}
423#[doc = "`read()` method returns [semr::R](R) reader structure"]
424impl crate::Readable for SEMR_SPEC {
425    type Reader = R;
426}
427#[doc = "`write(|w| ..)` method takes [semr::W](W) writer structure"]
428impl crate::Writable for SEMR_SPEC {
429    type Writer = W;
430    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
431    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
432}
433#[doc = "`reset()` method sets SEMR to value 0"]
434impl crate::Resettable for SEMR_SPEC {
435    const RESET_VALUE: Self::Ux = 0;
436}
ra6t1/sci0/semr.rs

ra6t1/sci0/
semr.rs
