ra6t1_pac/
src.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.0, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:52:24 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Sampling Rate Converter"]
28unsafe impl ::core::marker::Send for super::Src {}
29unsafe impl ::core::marker::Sync for super::Src {}
30impl super::Src {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Input Data Register"]
38    #[inline(always)]
39    pub const fn srcid(&self) -> &'static crate::common::Reg<self::Srcid_SPEC, crate::common::W> {
40        unsafe {
41            crate::common::Reg::<self::Srcid_SPEC, crate::common::W>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "Output Data Register"]
48    #[inline(always)]
49    pub const fn srcod(&self) -> &'static crate::common::Reg<self::Srcod_SPEC, crate::common::R> {
50        unsafe {
51            crate::common::Reg::<self::Srcod_SPEC, crate::common::R>::from_ptr(
52                self._svd2pac_as_ptr().add(4usize),
53            )
54        }
55    }
56
57    #[doc = "Input Data Control Register"]
58    #[inline(always)]
59    pub const fn srcidctrl(
60        &self,
61    ) -> &'static crate::common::Reg<self::Srcidctrl_SPEC, crate::common::RW> {
62        unsafe {
63            crate::common::Reg::<self::Srcidctrl_SPEC, crate::common::RW>::from_ptr(
64                self._svd2pac_as_ptr().add(8usize),
65            )
66        }
67    }
68
69    #[doc = "Output Data Control Register"]
70    #[inline(always)]
71    pub const fn srcodctrl(
72        &self,
73    ) -> &'static crate::common::Reg<self::Srcodctrl_SPEC, crate::common::RW> {
74        unsafe {
75            crate::common::Reg::<self::Srcodctrl_SPEC, crate::common::RW>::from_ptr(
76                self._svd2pac_as_ptr().add(10usize),
77            )
78        }
79    }
80
81    #[doc = "Control Register"]
82    #[inline(always)]
83    pub const fn srcctrl(
84        &self,
85    ) -> &'static crate::common::Reg<self::Srcctrl_SPEC, crate::common::RW> {
86        unsafe {
87            crate::common::Reg::<self::Srcctrl_SPEC, crate::common::RW>::from_ptr(
88                self._svd2pac_as_ptr().add(12usize),
89            )
90        }
91    }
92
93    #[doc = "Status Register"]
94    #[inline(always)]
95    pub const fn srcstat(
96        &self,
97    ) -> &'static crate::common::Reg<self::Srcstat_SPEC, crate::common::RW> {
98        unsafe {
99            crate::common::Reg::<self::Srcstat_SPEC, crate::common::RW>::from_ptr(
100                self._svd2pac_as_ptr().add(14usize),
101            )
102        }
103    }
104}
105#[doc(hidden)]
106#[derive(Copy, Clone, Eq, PartialEq)]
107pub struct Srcid_SPEC;
108impl crate::sealed::RegSpec for Srcid_SPEC {
109    type DataType = u32;
110}
111
112#[doc = "Input Data Register"]
113pub type Srcid = crate::RegValueT<Srcid_SPEC>;
114
115impl Srcid {
116    #[doc = "SRCID is a 32-bit writ-only register that is used to input the data before sampling rate conversion. All the bits are read as 0."]
117    #[inline(always)]
118    pub fn srcid(
119        self,
120    ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Srcid_SPEC, crate::common::W>
121    {
122        crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Srcid_SPEC,crate::common::W>::from_register(self,0)
123    }
124}
125impl ::core::default::Default for Srcid {
126    #[inline(always)]
127    fn default() -> Srcid {
128        <crate::RegValueT<Srcid_SPEC> as RegisterValue<_>>::new(0)
129    }
130}
131
132#[doc(hidden)]
133#[derive(Copy, Clone, Eq, PartialEq)]
134pub struct Srcod_SPEC;
135impl crate::sealed::RegSpec for Srcod_SPEC {
136    type DataType = u32;
137}
138
139#[doc = "Output Data Register"]
140pub type Srcod = crate::RegValueT<Srcod_SPEC>;
141
142impl Srcod {
143    #[doc = "SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The data in the 16-stage output data FIFO is read through SRCOD. When the number of data in the output data FIFO is zero after the start of conversion, the value previously read is read again."]
144    #[inline(always)]
145    pub fn srcod(
146        self,
147    ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Srcod_SPEC, crate::common::R>
148    {
149        crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Srcod_SPEC,crate::common::R>::from_register(self,0)
150    }
151}
152impl ::core::default::Default for Srcod {
153    #[inline(always)]
154    fn default() -> Srcod {
155        <crate::RegValueT<Srcod_SPEC> as RegisterValue<_>>::new(0)
156    }
157}
158
159#[doc(hidden)]
160#[derive(Copy, Clone, Eq, PartialEq)]
161pub struct Srcidctrl_SPEC;
162impl crate::sealed::RegSpec for Srcidctrl_SPEC {
163    type DataType = u16;
164}
165
166#[doc = "Input Data Control Register"]
167pub type Srcidctrl = crate::RegValueT<Srcidctrl_SPEC>;
168
169impl Srcidctrl {
170    #[doc = "Input Data Endian"]
171    #[inline(always)]
172    pub fn ied(
173        self,
174    ) -> crate::common::RegisterField<
175        9,
176        0x1,
177        1,
178        0,
179        srcidctrl::Ied,
180        srcidctrl::Ied,
181        Srcidctrl_SPEC,
182        crate::common::RW,
183    > {
184        crate::common::RegisterField::<
185            9,
186            0x1,
187            1,
188            0,
189            srcidctrl::Ied,
190            srcidctrl::Ied,
191            Srcidctrl_SPEC,
192            crate::common::RW,
193        >::from_register(self, 0)
194    }
195
196    #[doc = "Input FIFO Empty Interrupt Enable"]
197    #[inline(always)]
198    pub fn ien(
199        self,
200    ) -> crate::common::RegisterField<
201        8,
202        0x1,
203        1,
204        0,
205        srcidctrl::Ien,
206        srcidctrl::Ien,
207        Srcidctrl_SPEC,
208        crate::common::RW,
209    > {
210        crate::common::RegisterField::<
211            8,
212            0x1,
213            1,
214            0,
215            srcidctrl::Ien,
216            srcidctrl::Ien,
217            Srcidctrl_SPEC,
218            crate::common::RW,
219        >::from_register(self, 0)
220    }
221
222    #[doc = "Input FIFO Data Triggering Number"]
223    #[inline(always)]
224    pub fn iftrg(
225        self,
226    ) -> crate::common::RegisterField<
227        0,
228        0x3,
229        1,
230        0,
231        srcidctrl::Iftrg,
232        srcidctrl::Iftrg,
233        Srcidctrl_SPEC,
234        crate::common::RW,
235    > {
236        crate::common::RegisterField::<
237            0,
238            0x3,
239            1,
240            0,
241            srcidctrl::Iftrg,
242            srcidctrl::Iftrg,
243            Srcidctrl_SPEC,
244            crate::common::RW,
245        >::from_register(self, 0)
246    }
247}
248impl ::core::default::Default for Srcidctrl {
249    #[inline(always)]
250    fn default() -> Srcidctrl {
251        <crate::RegValueT<Srcidctrl_SPEC> as RegisterValue<_>>::new(0)
252    }
253}
254pub mod srcidctrl {
255
256    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
257    pub struct Ied_SPEC;
258    pub type Ied = crate::EnumBitfieldStruct<u8, Ied_SPEC>;
259    impl Ied {
260        #[doc = "Endian formats 1 are the same between the CPU and input data."]
261        pub const _0: Self = Self::new(0);
262
263        #[doc = "Endian formats 1 are different between the CPU and input data."]
264        pub const _1: Self = Self::new(1);
265    }
266    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
267    pub struct Ien_SPEC;
268    pub type Ien = crate::EnumBitfieldStruct<u8, Ien_SPEC>;
269    impl Ien {
270        #[doc = "Input FIFO empty interrupt is disabled."]
271        pub const _0: Self = Self::new(0);
272
273        #[doc = "Input FIFO empty interrupt is enabled."]
274        pub const _1: Self = Self::new(1);
275    }
276    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
277    pub struct Iftrg_SPEC;
278    pub type Iftrg = crate::EnumBitfieldStruct<u8, Iftrg_SPEC>;
279    impl Iftrg {
280        #[doc = "0"]
281        pub const _00: Self = Self::new(0);
282
283        #[doc = "2"]
284        pub const _01: Self = Self::new(1);
285
286        #[doc = "4"]
287        pub const _10: Self = Self::new(2);
288
289        #[doc = "6"]
290        pub const _11: Self = Self::new(3);
291    }
292}
293#[doc(hidden)]
294#[derive(Copy, Clone, Eq, PartialEq)]
295pub struct Srcodctrl_SPEC;
296impl crate::sealed::RegSpec for Srcodctrl_SPEC {
297    type DataType = u16;
298}
299
300#[doc = "Output Data Control Register"]
301pub type Srcodctrl = crate::RegValueT<Srcodctrl_SPEC>;
302
303impl Srcodctrl {
304    #[doc = "Output Data Channel Exchange"]
305    #[inline(always)]
306    pub fn och(
307        self,
308    ) -> crate::common::RegisterField<
309        10,
310        0x1,
311        1,
312        0,
313        srcodctrl::Och,
314        srcodctrl::Och,
315        Srcodctrl_SPEC,
316        crate::common::RW,
317    > {
318        crate::common::RegisterField::<
319            10,
320            0x1,
321            1,
322            0,
323            srcodctrl::Och,
324            srcodctrl::Och,
325            Srcodctrl_SPEC,
326            crate::common::RW,
327        >::from_register(self, 0)
328    }
329
330    #[doc = "Output Data Endian"]
331    #[inline(always)]
332    pub fn oed(
333        self,
334    ) -> crate::common::RegisterField<
335        9,
336        0x1,
337        1,
338        0,
339        srcodctrl::Oed,
340        srcodctrl::Oed,
341        Srcodctrl_SPEC,
342        crate::common::RW,
343    > {
344        crate::common::RegisterField::<
345            9,
346            0x1,
347            1,
348            0,
349            srcodctrl::Oed,
350            srcodctrl::Oed,
351            Srcodctrl_SPEC,
352            crate::common::RW,
353        >::from_register(self, 0)
354    }
355
356    #[doc = "Output Data FIFO Full Interrupt Enable"]
357    #[inline(always)]
358    pub fn oen(
359        self,
360    ) -> crate::common::RegisterField<
361        8,
362        0x1,
363        1,
364        0,
365        srcodctrl::Oen,
366        srcodctrl::Oen,
367        Srcodctrl_SPEC,
368        crate::common::RW,
369    > {
370        crate::common::RegisterField::<
371            8,
372            0x1,
373            1,
374            0,
375            srcodctrl::Oen,
376            srcodctrl::Oen,
377            Srcodctrl_SPEC,
378            crate::common::RW,
379        >::from_register(self, 0)
380    }
381
382    #[doc = "Output FIFO Data Trigger Number"]
383    #[inline(always)]
384    pub fn oftrg(
385        self,
386    ) -> crate::common::RegisterField<
387        0,
388        0x3,
389        1,
390        0,
391        srcodctrl::Oftrg,
392        srcodctrl::Oftrg,
393        Srcodctrl_SPEC,
394        crate::common::RW,
395    > {
396        crate::common::RegisterField::<
397            0,
398            0x3,
399            1,
400            0,
401            srcodctrl::Oftrg,
402            srcodctrl::Oftrg,
403            Srcodctrl_SPEC,
404            crate::common::RW,
405        >::from_register(self, 0)
406    }
407}
408impl ::core::default::Default for Srcodctrl {
409    #[inline(always)]
410    fn default() -> Srcodctrl {
411        <crate::RegValueT<Srcodctrl_SPEC> as RegisterValue<_>>::new(0)
412    }
413}
414pub mod srcodctrl {
415
416    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
417    pub struct Och_SPEC;
418    pub type Och = crate::EnumBitfieldStruct<u8, Och_SPEC>;
419    impl Och {
420        #[doc = "Does not exchange the channels (the same order as data input)"]
421        pub const _0: Self = Self::new(0);
422
423        #[doc = "Exchanges the channels (the opposite order from data input)"]
424        pub const _1: Self = Self::new(1);
425    }
426    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
427    pub struct Oed_SPEC;
428    pub type Oed = crate::EnumBitfieldStruct<u8, Oed_SPEC>;
429    impl Oed {
430        #[doc = "Endian formats are the same between the chip and input data."]
431        pub const _0: Self = Self::new(0);
432
433        #[doc = "Endian formats are different between the chip and input data."]
434        pub const _1: Self = Self::new(1);
435    }
436    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
437    pub struct Oen_SPEC;
438    pub type Oen = crate::EnumBitfieldStruct<u8, Oen_SPEC>;
439    impl Oen {
440        #[doc = "Output data FIFO full interrupt is disabled."]
441        pub const _0: Self = Self::new(0);
442
443        #[doc = "Output data FIFO full interrupt is enabled."]
444        pub const _1: Self = Self::new(1);
445    }
446    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
447    pub struct Oftrg_SPEC;
448    pub type Oftrg = crate::EnumBitfieldStruct<u8, Oftrg_SPEC>;
449    impl Oftrg {
450        #[doc = "1"]
451        pub const _00: Self = Self::new(0);
452
453        #[doc = "4"]
454        pub const _01: Self = Self::new(1);
455
456        #[doc = "8"]
457        pub const _10: Self = Self::new(2);
458
459        #[doc = "12"]
460        pub const _11: Self = Self::new(3);
461    }
462}
463#[doc(hidden)]
464#[derive(Copy, Clone, Eq, PartialEq)]
465pub struct Srcctrl_SPEC;
466impl crate::sealed::RegSpec for Srcctrl_SPEC {
467    type DataType = u16;
468}
469
470#[doc = "Control Register"]
471pub type Srcctrl = crate::RegValueT<Srcctrl_SPEC>;
472
473impl Srcctrl {
474    #[doc = "Filter Coefficient Table Access Enable"]
475    #[inline(always)]
476    pub fn ficrae(
477        self,
478    ) -> crate::common::RegisterField<
479        15,
480        0x1,
481        1,
482        0,
483        srcctrl::Ficrae,
484        srcctrl::Ficrae,
485        Srcctrl_SPEC,
486        crate::common::RW,
487    > {
488        crate::common::RegisterField::<
489            15,
490            0x1,
491            1,
492            0,
493            srcctrl::Ficrae,
494            srcctrl::Ficrae,
495            Srcctrl_SPEC,
496            crate::common::RW,
497        >::from_register(self, 0)
498    }
499
500    #[doc = "Conversion End Interrupt Enable"]
501    #[inline(always)]
502    pub fn ceen(
503        self,
504    ) -> crate::common::RegisterField<
505        13,
506        0x1,
507        1,
508        0,
509        srcctrl::Ceen,
510        srcctrl::Ceen,
511        Srcctrl_SPEC,
512        crate::common::RW,
513    > {
514        crate::common::RegisterField::<
515            13,
516            0x1,
517            1,
518            0,
519            srcctrl::Ceen,
520            srcctrl::Ceen,
521            Srcctrl_SPEC,
522            crate::common::RW,
523        >::from_register(self, 0)
524    }
525
526    #[doc = "Module Enable"]
527    #[inline(always)]
528    pub fn srcen(
529        self,
530    ) -> crate::common::RegisterField<
531        12,
532        0x1,
533        1,
534        0,
535        srcctrl::Srcen,
536        srcctrl::Srcen,
537        Srcctrl_SPEC,
538        crate::common::RW,
539    > {
540        crate::common::RegisterField::<
541            12,
542            0x1,
543            1,
544            0,
545            srcctrl::Srcen,
546            srcctrl::Srcen,
547            Srcctrl_SPEC,
548            crate::common::RW,
549        >::from_register(self, 0)
550    }
551
552    #[doc = "Output Data FIFO Underflow Interrupt Enable"]
553    #[inline(always)]
554    pub fn uden(
555        self,
556    ) -> crate::common::RegisterField<
557        11,
558        0x1,
559        1,
560        0,
561        srcctrl::Uden,
562        srcctrl::Uden,
563        Srcctrl_SPEC,
564        crate::common::RW,
565    > {
566        crate::common::RegisterField::<
567            11,
568            0x1,
569            1,
570            0,
571            srcctrl::Uden,
572            srcctrl::Uden,
573            Srcctrl_SPEC,
574            crate::common::RW,
575        >::from_register(self, 0)
576    }
577
578    #[doc = "Output Data FIFO Overwrite Interrupt Enable"]
579    #[inline(always)]
580    pub fn oven(
581        self,
582    ) -> crate::common::RegisterField<
583        10,
584        0x1,
585        1,
586        0,
587        srcctrl::Oven,
588        srcctrl::Oven,
589        Srcctrl_SPEC,
590        crate::common::RW,
591    > {
592        crate::common::RegisterField::<
593            10,
594            0x1,
595            1,
596            0,
597            srcctrl::Oven,
598            srcctrl::Oven,
599            Srcctrl_SPEC,
600            crate::common::RW,
601        >::from_register(self, 0)
602    }
603
604    #[doc = "Internal Work Memory Flush"]
605    #[inline(always)]
606    pub fn fl(
607        self,
608    ) -> crate::common::RegisterField<
609        9,
610        0x1,
611        1,
612        0,
613        srcctrl::Fl,
614        srcctrl::Fl,
615        Srcctrl_SPEC,
616        crate::common::W,
617    > {
618        crate::common::RegisterField::<
619            9,
620            0x1,
621            1,
622            0,
623            srcctrl::Fl,
624            srcctrl::Fl,
625            Srcctrl_SPEC,
626            crate::common::W,
627        >::from_register(self, 0)
628    }
629
630    #[doc = "Internal Work Memory Clear"]
631    #[inline(always)]
632    pub fn cl(
633        self,
634    ) -> crate::common::RegisterField<
635        8,
636        0x1,
637        1,
638        0,
639        srcctrl::Cl,
640        srcctrl::Cl,
641        Srcctrl_SPEC,
642        crate::common::W,
643    > {
644        crate::common::RegisterField::<
645            8,
646            0x1,
647            1,
648            0,
649            srcctrl::Cl,
650            srcctrl::Cl,
651            Srcctrl_SPEC,
652            crate::common::W,
653        >::from_register(self, 0)
654    }
655
656    #[doc = "Input Sampling Rate"]
657    #[inline(always)]
658    pub fn ifs(
659        self,
660    ) -> crate::common::RegisterField<
661        4,
662        0xf,
663        1,
664        0,
665        srcctrl::Ifs,
666        srcctrl::Ifs,
667        Srcctrl_SPEC,
668        crate::common::RW,
669    > {
670        crate::common::RegisterField::<
671            4,
672            0xf,
673            1,
674            0,
675            srcctrl::Ifs,
676            srcctrl::Ifs,
677            Srcctrl_SPEC,
678            crate::common::RW,
679        >::from_register(self, 0)
680    }
681
682    #[doc = "Output Sampling Rate"]
683    #[inline(always)]
684    pub fn ofs(
685        self,
686    ) -> crate::common::RegisterField<
687        0,
688        0x7,
689        1,
690        0,
691        srcctrl::Ofs,
692        srcctrl::Ofs,
693        Srcctrl_SPEC,
694        crate::common::RW,
695    > {
696        crate::common::RegisterField::<
697            0,
698            0x7,
699            1,
700            0,
701            srcctrl::Ofs,
702            srcctrl::Ofs,
703            Srcctrl_SPEC,
704            crate::common::RW,
705        >::from_register(self, 0)
706    }
707}
708impl ::core::default::Default for Srcctrl {
709    #[inline(always)]
710    fn default() -> Srcctrl {
711        <crate::RegValueT<Srcctrl_SPEC> as RegisterValue<_>>::new(0)
712    }
713}
714pub mod srcctrl {
715
716    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
717    pub struct Ficrae_SPEC;
718    pub type Ficrae = crate::EnumBitfieldStruct<u8, Ficrae_SPEC>;
719    impl Ficrae {
720        #[doc = "Reading/writing to filter coefficient table RAM is disabled."]
721        pub const _0: Self = Self::new(0);
722
723        #[doc = "Reading/writing to filter coefficient table RAM is enabled."]
724        pub const _1: Self = Self::new(1);
725    }
726    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
727    pub struct Ceen_SPEC;
728    pub type Ceen = crate::EnumBitfieldStruct<u8, Ceen_SPEC>;
729    impl Ceen {
730        #[doc = "Disables conversion end interrupt requests."]
731        pub const _0: Self = Self::new(0);
732
733        #[doc = "Enables conversion end interrupt requests."]
734        pub const _1: Self = Self::new(1);
735    }
736    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
737    pub struct Srcen_SPEC;
738    pub type Srcen = crate::EnumBitfieldStruct<u8, Srcen_SPEC>;
739    impl Srcen {
740        #[doc = "Disables this module operation."]
741        pub const _0: Self = Self::new(0);
742
743        #[doc = "Enables this module operation."]
744        pub const _1: Self = Self::new(1);
745    }
746    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
747    pub struct Uden_SPEC;
748    pub type Uden = crate::EnumBitfieldStruct<u8, Uden_SPEC>;
749    impl Uden {
750        #[doc = "Disables output data FIFO underflow interrupt requests."]
751        pub const _0: Self = Self::new(0);
752
753        #[doc = "Enables output data FIFO underflow interrupt requests."]
754        pub const _1: Self = Self::new(1);
755    }
756    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
757    pub struct Oven_SPEC;
758    pub type Oven = crate::EnumBitfieldStruct<u8, Oven_SPEC>;
759    impl Oven {
760        #[doc = "Output data FIFO overwrite interrupt is disabled."]
761        pub const _0: Self = Self::new(0);
762
763        #[doc = "Output data FIFO overwrite interrupt is enabled."]
764        pub const _1: Self = Self::new(1);
765    }
766    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
767    pub struct Fl_SPEC;
768    pub type Fl = crate::EnumBitfieldStruct<u8, Fl_SPEC>;
769    impl Fl {
770        #[doc = "no effect"]
771        pub const _0: Self = Self::new(0);
772
773        #[doc = "starts converting the sampling rate of all the data in the input FIFO, input buffer memory, and intermediate memory(i.e., flush processing)."]
774        pub const _1: Self = Self::new(1);
775    }
776    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
777    pub struct Cl_SPEC;
778    pub type Cl = crate::EnumBitfieldStruct<u8, Cl_SPEC>;
779    impl Cl {
780        #[doc = "no effect"]
781        pub const _0: Self = Self::new(0);
782
783        #[doc = "Clears the input FIFO, output FIFO, input buffer memory, intermediate memory and accumulator."]
784        pub const _1: Self = Self::new(1);
785    }
786    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
787    pub struct Ifs_SPEC;
788    pub type Ifs = crate::EnumBitfieldStruct<u8, Ifs_SPEC>;
789    impl Ifs {
790        #[doc = "8.0 kHz"]
791        pub const _0000: Self = Self::new(0);
792
793        #[doc = "11.025 kHz"]
794        pub const _0001: Self = Self::new(1);
795
796        #[doc = "12.0 kHz"]
797        pub const _0010: Self = Self::new(2);
798
799        #[doc = "Setting prohibited"]
800        pub const _0011: Self = Self::new(3);
801
802        #[doc = "16.0 kHz"]
803        pub const _0100: Self = Self::new(4);
804
805        #[doc = "22.05 kHz"]
806        pub const _0101: Self = Self::new(5);
807
808        #[doc = "24.0 kHz"]
809        pub const _0110: Self = Self::new(6);
810
811        #[doc = "Setting prohibited"]
812        pub const _0111: Self = Self::new(7);
813
814        #[doc = "32.0 kHz"]
815        pub const _1000: Self = Self::new(8);
816
817        #[doc = "44.1 kHz"]
818        pub const _1001: Self = Self::new(9);
819
820        #[doc = "48.0 kHz"]
821        pub const _1010: Self = Self::new(10);
822
823        #[doc = "Settings prohibited."]
824        pub const OTHERS: Self = Self::new(0);
825    }
826    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
827    pub struct Ofs_SPEC;
828    pub type Ofs = crate::EnumBitfieldStruct<u8, Ofs_SPEC>;
829    impl Ofs {
830        #[doc = "44.1 kHz"]
831        pub const _000: Self = Self::new(0);
832
833        #[doc = "48.0 kHz"]
834        pub const _001: Self = Self::new(1);
835
836        #[doc = "32.0 kHz"]
837        pub const _010: Self = Self::new(2);
838
839        #[doc = "Setting prohibited"]
840        pub const _011: Self = Self::new(3);
841
842        #[doc = "8.0 kHz  ( Valid only when IFS\\[3:0\\] =1001b )"]
843        pub const _100: Self = Self::new(4);
844
845        #[doc = "16.0 kHz  ( Valid only when IFS\\[3:0\\] =1001b )"]
846        pub const _101: Self = Self::new(5);
847
848        #[doc = "Settings other than above are prohibited."]
849        pub const OTHERS: Self = Self::new(0);
850    }
851}
852#[doc(hidden)]
853#[derive(Copy, Clone, Eq, PartialEq)]
854pub struct Srcstat_SPEC;
855impl crate::sealed::RegSpec for Srcstat_SPEC {
856    type DataType = u16;
857}
858
859#[doc = "Status Register"]
860pub type Srcstat = crate::RegValueT<Srcstat_SPEC>;
861
862impl Srcstat {
863    #[doc = "Output FIFO Data Count"]
864    #[inline(always)]
865    pub fn ofdn(
866        self,
867    ) -> crate::common::RegisterField<
868        11,
869        0x1f,
870        1,
871        0,
872        srcstat::Ofdn,
873        srcstat::Ofdn,
874        Srcstat_SPEC,
875        crate::common::R,
876    > {
877        crate::common::RegisterField::<
878            11,
879            0x1f,
880            1,
881            0,
882            srcstat::Ofdn,
883            srcstat::Ofdn,
884            Srcstat_SPEC,
885            crate::common::R,
886        >::from_register(self, 0)
887    }
888
889    #[doc = "Input FIFO Data Count"]
890    #[inline(always)]
891    pub fn ifdn(
892        self,
893    ) -> crate::common::RegisterField<
894        7,
895        0xf,
896        1,
897        0,
898        srcstat::Ifdn,
899        srcstat::Ifdn,
900        Srcstat_SPEC,
901        crate::common::R,
902    > {
903        crate::common::RegisterField::<
904            7,
905            0xf,
906            1,
907            0,
908            srcstat::Ifdn,
909            srcstat::Ifdn,
910            Srcstat_SPEC,
911            crate::common::R,
912        >::from_register(self, 0)
913    }
914
915    #[doc = "Conversion End Flag"]
916    #[inline(always)]
917    pub fn cef(
918        self,
919    ) -> crate::common::RegisterField<
920        5,
921        0x1,
922        1,
923        0,
924        srcstat::Cef,
925        srcstat::Cef,
926        Srcstat_SPEC,
927        crate::common::RW,
928    > {
929        crate::common::RegisterField::<
930            5,
931            0x1,
932            1,
933            0,
934            srcstat::Cef,
935            srcstat::Cef,
936            Srcstat_SPEC,
937            crate::common::RW,
938        >::from_register(self, 0)
939    }
940
941    #[doc = "Flush Processing Status Flag"]
942    #[inline(always)]
943    pub fn flf(
944        self,
945    ) -> crate::common::RegisterField<
946        4,
947        0x1,
948        1,
949        0,
950        srcstat::Flf,
951        srcstat::Flf,
952        Srcstat_SPEC,
953        crate::common::R,
954    > {
955        crate::common::RegisterField::<
956            4,
957            0x1,
958            1,
959            0,
960            srcstat::Flf,
961            srcstat::Flf,
962            Srcstat_SPEC,
963            crate::common::R,
964        >::from_register(self, 0)
965    }
966
967    #[doc = "Output FIFO Underflow Interrupt Request Flag"]
968    #[inline(always)]
969    pub fn udf(
970        self,
971    ) -> crate::common::RegisterField<
972        3,
973        0x1,
974        1,
975        0,
976        srcstat::Udf,
977        srcstat::Udf,
978        Srcstat_SPEC,
979        crate::common::RW,
980    > {
981        crate::common::RegisterField::<
982            3,
983            0x1,
984            1,
985            0,
986            srcstat::Udf,
987            srcstat::Udf,
988            Srcstat_SPEC,
989            crate::common::RW,
990        >::from_register(self, 0)
991    }
992
993    #[doc = "Output Data FIFO Overwrite Interrupt Request Flag"]
994    #[inline(always)]
995    pub fn ovf(
996        self,
997    ) -> crate::common::RegisterField<
998        2,
999        0x1,
1000        1,
1001        0,
1002        srcstat::Ovf,
1003        srcstat::Ovf,
1004        Srcstat_SPEC,
1005        crate::common::RW,
1006    > {
1007        crate::common::RegisterField::<
1008            2,
1009            0x1,
1010            1,
1011            0,
1012            srcstat::Ovf,
1013            srcstat::Ovf,
1014            Srcstat_SPEC,
1015            crate::common::RW,
1016        >::from_register(self, 0)
1017    }
1018
1019    #[doc = "Input Data FIFO Empty Interrupt Request Flag"]
1020    #[inline(always)]
1021    pub fn iint(
1022        self,
1023    ) -> crate::common::RegisterField<
1024        1,
1025        0x1,
1026        1,
1027        0,
1028        srcstat::Iint,
1029        srcstat::Iint,
1030        Srcstat_SPEC,
1031        crate::common::RW,
1032    > {
1033        crate::common::RegisterField::<
1034            1,
1035            0x1,
1036            1,
1037            0,
1038            srcstat::Iint,
1039            srcstat::Iint,
1040            Srcstat_SPEC,
1041            crate::common::RW,
1042        >::from_register(self, 0)
1043    }
1044
1045    #[doc = "Output Data FIFO Full Interrupt Request Flag"]
1046    #[inline(always)]
1047    pub fn oint(
1048        self,
1049    ) -> crate::common::RegisterField<
1050        0,
1051        0x1,
1052        1,
1053        0,
1054        srcstat::Oint,
1055        srcstat::Oint,
1056        Srcstat_SPEC,
1057        crate::common::RW,
1058    > {
1059        crate::common::RegisterField::<
1060            0,
1061            0x1,
1062            1,
1063            0,
1064            srcstat::Oint,
1065            srcstat::Oint,
1066            Srcstat_SPEC,
1067            crate::common::RW,
1068        >::from_register(self, 0)
1069    }
1070}
1071impl ::core::default::Default for Srcstat {
1072    #[inline(always)]
1073    fn default() -> Srcstat {
1074        <crate::RegValueT<Srcstat_SPEC> as RegisterValue<_>>::new(2)
1075    }
1076}
1077pub mod srcstat {
1078
1079    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1080    pub struct Ofdn_SPEC;
1081    pub type Ofdn = crate::EnumBitfieldStruct<u8, Ofdn_SPEC>;
1082    impl Ofdn {
1083        #[doc = "The value of OFDN indicatethe number of data units in the output FIFO."]
1084        pub const OFDN: Self = Self::new(0);
1085    }
1086    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1087    pub struct Ifdn_SPEC;
1088    pub type Ifdn = crate::EnumBitfieldStruct<u8, Ifdn_SPEC>;
1089    impl Ifdn {
1090        #[doc = "The value of IFDN indicatethe number of data units in the input FIFO."]
1091        pub const IFDN: Self = Self::new(0);
1092    }
1093    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1094    pub struct Cef_SPEC;
1095    pub type Cef = crate::EnumBitfieldStruct<u8, Cef_SPEC>;
1096    impl Cef {
1097        #[doc = "All of the output data has not been read out."]
1098        pub const _0: Self = Self::new(0);
1099
1100        #[doc = "All of the output data has been read out."]
1101        pub const _1: Self = Self::new(1);
1102    }
1103    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1104    pub struct Flf_SPEC;
1105    pub type Flf = crate::EnumBitfieldStruct<u8, Flf_SPEC>;
1106    impl Flf {
1107        #[doc = "Flash processing is completed."]
1108        pub const _0: Self = Self::new(0);
1109
1110        #[doc = "Flash processing is in progress."]
1111        pub const _1: Self = Self::new(1);
1112    }
1113    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1114    pub struct Udf_SPEC;
1115    pub type Udf = crate::EnumBitfieldStruct<u8, Udf_SPEC>;
1116    impl Udf {
1117        #[doc = "Output data FIFO has not been read out."]
1118        pub const _0: Self = Self::new(0);
1119
1120        #[doc = "Output data FIFO has been read out."]
1121        pub const _1: Self = Self::new(1);
1122    }
1123    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1124    pub struct Ovf_SPEC;
1125    pub type Ovf = crate::EnumBitfieldStruct<u8, Ovf_SPEC>;
1126    impl Ovf {
1127        #[doc = "Next data conversion processing is not completed."]
1128        pub const _0: Self = Self::new(0);
1129
1130        #[doc = "Next data conversion processing is completed."]
1131        pub const _1: Self = Self::new(1);
1132    }
1133    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1134    pub struct Iint_SPEC;
1135    pub type Iint = crate::EnumBitfieldStruct<u8, Iint_SPEC>;
1136    impl Iint {
1137        #[doc = "Number of data units in the input FIFO has not become equal to or smaller than the specified triggering number."]
1138        pub const _0: Self = Self::new(0);
1139
1140        #[doc = "Number of data units in the input FIFO has become equal to or smaller than the specified triggering number."]
1141        pub const _1: Self = Self::new(1);
1142    }
1143    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1144    pub struct Oint_SPEC;
1145    pub type Oint = crate::EnumBitfieldStruct<u8, Oint_SPEC>;
1146    impl Oint {
1147        #[doc = "Number of data units in the output FIFO has not become equal to or greater than the specified triggering number."]
1148        pub const _0: Self = Self::new(0);
1149
1150        #[doc = "Number of data units in the output FIFO has become equal to or greater than the specified triggering number."]
1151        pub const _1: Self = Self::new(1);
1152    }
1153}
ra6t1_pac/src.rs

ra6t1_pac/
src.rs
