ra6m4/usbfs/
dfifosel.rs

1#[doc = "Register `D%sFIFOSEL` reader"]
2pub struct R(crate::R<DFIFOSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DFIFOSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DFIFOSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DFIFOSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `D%sFIFOSEL` writer"]
17pub struct W(crate::W<DFIFOSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DFIFOSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DFIFOSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DFIFOSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CURPIPE` reader - FIFO Port Access Pipe Specification"]
38pub type CURPIPE_R = crate::FieldReader<u8, CURPIPE_A>;
39#[doc = "FIFO Port Access Pipe Specification\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CURPIPE_A {
43    #[doc = "0: Default Control Pipe"]
44    _0X0 = 0,
45    #[doc = "1: Pipe 1"]
46    _0X1 = 1,
47    #[doc = "2: Pipe 2"]
48    _0X2 = 2,
49    #[doc = "3: Pipe 3"]
50    _0X3 = 3,
51    #[doc = "4: Pipe 4"]
52    _0X4 = 4,
53    #[doc = "5: Pipe 5"]
54    _0X5 = 5,
55    #[doc = "6: Pipe 6"]
56    _0X6 = 6,
57    #[doc = "7: Pipe 7"]
58    _0X7 = 7,
59    #[doc = "8: Pipe 8"]
60    _0X8 = 8,
61    #[doc = "9: Pipe 9"]
62    _0X9 = 9,
63}
64impl From<CURPIPE_A> for u8 {
65    #[inline(always)]
66    fn from(variant: CURPIPE_A) -> Self {
67        variant as _
68    }
69}
70impl CURPIPE_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> Option<CURPIPE_A> {
74        match self.bits {
75            0 => Some(CURPIPE_A::_0X0),
76            1 => Some(CURPIPE_A::_0X1),
77            2 => Some(CURPIPE_A::_0X2),
78            3 => Some(CURPIPE_A::_0X3),
79            4 => Some(CURPIPE_A::_0X4),
80            5 => Some(CURPIPE_A::_0X5),
81            6 => Some(CURPIPE_A::_0X6),
82            7 => Some(CURPIPE_A::_0X7),
83            8 => Some(CURPIPE_A::_0X8),
84            9 => Some(CURPIPE_A::_0X9),
85            _ => None,
86        }
87    }
88    #[doc = "Checks if the value of the field is `_0X0`"]
89    #[inline(always)]
90    pub fn is_0x0(&self) -> bool {
91        *self == CURPIPE_A::_0X0
92    }
93    #[doc = "Checks if the value of the field is `_0X1`"]
94    #[inline(always)]
95    pub fn is_0x1(&self) -> bool {
96        *self == CURPIPE_A::_0X1
97    }
98    #[doc = "Checks if the value of the field is `_0X2`"]
99    #[inline(always)]
100    pub fn is_0x2(&self) -> bool {
101        *self == CURPIPE_A::_0X2
102    }
103    #[doc = "Checks if the value of the field is `_0X3`"]
104    #[inline(always)]
105    pub fn is_0x3(&self) -> bool {
106        *self == CURPIPE_A::_0X3
107    }
108    #[doc = "Checks if the value of the field is `_0X4`"]
109    #[inline(always)]
110    pub fn is_0x4(&self) -> bool {
111        *self == CURPIPE_A::_0X4
112    }
113    #[doc = "Checks if the value of the field is `_0X5`"]
114    #[inline(always)]
115    pub fn is_0x5(&self) -> bool {
116        *self == CURPIPE_A::_0X5
117    }
118    #[doc = "Checks if the value of the field is `_0X6`"]
119    #[inline(always)]
120    pub fn is_0x6(&self) -> bool {
121        *self == CURPIPE_A::_0X6
122    }
123    #[doc = "Checks if the value of the field is `_0X7`"]
124    #[inline(always)]
125    pub fn is_0x7(&self) -> bool {
126        *self == CURPIPE_A::_0X7
127    }
128    #[doc = "Checks if the value of the field is `_0X8`"]
129    #[inline(always)]
130    pub fn is_0x8(&self) -> bool {
131        *self == CURPIPE_A::_0X8
132    }
133    #[doc = "Checks if the value of the field is `_0X9`"]
134    #[inline(always)]
135    pub fn is_0x9(&self) -> bool {
136        *self == CURPIPE_A::_0X9
137    }
138}
139#[doc = "Field `CURPIPE` writer - FIFO Port Access Pipe Specification"]
140pub type CURPIPE_W<'a, const O: u8> =
141    crate::FieldWriter<'a, u16, DFIFOSEL_SPEC, u8, CURPIPE_A, 4, O>;
142impl<'a, const O: u8> CURPIPE_W<'a, O> {
143    #[doc = "Default Control Pipe"]
144    #[inline(always)]
145    pub fn _0x0(self) -> &'a mut W {
146        self.variant(CURPIPE_A::_0X0)
147    }
148    #[doc = "Pipe 1"]
149    #[inline(always)]
150    pub fn _0x1(self) -> &'a mut W {
151        self.variant(CURPIPE_A::_0X1)
152    }
153    #[doc = "Pipe 2"]
154    #[inline(always)]
155    pub fn _0x2(self) -> &'a mut W {
156        self.variant(CURPIPE_A::_0X2)
157    }
158    #[doc = "Pipe 3"]
159    #[inline(always)]
160    pub fn _0x3(self) -> &'a mut W {
161        self.variant(CURPIPE_A::_0X3)
162    }
163    #[doc = "Pipe 4"]
164    #[inline(always)]
165    pub fn _0x4(self) -> &'a mut W {
166        self.variant(CURPIPE_A::_0X4)
167    }
168    #[doc = "Pipe 5"]
169    #[inline(always)]
170    pub fn _0x5(self) -> &'a mut W {
171        self.variant(CURPIPE_A::_0X5)
172    }
173    #[doc = "Pipe 6"]
174    #[inline(always)]
175    pub fn _0x6(self) -> &'a mut W {
176        self.variant(CURPIPE_A::_0X6)
177    }
178    #[doc = "Pipe 7"]
179    #[inline(always)]
180    pub fn _0x7(self) -> &'a mut W {
181        self.variant(CURPIPE_A::_0X7)
182    }
183    #[doc = "Pipe 8"]
184    #[inline(always)]
185    pub fn _0x8(self) -> &'a mut W {
186        self.variant(CURPIPE_A::_0X8)
187    }
188    #[doc = "Pipe 9"]
189    #[inline(always)]
190    pub fn _0x9(self) -> &'a mut W {
191        self.variant(CURPIPE_A::_0X9)
192    }
193}
194#[doc = "Field `BIGEND` reader - FIFO Port Endian Control"]
195pub type BIGEND_R = crate::BitReader<BIGEND_A>;
196#[doc = "FIFO Port Endian Control\n\nValue on reset: 0"]
197#[derive(Clone, Copy, Debug, PartialEq, Eq)]
198pub enum BIGEND_A {
199    #[doc = "0: Little endian"]
200    _0 = 0,
201    #[doc = "1: Big endian"]
202    _1 = 1,
203}
204impl From<BIGEND_A> for bool {
205    #[inline(always)]
206    fn from(variant: BIGEND_A) -> Self {
207        variant as u8 != 0
208    }
209}
210impl BIGEND_R {
211    #[doc = "Get enumerated values variant"]
212    #[inline(always)]
213    pub fn variant(&self) -> BIGEND_A {
214        match self.bits {
215            false => BIGEND_A::_0,
216            true => BIGEND_A::_1,
217        }
218    }
219    #[doc = "Checks if the value of the field is `_0`"]
220    #[inline(always)]
221    pub fn is_0(&self) -> bool {
222        *self == BIGEND_A::_0
223    }
224    #[doc = "Checks if the value of the field is `_1`"]
225    #[inline(always)]
226    pub fn is_1(&self) -> bool {
227        *self == BIGEND_A::_1
228    }
229}
230#[doc = "Field `BIGEND` writer - FIFO Port Endian Control"]
231pub type BIGEND_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFIFOSEL_SPEC, BIGEND_A, O>;
232impl<'a, const O: u8> BIGEND_W<'a, O> {
233    #[doc = "Little endian"]
234    #[inline(always)]
235    pub fn _0(self) -> &'a mut W {
236        self.variant(BIGEND_A::_0)
237    }
238    #[doc = "Big endian"]
239    #[inline(always)]
240    pub fn _1(self) -> &'a mut W {
241        self.variant(BIGEND_A::_1)
242    }
243}
244#[doc = "Field `MBW` reader - FIFO Port Access Bit Width"]
245pub type MBW_R = crate::BitReader<MBW_A>;
246#[doc = "FIFO Port Access Bit Width\n\nValue on reset: 0"]
247#[derive(Clone, Copy, Debug, PartialEq, Eq)]
248pub enum MBW_A {
249    #[doc = "0: 8-bit width"]
250    _0 = 0,
251    #[doc = "1: 16-bit width"]
252    _1 = 1,
253}
254impl From<MBW_A> for bool {
255    #[inline(always)]
256    fn from(variant: MBW_A) -> Self {
257        variant as u8 != 0
258    }
259}
260impl MBW_R {
261    #[doc = "Get enumerated values variant"]
262    #[inline(always)]
263    pub fn variant(&self) -> MBW_A {
264        match self.bits {
265            false => MBW_A::_0,
266            true => MBW_A::_1,
267        }
268    }
269    #[doc = "Checks if the value of the field is `_0`"]
270    #[inline(always)]
271    pub fn is_0(&self) -> bool {
272        *self == MBW_A::_0
273    }
274    #[doc = "Checks if the value of the field is `_1`"]
275    #[inline(always)]
276    pub fn is_1(&self) -> bool {
277        *self == MBW_A::_1
278    }
279}
280#[doc = "Field `MBW` writer - FIFO Port Access Bit Width"]
281pub type MBW_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFIFOSEL_SPEC, MBW_A, O>;
282impl<'a, const O: u8> MBW_W<'a, O> {
283    #[doc = "8-bit width"]
284    #[inline(always)]
285    pub fn _0(self) -> &'a mut W {
286        self.variant(MBW_A::_0)
287    }
288    #[doc = "16-bit width"]
289    #[inline(always)]
290    pub fn _1(self) -> &'a mut W {
291        self.variant(MBW_A::_1)
292    }
293}
294#[doc = "Field `DREQE` reader - DMA/DTC Transfer Request Enable"]
295pub type DREQE_R = crate::BitReader<DREQE_A>;
296#[doc = "DMA/DTC Transfer Request Enable\n\nValue on reset: 0"]
297#[derive(Clone, Copy, Debug, PartialEq, Eq)]
298pub enum DREQE_A {
299    #[doc = "0: Disable DMA/DTC transfer request"]
300    _0 = 0,
301    #[doc = "1: Enable DMA/DTC transfer request"]
302    _1 = 1,
303}
304impl From<DREQE_A> for bool {
305    #[inline(always)]
306    fn from(variant: DREQE_A) -> Self {
307        variant as u8 != 0
308    }
309}
310impl DREQE_R {
311    #[doc = "Get enumerated values variant"]
312    #[inline(always)]
313    pub fn variant(&self) -> DREQE_A {
314        match self.bits {
315            false => DREQE_A::_0,
316            true => DREQE_A::_1,
317        }
318    }
319    #[doc = "Checks if the value of the field is `_0`"]
320    #[inline(always)]
321    pub fn is_0(&self) -> bool {
322        *self == DREQE_A::_0
323    }
324    #[doc = "Checks if the value of the field is `_1`"]
325    #[inline(always)]
326    pub fn is_1(&self) -> bool {
327        *self == DREQE_A::_1
328    }
329}
330#[doc = "Field `DREQE` writer - DMA/DTC Transfer Request Enable"]
331pub type DREQE_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFIFOSEL_SPEC, DREQE_A, O>;
332impl<'a, const O: u8> DREQE_W<'a, O> {
333    #[doc = "Disable DMA/DTC transfer request"]
334    #[inline(always)]
335    pub fn _0(self) -> &'a mut W {
336        self.variant(DREQE_A::_0)
337    }
338    #[doc = "Enable DMA/DTC transfer request"]
339    #[inline(always)]
340    pub fn _1(self) -> &'a mut W {
341        self.variant(DREQE_A::_1)
342    }
343}
344#[doc = "Field `DCLRM` reader - Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read"]
345pub type DCLRM_R = crate::BitReader<DCLRM_A>;
346#[doc = "Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read\n\nValue on reset: 0"]
347#[derive(Clone, Copy, Debug, PartialEq, Eq)]
348pub enum DCLRM_A {
349    #[doc = "0: Disable auto buffer clear mode"]
350    _0 = 0,
351    #[doc = "1: Enable auto buffer clear mode"]
352    _1 = 1,
353}
354impl From<DCLRM_A> for bool {
355    #[inline(always)]
356    fn from(variant: DCLRM_A) -> Self {
357        variant as u8 != 0
358    }
359}
360impl DCLRM_R {
361    #[doc = "Get enumerated values variant"]
362    #[inline(always)]
363    pub fn variant(&self) -> DCLRM_A {
364        match self.bits {
365            false => DCLRM_A::_0,
366            true => DCLRM_A::_1,
367        }
368    }
369    #[doc = "Checks if the value of the field is `_0`"]
370    #[inline(always)]
371    pub fn is_0(&self) -> bool {
372        *self == DCLRM_A::_0
373    }
374    #[doc = "Checks if the value of the field is `_1`"]
375    #[inline(always)]
376    pub fn is_1(&self) -> bool {
377        *self == DCLRM_A::_1
378    }
379}
380#[doc = "Field `DCLRM` writer - Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read"]
381pub type DCLRM_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFIFOSEL_SPEC, DCLRM_A, O>;
382impl<'a, const O: u8> DCLRM_W<'a, O> {
383    #[doc = "Disable auto buffer clear mode"]
384    #[inline(always)]
385    pub fn _0(self) -> &'a mut W {
386        self.variant(DCLRM_A::_0)
387    }
388    #[doc = "Enable auto buffer clear mode"]
389    #[inline(always)]
390    pub fn _1(self) -> &'a mut W {
391        self.variant(DCLRM_A::_1)
392    }
393}
394#[doc = "Buffer Pointer Rewind\n\nValue on reset: 0"]
395#[derive(Clone, Copy, Debug, PartialEq, Eq)]
396pub enum REW_AW {
397    #[doc = "0: Do not rewind buffer pointer"]
398    _0 = 0,
399    #[doc = "1: Rewind buffer pointer"]
400    _1 = 1,
401}
402impl From<REW_AW> for bool {
403    #[inline(always)]
404    fn from(variant: REW_AW) -> Self {
405        variant as u8 != 0
406    }
407}
408#[doc = "Field `REW` writer - Buffer Pointer Rewind"]
409pub type REW_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFIFOSEL_SPEC, REW_AW, O>;
410impl<'a, const O: u8> REW_W<'a, O> {
411    #[doc = "Do not rewind buffer pointer"]
412    #[inline(always)]
413    pub fn _0(self) -> &'a mut W {
414        self.variant(REW_AW::_0)
415    }
416    #[doc = "Rewind buffer pointer"]
417    #[inline(always)]
418    pub fn _1(self) -> &'a mut W {
419        self.variant(REW_AW::_1)
420    }
421}
422#[doc = "Field `RCNT` reader - Read Count Mode"]
423pub type RCNT_R = crate::BitReader<RCNT_A>;
424#[doc = "Read Count Mode\n\nValue on reset: 0"]
425#[derive(Clone, Copy, Debug, PartialEq, Eq)]
426pub enum RCNT_A {
427    #[doc = "0: Clear DTLN\\[8:0\\]
428bits in (CFIFOCTR.DTLN\\[8:0\\], D0FIFOCTR.DTLN\\[8:0\\], D1FIFOCTR.DTLN\\[8:0\\]) when all receive data is read from DnFIFO (after read of a single plane in double buffer mode)"]
429    _0 = 0,
430    #[doc = "1: Decrement DTLN\\[8:0\\]
431bits each time receive data is read from DnFIFO"]
432    _1 = 1,
433}
434impl From<RCNT_A> for bool {
435    #[inline(always)]
436    fn from(variant: RCNT_A) -> Self {
437        variant as u8 != 0
438    }
439}
440impl RCNT_R {
441    #[doc = "Get enumerated values variant"]
442    #[inline(always)]
443    pub fn variant(&self) -> RCNT_A {
444        match self.bits {
445            false => RCNT_A::_0,
446            true => RCNT_A::_1,
447        }
448    }
449    #[doc = "Checks if the value of the field is `_0`"]
450    #[inline(always)]
451    pub fn is_0(&self) -> bool {
452        *self == RCNT_A::_0
453    }
454    #[doc = "Checks if the value of the field is `_1`"]
455    #[inline(always)]
456    pub fn is_1(&self) -> bool {
457        *self == RCNT_A::_1
458    }
459}
460#[doc = "Field `RCNT` writer - Read Count Mode"]
461pub type RCNT_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFIFOSEL_SPEC, RCNT_A, O>;
462impl<'a, const O: u8> RCNT_W<'a, O> {
463    #[doc = "Clear DTLN\\[8:0\\]
464bits in (CFIFOCTR.DTLN\\[8:0\\], D0FIFOCTR.DTLN\\[8:0\\], D1FIFOCTR.DTLN\\[8:0\\]) when all receive data is read from DnFIFO (after read of a single plane in double buffer mode)"]
465    #[inline(always)]
466    pub fn _0(self) -> &'a mut W {
467        self.variant(RCNT_A::_0)
468    }
469    #[doc = "Decrement DTLN\\[8:0\\]
470bits each time receive data is read from DnFIFO"]
471    #[inline(always)]
472    pub fn _1(self) -> &'a mut W {
473        self.variant(RCNT_A::_1)
474    }
475}
476impl R {
477    #[doc = "Bits 0:3 - FIFO Port Access Pipe Specification"]
478    #[inline(always)]
479    pub fn curpipe(&self) -> CURPIPE_R {
480        CURPIPE_R::new((self.bits & 0x0f) as u8)
481    }
482    #[doc = "Bit 8 - FIFO Port Endian Control"]
483    #[inline(always)]
484    pub fn bigend(&self) -> BIGEND_R {
485        BIGEND_R::new(((self.bits >> 8) & 1) != 0)
486    }
487    #[doc = "Bit 10 - FIFO Port Access Bit Width"]
488    #[inline(always)]
489    pub fn mbw(&self) -> MBW_R {
490        MBW_R::new(((self.bits >> 10) & 1) != 0)
491    }
492    #[doc = "Bit 12 - DMA/DTC Transfer Request Enable"]
493    #[inline(always)]
494    pub fn dreqe(&self) -> DREQE_R {
495        DREQE_R::new(((self.bits >> 12) & 1) != 0)
496    }
497    #[doc = "Bit 13 - Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read"]
498    #[inline(always)]
499    pub fn dclrm(&self) -> DCLRM_R {
500        DCLRM_R::new(((self.bits >> 13) & 1) != 0)
501    }
502    #[doc = "Bit 15 - Read Count Mode"]
503    #[inline(always)]
504    pub fn rcnt(&self) -> RCNT_R {
505        RCNT_R::new(((self.bits >> 15) & 1) != 0)
506    }
507}
508impl W {
509    #[doc = "Bits 0:3 - FIFO Port Access Pipe Specification"]
510    #[inline(always)]
511    #[must_use]
512    pub fn curpipe(&mut self) -> CURPIPE_W<0> {
513        CURPIPE_W::new(self)
514    }
515    #[doc = "Bit 8 - FIFO Port Endian Control"]
516    #[inline(always)]
517    #[must_use]
518    pub fn bigend(&mut self) -> BIGEND_W<8> {
519        BIGEND_W::new(self)
520    }
521    #[doc = "Bit 10 - FIFO Port Access Bit Width"]
522    #[inline(always)]
523    #[must_use]
524    pub fn mbw(&mut self) -> MBW_W<10> {
525        MBW_W::new(self)
526    }
527    #[doc = "Bit 12 - DMA/DTC Transfer Request Enable"]
528    #[inline(always)]
529    #[must_use]
530    pub fn dreqe(&mut self) -> DREQE_W<12> {
531        DREQE_W::new(self)
532    }
533    #[doc = "Bit 13 - Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read"]
534    #[inline(always)]
535    #[must_use]
536    pub fn dclrm(&mut self) -> DCLRM_W<13> {
537        DCLRM_W::new(self)
538    }
539    #[doc = "Bit 14 - Buffer Pointer Rewind"]
540    #[inline(always)]
541    #[must_use]
542    pub fn rew(&mut self) -> REW_W<14> {
543        REW_W::new(self)
544    }
545    #[doc = "Bit 15 - Read Count Mode"]
546    #[inline(always)]
547    #[must_use]
548    pub fn rcnt(&mut self) -> RCNT_W<15> {
549        RCNT_W::new(self)
550    }
551    #[doc = "Writes raw bits to the register."]
552    #[inline(always)]
553    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
554        self.0.bits(bits);
555        self
556    }
557}
558#[doc = "D%sFIFO Port Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfifosel](index.html) module"]
559pub struct DFIFOSEL_SPEC;
560impl crate::RegisterSpec for DFIFOSEL_SPEC {
561    type Ux = u16;
562}
563#[doc = "`read()` method returns [dfifosel::R](R) reader structure"]
564impl crate::Readable for DFIFOSEL_SPEC {
565    type Reader = R;
566}
567#[doc = "`write(|w| ..)` method takes [dfifosel::W](W) writer structure"]
568impl crate::Writable for DFIFOSEL_SPEC {
569    type Writer = W;
570    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
571    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
572}
573#[doc = "`reset()` method sets D%sFIFOSEL to value 0"]
574impl crate::Resettable for DFIFOSEL_SPEC {
575    const RESET_VALUE: Self::Ux = 0;
576}
ra6m4/usbfs/dfifosel.rs

ra6m4/usbfs/
dfifosel.rs
