ra6m4/spi0/
spcr3.rs

1#[doc = "Register `SPCR3` reader"]
2pub struct R(crate::R<SPCR3_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SPCR3_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SPCR3_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SPCR3_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SPCR3` writer"]
17pub struct W(crate::W<SPCR3_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SPCR3_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SPCR3_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SPCR3_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ETXMD` reader - Extended Communication Mode Select"]
38pub type ETXMD_R = crate::BitReader<ETXMD_A>;
39#[doc = "Extended Communication Mode Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum ETXMD_A {
42    #[doc = "0: Full-duplex synchronous or transmit-only serial communications. \\[the SPCR.TXMD bit is enabled\\]"]
43    _0 = 0,
44    #[doc = "1: Receive-only serial communications in slave mode (SPCR.MSTR bit = 0). \\[the SPCR.TXMD bit is disabled\\]
45Setting is prohibited in master mode (SPCR.MSTR bit = 1)."]
46    _1 = 1,
47}
48impl From<ETXMD_A> for bool {
49    #[inline(always)]
50    fn from(variant: ETXMD_A) -> Self {
51        variant as u8 != 0
52    }
53}
54impl ETXMD_R {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub fn variant(&self) -> ETXMD_A {
58        match self.bits {
59            false => ETXMD_A::_0,
60            true => ETXMD_A::_1,
61        }
62    }
63    #[doc = "Checks if the value of the field is `_0`"]
64    #[inline(always)]
65    pub fn is_0(&self) -> bool {
66        *self == ETXMD_A::_0
67    }
68    #[doc = "Checks if the value of the field is `_1`"]
69    #[inline(always)]
70    pub fn is_1(&self) -> bool {
71        *self == ETXMD_A::_1
72    }
73}
74#[doc = "Field `ETXMD` writer - Extended Communication Mode Select"]
75pub type ETXMD_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPCR3_SPEC, ETXMD_A, O>;
76impl<'a, const O: u8> ETXMD_W<'a, O> {
77    #[doc = "Full-duplex synchronous or transmit-only serial communications. \\[the SPCR.TXMD bit is enabled\\]"]
78    #[inline(always)]
79    pub fn _0(self) -> &'a mut W {
80        self.variant(ETXMD_A::_0)
81    }
82    #[doc = "Receive-only serial communications in slave mode (SPCR.MSTR bit = 0). \\[the SPCR.TXMD bit is disabled\\]
83Setting is prohibited in master mode (SPCR.MSTR bit = 1)."]
84    #[inline(always)]
85    pub fn _1(self) -> &'a mut W {
86        self.variant(ETXMD_A::_1)
87    }
88}
89#[doc = "Field `BFDS` reader - Between Burst Transfer Frames Delay Select"]
90pub type BFDS_R = crate::BitReader<BFDS_A>;
91#[doc = "Between Burst Transfer Frames Delay Select\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq, Eq)]
93pub enum BFDS_A {
94    #[doc = "0: Delay (RSPCK delay, SSL negation delay and next-access delay) between frames is inserted in burst transfer."]
95    _0 = 0,
96    #[doc = "1: Delay between frames is not inserted in burst transfer."]
97    _1 = 1,
98}
99impl From<BFDS_A> for bool {
100    #[inline(always)]
101    fn from(variant: BFDS_A) -> Self {
102        variant as u8 != 0
103    }
104}
105impl BFDS_R {
106    #[doc = "Get enumerated values variant"]
107    #[inline(always)]
108    pub fn variant(&self) -> BFDS_A {
109        match self.bits {
110            false => BFDS_A::_0,
111            true => BFDS_A::_1,
112        }
113    }
114    #[doc = "Checks if the value of the field is `_0`"]
115    #[inline(always)]
116    pub fn is_0(&self) -> bool {
117        *self == BFDS_A::_0
118    }
119    #[doc = "Checks if the value of the field is `_1`"]
120    #[inline(always)]
121    pub fn is_1(&self) -> bool {
122        *self == BFDS_A::_1
123    }
124}
125#[doc = "Field `BFDS` writer - Between Burst Transfer Frames Delay Select"]
126pub type BFDS_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPCR3_SPEC, BFDS_A, O>;
127impl<'a, const O: u8> BFDS_W<'a, O> {
128    #[doc = "Delay (RSPCK delay, SSL negation delay and next-access delay) between frames is inserted in burst transfer."]
129    #[inline(always)]
130    pub fn _0(self) -> &'a mut W {
131        self.variant(BFDS_A::_0)
132    }
133    #[doc = "Delay between frames is not inserted in burst transfer."]
134    #[inline(always)]
135    pub fn _1(self) -> &'a mut W {
136        self.variant(BFDS_A::_1)
137    }
138}
139#[doc = "Field `CENDIE` reader - RSPI Communication End Interrupt Enable"]
140pub type CENDIE_R = crate::BitReader<CENDIE_A>;
141#[doc = "RSPI Communication End Interrupt Enable\n\nValue on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum CENDIE_A {
144    #[doc = "0: Communication end interrupt request is disabled."]
145    _0 = 0,
146    #[doc = "1: Communication end interrupt request is enabled."]
147    _1 = 1,
148}
149impl From<CENDIE_A> for bool {
150    #[inline(always)]
151    fn from(variant: CENDIE_A) -> Self {
152        variant as u8 != 0
153    }
154}
155impl CENDIE_R {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub fn variant(&self) -> CENDIE_A {
159        match self.bits {
160            false => CENDIE_A::_0,
161            true => CENDIE_A::_1,
162        }
163    }
164    #[doc = "Checks if the value of the field is `_0`"]
165    #[inline(always)]
166    pub fn is_0(&self) -> bool {
167        *self == CENDIE_A::_0
168    }
169    #[doc = "Checks if the value of the field is `_1`"]
170    #[inline(always)]
171    pub fn is_1(&self) -> bool {
172        *self == CENDIE_A::_1
173    }
174}
175#[doc = "Field `CENDIE` writer - RSPI Communication End Interrupt Enable"]
176pub type CENDIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPCR3_SPEC, CENDIE_A, O>;
177impl<'a, const O: u8> CENDIE_W<'a, O> {
178    #[doc = "Communication end interrupt request is disabled."]
179    #[inline(always)]
180    pub fn _0(self) -> &'a mut W {
181        self.variant(CENDIE_A::_0)
182    }
183    #[doc = "Communication end interrupt request is enabled."]
184    #[inline(always)]
185    pub fn _1(self) -> &'a mut W {
186        self.variant(CENDIE_A::_1)
187    }
188}
189impl R {
190    #[doc = "Bit 0 - Extended Communication Mode Select"]
191    #[inline(always)]
192    pub fn etxmd(&self) -> ETXMD_R {
193        ETXMD_R::new((self.bits & 1) != 0)
194    }
195    #[doc = "Bit 1 - Between Burst Transfer Frames Delay Select"]
196    #[inline(always)]
197    pub fn bfds(&self) -> BFDS_R {
198        BFDS_R::new(((self.bits >> 1) & 1) != 0)
199    }
200    #[doc = "Bit 4 - RSPI Communication End Interrupt Enable"]
201    #[inline(always)]
202    pub fn cendie(&self) -> CENDIE_R {
203        CENDIE_R::new(((self.bits >> 4) & 1) != 0)
204    }
205}
206impl W {
207    #[doc = "Bit 0 - Extended Communication Mode Select"]
208    #[inline(always)]
209    #[must_use]
210    pub fn etxmd(&mut self) -> ETXMD_W<0> {
211        ETXMD_W::new(self)
212    }
213    #[doc = "Bit 1 - Between Burst Transfer Frames Delay Select"]
214    #[inline(always)]
215    #[must_use]
216    pub fn bfds(&mut self) -> BFDS_W<1> {
217        BFDS_W::new(self)
218    }
219    #[doc = "Bit 4 - RSPI Communication End Interrupt Enable"]
220    #[inline(always)]
221    #[must_use]
222    pub fn cendie(&mut self) -> CENDIE_W<4> {
223        CENDIE_W::new(self)
224    }
225    #[doc = "Writes raw bits to the register."]
226    #[inline(always)]
227    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
228        self.0.bits(bits);
229        self
230    }
231}
232#[doc = "SPI Control Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spcr3](index.html) module"]
233pub struct SPCR3_SPEC;
234impl crate::RegisterSpec for SPCR3_SPEC {
235    type Ux = u8;
236}
237#[doc = "`read()` method returns [spcr3::R](R) reader structure"]
238impl crate::Readable for SPCR3_SPEC {
239    type Reader = R;
240}
241#[doc = "`write(|w| ..)` method takes [spcr3::W](W) writer structure"]
242impl crate::Writable for SPCR3_SPEC {
243    type Writer = W;
244    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
245    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
246}
247#[doc = "`reset()` method sets SPCR3 to value 0"]
248impl crate::Resettable for SPCR3_SPEC {
249    const RESET_VALUE: Self::Ux = 0;
250}
ra6m4/spi0/spcr3.rs

ra6m4/spi0/
spcr3.rs
