ra6m3/usbfs/
cfifosel.rs

1#[doc = "Register `CFIFOSEL` reader"]
2pub struct R(crate::R<CFIFOSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFIFOSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFIFOSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFIFOSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CFIFOSEL` writer"]
17pub struct W(crate::W<CFIFOSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFIFOSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFIFOSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFIFOSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CURPIPE` reader - CFIFO Port Access Pipe Specification"]
38pub type CURPIPE_R = crate::FieldReader<u8, CURPIPE_A>;
39#[doc = "CFIFO Port Access Pipe Specification\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CURPIPE_A {
43    #[doc = "0: DCP (Default control pipe)"]
44    _0000 = 0,
45    #[doc = "1: Pipe 1"]
46    _0001 = 1,
47    #[doc = "2: Pipe 2"]
48    _0010 = 2,
49    #[doc = "3: Pipe 3"]
50    _0011 = 3,
51    #[doc = "4: Pipe 4"]
52    _0100 = 4,
53    #[doc = "5: Pipe 5"]
54    _0101 = 5,
55    #[doc = "6: Pipe 6"]
56    _0110 = 6,
57    #[doc = "7: Pipe 7"]
58    _0111 = 7,
59    #[doc = "8: Pipe 8"]
60    _1000 = 8,
61    #[doc = "9: Pipe 9"]
62    _1001 = 9,
63}
64impl From<CURPIPE_A> for u8 {
65    #[inline(always)]
66    fn from(variant: CURPIPE_A) -> Self {
67        variant as _
68    }
69}
70impl CURPIPE_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> Option<CURPIPE_A> {
74        match self.bits {
75            0 => Some(CURPIPE_A::_0000),
76            1 => Some(CURPIPE_A::_0001),
77            2 => Some(CURPIPE_A::_0010),
78            3 => Some(CURPIPE_A::_0011),
79            4 => Some(CURPIPE_A::_0100),
80            5 => Some(CURPIPE_A::_0101),
81            6 => Some(CURPIPE_A::_0110),
82            7 => Some(CURPIPE_A::_0111),
83            8 => Some(CURPIPE_A::_1000),
84            9 => Some(CURPIPE_A::_1001),
85            _ => None,
86        }
87    }
88    #[doc = "Checks if the value of the field is `_0000`"]
89    #[inline(always)]
90    pub fn is_0000(&self) -> bool {
91        *self == CURPIPE_A::_0000
92    }
93    #[doc = "Checks if the value of the field is `_0001`"]
94    #[inline(always)]
95    pub fn is_0001(&self) -> bool {
96        *self == CURPIPE_A::_0001
97    }
98    #[doc = "Checks if the value of the field is `_0010`"]
99    #[inline(always)]
100    pub fn is_0010(&self) -> bool {
101        *self == CURPIPE_A::_0010
102    }
103    #[doc = "Checks if the value of the field is `_0011`"]
104    #[inline(always)]
105    pub fn is_0011(&self) -> bool {
106        *self == CURPIPE_A::_0011
107    }
108    #[doc = "Checks if the value of the field is `_0100`"]
109    #[inline(always)]
110    pub fn is_0100(&self) -> bool {
111        *self == CURPIPE_A::_0100
112    }
113    #[doc = "Checks if the value of the field is `_0101`"]
114    #[inline(always)]
115    pub fn is_0101(&self) -> bool {
116        *self == CURPIPE_A::_0101
117    }
118    #[doc = "Checks if the value of the field is `_0110`"]
119    #[inline(always)]
120    pub fn is_0110(&self) -> bool {
121        *self == CURPIPE_A::_0110
122    }
123    #[doc = "Checks if the value of the field is `_0111`"]
124    #[inline(always)]
125    pub fn is_0111(&self) -> bool {
126        *self == CURPIPE_A::_0111
127    }
128    #[doc = "Checks if the value of the field is `_1000`"]
129    #[inline(always)]
130    pub fn is_1000(&self) -> bool {
131        *self == CURPIPE_A::_1000
132    }
133    #[doc = "Checks if the value of the field is `_1001`"]
134    #[inline(always)]
135    pub fn is_1001(&self) -> bool {
136        *self == CURPIPE_A::_1001
137    }
138}
139#[doc = "Field `CURPIPE` writer - CFIFO Port Access Pipe Specification"]
140pub type CURPIPE_W<'a, const O: u8> =
141    crate::FieldWriter<'a, u16, CFIFOSEL_SPEC, u8, CURPIPE_A, 4, O>;
142impl<'a, const O: u8> CURPIPE_W<'a, O> {
143    #[doc = "DCP (Default control pipe)"]
144    #[inline(always)]
145    pub fn _0000(self) -> &'a mut W {
146        self.variant(CURPIPE_A::_0000)
147    }
148    #[doc = "Pipe 1"]
149    #[inline(always)]
150    pub fn _0001(self) -> &'a mut W {
151        self.variant(CURPIPE_A::_0001)
152    }
153    #[doc = "Pipe 2"]
154    #[inline(always)]
155    pub fn _0010(self) -> &'a mut W {
156        self.variant(CURPIPE_A::_0010)
157    }
158    #[doc = "Pipe 3"]
159    #[inline(always)]
160    pub fn _0011(self) -> &'a mut W {
161        self.variant(CURPIPE_A::_0011)
162    }
163    #[doc = "Pipe 4"]
164    #[inline(always)]
165    pub fn _0100(self) -> &'a mut W {
166        self.variant(CURPIPE_A::_0100)
167    }
168    #[doc = "Pipe 5"]
169    #[inline(always)]
170    pub fn _0101(self) -> &'a mut W {
171        self.variant(CURPIPE_A::_0101)
172    }
173    #[doc = "Pipe 6"]
174    #[inline(always)]
175    pub fn _0110(self) -> &'a mut W {
176        self.variant(CURPIPE_A::_0110)
177    }
178    #[doc = "Pipe 7"]
179    #[inline(always)]
180    pub fn _0111(self) -> &'a mut W {
181        self.variant(CURPIPE_A::_0111)
182    }
183    #[doc = "Pipe 8"]
184    #[inline(always)]
185    pub fn _1000(self) -> &'a mut W {
186        self.variant(CURPIPE_A::_1000)
187    }
188    #[doc = "Pipe 9"]
189    #[inline(always)]
190    pub fn _1001(self) -> &'a mut W {
191        self.variant(CURPIPE_A::_1001)
192    }
193}
194#[doc = "Field `ISEL` reader - CFIFO Port Access Direction When DCP is Selected"]
195pub type ISEL_R = crate::BitReader<ISEL_A>;
196#[doc = "CFIFO Port Access Direction When DCP is Selected\n\nValue on reset: 0"]
197#[derive(Clone, Copy, Debug, PartialEq, Eq)]
198pub enum ISEL_A {
199    #[doc = "0: Reading from the buffer memory is selected"]
200    _0 = 0,
201    #[doc = "1: Writing to the buffer memory is selected"]
202    _1 = 1,
203}
204impl From<ISEL_A> for bool {
205    #[inline(always)]
206    fn from(variant: ISEL_A) -> Self {
207        variant as u8 != 0
208    }
209}
210impl ISEL_R {
211    #[doc = "Get enumerated values variant"]
212    #[inline(always)]
213    pub fn variant(&self) -> ISEL_A {
214        match self.bits {
215            false => ISEL_A::_0,
216            true => ISEL_A::_1,
217        }
218    }
219    #[doc = "Checks if the value of the field is `_0`"]
220    #[inline(always)]
221    pub fn is_0(&self) -> bool {
222        *self == ISEL_A::_0
223    }
224    #[doc = "Checks if the value of the field is `_1`"]
225    #[inline(always)]
226    pub fn is_1(&self) -> bool {
227        *self == ISEL_A::_1
228    }
229}
230#[doc = "Field `ISEL` writer - CFIFO Port Access Direction When DCP is Selected"]
231pub type ISEL_W<'a, const O: u8> = crate::BitWriter<'a, u16, CFIFOSEL_SPEC, ISEL_A, O>;
232impl<'a, const O: u8> ISEL_W<'a, O> {
233    #[doc = "Reading from the buffer memory is selected"]
234    #[inline(always)]
235    pub fn _0(self) -> &'a mut W {
236        self.variant(ISEL_A::_0)
237    }
238    #[doc = "Writing to the buffer memory is selected"]
239    #[inline(always)]
240    pub fn _1(self) -> &'a mut W {
241        self.variant(ISEL_A::_1)
242    }
243}
244#[doc = "Field `BIGEND` reader - CFIFO Port Endian Control"]
245pub type BIGEND_R = crate::BitReader<BIGEND_A>;
246#[doc = "CFIFO Port Endian Control\n\nValue on reset: 0"]
247#[derive(Clone, Copy, Debug, PartialEq, Eq)]
248pub enum BIGEND_A {
249    #[doc = "0: Little endian"]
250    _0 = 0,
251    #[doc = "1: Big endian"]
252    _1 = 1,
253}
254impl From<BIGEND_A> for bool {
255    #[inline(always)]
256    fn from(variant: BIGEND_A) -> Self {
257        variant as u8 != 0
258    }
259}
260impl BIGEND_R {
261    #[doc = "Get enumerated values variant"]
262    #[inline(always)]
263    pub fn variant(&self) -> BIGEND_A {
264        match self.bits {
265            false => BIGEND_A::_0,
266            true => BIGEND_A::_1,
267        }
268    }
269    #[doc = "Checks if the value of the field is `_0`"]
270    #[inline(always)]
271    pub fn is_0(&self) -> bool {
272        *self == BIGEND_A::_0
273    }
274    #[doc = "Checks if the value of the field is `_1`"]
275    #[inline(always)]
276    pub fn is_1(&self) -> bool {
277        *self == BIGEND_A::_1
278    }
279}
280#[doc = "Field `BIGEND` writer - CFIFO Port Endian Control"]
281pub type BIGEND_W<'a, const O: u8> = crate::BitWriter<'a, u16, CFIFOSEL_SPEC, BIGEND_A, O>;
282impl<'a, const O: u8> BIGEND_W<'a, O> {
283    #[doc = "Little endian"]
284    #[inline(always)]
285    pub fn _0(self) -> &'a mut W {
286        self.variant(BIGEND_A::_0)
287    }
288    #[doc = "Big endian"]
289    #[inline(always)]
290    pub fn _1(self) -> &'a mut W {
291        self.variant(BIGEND_A::_1)
292    }
293}
294#[doc = "Field `MBW` reader - CFIFO Port Access Bit Width"]
295pub type MBW_R = crate::BitReader<MBW_A>;
296#[doc = "CFIFO Port Access Bit Width\n\nValue on reset: 0"]
297#[derive(Clone, Copy, Debug, PartialEq, Eq)]
298pub enum MBW_A {
299    #[doc = "0: 8-bit width"]
300    _0 = 0,
301    #[doc = "1: 16-bit width"]
302    _1 = 1,
303}
304impl From<MBW_A> for bool {
305    #[inline(always)]
306    fn from(variant: MBW_A) -> Self {
307        variant as u8 != 0
308    }
309}
310impl MBW_R {
311    #[doc = "Get enumerated values variant"]
312    #[inline(always)]
313    pub fn variant(&self) -> MBW_A {
314        match self.bits {
315            false => MBW_A::_0,
316            true => MBW_A::_1,
317        }
318    }
319    #[doc = "Checks if the value of the field is `_0`"]
320    #[inline(always)]
321    pub fn is_0(&self) -> bool {
322        *self == MBW_A::_0
323    }
324    #[doc = "Checks if the value of the field is `_1`"]
325    #[inline(always)]
326    pub fn is_1(&self) -> bool {
327        *self == MBW_A::_1
328    }
329}
330#[doc = "Field `MBW` writer - CFIFO Port Access Bit Width"]
331pub type MBW_W<'a, const O: u8> = crate::BitWriter<'a, u16, CFIFOSEL_SPEC, MBW_A, O>;
332impl<'a, const O: u8> MBW_W<'a, O> {
333    #[doc = "8-bit width"]
334    #[inline(always)]
335    pub fn _0(self) -> &'a mut W {
336        self.variant(MBW_A::_0)
337    }
338    #[doc = "16-bit width"]
339    #[inline(always)]
340    pub fn _1(self) -> &'a mut W {
341        self.variant(MBW_A::_1)
342    }
343}
344#[doc = "Field `REW` reader - Buffer Pointer Rewind"]
345pub type REW_R = crate::BitReader<REW_A>;
346#[doc = "Buffer Pointer Rewind\n\nValue on reset: 0"]
347#[derive(Clone, Copy, Debug, PartialEq, Eq)]
348pub enum REW_A {
349    #[doc = "0: The buffer pointer is not rewound."]
350    _0 = 0,
351    #[doc = "1: The buffer pointer is rewound."]
352    _1 = 1,
353}
354impl From<REW_A> for bool {
355    #[inline(always)]
356    fn from(variant: REW_A) -> Self {
357        variant as u8 != 0
358    }
359}
360impl REW_R {
361    #[doc = "Get enumerated values variant"]
362    #[inline(always)]
363    pub fn variant(&self) -> REW_A {
364        match self.bits {
365            false => REW_A::_0,
366            true => REW_A::_1,
367        }
368    }
369    #[doc = "Checks if the value of the field is `_0`"]
370    #[inline(always)]
371    pub fn is_0(&self) -> bool {
372        *self == REW_A::_0
373    }
374    #[doc = "Checks if the value of the field is `_1`"]
375    #[inline(always)]
376    pub fn is_1(&self) -> bool {
377        *self == REW_A::_1
378    }
379}
380#[doc = "Field `RCNT` reader - Read Count Mode"]
381pub type RCNT_R = crate::BitReader<RCNT_A>;
382#[doc = "Read Count Mode\n\nValue on reset: 0"]
383#[derive(Clone, Copy, Debug, PartialEq, Eq)]
384pub enum RCNT_A {
385    #[doc = "0: The DTLN\\[8:0\\]
386bits (CFIFOCRT.DTLN\\[8:0\\], D0FIFOCRT.DTLN\\[8:0\\], D1FIFOCRT.DTLN\\[8:0\\]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN\\[8:0\\]
387bit value is cleared when all the data has been read from only a single plane.)"]
388    _0 = 0,
389    #[doc = "1: The DTLN\\[8:0\\]
390bits are decremented each time the receive data is read from the CFIFO."]
391    _1 = 1,
392}
393impl From<RCNT_A> for bool {
394    #[inline(always)]
395    fn from(variant: RCNT_A) -> Self {
396        variant as u8 != 0
397    }
398}
399impl RCNT_R {
400    #[doc = "Get enumerated values variant"]
401    #[inline(always)]
402    pub fn variant(&self) -> RCNT_A {
403        match self.bits {
404            false => RCNT_A::_0,
405            true => RCNT_A::_1,
406        }
407    }
408    #[doc = "Checks if the value of the field is `_0`"]
409    #[inline(always)]
410    pub fn is_0(&self) -> bool {
411        *self == RCNT_A::_0
412    }
413    #[doc = "Checks if the value of the field is `_1`"]
414    #[inline(always)]
415    pub fn is_1(&self) -> bool {
416        *self == RCNT_A::_1
417    }
418}
419#[doc = "Field `RCNT` writer - Read Count Mode"]
420pub type RCNT_W<'a, const O: u8> = crate::BitWriter<'a, u16, CFIFOSEL_SPEC, RCNT_A, O>;
421impl<'a, const O: u8> RCNT_W<'a, O> {
422    #[doc = "The DTLN\\[8:0\\]
423bits (CFIFOCRT.DTLN\\[8:0\\], D0FIFOCRT.DTLN\\[8:0\\], D1FIFOCRT.DTLN\\[8:0\\]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN\\[8:0\\]
424bit value is cleared when all the data has been read from only a single plane.)"]
425    #[inline(always)]
426    pub fn _0(self) -> &'a mut W {
427        self.variant(RCNT_A::_0)
428    }
429    #[doc = "The DTLN\\[8:0\\]
430bits are decremented each time the receive data is read from the CFIFO."]
431    #[inline(always)]
432    pub fn _1(self) -> &'a mut W {
433        self.variant(RCNT_A::_1)
434    }
435}
436impl R {
437    #[doc = "Bits 0:3 - CFIFO Port Access Pipe Specification"]
438    #[inline(always)]
439    pub fn curpipe(&self) -> CURPIPE_R {
440        CURPIPE_R::new((self.bits & 0x0f) as u8)
441    }
442    #[doc = "Bit 5 - CFIFO Port Access Direction When DCP is Selected"]
443    #[inline(always)]
444    pub fn isel(&self) -> ISEL_R {
445        ISEL_R::new(((self.bits >> 5) & 1) != 0)
446    }
447    #[doc = "Bit 8 - CFIFO Port Endian Control"]
448    #[inline(always)]
449    pub fn bigend(&self) -> BIGEND_R {
450        BIGEND_R::new(((self.bits >> 8) & 1) != 0)
451    }
452    #[doc = "Bit 10 - CFIFO Port Access Bit Width"]
453    #[inline(always)]
454    pub fn mbw(&self) -> MBW_R {
455        MBW_R::new(((self.bits >> 10) & 1) != 0)
456    }
457    #[doc = "Bit 14 - Buffer Pointer Rewind"]
458    #[inline(always)]
459    pub fn rew(&self) -> REW_R {
460        REW_R::new(((self.bits >> 14) & 1) != 0)
461    }
462    #[doc = "Bit 15 - Read Count Mode"]
463    #[inline(always)]
464    pub fn rcnt(&self) -> RCNT_R {
465        RCNT_R::new(((self.bits >> 15) & 1) != 0)
466    }
467}
468impl W {
469    #[doc = "Bits 0:3 - CFIFO Port Access Pipe Specification"]
470    #[inline(always)]
471    #[must_use]
472    pub fn curpipe(&mut self) -> CURPIPE_W<0> {
473        CURPIPE_W::new(self)
474    }
475    #[doc = "Bit 5 - CFIFO Port Access Direction When DCP is Selected"]
476    #[inline(always)]
477    #[must_use]
478    pub fn isel(&mut self) -> ISEL_W<5> {
479        ISEL_W::new(self)
480    }
481    #[doc = "Bit 8 - CFIFO Port Endian Control"]
482    #[inline(always)]
483    #[must_use]
484    pub fn bigend(&mut self) -> BIGEND_W<8> {
485        BIGEND_W::new(self)
486    }
487    #[doc = "Bit 10 - CFIFO Port Access Bit Width"]
488    #[inline(always)]
489    #[must_use]
490    pub fn mbw(&mut self) -> MBW_W<10> {
491        MBW_W::new(self)
492    }
493    #[doc = "Bit 15 - Read Count Mode"]
494    #[inline(always)]
495    #[must_use]
496    pub fn rcnt(&mut self) -> RCNT_W<15> {
497        RCNT_W::new(self)
498    }
499    #[doc = "Writes raw bits to the register."]
500    #[inline(always)]
501    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
502        self.0.bits(bits);
503        self
504    }
505}
506#[doc = "CFIFO Port Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfifosel](index.html) module"]
507pub struct CFIFOSEL_SPEC;
508impl crate::RegisterSpec for CFIFOSEL_SPEC {
509    type Ux = u16;
510}
511#[doc = "`read()` method returns [cfifosel::R](R) reader structure"]
512impl crate::Readable for CFIFOSEL_SPEC {
513    type Reader = R;
514}
515#[doc = "`write(|w| ..)` method takes [cfifosel::W](W) writer structure"]
516impl crate::Writable for CFIFOSEL_SPEC {
517    type Writer = W;
518    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
519    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
520}
521#[doc = "`reset()` method sets CFIFOSEL to value 0"]
522impl crate::Resettable for CFIFOSEL_SPEC {
523    const RESET_VALUE: Self::Ux = 0;
524}
ra6m3/usbfs/cfifosel.rs

ra6m3/usbfs/
cfifosel.rs
