ra6m2/edmac0/
trimd.rs

1#[doc = "Register `TRIMD` reader"]
2pub struct R(crate::R<TRIMD_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TRIMD_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TRIMD_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TRIMD_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `TRIMD` writer"]
17pub struct W(crate::W<TRIMD_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<TRIMD_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<TRIMD_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<TRIMD_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TIS` reader - Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt."]
38pub type TIS_R = crate::BitReader<TIS_A>;
39#[doc = "Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt.\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum TIS_A {
42    #[doc = "0: Transmit Interrupt is disabled."]
43    _0 = 0,
44    #[doc = "1: Transmit Interrupt is enabled."]
45    _1 = 1,
46}
47impl From<TIS_A> for bool {
48    #[inline(always)]
49    fn from(variant: TIS_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl TIS_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> TIS_A {
57        match self.bits {
58            false => TIS_A::_0,
59            true => TIS_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == TIS_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == TIS_A::_1
71    }
72}
73#[doc = "Field `TIS` writer - Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt."]
74pub type TIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, TRIMD_SPEC, TIS_A, O>;
75impl<'a, const O: u8> TIS_W<'a, O> {
76    #[doc = "Transmit Interrupt is disabled."]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(TIS_A::_0)
80    }
81    #[doc = "Transmit Interrupt is enabled."]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(TIS_A::_1)
85    }
86}
87#[doc = "Field `TIM` reader - Transmit Interrupt Mode"]
88pub type TIM_R = crate::BitReader<TIM_A>;
89#[doc = "Transmit Interrupt Mode\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum TIM_A {
92    #[doc = "0: Transmission complete interrupt mode: An interrupt occurs when a frame has been transmitted."]
93    _0 = 0,
94    #[doc = "1: Write-back complete interrupt mode: An interrupt occurs when write-back to the transmit descriptor has been completed."]
95    _1 = 1,
96}
97impl From<TIM_A> for bool {
98    #[inline(always)]
99    fn from(variant: TIM_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl TIM_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> TIM_A {
107        match self.bits {
108            false => TIM_A::_0,
109            true => TIM_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == TIM_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == TIM_A::_1
121    }
122}
123#[doc = "Field `TIM` writer - Transmit Interrupt Mode"]
124pub type TIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, TRIMD_SPEC, TIM_A, O>;
125impl<'a, const O: u8> TIM_W<'a, O> {
126    #[doc = "Transmission complete interrupt mode: An interrupt occurs when a frame has been transmitted."]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(TIM_A::_0)
130    }
131    #[doc = "Write-back complete interrupt mode: An interrupt occurs when write-back to the transmit descriptor has been completed."]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(TIM_A::_1)
135    }
136}
137impl R {
138    #[doc = "Bit 0 - Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt."]
139    #[inline(always)]
140    pub fn tis(&self) -> TIS_R {
141        TIS_R::new((self.bits & 1) != 0)
142    }
143    #[doc = "Bit 4 - Transmit Interrupt Mode"]
144    #[inline(always)]
145    pub fn tim(&self) -> TIM_R {
146        TIM_R::new(((self.bits >> 4) & 1) != 0)
147    }
148}
149impl W {
150    #[doc = "Bit 0 - Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt."]
151    #[inline(always)]
152    #[must_use]
153    pub fn tis(&mut self) -> TIS_W<0> {
154        TIS_W::new(self)
155    }
156    #[doc = "Bit 4 - Transmit Interrupt Mode"]
157    #[inline(always)]
158    #[must_use]
159    pub fn tim(&mut self) -> TIM_W<4> {
160        TIM_W::new(self)
161    }
162    #[doc = "Writes raw bits to the register."]
163    #[inline(always)]
164    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
165        self.0.bits(bits);
166        self
167    }
168}
169#[doc = "Transmit Interrupt Setting Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [trimd](index.html) module"]
170pub struct TRIMD_SPEC;
171impl crate::RegisterSpec for TRIMD_SPEC {
172    type Ux = u32;
173}
174#[doc = "`read()` method returns [trimd::R](R) reader structure"]
175impl crate::Readable for TRIMD_SPEC {
176    type Reader = R;
177}
178#[doc = "`write(|w| ..)` method takes [trimd::W](W) writer structure"]
179impl crate::Writable for TRIMD_SPEC {
180    type Writer = W;
181    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
182    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
183}
184#[doc = "`reset()` method sets TRIMD to value 0"]
185impl crate::Resettable for TRIMD_SPEC {
186    const RESET_VALUE: Self::Ux = 0;
187}
ra6m2/edmac0/trimd.rs

ra6m2/edmac0/
trimd.rs
