1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"BUS Control"]
28unsafe impl ::core::marker::Send for super::Bus {}
29unsafe impl ::core::marker::Sync for super::Bus {}
30impl super::Bus {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "CS0 Control Register"]
38 #[inline(always)]
39 pub const fn cs0cr(&self) -> &'static crate::common::Reg<self::Cs0Cr_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Cs0Cr_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(2050usize),
43 )
44 }
45 }
46
47 #[doc = "CS%s Control Register"]
48 #[inline(always)]
49 pub const fn cscr(
50 &self,
51 ) -> &'static crate::common::ClusterRegisterArray<
52 crate::common::Reg<self::Cscr_SPEC, crate::common::RW>,
53 7,
54 0x10,
55 > {
56 unsafe {
57 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x812usize))
58 }
59 }
60 #[inline(always)]
61 pub const fn cs1cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
62 unsafe {
63 crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
64 self._svd2pac_as_ptr().add(0x812usize),
65 )
66 }
67 }
68 #[inline(always)]
69 pub const fn cs2cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
70 unsafe {
71 crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
72 self._svd2pac_as_ptr().add(0x822usize),
73 )
74 }
75 }
76 #[inline(always)]
77 pub const fn cs3cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
78 unsafe {
79 crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
80 self._svd2pac_as_ptr().add(0x832usize),
81 )
82 }
83 }
84 #[inline(always)]
85 pub const fn cs4cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
86 unsafe {
87 crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
88 self._svd2pac_as_ptr().add(0x842usize),
89 )
90 }
91 }
92 #[inline(always)]
93 pub const fn cs5cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
94 unsafe {
95 crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
96 self._svd2pac_as_ptr().add(0x852usize),
97 )
98 }
99 }
100 #[inline(always)]
101 pub const fn cs6cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
102 unsafe {
103 crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
104 self._svd2pac_as_ptr().add(0x862usize),
105 )
106 }
107 }
108 #[inline(always)]
109 pub const fn cs7cr(&self) -> &'static crate::common::Reg<self::Cscr_SPEC, crate::common::RW> {
110 unsafe {
111 crate::common::Reg::<self::Cscr_SPEC, crate::common::RW>::from_ptr(
112 self._svd2pac_as_ptr().add(0x872usize),
113 )
114 }
115 }
116
117 #[doc = "CS%s Recovery Cycle Register"]
118 #[inline(always)]
119 pub const fn csrec(
120 &self,
121 ) -> &'static crate::common::ClusterRegisterArray<
122 crate::common::Reg<self::Csrec_SPEC, crate::common::RW>,
123 8,
124 0x10,
125 > {
126 unsafe {
127 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x80ausize))
128 }
129 }
130 #[inline(always)]
131 pub const fn cs0rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
132 unsafe {
133 crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
134 self._svd2pac_as_ptr().add(0x80ausize),
135 )
136 }
137 }
138 #[inline(always)]
139 pub const fn cs1rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
140 unsafe {
141 crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
142 self._svd2pac_as_ptr().add(0x81ausize),
143 )
144 }
145 }
146 #[inline(always)]
147 pub const fn cs2rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
148 unsafe {
149 crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
150 self._svd2pac_as_ptr().add(0x82ausize),
151 )
152 }
153 }
154 #[inline(always)]
155 pub const fn cs3rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
156 unsafe {
157 crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
158 self._svd2pac_as_ptr().add(0x83ausize),
159 )
160 }
161 }
162 #[inline(always)]
163 pub const fn cs4rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
164 unsafe {
165 crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
166 self._svd2pac_as_ptr().add(0x84ausize),
167 )
168 }
169 }
170 #[inline(always)]
171 pub const fn cs5rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
172 unsafe {
173 crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
174 self._svd2pac_as_ptr().add(0x85ausize),
175 )
176 }
177 }
178 #[inline(always)]
179 pub const fn cs6rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
180 unsafe {
181 crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
182 self._svd2pac_as_ptr().add(0x86ausize),
183 )
184 }
185 }
186 #[inline(always)]
187 pub const fn cs7rec(&self) -> &'static crate::common::Reg<self::Csrec_SPEC, crate::common::RW> {
188 unsafe {
189 crate::common::Reg::<self::Csrec_SPEC, crate::common::RW>::from_ptr(
190 self._svd2pac_as_ptr().add(0x87ausize),
191 )
192 }
193 }
194
195 #[doc = "CS Recovery Cycle Insertion Enable Register"]
196 #[inline(always)]
197 pub const fn csrecen(
198 &self,
199 ) -> &'static crate::common::Reg<self::Csrecen_SPEC, crate::common::RW> {
200 unsafe {
201 crate::common::Reg::<self::Csrecen_SPEC, crate::common::RW>::from_ptr(
202 self._svd2pac_as_ptr().add(2176usize),
203 )
204 }
205 }
206
207 #[doc = "CS%s Mode Register"]
208 #[inline(always)]
209 pub const fn csmod(
210 &self,
211 ) -> &'static crate::common::ClusterRegisterArray<
212 crate::common::Reg<self::Csmod_SPEC, crate::common::RW>,
213 8,
214 0x10,
215 > {
216 unsafe {
217 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x2usize))
218 }
219 }
220 #[inline(always)]
221 pub const fn cs0mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
222 unsafe {
223 crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
224 self._svd2pac_as_ptr().add(0x2usize),
225 )
226 }
227 }
228 #[inline(always)]
229 pub const fn cs1mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
230 unsafe {
231 crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
232 self._svd2pac_as_ptr().add(0x12usize),
233 )
234 }
235 }
236 #[inline(always)]
237 pub const fn cs2mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
238 unsafe {
239 crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
240 self._svd2pac_as_ptr().add(0x22usize),
241 )
242 }
243 }
244 #[inline(always)]
245 pub const fn cs3mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
246 unsafe {
247 crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
248 self._svd2pac_as_ptr().add(0x32usize),
249 )
250 }
251 }
252 #[inline(always)]
253 pub const fn cs4mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
254 unsafe {
255 crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
256 self._svd2pac_as_ptr().add(0x42usize),
257 )
258 }
259 }
260 #[inline(always)]
261 pub const fn cs5mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
262 unsafe {
263 crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
264 self._svd2pac_as_ptr().add(0x52usize),
265 )
266 }
267 }
268 #[inline(always)]
269 pub const fn cs6mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
270 unsafe {
271 crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
272 self._svd2pac_as_ptr().add(0x62usize),
273 )
274 }
275 }
276 #[inline(always)]
277 pub const fn cs7mod(&self) -> &'static crate::common::Reg<self::Csmod_SPEC, crate::common::RW> {
278 unsafe {
279 crate::common::Reg::<self::Csmod_SPEC, crate::common::RW>::from_ptr(
280 self._svd2pac_as_ptr().add(0x72usize),
281 )
282 }
283 }
284
285 #[doc = "CS%s Wait Control Register 1"]
286 #[inline(always)]
287 pub const fn cswcr1(
288 &self,
289 ) -> &'static crate::common::ClusterRegisterArray<
290 crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW>,
291 8,
292 0x10,
293 > {
294 unsafe {
295 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x4usize))
296 }
297 }
298 #[inline(always)]
299 pub const fn cs0wcr1(
300 &self,
301 ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
302 unsafe {
303 crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
304 self._svd2pac_as_ptr().add(0x4usize),
305 )
306 }
307 }
308 #[inline(always)]
309 pub const fn cs1wcr1(
310 &self,
311 ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
312 unsafe {
313 crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
314 self._svd2pac_as_ptr().add(0x14usize),
315 )
316 }
317 }
318 #[inline(always)]
319 pub const fn cs2wcr1(
320 &self,
321 ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
322 unsafe {
323 crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
324 self._svd2pac_as_ptr().add(0x24usize),
325 )
326 }
327 }
328 #[inline(always)]
329 pub const fn cs3wcr1(
330 &self,
331 ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
332 unsafe {
333 crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
334 self._svd2pac_as_ptr().add(0x34usize),
335 )
336 }
337 }
338 #[inline(always)]
339 pub const fn cs4wcr1(
340 &self,
341 ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
342 unsafe {
343 crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
344 self._svd2pac_as_ptr().add(0x44usize),
345 )
346 }
347 }
348 #[inline(always)]
349 pub const fn cs5wcr1(
350 &self,
351 ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
352 unsafe {
353 crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
354 self._svd2pac_as_ptr().add(0x54usize),
355 )
356 }
357 }
358 #[inline(always)]
359 pub const fn cs6wcr1(
360 &self,
361 ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
362 unsafe {
363 crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
364 self._svd2pac_as_ptr().add(0x64usize),
365 )
366 }
367 }
368 #[inline(always)]
369 pub const fn cs7wcr1(
370 &self,
371 ) -> &'static crate::common::Reg<self::Cswcr1_SPEC, crate::common::RW> {
372 unsafe {
373 crate::common::Reg::<self::Cswcr1_SPEC, crate::common::RW>::from_ptr(
374 self._svd2pac_as_ptr().add(0x74usize),
375 )
376 }
377 }
378
379 #[doc = "CS%s Wait Control Register 2"]
380 #[inline(always)]
381 pub const fn cswcr2(
382 &self,
383 ) -> &'static crate::common::ClusterRegisterArray<
384 crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW>,
385 8,
386 0x10,
387 > {
388 unsafe {
389 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x8usize))
390 }
391 }
392 #[inline(always)]
393 pub const fn cs0wcr2(
394 &self,
395 ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
396 unsafe {
397 crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
398 self._svd2pac_as_ptr().add(0x8usize),
399 )
400 }
401 }
402 #[inline(always)]
403 pub const fn cs1wcr2(
404 &self,
405 ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
406 unsafe {
407 crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
408 self._svd2pac_as_ptr().add(0x18usize),
409 )
410 }
411 }
412 #[inline(always)]
413 pub const fn cs2wcr2(
414 &self,
415 ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
416 unsafe {
417 crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
418 self._svd2pac_as_ptr().add(0x28usize),
419 )
420 }
421 }
422 #[inline(always)]
423 pub const fn cs3wcr2(
424 &self,
425 ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
426 unsafe {
427 crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
428 self._svd2pac_as_ptr().add(0x38usize),
429 )
430 }
431 }
432 #[inline(always)]
433 pub const fn cs4wcr2(
434 &self,
435 ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
436 unsafe {
437 crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
438 self._svd2pac_as_ptr().add(0x48usize),
439 )
440 }
441 }
442 #[inline(always)]
443 pub const fn cs5wcr2(
444 &self,
445 ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
446 unsafe {
447 crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
448 self._svd2pac_as_ptr().add(0x58usize),
449 )
450 }
451 }
452 #[inline(always)]
453 pub const fn cs6wcr2(
454 &self,
455 ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
456 unsafe {
457 crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
458 self._svd2pac_as_ptr().add(0x68usize),
459 )
460 }
461 }
462 #[inline(always)]
463 pub const fn cs7wcr2(
464 &self,
465 ) -> &'static crate::common::Reg<self::Cswcr2_SPEC, crate::common::RW> {
466 unsafe {
467 crate::common::Reg::<self::Cswcr2_SPEC, crate::common::RW>::from_ptr(
468 self._svd2pac_as_ptr().add(0x78usize),
469 )
470 }
471 }
472
473 #[doc = "SDC Control Register"]
474 #[inline(always)]
475 pub const fn sdccr(&self) -> &'static crate::common::Reg<self::Sdccr_SPEC, crate::common::RW> {
476 unsafe {
477 crate::common::Reg::<self::Sdccr_SPEC, crate::common::RW>::from_ptr(
478 self._svd2pac_as_ptr().add(3072usize),
479 )
480 }
481 }
482
483 #[doc = "SDC Mode Register"]
484 #[inline(always)]
485 pub const fn sdcmod(
486 &self,
487 ) -> &'static crate::common::Reg<self::Sdcmod_SPEC, crate::common::RW> {
488 unsafe {
489 crate::common::Reg::<self::Sdcmod_SPEC, crate::common::RW>::from_ptr(
490 self._svd2pac_as_ptr().add(3073usize),
491 )
492 }
493 }
494
495 #[doc = "SDRAM Access Mode Register"]
496 #[inline(always)]
497 pub const fn sdamod(
498 &self,
499 ) -> &'static crate::common::Reg<self::Sdamod_SPEC, crate::common::RW> {
500 unsafe {
501 crate::common::Reg::<self::Sdamod_SPEC, crate::common::RW>::from_ptr(
502 self._svd2pac_as_ptr().add(3074usize),
503 )
504 }
505 }
506
507 #[doc = "SDRAM Self-Refresh Control Register"]
508 #[inline(always)]
509 pub const fn sdself(
510 &self,
511 ) -> &'static crate::common::Reg<self::Sdself_SPEC, crate::common::RW> {
512 unsafe {
513 crate::common::Reg::<self::Sdself_SPEC, crate::common::RW>::from_ptr(
514 self._svd2pac_as_ptr().add(3088usize),
515 )
516 }
517 }
518
519 #[doc = "SDRAM Refresh Control Register"]
520 #[inline(always)]
521 pub const fn sdrfcr(
522 &self,
523 ) -> &'static crate::common::Reg<self::Sdrfcr_SPEC, crate::common::RW> {
524 unsafe {
525 crate::common::Reg::<self::Sdrfcr_SPEC, crate::common::RW>::from_ptr(
526 self._svd2pac_as_ptr().add(3092usize),
527 )
528 }
529 }
530
531 #[doc = "SDRAM Auto-Refresh Control Register"]
532 #[inline(always)]
533 pub const fn sdrfen(
534 &self,
535 ) -> &'static crate::common::Reg<self::Sdrfen_SPEC, crate::common::RW> {
536 unsafe {
537 crate::common::Reg::<self::Sdrfen_SPEC, crate::common::RW>::from_ptr(
538 self._svd2pac_as_ptr().add(3094usize),
539 )
540 }
541 }
542
543 #[doc = "SDRAM Initialization Sequence Control Register"]
544 #[inline(always)]
545 pub const fn sdicr(&self) -> &'static crate::common::Reg<self::Sdicr_SPEC, crate::common::RW> {
546 unsafe {
547 crate::common::Reg::<self::Sdicr_SPEC, crate::common::RW>::from_ptr(
548 self._svd2pac_as_ptr().add(3104usize),
549 )
550 }
551 }
552
553 #[doc = "SDRAM Initialization Register"]
554 #[inline(always)]
555 pub const fn sdir(&self) -> &'static crate::common::Reg<self::Sdir_SPEC, crate::common::RW> {
556 unsafe {
557 crate::common::Reg::<self::Sdir_SPEC, crate::common::RW>::from_ptr(
558 self._svd2pac_as_ptr().add(3108usize),
559 )
560 }
561 }
562
563 #[doc = "SDRAM Address Register"]
564 #[inline(always)]
565 pub const fn sdadr(&self) -> &'static crate::common::Reg<self::Sdadr_SPEC, crate::common::RW> {
566 unsafe {
567 crate::common::Reg::<self::Sdadr_SPEC, crate::common::RW>::from_ptr(
568 self._svd2pac_as_ptr().add(3136usize),
569 )
570 }
571 }
572
573 #[doc = "SDRAM Timing Register"]
574 #[inline(always)]
575 pub const fn sdtr(&self) -> &'static crate::common::Reg<self::Sdtr_SPEC, crate::common::RW> {
576 unsafe {
577 crate::common::Reg::<self::Sdtr_SPEC, crate::common::RW>::from_ptr(
578 self._svd2pac_as_ptr().add(3140usize),
579 )
580 }
581 }
582
583 #[doc = "SDRAM Mode Register"]
584 #[inline(always)]
585 pub const fn sdmod(&self) -> &'static crate::common::Reg<self::Sdmod_SPEC, crate::common::RW> {
586 unsafe {
587 crate::common::Reg::<self::Sdmod_SPEC, crate::common::RW>::from_ptr(
588 self._svd2pac_as_ptr().add(3144usize),
589 )
590 }
591 }
592
593 #[doc = "SDRAM Status Register"]
594 #[inline(always)]
595 pub const fn sdsr(&self) -> &'static crate::common::Reg<self::Sdsr_SPEC, crate::common::R> {
596 unsafe {
597 crate::common::Reg::<self::Sdsr_SPEC, crate::common::R>::from_ptr(
598 self._svd2pac_as_ptr().add(3152usize),
599 )
600 }
601 }
602
603 #[doc = "Bus Error Address Register %s"]
604 #[inline(always)]
605 pub const fn buserradd(
606 &self,
607 ) -> &'static crate::common::ClusterRegisterArray<
608 crate::common::Reg<self::Buserradd_SPEC, crate::common::R>,
609 11,
610 0x10,
611 > {
612 unsafe {
613 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1800usize))
614 }
615 }
616 #[inline(always)]
617 pub const fn bus1erradd(
618 &self,
619 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
620 unsafe {
621 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
622 self._svd2pac_as_ptr().add(0x1800usize),
623 )
624 }
625 }
626 #[inline(always)]
627 pub const fn bus2erradd(
628 &self,
629 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
630 unsafe {
631 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
632 self._svd2pac_as_ptr().add(0x1810usize),
633 )
634 }
635 }
636 #[inline(always)]
637 pub const fn bus3erradd(
638 &self,
639 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
640 unsafe {
641 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
642 self._svd2pac_as_ptr().add(0x1820usize),
643 )
644 }
645 }
646 #[inline(always)]
647 pub const fn bus4erradd(
648 &self,
649 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
650 unsafe {
651 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
652 self._svd2pac_as_ptr().add(0x1830usize),
653 )
654 }
655 }
656 #[inline(always)]
657 pub const fn bus5erradd(
658 &self,
659 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
660 unsafe {
661 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
662 self._svd2pac_as_ptr().add(0x1840usize),
663 )
664 }
665 }
666 #[inline(always)]
667 pub const fn bus6erradd(
668 &self,
669 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
670 unsafe {
671 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
672 self._svd2pac_as_ptr().add(0x1850usize),
673 )
674 }
675 }
676 #[inline(always)]
677 pub const fn bus7erradd(
678 &self,
679 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
680 unsafe {
681 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
682 self._svd2pac_as_ptr().add(0x1860usize),
683 )
684 }
685 }
686 #[inline(always)]
687 pub const fn bus8erradd(
688 &self,
689 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
690 unsafe {
691 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
692 self._svd2pac_as_ptr().add(0x1870usize),
693 )
694 }
695 }
696 #[inline(always)]
697 pub const fn bus9erradd(
698 &self,
699 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
700 unsafe {
701 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
702 self._svd2pac_as_ptr().add(0x1880usize),
703 )
704 }
705 }
706 #[inline(always)]
707 pub const fn bus10erradd(
708 &self,
709 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
710 unsafe {
711 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
712 self._svd2pac_as_ptr().add(0x1890usize),
713 )
714 }
715 }
716 #[inline(always)]
717 pub const fn bus11erradd(
718 &self,
719 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
720 unsafe {
721 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
722 self._svd2pac_as_ptr().add(0x18a0usize),
723 )
724 }
725 }
726
727 #[doc = "Bus Error Status Register %s"]
728 #[inline(always)]
729 pub const fn buserrstat(
730 &self,
731 ) -> &'static crate::common::ClusterRegisterArray<
732 crate::common::Reg<self::Buserrstat_SPEC, crate::common::R>,
733 11,
734 0x10,
735 > {
736 unsafe {
737 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1804usize))
738 }
739 }
740 #[inline(always)]
741 pub const fn bus1errstat(
742 &self,
743 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
744 unsafe {
745 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
746 self._svd2pac_as_ptr().add(0x1804usize),
747 )
748 }
749 }
750 #[inline(always)]
751 pub const fn bus2errstat(
752 &self,
753 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
754 unsafe {
755 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
756 self._svd2pac_as_ptr().add(0x1814usize),
757 )
758 }
759 }
760 #[inline(always)]
761 pub const fn bus3errstat(
762 &self,
763 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
764 unsafe {
765 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
766 self._svd2pac_as_ptr().add(0x1824usize),
767 )
768 }
769 }
770 #[inline(always)]
771 pub const fn bus4errstat(
772 &self,
773 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
774 unsafe {
775 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
776 self._svd2pac_as_ptr().add(0x1834usize),
777 )
778 }
779 }
780 #[inline(always)]
781 pub const fn bus5errstat(
782 &self,
783 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
784 unsafe {
785 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
786 self._svd2pac_as_ptr().add(0x1844usize),
787 )
788 }
789 }
790 #[inline(always)]
791 pub const fn bus6errstat(
792 &self,
793 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
794 unsafe {
795 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
796 self._svd2pac_as_ptr().add(0x1854usize),
797 )
798 }
799 }
800 #[inline(always)]
801 pub const fn bus7errstat(
802 &self,
803 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
804 unsafe {
805 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
806 self._svd2pac_as_ptr().add(0x1864usize),
807 )
808 }
809 }
810 #[inline(always)]
811 pub const fn bus8errstat(
812 &self,
813 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
814 unsafe {
815 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
816 self._svd2pac_as_ptr().add(0x1874usize),
817 )
818 }
819 }
820 #[inline(always)]
821 pub const fn bus9errstat(
822 &self,
823 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
824 unsafe {
825 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
826 self._svd2pac_as_ptr().add(0x1884usize),
827 )
828 }
829 }
830 #[inline(always)]
831 pub const fn bus10errstat(
832 &self,
833 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
834 unsafe {
835 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
836 self._svd2pac_as_ptr().add(0x1894usize),
837 )
838 }
839 }
840 #[inline(always)]
841 pub const fn bus11errstat(
842 &self,
843 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
844 unsafe {
845 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
846 self._svd2pac_as_ptr().add(0x18a4usize),
847 )
848 }
849 }
850
851 #[doc = "Master Bus Control Register SYS"]
852 #[inline(always)]
853 pub const fn busmcntsys(
854 &self,
855 ) -> &'static crate::common::Reg<self::Busmcntsys_SPEC, crate::common::RW> {
856 unsafe {
857 crate::common::Reg::<self::Busmcntsys_SPEC, crate::common::RW>::from_ptr(
858 self._svd2pac_as_ptr().add(4104usize),
859 )
860 }
861 }
862
863 #[doc = "Master Bus Control Register DMA"]
864 #[inline(always)]
865 pub const fn busmcntdma(
866 &self,
867 ) -> &'static crate::common::Reg<self::Busmcntdma_SPEC, crate::common::RW> {
868 unsafe {
869 crate::common::Reg::<self::Busmcntdma_SPEC, crate::common::RW>::from_ptr(
870 self._svd2pac_as_ptr().add(4108usize),
871 )
872 }
873 }
874
875 #[doc = "Master Bus Control Register %s"]
876 #[inline(always)]
877 pub const fn busmcnt(
878 &self,
879 ) -> &'static crate::common::ClusterRegisterArray<
880 crate::common::Reg<self::Busmcnt_SPEC, crate::common::RW>,
881 2,
882 0x4,
883 > {
884 unsafe {
885 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1010usize))
886 }
887 }
888 #[inline(always)]
889 pub const fn busmcntedm(
890 &self,
891 ) -> &'static crate::common::Reg<self::Busmcnt_SPEC, crate::common::RW> {
892 unsafe {
893 crate::common::Reg::<self::Busmcnt_SPEC, crate::common::RW>::from_ptr(
894 self._svd2pac_as_ptr().add(0x1010usize),
895 )
896 }
897 }
898 #[inline(always)]
899 pub const fn busmcntgpx(
900 &self,
901 ) -> &'static crate::common::Reg<self::Busmcnt_SPEC, crate::common::RW> {
902 unsafe {
903 crate::common::Reg::<self::Busmcnt_SPEC, crate::common::RW>::from_ptr(
904 self._svd2pac_as_ptr().add(0x1014usize),
905 )
906 }
907 }
908
909 #[doc = "Slave Bus Control Register MBIU"]
910 #[inline(always)]
911 pub const fn busscntmbiu(
912 &self,
913 ) -> &'static crate::common::Reg<self::Busscntmbiu_SPEC, crate::common::RW> {
914 unsafe {
915 crate::common::Reg::<self::Busscntmbiu_SPEC, crate::common::RW>::from_ptr(
916 self._svd2pac_as_ptr().add(4360usize),
917 )
918 }
919 }
920
921 #[doc = "Slave Bus Control Register %s"]
922 #[inline(always)]
923 pub const fn busscnt(
924 &self,
925 ) -> &'static crate::common::ClusterRegisterArray<
926 crate::common::Reg<self::Busscnt_SPEC, crate::common::RW>,
927 4,
928 0x4,
929 > {
930 unsafe {
931 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1130usize))
932 }
933 }
934 #[inline(always)]
935 pub const fn busscntfbu(
936 &self,
937 ) -> &'static crate::common::Reg<self::Busscnt_SPEC, crate::common::RW> {
938 unsafe {
939 crate::common::Reg::<self::Busscnt_SPEC, crate::common::RW>::from_ptr(
940 self._svd2pac_as_ptr().add(0x1130usize),
941 )
942 }
943 }
944 #[inline(always)]
945 pub const fn busscntext(
946 &self,
947 ) -> &'static crate::common::Reg<self::Busscnt_SPEC, crate::common::RW> {
948 unsafe {
949 crate::common::Reg::<self::Busscnt_SPEC, crate::common::RW>::from_ptr(
950 self._svd2pac_as_ptr().add(0x1134usize),
951 )
952 }
953 }
954 #[inline(always)]
955 pub const fn busscntext2(
956 &self,
957 ) -> &'static crate::common::Reg<self::Busscnt_SPEC, crate::common::RW> {
958 unsafe {
959 crate::common::Reg::<self::Busscnt_SPEC, crate::common::RW>::from_ptr(
960 self._svd2pac_as_ptr().add(0x1138usize),
961 )
962 }
963 }
964 #[inline(always)]
965 pub const fn busscntgpx(
966 &self,
967 ) -> &'static crate::common::Reg<self::Busscnt_SPEC, crate::common::RW> {
968 unsafe {
969 crate::common::Reg::<self::Busscnt_SPEC, crate::common::RW>::from_ptr(
970 self._svd2pac_as_ptr().add(0x113cusize),
971 )
972 }
973 }
974}
975#[doc(hidden)]
976#[derive(Copy, Clone, Eq, PartialEq)]
977pub struct Cs0Cr_SPEC;
978impl crate::sealed::RegSpec for Cs0Cr_SPEC {
979 type DataType = u16;
980}
981
982#[doc = "CS0 Control Register"]
983pub type Cs0Cr = crate::RegValueT<Cs0Cr_SPEC>;
984
985impl Cs0Cr {
986 #[doc = "Address/Data Multiplexed I/O Interface Select"]
987 #[inline(always)]
988 pub fn mpxen(
989 self,
990 ) -> crate::common::RegisterField<
991 12,
992 0x1,
993 1,
994 0,
995 cs0cr::Mpxen,
996 cs0cr::Mpxen,
997 Cs0Cr_SPEC,
998 crate::common::RW,
999 > {
1000 crate::common::RegisterField::<
1001 12,
1002 0x1,
1003 1,
1004 0,
1005 cs0cr::Mpxen,
1006 cs0cr::Mpxen,
1007 Cs0Cr_SPEC,
1008 crate::common::RW,
1009 >::from_register(self, 0)
1010 }
1011
1012 #[doc = "Endian Mode"]
1013 #[inline(always)]
1014 pub fn emode(
1015 self,
1016 ) -> crate::common::RegisterField<
1017 8,
1018 0x1,
1019 1,
1020 0,
1021 cs0cr::Emode,
1022 cs0cr::Emode,
1023 Cs0Cr_SPEC,
1024 crate::common::RW,
1025 > {
1026 crate::common::RegisterField::<
1027 8,
1028 0x1,
1029 1,
1030 0,
1031 cs0cr::Emode,
1032 cs0cr::Emode,
1033 Cs0Cr_SPEC,
1034 crate::common::RW,
1035 >::from_register(self, 0)
1036 }
1037
1038 #[doc = "External Bus Width Select"]
1039 #[inline(always)]
1040 pub fn bsize(
1041 self,
1042 ) -> crate::common::RegisterField<
1043 4,
1044 0x3,
1045 1,
1046 0,
1047 cs0cr::Bsize,
1048 cs0cr::Bsize,
1049 Cs0Cr_SPEC,
1050 crate::common::RW,
1051 > {
1052 crate::common::RegisterField::<
1053 4,
1054 0x3,
1055 1,
1056 0,
1057 cs0cr::Bsize,
1058 cs0cr::Bsize,
1059 Cs0Cr_SPEC,
1060 crate::common::RW,
1061 >::from_register(self, 0)
1062 }
1063
1064 #[doc = "Operation Enable"]
1065 #[inline(always)]
1066 pub fn exenb(
1067 self,
1068 ) -> crate::common::RegisterField<
1069 0,
1070 0x1,
1071 1,
1072 0,
1073 cs0cr::Exenb,
1074 cs0cr::Exenb,
1075 Cs0Cr_SPEC,
1076 crate::common::RW,
1077 > {
1078 crate::common::RegisterField::<
1079 0,
1080 0x1,
1081 1,
1082 0,
1083 cs0cr::Exenb,
1084 cs0cr::Exenb,
1085 Cs0Cr_SPEC,
1086 crate::common::RW,
1087 >::from_register(self, 0)
1088 }
1089}
1090impl ::core::default::Default for Cs0Cr {
1091 #[inline(always)]
1092 fn default() -> Cs0Cr {
1093 <crate::RegValueT<Cs0Cr_SPEC> as RegisterValue<_>>::new(33)
1094 }
1095}
1096pub mod cs0cr {
1097
1098 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1099 pub struct Mpxen_SPEC;
1100 pub type Mpxen = crate::EnumBitfieldStruct<u8, Mpxen_SPEC>;
1101 impl Mpxen {
1102 #[doc = "Separate bus interface is selected for area n"]
1103 pub const _0: Self = Self::new(0);
1104
1105 #[doc = "Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)"]
1106 pub const _1: Self = Self::new(1);
1107 }
1108 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1109 pub struct Emode_SPEC;
1110 pub type Emode = crate::EnumBitfieldStruct<u8, Emode_SPEC>;
1111 impl Emode {
1112 #[doc = "Little Endian"]
1113 pub const _0: Self = Self::new(0);
1114
1115 #[doc = "Big Endian"]
1116 pub const _1: Self = Self::new(1);
1117 }
1118 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1119 pub struct Bsize_SPEC;
1120 pub type Bsize = crate::EnumBitfieldStruct<u8, Bsize_SPEC>;
1121 impl Bsize {
1122 #[doc = "A 16-bit bus space"]
1123 pub const _00: Self = Self::new(0);
1124
1125 #[doc = "Setting prohibited"]
1126 pub const _01: Self = Self::new(1);
1127
1128 #[doc = "An 8-bit bus space"]
1129 pub const _10: Self = Self::new(2);
1130
1131 #[doc = "Setting prohibited"]
1132 pub const _11: Self = Self::new(3);
1133 }
1134 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1135 pub struct Exenb_SPEC;
1136 pub type Exenb = crate::EnumBitfieldStruct<u8, Exenb_SPEC>;
1137 impl Exenb {
1138 #[doc = "Disable operation"]
1139 pub const _0: Self = Self::new(0);
1140
1141 #[doc = "Enable operation"]
1142 pub const _1: Self = Self::new(1);
1143 }
1144}
1145#[doc(hidden)]
1146#[derive(Copy, Clone, Eq, PartialEq)]
1147pub struct Cscr_SPEC;
1148impl crate::sealed::RegSpec for Cscr_SPEC {
1149 type DataType = u16;
1150}
1151
1152#[doc = "CS%s Control Register"]
1153pub type Cscr = crate::RegValueT<Cscr_SPEC>;
1154
1155impl Cscr {
1156 #[doc = "Address/Data Multiplexed I/O Interface Select"]
1157 #[inline(always)]
1158 pub fn mpxen(
1159 self,
1160 ) -> crate::common::RegisterField<
1161 12,
1162 0x1,
1163 1,
1164 0,
1165 cscr::Mpxen,
1166 cscr::Mpxen,
1167 Cscr_SPEC,
1168 crate::common::RW,
1169 > {
1170 crate::common::RegisterField::<
1171 12,
1172 0x1,
1173 1,
1174 0,
1175 cscr::Mpxen,
1176 cscr::Mpxen,
1177 Cscr_SPEC,
1178 crate::common::RW,
1179 >::from_register(self, 0)
1180 }
1181
1182 #[doc = "Endian Mode"]
1183 #[inline(always)]
1184 pub fn emode(
1185 self,
1186 ) -> crate::common::RegisterField<
1187 8,
1188 0x1,
1189 1,
1190 0,
1191 cscr::Emode,
1192 cscr::Emode,
1193 Cscr_SPEC,
1194 crate::common::RW,
1195 > {
1196 crate::common::RegisterField::<
1197 8,
1198 0x1,
1199 1,
1200 0,
1201 cscr::Emode,
1202 cscr::Emode,
1203 Cscr_SPEC,
1204 crate::common::RW,
1205 >::from_register(self, 0)
1206 }
1207
1208 #[doc = "External Bus Width Select"]
1209 #[inline(always)]
1210 pub fn bsize(
1211 self,
1212 ) -> crate::common::RegisterField<
1213 4,
1214 0x3,
1215 1,
1216 0,
1217 cscr::Bsize,
1218 cscr::Bsize,
1219 Cscr_SPEC,
1220 crate::common::RW,
1221 > {
1222 crate::common::RegisterField::<
1223 4,
1224 0x3,
1225 1,
1226 0,
1227 cscr::Bsize,
1228 cscr::Bsize,
1229 Cscr_SPEC,
1230 crate::common::RW,
1231 >::from_register(self, 0)
1232 }
1233
1234 #[doc = "Operation Enable"]
1235 #[inline(always)]
1236 pub fn exenb(
1237 self,
1238 ) -> crate::common::RegisterField<
1239 0,
1240 0x1,
1241 1,
1242 0,
1243 cscr::Exenb,
1244 cscr::Exenb,
1245 Cscr_SPEC,
1246 crate::common::RW,
1247 > {
1248 crate::common::RegisterField::<
1249 0,
1250 0x1,
1251 1,
1252 0,
1253 cscr::Exenb,
1254 cscr::Exenb,
1255 Cscr_SPEC,
1256 crate::common::RW,
1257 >::from_register(self, 0)
1258 }
1259}
1260impl ::core::default::Default for Cscr {
1261 #[inline(always)]
1262 fn default() -> Cscr {
1263 <crate::RegValueT<Cscr_SPEC> as RegisterValue<_>>::new(0)
1264 }
1265}
1266pub mod cscr {
1267
1268 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1269 pub struct Mpxen_SPEC;
1270 pub type Mpxen = crate::EnumBitfieldStruct<u8, Mpxen_SPEC>;
1271 impl Mpxen {
1272 #[doc = "Separate bus interface is selected for area n"]
1273 pub const _0: Self = Self::new(0);
1274
1275 #[doc = "Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)"]
1276 pub const _1: Self = Self::new(1);
1277 }
1278 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1279 pub struct Emode_SPEC;
1280 pub type Emode = crate::EnumBitfieldStruct<u8, Emode_SPEC>;
1281 impl Emode {
1282 #[doc = "Little Endian"]
1283 pub const _0: Self = Self::new(0);
1284
1285 #[doc = "Big Endian"]
1286 pub const _1: Self = Self::new(1);
1287 }
1288 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1289 pub struct Bsize_SPEC;
1290 pub type Bsize = crate::EnumBitfieldStruct<u8, Bsize_SPEC>;
1291 impl Bsize {
1292 #[doc = "A 16-bit bus space"]
1293 pub const _00: Self = Self::new(0);
1294
1295 #[doc = "Setting prohibited"]
1296 pub const _01: Self = Self::new(1);
1297
1298 #[doc = "An 8-bit bus space"]
1299 pub const _10: Self = Self::new(2);
1300
1301 #[doc = "Setting prohibited"]
1302 pub const _11: Self = Self::new(3);
1303 }
1304 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1305 pub struct Exenb_SPEC;
1306 pub type Exenb = crate::EnumBitfieldStruct<u8, Exenb_SPEC>;
1307 impl Exenb {
1308 #[doc = "Disable operation"]
1309 pub const _0: Self = Self::new(0);
1310
1311 #[doc = "Enable operation"]
1312 pub const _1: Self = Self::new(1);
1313 }
1314}
1315#[doc(hidden)]
1316#[derive(Copy, Clone, Eq, PartialEq)]
1317pub struct Csrec_SPEC;
1318impl crate::sealed::RegSpec for Csrec_SPEC {
1319 type DataType = u16;
1320}
1321
1322#[doc = "CS%s Recovery Cycle Register"]
1323pub type Csrec = crate::RegValueT<Csrec_SPEC>;
1324
1325impl Csrec {
1326 #[doc = "Write Recovery"]
1327 #[inline(always)]
1328 pub fn wrcv(
1329 self,
1330 ) -> crate::common::RegisterField<
1331 8,
1332 0xf,
1333 1,
1334 0,
1335 csrec::Wrcv,
1336 csrec::Wrcv,
1337 Csrec_SPEC,
1338 crate::common::RW,
1339 > {
1340 crate::common::RegisterField::<
1341 8,
1342 0xf,
1343 1,
1344 0,
1345 csrec::Wrcv,
1346 csrec::Wrcv,
1347 Csrec_SPEC,
1348 crate::common::RW,
1349 >::from_register(self, 0)
1350 }
1351
1352 #[doc = "Read Recovery"]
1353 #[inline(always)]
1354 pub fn rrcv(
1355 self,
1356 ) -> crate::common::RegisterField<
1357 0,
1358 0xf,
1359 1,
1360 0,
1361 csrec::Rrcv,
1362 csrec::Rrcv,
1363 Csrec_SPEC,
1364 crate::common::RW,
1365 > {
1366 crate::common::RegisterField::<
1367 0,
1368 0xf,
1369 1,
1370 0,
1371 csrec::Rrcv,
1372 csrec::Rrcv,
1373 Csrec_SPEC,
1374 crate::common::RW,
1375 >::from_register(self, 0)
1376 }
1377}
1378impl ::core::default::Default for Csrec {
1379 #[inline(always)]
1380 fn default() -> Csrec {
1381 <crate::RegValueT<Csrec_SPEC> as RegisterValue<_>>::new(0)
1382 }
1383}
1384pub mod csrec {
1385
1386 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1387 pub struct Wrcv_SPEC;
1388 pub type Wrcv = crate::EnumBitfieldStruct<u8, Wrcv_SPEC>;
1389 impl Wrcv {
1390 #[doc = "No recovery cycle is inserted."]
1391 pub const _0_X_0: Self = Self::new(0);
1392 }
1393 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1394 pub struct Rrcv_SPEC;
1395 pub type Rrcv = crate::EnumBitfieldStruct<u8, Rrcv_SPEC>;
1396 impl Rrcv {
1397 #[doc = "No recovery cycle is inserted."]
1398 pub const _0_X_0: Self = Self::new(0);
1399 }
1400}
1401#[doc(hidden)]
1402#[derive(Copy, Clone, Eq, PartialEq)]
1403pub struct Csrecen_SPEC;
1404impl crate::sealed::RegSpec for Csrecen_SPEC {
1405 type DataType = u16;
1406}
1407
1408#[doc = "CS Recovery Cycle Insertion Enable Register"]
1409pub type Csrecen = crate::RegValueT<Csrecen_SPEC>;
1410
1411impl Csrecen {
1412 #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 7"]
1413 #[inline(always)]
1414 pub fn rcvenm7(
1415 self,
1416 ) -> crate::common::RegisterField<
1417 15,
1418 0x1,
1419 1,
1420 0,
1421 csrecen::Rcvenm7,
1422 csrecen::Rcvenm7,
1423 Csrecen_SPEC,
1424 crate::common::RW,
1425 > {
1426 crate::common::RegisterField::<
1427 15,
1428 0x1,
1429 1,
1430 0,
1431 csrecen::Rcvenm7,
1432 csrecen::Rcvenm7,
1433 Csrecen_SPEC,
1434 crate::common::RW,
1435 >::from_register(self, 0)
1436 }
1437
1438 #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 6"]
1439 #[inline(always)]
1440 pub fn rcvenm6(
1441 self,
1442 ) -> crate::common::RegisterField<
1443 14,
1444 0x1,
1445 1,
1446 0,
1447 csrecen::Rcvenm6,
1448 csrecen::Rcvenm6,
1449 Csrecen_SPEC,
1450 crate::common::RW,
1451 > {
1452 crate::common::RegisterField::<
1453 14,
1454 0x1,
1455 1,
1456 0,
1457 csrecen::Rcvenm6,
1458 csrecen::Rcvenm6,
1459 Csrecen_SPEC,
1460 crate::common::RW,
1461 >::from_register(self, 0)
1462 }
1463
1464 #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 5"]
1465 #[inline(always)]
1466 pub fn rcvenm5(
1467 self,
1468 ) -> crate::common::RegisterField<
1469 13,
1470 0x1,
1471 1,
1472 0,
1473 csrecen::Rcvenm5,
1474 csrecen::Rcvenm5,
1475 Csrecen_SPEC,
1476 crate::common::RW,
1477 > {
1478 crate::common::RegisterField::<
1479 13,
1480 0x1,
1481 1,
1482 0,
1483 csrecen::Rcvenm5,
1484 csrecen::Rcvenm5,
1485 Csrecen_SPEC,
1486 crate::common::RW,
1487 >::from_register(self, 0)
1488 }
1489
1490 #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 4"]
1491 #[inline(always)]
1492 pub fn rcvenm4(
1493 self,
1494 ) -> crate::common::RegisterField<
1495 12,
1496 0x1,
1497 1,
1498 0,
1499 csrecen::Rcvenm4,
1500 csrecen::Rcvenm4,
1501 Csrecen_SPEC,
1502 crate::common::RW,
1503 > {
1504 crate::common::RegisterField::<
1505 12,
1506 0x1,
1507 1,
1508 0,
1509 csrecen::Rcvenm4,
1510 csrecen::Rcvenm4,
1511 Csrecen_SPEC,
1512 crate::common::RW,
1513 >::from_register(self, 0)
1514 }
1515
1516 #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 3"]
1517 #[inline(always)]
1518 pub fn rcvenm3(
1519 self,
1520 ) -> crate::common::RegisterField<
1521 11,
1522 0x1,
1523 1,
1524 0,
1525 csrecen::Rcvenm3,
1526 csrecen::Rcvenm3,
1527 Csrecen_SPEC,
1528 crate::common::RW,
1529 > {
1530 crate::common::RegisterField::<
1531 11,
1532 0x1,
1533 1,
1534 0,
1535 csrecen::Rcvenm3,
1536 csrecen::Rcvenm3,
1537 Csrecen_SPEC,
1538 crate::common::RW,
1539 >::from_register(self, 0)
1540 }
1541
1542 #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 2"]
1543 #[inline(always)]
1544 pub fn rcvenm2(
1545 self,
1546 ) -> crate::common::RegisterField<
1547 10,
1548 0x1,
1549 1,
1550 0,
1551 csrecen::Rcvenm2,
1552 csrecen::Rcvenm2,
1553 Csrecen_SPEC,
1554 crate::common::RW,
1555 > {
1556 crate::common::RegisterField::<
1557 10,
1558 0x1,
1559 1,
1560 0,
1561 csrecen::Rcvenm2,
1562 csrecen::Rcvenm2,
1563 Csrecen_SPEC,
1564 crate::common::RW,
1565 >::from_register(self, 0)
1566 }
1567
1568 #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 1"]
1569 #[inline(always)]
1570 pub fn rcvenm1(
1571 self,
1572 ) -> crate::common::RegisterField<
1573 9,
1574 0x1,
1575 1,
1576 0,
1577 csrecen::Rcvenm1,
1578 csrecen::Rcvenm1,
1579 Csrecen_SPEC,
1580 crate::common::RW,
1581 > {
1582 crate::common::RegisterField::<
1583 9,
1584 0x1,
1585 1,
1586 0,
1587 csrecen::Rcvenm1,
1588 csrecen::Rcvenm1,
1589 Csrecen_SPEC,
1590 crate::common::RW,
1591 >::from_register(self, 0)
1592 }
1593
1594 #[doc = "Multiplexed Bus Recovery Cycle Insertion Enable 0"]
1595 #[inline(always)]
1596 pub fn rcvenm0(
1597 self,
1598 ) -> crate::common::RegisterField<
1599 8,
1600 0x1,
1601 1,
1602 0,
1603 csrecen::Rcvenm0,
1604 csrecen::Rcvenm0,
1605 Csrecen_SPEC,
1606 crate::common::RW,
1607 > {
1608 crate::common::RegisterField::<
1609 8,
1610 0x1,
1611 1,
1612 0,
1613 csrecen::Rcvenm0,
1614 csrecen::Rcvenm0,
1615 Csrecen_SPEC,
1616 crate::common::RW,
1617 >::from_register(self, 0)
1618 }
1619
1620 #[doc = "Separate Bus Recovery Cycle Insertion Enable 7"]
1621 #[inline(always)]
1622 pub fn rcven7(
1623 self,
1624 ) -> crate::common::RegisterField<
1625 7,
1626 0x1,
1627 1,
1628 0,
1629 csrecen::Rcven7,
1630 csrecen::Rcven7,
1631 Csrecen_SPEC,
1632 crate::common::RW,
1633 > {
1634 crate::common::RegisterField::<
1635 7,
1636 0x1,
1637 1,
1638 0,
1639 csrecen::Rcven7,
1640 csrecen::Rcven7,
1641 Csrecen_SPEC,
1642 crate::common::RW,
1643 >::from_register(self, 0)
1644 }
1645
1646 #[doc = "Separate Bus Recovery Cycle Insertion Enable 6"]
1647 #[inline(always)]
1648 pub fn rcven6(
1649 self,
1650 ) -> crate::common::RegisterField<
1651 6,
1652 0x1,
1653 1,
1654 0,
1655 csrecen::Rcven6,
1656 csrecen::Rcven6,
1657 Csrecen_SPEC,
1658 crate::common::RW,
1659 > {
1660 crate::common::RegisterField::<
1661 6,
1662 0x1,
1663 1,
1664 0,
1665 csrecen::Rcven6,
1666 csrecen::Rcven6,
1667 Csrecen_SPEC,
1668 crate::common::RW,
1669 >::from_register(self, 0)
1670 }
1671
1672 #[doc = "Separate Bus Recovery Cycle Insertion Enable 5"]
1673 #[inline(always)]
1674 pub fn rcven5(
1675 self,
1676 ) -> crate::common::RegisterField<
1677 5,
1678 0x1,
1679 1,
1680 0,
1681 csrecen::Rcven5,
1682 csrecen::Rcven5,
1683 Csrecen_SPEC,
1684 crate::common::RW,
1685 > {
1686 crate::common::RegisterField::<
1687 5,
1688 0x1,
1689 1,
1690 0,
1691 csrecen::Rcven5,
1692 csrecen::Rcven5,
1693 Csrecen_SPEC,
1694 crate::common::RW,
1695 >::from_register(self, 0)
1696 }
1697
1698 #[doc = "Separate Bus Recovery Cycle Insertion Enable 4"]
1699 #[inline(always)]
1700 pub fn rcven4(
1701 self,
1702 ) -> crate::common::RegisterField<
1703 4,
1704 0x1,
1705 1,
1706 0,
1707 csrecen::Rcven4,
1708 csrecen::Rcven4,
1709 Csrecen_SPEC,
1710 crate::common::RW,
1711 > {
1712 crate::common::RegisterField::<
1713 4,
1714 0x1,
1715 1,
1716 0,
1717 csrecen::Rcven4,
1718 csrecen::Rcven4,
1719 Csrecen_SPEC,
1720 crate::common::RW,
1721 >::from_register(self, 0)
1722 }
1723
1724 #[doc = "Separate Bus Recovery Cycle Insertion Enable 3"]
1725 #[inline(always)]
1726 pub fn rcven3(
1727 self,
1728 ) -> crate::common::RegisterField<
1729 3,
1730 0x1,
1731 1,
1732 0,
1733 csrecen::Rcven3,
1734 csrecen::Rcven3,
1735 Csrecen_SPEC,
1736 crate::common::RW,
1737 > {
1738 crate::common::RegisterField::<
1739 3,
1740 0x1,
1741 1,
1742 0,
1743 csrecen::Rcven3,
1744 csrecen::Rcven3,
1745 Csrecen_SPEC,
1746 crate::common::RW,
1747 >::from_register(self, 0)
1748 }
1749
1750 #[doc = "Separate Bus Recovery Cycle Insertion Enable 2"]
1751 #[inline(always)]
1752 pub fn rcven2(
1753 self,
1754 ) -> crate::common::RegisterField<
1755 2,
1756 0x1,
1757 1,
1758 0,
1759 csrecen::Rcven2,
1760 csrecen::Rcven2,
1761 Csrecen_SPEC,
1762 crate::common::RW,
1763 > {
1764 crate::common::RegisterField::<
1765 2,
1766 0x1,
1767 1,
1768 0,
1769 csrecen::Rcven2,
1770 csrecen::Rcven2,
1771 Csrecen_SPEC,
1772 crate::common::RW,
1773 >::from_register(self, 0)
1774 }
1775
1776 #[doc = "Separate Bus Recovery Cycle Insertion Enable 1"]
1777 #[inline(always)]
1778 pub fn rcven1(
1779 self,
1780 ) -> crate::common::RegisterField<
1781 1,
1782 0x1,
1783 1,
1784 0,
1785 csrecen::Rcven1,
1786 csrecen::Rcven1,
1787 Csrecen_SPEC,
1788 crate::common::RW,
1789 > {
1790 crate::common::RegisterField::<
1791 1,
1792 0x1,
1793 1,
1794 0,
1795 csrecen::Rcven1,
1796 csrecen::Rcven1,
1797 Csrecen_SPEC,
1798 crate::common::RW,
1799 >::from_register(self, 0)
1800 }
1801
1802 #[doc = "Separate Bus Recovery Cycle Insertion Enable 0"]
1803 #[inline(always)]
1804 pub fn rcven0(
1805 self,
1806 ) -> crate::common::RegisterField<
1807 0,
1808 0x1,
1809 1,
1810 0,
1811 csrecen::Rcven0,
1812 csrecen::Rcven0,
1813 Csrecen_SPEC,
1814 crate::common::RW,
1815 > {
1816 crate::common::RegisterField::<
1817 0,
1818 0x1,
1819 1,
1820 0,
1821 csrecen::Rcven0,
1822 csrecen::Rcven0,
1823 Csrecen_SPEC,
1824 crate::common::RW,
1825 >::from_register(self, 0)
1826 }
1827}
1828impl ::core::default::Default for Csrecen {
1829 #[inline(always)]
1830 fn default() -> Csrecen {
1831 <crate::RegValueT<Csrecen_SPEC> as RegisterValue<_>>::new(15934)
1832 }
1833}
1834pub mod csrecen {
1835
1836 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1837 pub struct Rcvenm7_SPEC;
1838 pub type Rcvenm7 = crate::EnumBitfieldStruct<u8, Rcvenm7_SPEC>;
1839 impl Rcvenm7 {
1840 #[doc = "Recovery cycle insertion is disabled."]
1841 pub const _0: Self = Self::new(0);
1842
1843 #[doc = "Recovery cycle insertion is enabled."]
1844 pub const _1: Self = Self::new(1);
1845 }
1846 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1847 pub struct Rcvenm6_SPEC;
1848 pub type Rcvenm6 = crate::EnumBitfieldStruct<u8, Rcvenm6_SPEC>;
1849 impl Rcvenm6 {
1850 #[doc = "Recovery cycle insertion is disabled."]
1851 pub const _0: Self = Self::new(0);
1852
1853 #[doc = "Recovery cycle insertion is enabled."]
1854 pub const _1: Self = Self::new(1);
1855 }
1856 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1857 pub struct Rcvenm5_SPEC;
1858 pub type Rcvenm5 = crate::EnumBitfieldStruct<u8, Rcvenm5_SPEC>;
1859 impl Rcvenm5 {
1860 #[doc = "Recovery cycle insertion is disabled."]
1861 pub const _0: Self = Self::new(0);
1862
1863 #[doc = "Recovery cycle insertion is enabled."]
1864 pub const _1: Self = Self::new(1);
1865 }
1866 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1867 pub struct Rcvenm4_SPEC;
1868 pub type Rcvenm4 = crate::EnumBitfieldStruct<u8, Rcvenm4_SPEC>;
1869 impl Rcvenm4 {
1870 #[doc = "Recovery cycle insertion is disabled."]
1871 pub const _0: Self = Self::new(0);
1872
1873 #[doc = "Recovery cycle insertion is enabled."]
1874 pub const _1: Self = Self::new(1);
1875 }
1876 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1877 pub struct Rcvenm3_SPEC;
1878 pub type Rcvenm3 = crate::EnumBitfieldStruct<u8, Rcvenm3_SPEC>;
1879 impl Rcvenm3 {
1880 #[doc = "Recovery cycle insertion is disabled."]
1881 pub const _0: Self = Self::new(0);
1882
1883 #[doc = "Recovery cycle insertion is enabled."]
1884 pub const _1: Self = Self::new(1);
1885 }
1886 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1887 pub struct Rcvenm2_SPEC;
1888 pub type Rcvenm2 = crate::EnumBitfieldStruct<u8, Rcvenm2_SPEC>;
1889 impl Rcvenm2 {
1890 #[doc = "Recovery cycle insertion is disabled."]
1891 pub const _0: Self = Self::new(0);
1892
1893 #[doc = "Recovery cycle insertion is enabled."]
1894 pub const _1: Self = Self::new(1);
1895 }
1896 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1897 pub struct Rcvenm1_SPEC;
1898 pub type Rcvenm1 = crate::EnumBitfieldStruct<u8, Rcvenm1_SPEC>;
1899 impl Rcvenm1 {
1900 #[doc = "Recovery cycle insertion is disabled."]
1901 pub const _0: Self = Self::new(0);
1902
1903 #[doc = "Recovery cycle insertion is enabled."]
1904 pub const _1: Self = Self::new(1);
1905 }
1906 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1907 pub struct Rcvenm0_SPEC;
1908 pub type Rcvenm0 = crate::EnumBitfieldStruct<u8, Rcvenm0_SPEC>;
1909 impl Rcvenm0 {
1910 #[doc = "Recovery cycle insertion is disabled."]
1911 pub const _0: Self = Self::new(0);
1912
1913 #[doc = "Recovery cycle insertion is enabled."]
1914 pub const _1: Self = Self::new(1);
1915 }
1916 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1917 pub struct Rcven7_SPEC;
1918 pub type Rcven7 = crate::EnumBitfieldStruct<u8, Rcven7_SPEC>;
1919 impl Rcven7 {
1920 #[doc = "Recovery cycle insertion is disabled."]
1921 pub const _0: Self = Self::new(0);
1922
1923 #[doc = "Recovery cycle insertion is enabled."]
1924 pub const _1: Self = Self::new(1);
1925 }
1926 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1927 pub struct Rcven6_SPEC;
1928 pub type Rcven6 = crate::EnumBitfieldStruct<u8, Rcven6_SPEC>;
1929 impl Rcven6 {
1930 #[doc = "Recovery cycle insertion is disabled."]
1931 pub const _0: Self = Self::new(0);
1932
1933 #[doc = "Recovery cycle insertion is enabled."]
1934 pub const _1: Self = Self::new(1);
1935 }
1936 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1937 pub struct Rcven5_SPEC;
1938 pub type Rcven5 = crate::EnumBitfieldStruct<u8, Rcven5_SPEC>;
1939 impl Rcven5 {
1940 #[doc = "Recovery cycle insertion is disabled."]
1941 pub const _0: Self = Self::new(0);
1942
1943 #[doc = "Recovery cycle insertion is enabled."]
1944 pub const _1: Self = Self::new(1);
1945 }
1946 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1947 pub struct Rcven4_SPEC;
1948 pub type Rcven4 = crate::EnumBitfieldStruct<u8, Rcven4_SPEC>;
1949 impl Rcven4 {
1950 #[doc = "Recovery cycle insertion is disabled."]
1951 pub const _0: Self = Self::new(0);
1952
1953 #[doc = "Recovery cycle insertion is enabled."]
1954 pub const _1: Self = Self::new(1);
1955 }
1956 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1957 pub struct Rcven3_SPEC;
1958 pub type Rcven3 = crate::EnumBitfieldStruct<u8, Rcven3_SPEC>;
1959 impl Rcven3 {
1960 #[doc = "Recovery cycle insertion is disabled."]
1961 pub const _0: Self = Self::new(0);
1962
1963 #[doc = "Recovery cycle insertion is enabled."]
1964 pub const _1: Self = Self::new(1);
1965 }
1966 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1967 pub struct Rcven2_SPEC;
1968 pub type Rcven2 = crate::EnumBitfieldStruct<u8, Rcven2_SPEC>;
1969 impl Rcven2 {
1970 #[doc = "Recovery cycle insertion is disabled."]
1971 pub const _0: Self = Self::new(0);
1972
1973 #[doc = "Recovery cycle insertion is enabled."]
1974 pub const _1: Self = Self::new(1);
1975 }
1976 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1977 pub struct Rcven1_SPEC;
1978 pub type Rcven1 = crate::EnumBitfieldStruct<u8, Rcven1_SPEC>;
1979 impl Rcven1 {
1980 #[doc = "Recovery cycle insertion is disabled."]
1981 pub const _0: Self = Self::new(0);
1982
1983 #[doc = "Recovery cycle insertion is enabled."]
1984 pub const _1: Self = Self::new(1);
1985 }
1986 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1987 pub struct Rcven0_SPEC;
1988 pub type Rcven0 = crate::EnumBitfieldStruct<u8, Rcven0_SPEC>;
1989 impl Rcven0 {
1990 #[doc = "Recovery cycle insertion is disabled."]
1991 pub const _0: Self = Self::new(0);
1992
1993 #[doc = "Recovery cycle insertion is enabled."]
1994 pub const _1: Self = Self::new(1);
1995 }
1996}
1997#[doc(hidden)]
1998#[derive(Copy, Clone, Eq, PartialEq)]
1999pub struct Csmod_SPEC;
2000impl crate::sealed::RegSpec for Csmod_SPEC {
2001 type DataType = u16;
2002}
2003
2004#[doc = "CS%s Mode Register"]
2005pub type Csmod = crate::RegValueT<Csmod_SPEC>;
2006
2007impl Csmod {
2008 #[doc = "Page Read Access Mode Select"]
2009 #[inline(always)]
2010 pub fn prmod(
2011 self,
2012 ) -> crate::common::RegisterField<
2013 15,
2014 0x1,
2015 1,
2016 0,
2017 csmod::Prmod,
2018 csmod::Prmod,
2019 Csmod_SPEC,
2020 crate::common::RW,
2021 > {
2022 crate::common::RegisterField::<
2023 15,
2024 0x1,
2025 1,
2026 0,
2027 csmod::Prmod,
2028 csmod::Prmod,
2029 Csmod_SPEC,
2030 crate::common::RW,
2031 >::from_register(self, 0)
2032 }
2033
2034 #[doc = "Page Write Access Enable"]
2035 #[inline(always)]
2036 pub fn pwenb(
2037 self,
2038 ) -> crate::common::RegisterField<
2039 9,
2040 0x1,
2041 1,
2042 0,
2043 csmod::Pwenb,
2044 csmod::Pwenb,
2045 Csmod_SPEC,
2046 crate::common::RW,
2047 > {
2048 crate::common::RegisterField::<
2049 9,
2050 0x1,
2051 1,
2052 0,
2053 csmod::Pwenb,
2054 csmod::Pwenb,
2055 Csmod_SPEC,
2056 crate::common::RW,
2057 >::from_register(self, 0)
2058 }
2059
2060 #[doc = "Page Read Access Enable"]
2061 #[inline(always)]
2062 pub fn prenb(
2063 self,
2064 ) -> crate::common::RegisterField<
2065 8,
2066 0x1,
2067 1,
2068 0,
2069 csmod::Prenb,
2070 csmod::Prenb,
2071 Csmod_SPEC,
2072 crate::common::RW,
2073 > {
2074 crate::common::RegisterField::<
2075 8,
2076 0x1,
2077 1,
2078 0,
2079 csmod::Prenb,
2080 csmod::Prenb,
2081 Csmod_SPEC,
2082 crate::common::RW,
2083 >::from_register(self, 0)
2084 }
2085
2086 #[doc = "External Wait Enable"]
2087 #[inline(always)]
2088 pub fn ewenb(
2089 self,
2090 ) -> crate::common::RegisterField<
2091 3,
2092 0x1,
2093 1,
2094 0,
2095 csmod::Ewenb,
2096 csmod::Ewenb,
2097 Csmod_SPEC,
2098 crate::common::RW,
2099 > {
2100 crate::common::RegisterField::<
2101 3,
2102 0x1,
2103 1,
2104 0,
2105 csmod::Ewenb,
2106 csmod::Ewenb,
2107 Csmod_SPEC,
2108 crate::common::RW,
2109 >::from_register(self, 0)
2110 }
2111
2112 #[doc = "Write Access Mode Select"]
2113 #[inline(always)]
2114 pub fn wrmod(
2115 self,
2116 ) -> crate::common::RegisterField<
2117 0,
2118 0x1,
2119 1,
2120 0,
2121 csmod::Wrmod,
2122 csmod::Wrmod,
2123 Csmod_SPEC,
2124 crate::common::RW,
2125 > {
2126 crate::common::RegisterField::<
2127 0,
2128 0x1,
2129 1,
2130 0,
2131 csmod::Wrmod,
2132 csmod::Wrmod,
2133 Csmod_SPEC,
2134 crate::common::RW,
2135 >::from_register(self, 0)
2136 }
2137}
2138impl ::core::default::Default for Csmod {
2139 #[inline(always)]
2140 fn default() -> Csmod {
2141 <crate::RegValueT<Csmod_SPEC> as RegisterValue<_>>::new(0)
2142 }
2143}
2144pub mod csmod {
2145
2146 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2147 pub struct Prmod_SPEC;
2148 pub type Prmod = crate::EnumBitfieldStruct<u8, Prmod_SPEC>;
2149 impl Prmod {
2150 #[doc = "Normal access compatible mode"]
2151 pub const _0: Self = Self::new(0);
2152
2153 #[doc = "External data read continuous assertion mode"]
2154 pub const _1: Self = Self::new(1);
2155 }
2156 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2157 pub struct Pwenb_SPEC;
2158 pub type Pwenb = crate::EnumBitfieldStruct<u8, Pwenb_SPEC>;
2159 impl Pwenb {
2160 #[doc = "Disable"]
2161 pub const _0: Self = Self::new(0);
2162
2163 #[doc = "Enable"]
2164 pub const _1: Self = Self::new(1);
2165 }
2166 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2167 pub struct Prenb_SPEC;
2168 pub type Prenb = crate::EnumBitfieldStruct<u8, Prenb_SPEC>;
2169 impl Prenb {
2170 #[doc = "Disable"]
2171 pub const _0: Self = Self::new(0);
2172
2173 #[doc = "Enable"]
2174 pub const _1: Self = Self::new(1);
2175 }
2176 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2177 pub struct Ewenb_SPEC;
2178 pub type Ewenb = crate::EnumBitfieldStruct<u8, Ewenb_SPEC>;
2179 impl Ewenb {
2180 #[doc = "Disable"]
2181 pub const _0: Self = Self::new(0);
2182
2183 #[doc = "Enable"]
2184 pub const _1: Self = Self::new(1);
2185 }
2186 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2187 pub struct Wrmod_SPEC;
2188 pub type Wrmod = crate::EnumBitfieldStruct<u8, Wrmod_SPEC>;
2189 impl Wrmod {
2190 #[doc = "Byte strobe mode"]
2191 pub const _0: Self = Self::new(0);
2192
2193 #[doc = "Single write strobe mode"]
2194 pub const _1: Self = Self::new(1);
2195 }
2196}
2197#[doc(hidden)]
2198#[derive(Copy, Clone, Eq, PartialEq)]
2199pub struct Cswcr1_SPEC;
2200impl crate::sealed::RegSpec for Cswcr1_SPEC {
2201 type DataType = u32;
2202}
2203
2204#[doc = "CS%s Wait Control Register 1"]
2205pub type Cswcr1 = crate::RegValueT<Cswcr1_SPEC>;
2206
2207impl Cswcr1 {
2208 #[doc = "Normal Read Cycle Wait Select"]
2209 #[inline(always)]
2210 pub fn csrwait(
2211 self,
2212 ) -> crate::common::RegisterField<
2213 24,
2214 0x1f,
2215 1,
2216 0,
2217 cswcr1::Csrwait,
2218 cswcr1::Csrwait,
2219 Cswcr1_SPEC,
2220 crate::common::RW,
2221 > {
2222 crate::common::RegisterField::<
2223 24,
2224 0x1f,
2225 1,
2226 0,
2227 cswcr1::Csrwait,
2228 cswcr1::Csrwait,
2229 Cswcr1_SPEC,
2230 crate::common::RW,
2231 >::from_register(self, 0)
2232 }
2233
2234 #[doc = "Normal Write Cycle Wait Select"]
2235 #[inline(always)]
2236 pub fn cswwait(
2237 self,
2238 ) -> crate::common::RegisterField<
2239 16,
2240 0x1f,
2241 1,
2242 0,
2243 cswcr1::Cswwait,
2244 cswcr1::Cswwait,
2245 Cswcr1_SPEC,
2246 crate::common::RW,
2247 > {
2248 crate::common::RegisterField::<
2249 16,
2250 0x1f,
2251 1,
2252 0,
2253 cswcr1::Cswwait,
2254 cswcr1::Cswwait,
2255 Cswcr1_SPEC,
2256 crate::common::RW,
2257 >::from_register(self, 0)
2258 }
2259
2260 #[doc = "Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1."]
2261 #[inline(always)]
2262 pub fn csprwait(
2263 self,
2264 ) -> crate::common::RegisterField<
2265 8,
2266 0x7,
2267 1,
2268 0,
2269 cswcr1::Csprwait,
2270 cswcr1::Csprwait,
2271 Cswcr1_SPEC,
2272 crate::common::RW,
2273 > {
2274 crate::common::RegisterField::<
2275 8,
2276 0x7,
2277 1,
2278 0,
2279 cswcr1::Csprwait,
2280 cswcr1::Csprwait,
2281 Cswcr1_SPEC,
2282 crate::common::RW,
2283 >::from_register(self, 0)
2284 }
2285
2286 #[doc = "Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1."]
2287 #[inline(always)]
2288 pub fn cspwwait(
2289 self,
2290 ) -> crate::common::RegisterField<
2291 0,
2292 0x7,
2293 1,
2294 0,
2295 cswcr1::Cspwwait,
2296 cswcr1::Cspwwait,
2297 Cswcr1_SPEC,
2298 crate::common::RW,
2299 > {
2300 crate::common::RegisterField::<
2301 0,
2302 0x7,
2303 1,
2304 0,
2305 cswcr1::Cspwwait,
2306 cswcr1::Cspwwait,
2307 Cswcr1_SPEC,
2308 crate::common::RW,
2309 >::from_register(self, 0)
2310 }
2311}
2312impl ::core::default::Default for Cswcr1 {
2313 #[inline(always)]
2314 fn default() -> Cswcr1 {
2315 <crate::RegValueT<Cswcr1_SPEC> as RegisterValue<_>>::new(117901063)
2316 }
2317}
2318pub mod cswcr1 {
2319
2320 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2321 pub struct Csrwait_SPEC;
2322 pub type Csrwait = crate::EnumBitfieldStruct<u8, Csrwait_SPEC>;
2323 impl Csrwait {
2324 #[doc = "No wait is inserted."]
2325 pub const _0_X_00: Self = Self::new(0);
2326 }
2327 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2328 pub struct Cswwait_SPEC;
2329 pub type Cswwait = crate::EnumBitfieldStruct<u8, Cswwait_SPEC>;
2330 impl Cswwait {
2331 #[doc = "No wait is inserted."]
2332 pub const _0_X_00: Self = Self::new(0);
2333 }
2334 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2335 pub struct Csprwait_SPEC;
2336 pub type Csprwait = crate::EnumBitfieldStruct<u8, Csprwait_SPEC>;
2337 impl Csprwait {
2338 #[doc = "No wait is inserted."]
2339 pub const _0_X_0: Self = Self::new(0);
2340 }
2341 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2342 pub struct Cspwwait_SPEC;
2343 pub type Cspwwait = crate::EnumBitfieldStruct<u8, Cspwwait_SPEC>;
2344 impl Cspwwait {
2345 #[doc = "No wait is inserted."]
2346 pub const _0_X_0: Self = Self::new(0);
2347 }
2348}
2349#[doc(hidden)]
2350#[derive(Copy, Clone, Eq, PartialEq)]
2351pub struct Cswcr2_SPEC;
2352impl crate::sealed::RegSpec for Cswcr2_SPEC {
2353 type DataType = u32;
2354}
2355
2356#[doc = "CS%s Wait Control Register 2"]
2357pub type Cswcr2 = crate::RegValueT<Cswcr2_SPEC>;
2358
2359impl Cswcr2 {
2360 #[doc = "CS Assert Wait Select"]
2361 #[inline(always)]
2362 pub fn cson(
2363 self,
2364 ) -> crate::common::RegisterField<
2365 28,
2366 0x7,
2367 1,
2368 0,
2369 cswcr2::Cson,
2370 cswcr2::Cson,
2371 Cswcr2_SPEC,
2372 crate::common::RW,
2373 > {
2374 crate::common::RegisterField::<
2375 28,
2376 0x7,
2377 1,
2378 0,
2379 cswcr2::Cson,
2380 cswcr2::Cson,
2381 Cswcr2_SPEC,
2382 crate::common::RW,
2383 >::from_register(self, 0)
2384 }
2385
2386 #[doc = "Write Data Output Wait Select"]
2387 #[inline(always)]
2388 pub fn wdon(
2389 self,
2390 ) -> crate::common::RegisterField<
2391 24,
2392 0x7,
2393 1,
2394 0,
2395 cswcr2::Wdon,
2396 cswcr2::Wdon,
2397 Cswcr2_SPEC,
2398 crate::common::RW,
2399 > {
2400 crate::common::RegisterField::<
2401 24,
2402 0x7,
2403 1,
2404 0,
2405 cswcr2::Wdon,
2406 cswcr2::Wdon,
2407 Cswcr2_SPEC,
2408 crate::common::RW,
2409 >::from_register(self, 0)
2410 }
2411
2412 #[doc = "WR Assert Wait Select"]
2413 #[inline(always)]
2414 pub fn wron(
2415 self,
2416 ) -> crate::common::RegisterField<
2417 20,
2418 0x7,
2419 1,
2420 0,
2421 cswcr2::Wron,
2422 cswcr2::Wron,
2423 Cswcr2_SPEC,
2424 crate::common::RW,
2425 > {
2426 crate::common::RegisterField::<
2427 20,
2428 0x7,
2429 1,
2430 0,
2431 cswcr2::Wron,
2432 cswcr2::Wron,
2433 Cswcr2_SPEC,
2434 crate::common::RW,
2435 >::from_register(self, 0)
2436 }
2437
2438 #[doc = "RD Assert Wait Select"]
2439 #[inline(always)]
2440 pub fn rdon(
2441 self,
2442 ) -> crate::common::RegisterField<
2443 16,
2444 0x7,
2445 1,
2446 0,
2447 cswcr2::Rdon,
2448 cswcr2::Rdon,
2449 Cswcr2_SPEC,
2450 crate::common::RW,
2451 > {
2452 crate::common::RegisterField::<
2453 16,
2454 0x7,
2455 1,
2456 0,
2457 cswcr2::Rdon,
2458 cswcr2::Rdon,
2459 Cswcr2_SPEC,
2460 crate::common::RW,
2461 >::from_register(self, 0)
2462 }
2463
2464 #[doc = "Address Cycle Wait Select"]
2465 #[inline(always)]
2466 pub fn r#await(
2467 self,
2468 ) -> crate::common::RegisterField<
2469 12,
2470 0x3,
2471 1,
2472 0,
2473 cswcr2::Await,
2474 cswcr2::Await,
2475 Cswcr2_SPEC,
2476 crate::common::RW,
2477 > {
2478 crate::common::RegisterField::<
2479 12,
2480 0x3,
2481 1,
2482 0,
2483 cswcr2::Await,
2484 cswcr2::Await,
2485 Cswcr2_SPEC,
2486 crate::common::RW,
2487 >::from_register(self, 0)
2488 }
2489
2490 #[doc = "Write Data Output Extension Cycle Select"]
2491 #[inline(always)]
2492 pub fn wdoff(
2493 self,
2494 ) -> crate::common::RegisterField<
2495 8,
2496 0x7,
2497 1,
2498 0,
2499 cswcr2::Wdoff,
2500 cswcr2::Wdoff,
2501 Cswcr2_SPEC,
2502 crate::common::RW,
2503 > {
2504 crate::common::RegisterField::<
2505 8,
2506 0x7,
2507 1,
2508 0,
2509 cswcr2::Wdoff,
2510 cswcr2::Wdoff,
2511 Cswcr2_SPEC,
2512 crate::common::RW,
2513 >::from_register(self, 0)
2514 }
2515
2516 #[doc = "Write-Access CS Extension Cycle Select"]
2517 #[inline(always)]
2518 pub fn cswoff(
2519 self,
2520 ) -> crate::common::RegisterField<
2521 4,
2522 0x7,
2523 1,
2524 0,
2525 cswcr2::Cswoff,
2526 cswcr2::Cswoff,
2527 Cswcr2_SPEC,
2528 crate::common::RW,
2529 > {
2530 crate::common::RegisterField::<
2531 4,
2532 0x7,
2533 1,
2534 0,
2535 cswcr2::Cswoff,
2536 cswcr2::Cswoff,
2537 Cswcr2_SPEC,
2538 crate::common::RW,
2539 >::from_register(self, 0)
2540 }
2541
2542 #[doc = "Read-Access CS Extension Cycle Select"]
2543 #[inline(always)]
2544 pub fn csroff(
2545 self,
2546 ) -> crate::common::RegisterField<
2547 0,
2548 0x7,
2549 1,
2550 0,
2551 cswcr2::Csroff,
2552 cswcr2::Csroff,
2553 Cswcr2_SPEC,
2554 crate::common::RW,
2555 > {
2556 crate::common::RegisterField::<
2557 0,
2558 0x7,
2559 1,
2560 0,
2561 cswcr2::Csroff,
2562 cswcr2::Csroff,
2563 Cswcr2_SPEC,
2564 crate::common::RW,
2565 >::from_register(self, 0)
2566 }
2567}
2568impl ::core::default::Default for Cswcr2 {
2569 #[inline(always)]
2570 fn default() -> Cswcr2 {
2571 <crate::RegValueT<Cswcr2_SPEC> as RegisterValue<_>>::new(7)
2572 }
2573}
2574pub mod cswcr2 {
2575
2576 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2577 pub struct Cson_SPEC;
2578 pub type Cson = crate::EnumBitfieldStruct<u8, Cson_SPEC>;
2579 impl Cson {
2580 #[doc = "No wait is inserted."]
2581 pub const _0_X_0: Self = Self::new(0);
2582 }
2583 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2584 pub struct Wdon_SPEC;
2585 pub type Wdon = crate::EnumBitfieldStruct<u8, Wdon_SPEC>;
2586 impl Wdon {
2587 #[doc = "No wait is inserted."]
2588 pub const _0_X_0: Self = Self::new(0);
2589 }
2590 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2591 pub struct Wron_SPEC;
2592 pub type Wron = crate::EnumBitfieldStruct<u8, Wron_SPEC>;
2593 impl Wron {
2594 #[doc = "No wait is inserted."]
2595 pub const _0_X_0: Self = Self::new(0);
2596 }
2597 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2598 pub struct Rdon_SPEC;
2599 pub type Rdon = crate::EnumBitfieldStruct<u8, Rdon_SPEC>;
2600 impl Rdon {
2601 #[doc = "No wait is inserted."]
2602 pub const _0_X_0: Self = Self::new(0);
2603 }
2604 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2605 pub struct Await_SPEC;
2606 pub type Await = crate::EnumBitfieldStruct<u8, Await_SPEC>;
2607 impl Await {
2608 #[doc = "No wait is inserted."]
2609 pub const _0_X_0: Self = Self::new(0);
2610 }
2611 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2612 pub struct Wdoff_SPEC;
2613 pub type Wdoff = crate::EnumBitfieldStruct<u8, Wdoff_SPEC>;
2614 impl Wdoff {
2615 #[doc = "No wait is inserted."]
2616 pub const _0_X_0: Self = Self::new(0);
2617 }
2618 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2619 pub struct Cswoff_SPEC;
2620 pub type Cswoff = crate::EnumBitfieldStruct<u8, Cswoff_SPEC>;
2621 impl Cswoff {
2622 #[doc = "No wait is inserted."]
2623 pub const _0_X_0: Self = Self::new(0);
2624 }
2625 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2626 pub struct Csroff_SPEC;
2627 pub type Csroff = crate::EnumBitfieldStruct<u8, Csroff_SPEC>;
2628 impl Csroff {
2629 #[doc = "No wait is inserted."]
2630 pub const _0_X_0: Self = Self::new(0);
2631 }
2632}
2633#[doc(hidden)]
2634#[derive(Copy, Clone, Eq, PartialEq)]
2635pub struct Sdccr_SPEC;
2636impl crate::sealed::RegSpec for Sdccr_SPEC {
2637 type DataType = u8;
2638}
2639
2640#[doc = "SDC Control Register"]
2641pub type Sdccr = crate::RegValueT<Sdccr_SPEC>;
2642
2643impl Sdccr {
2644 #[doc = "SDRAM Bus Width Select"]
2645 #[inline(always)]
2646 pub fn bsize(
2647 self,
2648 ) -> crate::common::RegisterField<
2649 4,
2650 0x3,
2651 1,
2652 0,
2653 sdccr::Bsize,
2654 sdccr::Bsize,
2655 Sdccr_SPEC,
2656 crate::common::RW,
2657 > {
2658 crate::common::RegisterField::<
2659 4,
2660 0x3,
2661 1,
2662 0,
2663 sdccr::Bsize,
2664 sdccr::Bsize,
2665 Sdccr_SPEC,
2666 crate::common::RW,
2667 >::from_register(self, 0)
2668 }
2669
2670 #[doc = "Operation Enable"]
2671 #[inline(always)]
2672 pub fn exenb(
2673 self,
2674 ) -> crate::common::RegisterField<
2675 0,
2676 0x1,
2677 1,
2678 0,
2679 sdccr::Exenb,
2680 sdccr::Exenb,
2681 Sdccr_SPEC,
2682 crate::common::RW,
2683 > {
2684 crate::common::RegisterField::<
2685 0,
2686 0x1,
2687 1,
2688 0,
2689 sdccr::Exenb,
2690 sdccr::Exenb,
2691 Sdccr_SPEC,
2692 crate::common::RW,
2693 >::from_register(self, 0)
2694 }
2695}
2696impl ::core::default::Default for Sdccr {
2697 #[inline(always)]
2698 fn default() -> Sdccr {
2699 <crate::RegValueT<Sdccr_SPEC> as RegisterValue<_>>::new(0)
2700 }
2701}
2702pub mod sdccr {
2703
2704 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2705 pub struct Bsize_SPEC;
2706 pub type Bsize = crate::EnumBitfieldStruct<u8, Bsize_SPEC>;
2707 impl Bsize {
2708 #[doc = "A 16-bit bus space"]
2709 pub const _00: Self = Self::new(0);
2710
2711 #[doc = "Setting prohibited"]
2712 pub const _01: Self = Self::new(1);
2713
2714 #[doc = "An 8-bit bus space"]
2715 pub const _10: Self = Self::new(2);
2716
2717 #[doc = "Setting prohibited"]
2718 pub const _11: Self = Self::new(3);
2719 }
2720 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2721 pub struct Exenb_SPEC;
2722 pub type Exenb = crate::EnumBitfieldStruct<u8, Exenb_SPEC>;
2723 impl Exenb {
2724 #[doc = "Disable"]
2725 pub const _0: Self = Self::new(0);
2726
2727 #[doc = "Enable"]
2728 pub const _1: Self = Self::new(1);
2729 }
2730}
2731#[doc(hidden)]
2732#[derive(Copy, Clone, Eq, PartialEq)]
2733pub struct Sdcmod_SPEC;
2734impl crate::sealed::RegSpec for Sdcmod_SPEC {
2735 type DataType = u8;
2736}
2737
2738#[doc = "SDC Mode Register"]
2739pub type Sdcmod = crate::RegValueT<Sdcmod_SPEC>;
2740
2741impl Sdcmod {
2742 #[doc = "Endian Mode"]
2743 #[inline(always)]
2744 pub fn emode(
2745 self,
2746 ) -> crate::common::RegisterField<
2747 0,
2748 0x1,
2749 1,
2750 0,
2751 sdcmod::Emode,
2752 sdcmod::Emode,
2753 Sdcmod_SPEC,
2754 crate::common::RW,
2755 > {
2756 crate::common::RegisterField::<
2757 0,
2758 0x1,
2759 1,
2760 0,
2761 sdcmod::Emode,
2762 sdcmod::Emode,
2763 Sdcmod_SPEC,
2764 crate::common::RW,
2765 >::from_register(self, 0)
2766 }
2767}
2768impl ::core::default::Default for Sdcmod {
2769 #[inline(always)]
2770 fn default() -> Sdcmod {
2771 <crate::RegValueT<Sdcmod_SPEC> as RegisterValue<_>>::new(0)
2772 }
2773}
2774pub mod sdcmod {
2775
2776 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2777 pub struct Emode_SPEC;
2778 pub type Emode = crate::EnumBitfieldStruct<u8, Emode_SPEC>;
2779 impl Emode {
2780 #[doc = "Endian order of SDRAM address space is the same as the endian order of the operating mode"]
2781 pub const _0: Self = Self::new(0);
2782
2783 #[doc = "Endian order of SDRAM address space is not the endian order of the operating mode."]
2784 pub const _1: Self = Self::new(1);
2785 }
2786}
2787#[doc(hidden)]
2788#[derive(Copy, Clone, Eq, PartialEq)]
2789pub struct Sdamod_SPEC;
2790impl crate::sealed::RegSpec for Sdamod_SPEC {
2791 type DataType = u8;
2792}
2793
2794#[doc = "SDRAM Access Mode Register"]
2795pub type Sdamod = crate::RegValueT<Sdamod_SPEC>;
2796
2797impl Sdamod {
2798 #[doc = "Continuous Access Enable"]
2799 #[inline(always)]
2800 pub fn be(
2801 self,
2802 ) -> crate::common::RegisterField<
2803 0,
2804 0x1,
2805 1,
2806 0,
2807 sdamod::Be,
2808 sdamod::Be,
2809 Sdamod_SPEC,
2810 crate::common::RW,
2811 > {
2812 crate::common::RegisterField::<
2813 0,
2814 0x1,
2815 1,
2816 0,
2817 sdamod::Be,
2818 sdamod::Be,
2819 Sdamod_SPEC,
2820 crate::common::RW,
2821 >::from_register(self, 0)
2822 }
2823}
2824impl ::core::default::Default for Sdamod {
2825 #[inline(always)]
2826 fn default() -> Sdamod {
2827 <crate::RegValueT<Sdamod_SPEC> as RegisterValue<_>>::new(0)
2828 }
2829}
2830pub mod sdamod {
2831
2832 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2833 pub struct Be_SPEC;
2834 pub type Be = crate::EnumBitfieldStruct<u8, Be_SPEC>;
2835 impl Be {
2836 #[doc = "Disable"]
2837 pub const _0: Self = Self::new(0);
2838
2839 #[doc = "Enable."]
2840 pub const _1: Self = Self::new(1);
2841 }
2842}
2843#[doc(hidden)]
2844#[derive(Copy, Clone, Eq, PartialEq)]
2845pub struct Sdself_SPEC;
2846impl crate::sealed::RegSpec for Sdself_SPEC {
2847 type DataType = u8;
2848}
2849
2850#[doc = "SDRAM Self-Refresh Control Register"]
2851pub type Sdself = crate::RegValueT<Sdself_SPEC>;
2852
2853impl Sdself {
2854 #[doc = "SDRAM Self-Refresh Enable"]
2855 #[inline(always)]
2856 pub fn sfen(
2857 self,
2858 ) -> crate::common::RegisterField<
2859 0,
2860 0x1,
2861 1,
2862 0,
2863 sdself::Sfen,
2864 sdself::Sfen,
2865 Sdself_SPEC,
2866 crate::common::RW,
2867 > {
2868 crate::common::RegisterField::<
2869 0,
2870 0x1,
2871 1,
2872 0,
2873 sdself::Sfen,
2874 sdself::Sfen,
2875 Sdself_SPEC,
2876 crate::common::RW,
2877 >::from_register(self, 0)
2878 }
2879}
2880impl ::core::default::Default for Sdself {
2881 #[inline(always)]
2882 fn default() -> Sdself {
2883 <crate::RegValueT<Sdself_SPEC> as RegisterValue<_>>::new(0)
2884 }
2885}
2886pub mod sdself {
2887
2888 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2889 pub struct Sfen_SPEC;
2890 pub type Sfen = crate::EnumBitfieldStruct<u8, Sfen_SPEC>;
2891 impl Sfen {
2892 #[doc = "Disable"]
2893 pub const _0: Self = Self::new(0);
2894
2895 #[doc = "Enable"]
2896 pub const _1: Self = Self::new(1);
2897 }
2898}
2899#[doc(hidden)]
2900#[derive(Copy, Clone, Eq, PartialEq)]
2901pub struct Sdrfcr_SPEC;
2902impl crate::sealed::RegSpec for Sdrfcr_SPEC {
2903 type DataType = u16;
2904}
2905
2906#[doc = "SDRAM Refresh Control Register"]
2907pub type Sdrfcr = crate::RegValueT<Sdrfcr_SPEC>;
2908
2909impl Sdrfcr {
2910 #[doc = "Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count Setting. ( REFW+1 Cycles )"]
2911 #[inline(always)]
2912 pub fn refw(
2913 self,
2914 ) -> crate::common::RegisterField<12, 0xf, 1, 0, u8, u8, Sdrfcr_SPEC, crate::common::RW> {
2915 crate::common::RegisterField::<12,0xf,1,0,u8,u8,Sdrfcr_SPEC,crate::common::RW>::from_register(self,0)
2916 }
2917
2918 #[doc = "Auto-Refresh Request Interval Setting"]
2919 #[inline(always)]
2920 pub fn rfc(
2921 self,
2922 ) -> crate::common::RegisterField<
2923 0,
2924 0xfff,
2925 1,
2926 0,
2927 sdrfcr::Rfc,
2928 sdrfcr::Rfc,
2929 Sdrfcr_SPEC,
2930 crate::common::RW,
2931 > {
2932 crate::common::RegisterField::<
2933 0,
2934 0xfff,
2935 1,
2936 0,
2937 sdrfcr::Rfc,
2938 sdrfcr::Rfc,
2939 Sdrfcr_SPEC,
2940 crate::common::RW,
2941 >::from_register(self, 0)
2942 }
2943}
2944impl ::core::default::Default for Sdrfcr {
2945 #[inline(always)]
2946 fn default() -> Sdrfcr {
2947 <crate::RegValueT<Sdrfcr_SPEC> as RegisterValue<_>>::new(1)
2948 }
2949}
2950pub mod sdrfcr {
2951
2952 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2953 pub struct Rfc_SPEC;
2954 pub type Rfc = crate::EnumBitfieldStruct<u8, Rfc_SPEC>;
2955 impl Rfc {
2956 #[doc = "Setting prohibited"]
2957 pub const _0_X_0: Self = Self::new(0);
2958 }
2959}
2960#[doc(hidden)]
2961#[derive(Copy, Clone, Eq, PartialEq)]
2962pub struct Sdrfen_SPEC;
2963impl crate::sealed::RegSpec for Sdrfen_SPEC {
2964 type DataType = u8;
2965}
2966
2967#[doc = "SDRAM Auto-Refresh Control Register"]
2968pub type Sdrfen = crate::RegValueT<Sdrfen_SPEC>;
2969
2970impl Sdrfen {
2971 #[doc = "Auto-Refresh Operation Enable"]
2972 #[inline(always)]
2973 pub fn rfen(
2974 self,
2975 ) -> crate::common::RegisterField<
2976 0,
2977 0x1,
2978 1,
2979 0,
2980 sdrfen::Rfen,
2981 sdrfen::Rfen,
2982 Sdrfen_SPEC,
2983 crate::common::RW,
2984 > {
2985 crate::common::RegisterField::<
2986 0,
2987 0x1,
2988 1,
2989 0,
2990 sdrfen::Rfen,
2991 sdrfen::Rfen,
2992 Sdrfen_SPEC,
2993 crate::common::RW,
2994 >::from_register(self, 0)
2995 }
2996}
2997impl ::core::default::Default for Sdrfen {
2998 #[inline(always)]
2999 fn default() -> Sdrfen {
3000 <crate::RegValueT<Sdrfen_SPEC> as RegisterValue<_>>::new(0)
3001 }
3002}
3003pub mod sdrfen {
3004
3005 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3006 pub struct Rfen_SPEC;
3007 pub type Rfen = crate::EnumBitfieldStruct<u8, Rfen_SPEC>;
3008 impl Rfen {
3009 #[doc = "Disable"]
3010 pub const _0: Self = Self::new(0);
3011
3012 #[doc = "Enable"]
3013 pub const _1: Self = Self::new(1);
3014 }
3015}
3016#[doc(hidden)]
3017#[derive(Copy, Clone, Eq, PartialEq)]
3018pub struct Sdicr_SPEC;
3019impl crate::sealed::RegSpec for Sdicr_SPEC {
3020 type DataType = u8;
3021}
3022
3023#[doc = "SDRAM Initialization Sequence Control Register"]
3024pub type Sdicr = crate::RegValueT<Sdicr_SPEC>;
3025
3026impl Sdicr {
3027 #[doc = "Initialization Sequence Start"]
3028 #[inline(always)]
3029 pub fn inirq(
3030 self,
3031 ) -> crate::common::RegisterField<
3032 0,
3033 0x1,
3034 1,
3035 0,
3036 sdicr::Inirq,
3037 sdicr::Inirq,
3038 Sdicr_SPEC,
3039 crate::common::RW,
3040 > {
3041 crate::common::RegisterField::<
3042 0,
3043 0x1,
3044 1,
3045 0,
3046 sdicr::Inirq,
3047 sdicr::Inirq,
3048 Sdicr_SPEC,
3049 crate::common::RW,
3050 >::from_register(self, 0)
3051 }
3052}
3053impl ::core::default::Default for Sdicr {
3054 #[inline(always)]
3055 fn default() -> Sdicr {
3056 <crate::RegValueT<Sdicr_SPEC> as RegisterValue<_>>::new(0)
3057 }
3058}
3059pub mod sdicr {
3060
3061 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3062 pub struct Inirq_SPEC;
3063 pub type Inirq = crate::EnumBitfieldStruct<u8, Inirq_SPEC>;
3064 impl Inirq {
3065 #[doc = "Invalid"]
3066 pub const _0: Self = Self::new(0);
3067
3068 #[doc = "Initialization sequence starts"]
3069 pub const _1: Self = Self::new(1);
3070 }
3071}
3072#[doc(hidden)]
3073#[derive(Copy, Clone, Eq, PartialEq)]
3074pub struct Sdir_SPEC;
3075impl crate::sealed::RegSpec for Sdir_SPEC {
3076 type DataType = u16;
3077}
3078
3079#[doc = "SDRAM Initialization Register"]
3080pub type Sdir = crate::RegValueT<Sdir_SPEC>;
3081
3082impl Sdir {
3083 #[doc = "Initialization Precharge Cycle Count (PRC+3 cycles)"]
3084 #[inline(always)]
3085 pub fn prc(
3086 self,
3087 ) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, Sdir_SPEC, crate::common::RW> {
3088 crate::common::RegisterField::<8,0x7,1,0,u8,u8,Sdir_SPEC,crate::common::RW>::from_register(self,0)
3089 }
3090
3091 #[doc = "Initialization Auto-Refresh Count"]
3092 #[inline(always)]
3093 pub fn arfc(
3094 self,
3095 ) -> crate::common::RegisterField<
3096 4,
3097 0xf,
3098 1,
3099 0,
3100 sdir::Arfc,
3101 sdir::Arfc,
3102 Sdir_SPEC,
3103 crate::common::RW,
3104 > {
3105 crate::common::RegisterField::<
3106 4,
3107 0xf,
3108 1,
3109 0,
3110 sdir::Arfc,
3111 sdir::Arfc,
3112 Sdir_SPEC,
3113 crate::common::RW,
3114 >::from_register(self, 0)
3115 }
3116
3117 #[doc = "Initialization Auto-Refresh Interval (ARFI+3 cycles )"]
3118 #[inline(always)]
3119 pub fn arfi(
3120 self,
3121 ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, Sdir_SPEC, crate::common::RW> {
3122 crate::common::RegisterField::<0,0xf,1,0,u8,u8,Sdir_SPEC,crate::common::RW>::from_register(self,0)
3123 }
3124}
3125impl ::core::default::Default for Sdir {
3126 #[inline(always)]
3127 fn default() -> Sdir {
3128 <crate::RegValueT<Sdir_SPEC> as RegisterValue<_>>::new(16)
3129 }
3130}
3131pub mod sdir {
3132
3133 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3134 pub struct Arfc_SPEC;
3135 pub type Arfc = crate::EnumBitfieldStruct<u8, Arfc_SPEC>;
3136 impl Arfc {
3137 #[doc = "Setting prohibited"]
3138 pub const _0_X_0: Self = Self::new(0);
3139 }
3140}
3141#[doc(hidden)]
3142#[derive(Copy, Clone, Eq, PartialEq)]
3143pub struct Sdadr_SPEC;
3144impl crate::sealed::RegSpec for Sdadr_SPEC {
3145 type DataType = u8;
3146}
3147
3148#[doc = "SDRAM Address Register"]
3149pub type Sdadr = crate::RegValueT<Sdadr_SPEC>;
3150
3151impl Sdadr {
3152 #[doc = "Address Multiplex Select"]
3153 #[inline(always)]
3154 pub fn mxc(
3155 self,
3156 ) -> crate::common::RegisterField<
3157 0,
3158 0x3,
3159 1,
3160 0,
3161 sdadr::Mxc,
3162 sdadr::Mxc,
3163 Sdadr_SPEC,
3164 crate::common::RW,
3165 > {
3166 crate::common::RegisterField::<
3167 0,
3168 0x3,
3169 1,
3170 0,
3171 sdadr::Mxc,
3172 sdadr::Mxc,
3173 Sdadr_SPEC,
3174 crate::common::RW,
3175 >::from_register(self, 0)
3176 }
3177}
3178impl ::core::default::Default for Sdadr {
3179 #[inline(always)]
3180 fn default() -> Sdadr {
3181 <crate::RegValueT<Sdadr_SPEC> as RegisterValue<_>>::new(0)
3182 }
3183}
3184pub mod sdadr {
3185
3186 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3187 pub struct Mxc_SPEC;
3188 pub type Mxc = crate::EnumBitfieldStruct<u8, Mxc_SPEC>;
3189 impl Mxc {
3190 #[doc = "8-bit shift"]
3191 pub const _00: Self = Self::new(0);
3192
3193 #[doc = "9-bit shift"]
3194 pub const _01: Self = Self::new(1);
3195
3196 #[doc = "10-bit shift"]
3197 pub const _10: Self = Self::new(2);
3198
3199 #[doc = "11-bit shift"]
3200 pub const _11: Self = Self::new(3);
3201 }
3202}
3203#[doc(hidden)]
3204#[derive(Copy, Clone, Eq, PartialEq)]
3205pub struct Sdtr_SPEC;
3206impl crate::sealed::RegSpec for Sdtr_SPEC {
3207 type DataType = u32;
3208}
3209
3210#[doc = "SDRAM Timing Register"]
3211pub type Sdtr = crate::RegValueT<Sdtr_SPEC>;
3212
3213impl Sdtr {
3214 #[doc = "Row Active Interval"]
3215 #[inline(always)]
3216 pub fn ras(
3217 self,
3218 ) -> crate::common::RegisterField<
3219 16,
3220 0x7,
3221 1,
3222 0,
3223 sdtr::Ras,
3224 sdtr::Ras,
3225 Sdtr_SPEC,
3226 crate::common::RW,
3227 > {
3228 crate::common::RegisterField::<
3229 16,
3230 0x7,
3231 1,
3232 0,
3233 sdtr::Ras,
3234 sdtr::Ras,
3235 Sdtr_SPEC,
3236 crate::common::RW,
3237 >::from_register(self, 0)
3238 }
3239
3240 #[doc = "Row Column Latency ( RCD+1 cycles )"]
3241 #[inline(always)]
3242 pub fn rcd(
3243 self,
3244 ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, Sdtr_SPEC, crate::common::RW> {
3245 crate::common::RegisterField::<12,0x3,1,0,u8,u8,Sdtr_SPEC,crate::common::RW>::from_register(self,0)
3246 }
3247
3248 #[doc = "Row Precharge Interval ( RP+1 cycles )"]
3249 #[inline(always)]
3250 pub fn rp(
3251 self,
3252 ) -> crate::common::RegisterField<9, 0x7, 1, 0, u8, u8, Sdtr_SPEC, crate::common::RW> {
3253 crate::common::RegisterField::<9,0x7,1,0,u8,u8,Sdtr_SPEC,crate::common::RW>::from_register(self,0)
3254 }
3255
3256 #[doc = "Write Recovery Interval"]
3257 #[inline(always)]
3258 pub fn wr(
3259 self,
3260 ) -> crate::common::RegisterField<8, 0x1, 1, 0, sdtr::Wr, sdtr::Wr, Sdtr_SPEC, crate::common::RW>
3261 {
3262 crate::common::RegisterField::<8,0x1,1,0,sdtr::Wr,sdtr::Wr,Sdtr_SPEC,crate::common::RW>::from_register(self,0)
3263 }
3264
3265 #[doc = "SDRAMC Column Latency"]
3266 #[inline(always)]
3267 pub fn cl(
3268 self,
3269 ) -> crate::common::RegisterField<0, 0x7, 1, 0, sdtr::Cl, sdtr::Cl, Sdtr_SPEC, crate::common::RW>
3270 {
3271 crate::common::RegisterField::<0,0x7,1,0,sdtr::Cl,sdtr::Cl,Sdtr_SPEC,crate::common::RW>::from_register(self,0)
3272 }
3273}
3274impl ::core::default::Default for Sdtr {
3275 #[inline(always)]
3276 fn default() -> Sdtr {
3277 <crate::RegValueT<Sdtr_SPEC> as RegisterValue<_>>::new(2)
3278 }
3279}
3280pub mod sdtr {
3281
3282 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3283 pub struct Ras_SPEC;
3284 pub type Ras = crate::EnumBitfieldStruct<u8, Ras_SPEC>;
3285 impl Ras {
3286 #[doc = "1 cycle"]
3287 pub const _000: Self = Self::new(0);
3288
3289 #[doc = "2 cycles"]
3290 pub const _001: Self = Self::new(1);
3291
3292 #[doc = "3 cycles"]
3293 pub const _010: Self = Self::new(2);
3294
3295 #[doc = "4 cycles"]
3296 pub const _011: Self = Self::new(3);
3297
3298 #[doc = "5 cycles"]
3299 pub const _100: Self = Self::new(4);
3300
3301 #[doc = "6 cycles"]
3302 pub const _101: Self = Self::new(5);
3303
3304 #[doc = "7 cycles"]
3305 pub const _110: Self = Self::new(6);
3306
3307 #[doc = "Setting prohibited"]
3308 pub const _111: Self = Self::new(7);
3309 }
3310 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3311 pub struct Wr_SPEC;
3312 pub type Wr = crate::EnumBitfieldStruct<u8, Wr_SPEC>;
3313 impl Wr {
3314 #[doc = "1 cycle"]
3315 pub const _0: Self = Self::new(0);
3316
3317 #[doc = "2 cycles"]
3318 pub const _1: Self = Self::new(1);
3319 }
3320 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3321 pub struct Cl_SPEC;
3322 pub type Cl = crate::EnumBitfieldStruct<u8, Cl_SPEC>;
3323 impl Cl {
3324 #[doc = "1 cycle"]
3325 pub const _001: Self = Self::new(1);
3326
3327 #[doc = "2 cycles"]
3328 pub const _010: Self = Self::new(2);
3329
3330 #[doc = "3 cycles"]
3331 pub const _011: Self = Self::new(3);
3332 }
3333}
3334#[doc(hidden)]
3335#[derive(Copy, Clone, Eq, PartialEq)]
3336pub struct Sdmod_SPEC;
3337impl crate::sealed::RegSpec for Sdmod_SPEC {
3338 type DataType = u16;
3339}
3340
3341#[doc = "SDRAM Mode Register"]
3342pub type Sdmod = crate::RegValueT<Sdmod_SPEC>;
3343
3344impl Sdmod {
3345 #[doc = "Mode Register SettingWriting to these bits: Mode register set command is issued."]
3346 #[inline(always)]
3347 pub fn mr(
3348 self,
3349 ) -> crate::common::RegisterField<0, 0x7fff, 1, 0, u16, u16, Sdmod_SPEC, crate::common::RW>
3350 {
3351 crate::common::RegisterField::<0,0x7fff,1,0,u16,u16,Sdmod_SPEC,crate::common::RW>::from_register(self,0)
3352 }
3353}
3354impl ::core::default::Default for Sdmod {
3355 #[inline(always)]
3356 fn default() -> Sdmod {
3357 <crate::RegValueT<Sdmod_SPEC> as RegisterValue<_>>::new(0)
3358 }
3359}
3360
3361#[doc(hidden)]
3362#[derive(Copy, Clone, Eq, PartialEq)]
3363pub struct Sdsr_SPEC;
3364impl crate::sealed::RegSpec for Sdsr_SPEC {
3365 type DataType = u8;
3366}
3367
3368#[doc = "SDRAM Status Register"]
3369pub type Sdsr = crate::RegValueT<Sdsr_SPEC>;
3370
3371impl Sdsr {
3372 #[doc = "Self-Refresh Transition/Recovery Status"]
3373 #[inline(always)]
3374 pub fn srfst(
3375 self,
3376 ) -> crate::common::RegisterField<
3377 4,
3378 0x1,
3379 1,
3380 0,
3381 sdsr::Srfst,
3382 sdsr::Srfst,
3383 Sdsr_SPEC,
3384 crate::common::R,
3385 > {
3386 crate::common::RegisterField::<
3387 4,
3388 0x1,
3389 1,
3390 0,
3391 sdsr::Srfst,
3392 sdsr::Srfst,
3393 Sdsr_SPEC,
3394 crate::common::R,
3395 >::from_register(self, 0)
3396 }
3397
3398 #[doc = "Initialization Status"]
3399 #[inline(always)]
3400 pub fn inist(
3401 self,
3402 ) -> crate::common::RegisterField<
3403 3,
3404 0x1,
3405 1,
3406 0,
3407 sdsr::Inist,
3408 sdsr::Inist,
3409 Sdsr_SPEC,
3410 crate::common::R,
3411 > {
3412 crate::common::RegisterField::<
3413 3,
3414 0x1,
3415 1,
3416 0,
3417 sdsr::Inist,
3418 sdsr::Inist,
3419 Sdsr_SPEC,
3420 crate::common::R,
3421 >::from_register(self, 0)
3422 }
3423
3424 #[doc = "Mode Register Setting Status"]
3425 #[inline(always)]
3426 pub fn mrsst(
3427 self,
3428 ) -> crate::common::RegisterField<
3429 0,
3430 0x1,
3431 1,
3432 0,
3433 sdsr::Mrsst,
3434 sdsr::Mrsst,
3435 Sdsr_SPEC,
3436 crate::common::R,
3437 > {
3438 crate::common::RegisterField::<
3439 0,
3440 0x1,
3441 1,
3442 0,
3443 sdsr::Mrsst,
3444 sdsr::Mrsst,
3445 Sdsr_SPEC,
3446 crate::common::R,
3447 >::from_register(self, 0)
3448 }
3449}
3450impl ::core::default::Default for Sdsr {
3451 #[inline(always)]
3452 fn default() -> Sdsr {
3453 <crate::RegValueT<Sdsr_SPEC> as RegisterValue<_>>::new(0)
3454 }
3455}
3456pub mod sdsr {
3457
3458 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3459 pub struct Srfst_SPEC;
3460 pub type Srfst = crate::EnumBitfieldStruct<u8, Srfst_SPEC>;
3461 impl Srfst {
3462 #[doc = "Transition/recovery not in progress"]
3463 pub const _0: Self = Self::new(0);
3464
3465 #[doc = "Transition/recovery in progress"]
3466 pub const _1: Self = Self::new(1);
3467 }
3468 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3469 pub struct Inist_SPEC;
3470 pub type Inist = crate::EnumBitfieldStruct<u8, Inist_SPEC>;
3471 impl Inist {
3472 #[doc = "Initialization sequence not in progress"]
3473 pub const _0: Self = Self::new(0);
3474
3475 #[doc = "Initialization sequence in progress"]
3476 pub const _1: Self = Self::new(1);
3477 }
3478 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3479 pub struct Mrsst_SPEC;
3480 pub type Mrsst = crate::EnumBitfieldStruct<u8, Mrsst_SPEC>;
3481 impl Mrsst {
3482 #[doc = "Mode register setting not in progress"]
3483 pub const _0: Self = Self::new(0);
3484
3485 #[doc = "Mode register setting in progress"]
3486 pub const _1: Self = Self::new(1);
3487 }
3488}
3489#[doc(hidden)]
3490#[derive(Copy, Clone, Eq, PartialEq)]
3491pub struct Buserradd_SPEC;
3492impl crate::sealed::RegSpec for Buserradd_SPEC {
3493 type DataType = u32;
3494}
3495
3496#[doc = "Bus Error Address Register %s"]
3497pub type Buserradd = crate::RegValueT<Buserradd_SPEC>;
3498
3499impl Buserradd {
3500 #[doc = "Bus Error AddressWhen a bus error occurs, It stores an error address."]
3501 #[inline(always)]
3502 pub fn berad(
3503 self,
3504 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Buserradd_SPEC, crate::common::R>
3505 {
3506 crate::common::RegisterField::<
3507 0,
3508 0xffffffff,
3509 1,
3510 0,
3511 u32,
3512 u32,
3513 Buserradd_SPEC,
3514 crate::common::R,
3515 >::from_register(self, 0)
3516 }
3517}
3518impl ::core::default::Default for Buserradd {
3519 #[inline(always)]
3520 fn default() -> Buserradd {
3521 <crate::RegValueT<Buserradd_SPEC> as RegisterValue<_>>::new(0)
3522 }
3523}
3524
3525#[doc(hidden)]
3526#[derive(Copy, Clone, Eq, PartialEq)]
3527pub struct Buserrstat_SPEC;
3528impl crate::sealed::RegSpec for Buserrstat_SPEC {
3529 type DataType = u8;
3530}
3531
3532#[doc = "Bus Error Status Register %s"]
3533pub type Buserrstat = crate::RegValueT<Buserrstat_SPEC>;
3534
3535impl Buserrstat {
3536 #[doc = "Bus Error StatusWhen bus error assert, error flag occurs."]
3537 #[inline(always)]
3538 pub fn errstat(
3539 self,
3540 ) -> crate::common::RegisterField<
3541 7,
3542 0x1,
3543 1,
3544 0,
3545 buserrstat::Errstat,
3546 buserrstat::Errstat,
3547 Buserrstat_SPEC,
3548 crate::common::R,
3549 > {
3550 crate::common::RegisterField::<
3551 7,
3552 0x1,
3553 1,
3554 0,
3555 buserrstat::Errstat,
3556 buserrstat::Errstat,
3557 Buserrstat_SPEC,
3558 crate::common::R,
3559 >::from_register(self, 0)
3560 }
3561
3562 #[doc = "Error access statusThe status at the time of the error"]
3563 #[inline(always)]
3564 pub fn accstat(
3565 self,
3566 ) -> crate::common::RegisterField<
3567 0,
3568 0x1,
3569 1,
3570 0,
3571 buserrstat::Accstat,
3572 buserrstat::Accstat,
3573 Buserrstat_SPEC,
3574 crate::common::R,
3575 > {
3576 crate::common::RegisterField::<
3577 0,
3578 0x1,
3579 1,
3580 0,
3581 buserrstat::Accstat,
3582 buserrstat::Accstat,
3583 Buserrstat_SPEC,
3584 crate::common::R,
3585 >::from_register(self, 0)
3586 }
3587}
3588impl ::core::default::Default for Buserrstat {
3589 #[inline(always)]
3590 fn default() -> Buserrstat {
3591 <crate::RegValueT<Buserrstat_SPEC> as RegisterValue<_>>::new(0)
3592 }
3593}
3594pub mod buserrstat {
3595
3596 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3597 pub struct Errstat_SPEC;
3598 pub type Errstat = crate::EnumBitfieldStruct<u8, Errstat_SPEC>;
3599 impl Errstat {
3600 #[doc = "No bus error occurred"]
3601 pub const _0: Self = Self::new(0);
3602
3603 #[doc = "Bus error occurred"]
3604 pub const _1: Self = Self::new(1);
3605 }
3606 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3607 pub struct Accstat_SPEC;
3608 pub type Accstat = crate::EnumBitfieldStruct<u8, Accstat_SPEC>;
3609 impl Accstat {
3610 #[doc = "Read access"]
3611 pub const _0: Self = Self::new(0);
3612
3613 #[doc = "Write Access"]
3614 pub const _1: Self = Self::new(1);
3615 }
3616}
3617#[doc(hidden)]
3618#[derive(Copy, Clone, Eq, PartialEq)]
3619pub struct Busmcntsys_SPEC;
3620impl crate::sealed::RegSpec for Busmcntsys_SPEC {
3621 type DataType = u16;
3622}
3623
3624#[doc = "Master Bus Control Register SYS"]
3625pub type Busmcntsys = crate::RegValueT<Busmcntsys_SPEC>;
3626
3627impl Busmcntsys {
3628 #[doc = "Ignore Error Responses"]
3629 #[inline(always)]
3630 pub fn ieres(
3631 self,
3632 ) -> crate::common::RegisterField<
3633 15,
3634 0x1,
3635 1,
3636 0,
3637 busmcntsys::Ieres,
3638 busmcntsys::Ieres,
3639 Busmcntsys_SPEC,
3640 crate::common::RW,
3641 > {
3642 crate::common::RegisterField::<
3643 15,
3644 0x1,
3645 1,
3646 0,
3647 busmcntsys::Ieres,
3648 busmcntsys::Ieres,
3649 Busmcntsys_SPEC,
3650 crate::common::RW,
3651 >::from_register(self, 0)
3652 }
3653}
3654impl ::core::default::Default for Busmcntsys {
3655 #[inline(always)]
3656 fn default() -> Busmcntsys {
3657 <crate::RegValueT<Busmcntsys_SPEC> as RegisterValue<_>>::new(0)
3658 }
3659}
3660pub mod busmcntsys {
3661
3662 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3663 pub struct Ieres_SPEC;
3664 pub type Ieres = crate::EnumBitfieldStruct<u8, Ieres_SPEC>;
3665 impl Ieres {
3666 #[doc = "Bus error will be reported."]
3667 pub const _0: Self = Self::new(0);
3668
3669 #[doc = "Bus error will not be reported."]
3670 pub const _1: Self = Self::new(1);
3671 }
3672}
3673#[doc(hidden)]
3674#[derive(Copy, Clone, Eq, PartialEq)]
3675pub struct Busmcntdma_SPEC;
3676impl crate::sealed::RegSpec for Busmcntdma_SPEC {
3677 type DataType = u16;
3678}
3679
3680#[doc = "Master Bus Control Register DMA"]
3681pub type Busmcntdma = crate::RegValueT<Busmcntdma_SPEC>;
3682
3683impl Busmcntdma {
3684 #[doc = "Ignore Error Responses"]
3685 #[inline(always)]
3686 pub fn ieres(
3687 self,
3688 ) -> crate::common::RegisterField<
3689 15,
3690 0x1,
3691 1,
3692 0,
3693 busmcntdma::Ieres,
3694 busmcntdma::Ieres,
3695 Busmcntdma_SPEC,
3696 crate::common::RW,
3697 > {
3698 crate::common::RegisterField::<
3699 15,
3700 0x1,
3701 1,
3702 0,
3703 busmcntdma::Ieres,
3704 busmcntdma::Ieres,
3705 Busmcntdma_SPEC,
3706 crate::common::RW,
3707 >::from_register(self, 0)
3708 }
3709}
3710impl ::core::default::Default for Busmcntdma {
3711 #[inline(always)]
3712 fn default() -> Busmcntdma {
3713 <crate::RegValueT<Busmcntdma_SPEC> as RegisterValue<_>>::new(0)
3714 }
3715}
3716pub mod busmcntdma {
3717
3718 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3719 pub struct Ieres_SPEC;
3720 pub type Ieres = crate::EnumBitfieldStruct<u8, Ieres_SPEC>;
3721 impl Ieres {
3722 #[doc = "Bus error will be reported."]
3723 pub const _0: Self = Self::new(0);
3724
3725 #[doc = "Bus error will not be reported."]
3726 pub const _1: Self = Self::new(1);
3727 }
3728}
3729#[doc(hidden)]
3730#[derive(Copy, Clone, Eq, PartialEq)]
3731pub struct Busmcnt_SPEC;
3732impl crate::sealed::RegSpec for Busmcnt_SPEC {
3733 type DataType = u16;
3734}
3735
3736#[doc = "Master Bus Control Register %s"]
3737pub type Busmcnt = crate::RegValueT<Busmcnt_SPEC>;
3738
3739impl Busmcnt {
3740 #[doc = "Ignore Error Responses"]
3741 #[inline(always)]
3742 pub fn ieres(
3743 self,
3744 ) -> crate::common::RegisterField<
3745 15,
3746 0x1,
3747 1,
3748 0,
3749 busmcnt::Ieres,
3750 busmcnt::Ieres,
3751 Busmcnt_SPEC,
3752 crate::common::RW,
3753 > {
3754 crate::common::RegisterField::<
3755 15,
3756 0x1,
3757 1,
3758 0,
3759 busmcnt::Ieres,
3760 busmcnt::Ieres,
3761 Busmcnt_SPEC,
3762 crate::common::RW,
3763 >::from_register(self, 0)
3764 }
3765}
3766impl ::core::default::Default for Busmcnt {
3767 #[inline(always)]
3768 fn default() -> Busmcnt {
3769 <crate::RegValueT<Busmcnt_SPEC> as RegisterValue<_>>::new(0)
3770 }
3771}
3772pub mod busmcnt {
3773
3774 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3775 pub struct Ieres_SPEC;
3776 pub type Ieres = crate::EnumBitfieldStruct<u8, Ieres_SPEC>;
3777 impl Ieres {
3778 #[doc = "Bus error will be reported."]
3779 pub const _0: Self = Self::new(0);
3780
3781 #[doc = "Bus error will not be reported."]
3782 pub const _1: Self = Self::new(1);
3783 }
3784}
3785#[doc(hidden)]
3786#[derive(Copy, Clone, Eq, PartialEq)]
3787pub struct Busscntmbiu_SPEC;
3788impl crate::sealed::RegSpec for Busscntmbiu_SPEC {
3789 type DataType = u16;
3790}
3791
3792#[doc = "Slave Bus Control Register MBIU"]
3793pub type Busscntmbiu = crate::RegValueT<Busscntmbiu_SPEC>;
3794
3795impl Busscntmbiu {
3796 #[doc = "Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back."]
3797 #[inline(always)]
3798 pub fn ewres(
3799 self,
3800 ) -> crate::common::RegisterField<
3801 8,
3802 0x1,
3803 1,
3804 0,
3805 busscntmbiu::Ewres,
3806 busscntmbiu::Ewres,
3807 Busscntmbiu_SPEC,
3808 crate::common::RW,
3809 > {
3810 crate::common::RegisterField::<
3811 8,
3812 0x1,
3813 1,
3814 0,
3815 busscntmbiu::Ewres,
3816 busscntmbiu::Ewres,
3817 Busscntmbiu_SPEC,
3818 crate::common::RW,
3819 >::from_register(self, 0)
3820 }
3821
3822 #[doc = "Arbitration MethodSpecify the priority between groups"]
3823 #[inline(always)]
3824 pub fn arbmet(
3825 self,
3826 ) -> crate::common::RegisterField<
3827 4,
3828 0x3,
3829 1,
3830 0,
3831 busscntmbiu::Arbmet,
3832 busscntmbiu::Arbmet,
3833 Busscntmbiu_SPEC,
3834 crate::common::RW,
3835 > {
3836 crate::common::RegisterField::<
3837 4,
3838 0x3,
3839 1,
3840 0,
3841 busscntmbiu::Arbmet,
3842 busscntmbiu::Arbmet,
3843 Busscntmbiu_SPEC,
3844 crate::common::RW,
3845 >::from_register(self, 0)
3846 }
3847}
3848impl ::core::default::Default for Busscntmbiu {
3849 #[inline(always)]
3850 fn default() -> Busscntmbiu {
3851 <crate::RegValueT<Busscntmbiu_SPEC> as RegisterValue<_>>::new(0)
3852 }
3853}
3854pub mod busscntmbiu {
3855
3856 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3857 pub struct Ewres_SPEC;
3858 pub type Ewres = crate::EnumBitfieldStruct<u8, Ewres_SPEC>;
3859 impl Ewres {
3860 #[doc = "Not accepted."]
3861 pub const _0: Self = Self::new(0);
3862
3863 #[doc = "Accepted but error response is ignored."]
3864 pub const _1: Self = Self::new(1);
3865 }
3866 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3867 pub struct Arbmet_SPEC;
3868 pub type Arbmet = crate::EnumBitfieldStruct<u8, Arbmet_SPEC>;
3869 impl Arbmet {
3870 #[doc = "fixed priority"]
3871 pub const _00: Self = Self::new(0);
3872
3873 #[doc = "round-robin"]
3874 pub const _01: Self = Self::new(1);
3875 }
3876}
3877#[doc(hidden)]
3878#[derive(Copy, Clone, Eq, PartialEq)]
3879pub struct Busscnt_SPEC;
3880impl crate::sealed::RegSpec for Busscnt_SPEC {
3881 type DataType = u16;
3882}
3883
3884#[doc = "Slave Bus Control Register %s"]
3885pub type Busscnt = crate::RegValueT<Busscnt_SPEC>;
3886
3887impl Busscnt {
3888 #[doc = "Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back."]
3889 #[inline(always)]
3890 pub fn ewres(
3891 self,
3892 ) -> crate::common::RegisterField<
3893 8,
3894 0x1,
3895 1,
3896 0,
3897 busscnt::Ewres,
3898 busscnt::Ewres,
3899 Busscnt_SPEC,
3900 crate::common::RW,
3901 > {
3902 crate::common::RegisterField::<
3903 8,
3904 0x1,
3905 1,
3906 0,
3907 busscnt::Ewres,
3908 busscnt::Ewres,
3909 Busscnt_SPEC,
3910 crate::common::RW,
3911 >::from_register(self, 0)
3912 }
3913
3914 #[doc = "Arbitration MethodSpecify the priority between groups"]
3915 #[inline(always)]
3916 pub fn arbmet(
3917 self,
3918 ) -> crate::common::RegisterField<
3919 4,
3920 0x3,
3921 1,
3922 0,
3923 busscnt::Arbmet,
3924 busscnt::Arbmet,
3925 Busscnt_SPEC,
3926 crate::common::RW,
3927 > {
3928 crate::common::RegisterField::<
3929 4,
3930 0x3,
3931 1,
3932 0,
3933 busscnt::Arbmet,
3934 busscnt::Arbmet,
3935 Busscnt_SPEC,
3936 crate::common::RW,
3937 >::from_register(self, 0)
3938 }
3939}
3940impl ::core::default::Default for Busscnt {
3941 #[inline(always)]
3942 fn default() -> Busscnt {
3943 <crate::RegValueT<Busscnt_SPEC> as RegisterValue<_>>::new(0)
3944 }
3945}
3946pub mod busscnt {
3947
3948 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3949 pub struct Ewres_SPEC;
3950 pub type Ewres = crate::EnumBitfieldStruct<u8, Ewres_SPEC>;
3951 impl Ewres {
3952 #[doc = "Not accepted."]
3953 pub const _0: Self = Self::new(0);
3954
3955 #[doc = "Accepted but error response is ignored."]
3956 pub const _1: Self = Self::new(1);
3957 }
3958 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3959 pub struct Arbmet_SPEC;
3960 pub type Arbmet = crate::EnumBitfieldStruct<u8, Arbmet_SPEC>;
3961 impl Arbmet {
3962 #[doc = "fixed priority"]
3963 pub const _00: Self = Self::new(0);
3964
3965 #[doc = "round-robin"]
3966 pub const _01: Self = Self::new(1);
3967 }
3968}