ra6m2_pac/
qspi.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:11:44 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Quad-SPI"]
28unsafe impl ::core::marker::Send for super::Qspi {}
29unsafe impl ::core::marker::Sync for super::Qspi {}
30impl super::Qspi {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Transfer Mode Control Register"]
38    #[inline(always)]
39    pub const fn sfmsmd(
40        &self,
41    ) -> &'static crate::common::Reg<self::Sfmsmd_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::Sfmsmd_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(0usize),
45            )
46        }
47    }
48
49    #[doc = "Chip Selection Control Register"]
50    #[inline(always)]
51    pub const fn sfmssc(
52        &self,
53    ) -> &'static crate::common::Reg<self::Sfmssc_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::Sfmssc_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(4usize),
57            )
58        }
59    }
60
61    #[doc = "Clock Control Register"]
62    #[inline(always)]
63    pub const fn sfmskc(
64        &self,
65    ) -> &'static crate::common::Reg<self::Sfmskc_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::Sfmskc_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(8usize),
69            )
70        }
71    }
72
73    #[doc = "Status Register"]
74    #[inline(always)]
75    pub const fn sfmsst(&self) -> &'static crate::common::Reg<self::Sfmsst_SPEC, crate::common::R> {
76        unsafe {
77            crate::common::Reg::<self::Sfmsst_SPEC, crate::common::R>::from_ptr(
78                self._svd2pac_as_ptr().add(12usize),
79            )
80        }
81    }
82
83    #[doc = "Communication Port Register"]
84    #[inline(always)]
85    pub const fn sfmcom(
86        &self,
87    ) -> &'static crate::common::Reg<self::Sfmcom_SPEC, crate::common::RW> {
88        unsafe {
89            crate::common::Reg::<self::Sfmcom_SPEC, crate::common::RW>::from_ptr(
90                self._svd2pac_as_ptr().add(16usize),
91            )
92        }
93    }
94
95    #[doc = "Communication Mode Control Register"]
96    #[inline(always)]
97    pub const fn sfmcmd(
98        &self,
99    ) -> &'static crate::common::Reg<self::Sfmcmd_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::Sfmcmd_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(20usize),
103            )
104        }
105    }
106
107    #[doc = "Communication Status Register"]
108    #[inline(always)]
109    pub const fn sfmcst(
110        &self,
111    ) -> &'static crate::common::Reg<self::Sfmcst_SPEC, crate::common::RW> {
112        unsafe {
113            crate::common::Reg::<self::Sfmcst_SPEC, crate::common::RW>::from_ptr(
114                self._svd2pac_as_ptr().add(24usize),
115            )
116        }
117    }
118
119    #[doc = "Instruction Code Register"]
120    #[inline(always)]
121    pub const fn sfmsic(
122        &self,
123    ) -> &'static crate::common::Reg<self::Sfmsic_SPEC, crate::common::RW> {
124        unsafe {
125            crate::common::Reg::<self::Sfmsic_SPEC, crate::common::RW>::from_ptr(
126                self._svd2pac_as_ptr().add(32usize),
127            )
128        }
129    }
130
131    #[doc = "Address Mode Control Register"]
132    #[inline(always)]
133    pub const fn sfmsac(
134        &self,
135    ) -> &'static crate::common::Reg<self::Sfmsac_SPEC, crate::common::RW> {
136        unsafe {
137            crate::common::Reg::<self::Sfmsac_SPEC, crate::common::RW>::from_ptr(
138                self._svd2pac_as_ptr().add(36usize),
139            )
140        }
141    }
142
143    #[doc = "Dummy Cycle Control Register"]
144    #[inline(always)]
145    pub const fn sfmsdc(
146        &self,
147    ) -> &'static crate::common::Reg<self::Sfmsdc_SPEC, crate::common::RW> {
148        unsafe {
149            crate::common::Reg::<self::Sfmsdc_SPEC, crate::common::RW>::from_ptr(
150                self._svd2pac_as_ptr().add(40usize),
151            )
152        }
153    }
154
155    #[doc = "SPI Protocol Control Register"]
156    #[inline(always)]
157    pub const fn sfmspc(
158        &self,
159    ) -> &'static crate::common::Reg<self::Sfmspc_SPEC, crate::common::RW> {
160        unsafe {
161            crate::common::Reg::<self::Sfmspc_SPEC, crate::common::RW>::from_ptr(
162                self._svd2pac_as_ptr().add(48usize),
163            )
164        }
165    }
166
167    #[doc = "Port Control Register"]
168    #[inline(always)]
169    pub const fn sfmpmd(
170        &self,
171    ) -> &'static crate::common::Reg<self::Sfmpmd_SPEC, crate::common::RW> {
172        unsafe {
173            crate::common::Reg::<self::Sfmpmd_SPEC, crate::common::RW>::from_ptr(
174                self._svd2pac_as_ptr().add(52usize),
175            )
176        }
177    }
178
179    #[doc = "External QSPI Address Register 1"]
180    #[inline(always)]
181    pub const fn sfmcnt1(
182        &self,
183    ) -> &'static crate::common::Reg<self::Sfmcnt1_SPEC, crate::common::RW> {
184        unsafe {
185            crate::common::Reg::<self::Sfmcnt1_SPEC, crate::common::RW>::from_ptr(
186                self._svd2pac_as_ptr().add(2052usize),
187            )
188        }
189    }
190}
191#[doc(hidden)]
192#[derive(Copy, Clone, Eq, PartialEq)]
193pub struct Sfmsmd_SPEC;
194impl crate::sealed::RegSpec for Sfmsmd_SPEC {
195    type DataType = u32;
196}
197
198#[doc = "Transfer Mode Control Register"]
199pub type Sfmsmd = crate::RegValueT<Sfmsmd_SPEC>;
200
201impl Sfmsmd {
202    #[doc = "Read instruction code selection."]
203    #[inline(always)]
204    pub fn sfmcce(
205        self,
206    ) -> crate::common::RegisterField<
207        15,
208        0x1,
209        1,
210        0,
211        sfmsmd::Sfmcce,
212        sfmsmd::Sfmcce,
213        Sfmsmd_SPEC,
214        crate::common::RW,
215    > {
216        crate::common::RegisterField::<
217            15,
218            0x1,
219            1,
220            0,
221            sfmsmd::Sfmcce,
222            sfmsmd::Sfmcce,
223            Sfmsmd_SPEC,
224            crate::common::RW,
225        >::from_register(self, 0)
226    }
227
228    #[doc = "Setup time adjustment for serial transmission"]
229    #[inline(always)]
230    pub fn sfmosw(
231        self,
232    ) -> crate::common::RegisterField<
233        11,
234        0x1,
235        1,
236        0,
237        sfmsmd::Sfmosw,
238        sfmsmd::Sfmosw,
239        Sfmsmd_SPEC,
240        crate::common::RW,
241    > {
242        crate::common::RegisterField::<
243            11,
244            0x1,
245            1,
246            0,
247            sfmsmd::Sfmosw,
248            sfmsmd::Sfmosw,
249            Sfmsmd_SPEC,
250            crate::common::RW,
251        >::from_register(self, 0)
252    }
253
254    #[doc = "Hold time adjustment for serial transmission"]
255    #[inline(always)]
256    pub fn sfmohw(
257        self,
258    ) -> crate::common::RegisterField<
259        10,
260        0x1,
261        1,
262        0,
263        sfmsmd::Sfmohw,
264        sfmsmd::Sfmohw,
265        Sfmsmd_SPEC,
266        crate::common::RW,
267    > {
268        crate::common::RegisterField::<
269            10,
270            0x1,
271            1,
272            0,
273            sfmsmd::Sfmohw,
274            sfmsmd::Sfmohw,
275            Sfmsmd_SPEC,
276            crate::common::RW,
277        >::from_register(self, 0)
278    }
279
280    #[doc = "Extension of the I/O buffer output enable signal for the serial interface"]
281    #[inline(always)]
282    pub fn sfmoex(
283        self,
284    ) -> crate::common::RegisterField<
285        9,
286        0x1,
287        1,
288        0,
289        sfmsmd::Sfmoex,
290        sfmsmd::Sfmoex,
291        Sfmsmd_SPEC,
292        crate::common::RW,
293    > {
294        crate::common::RegisterField::<
295            9,
296            0x1,
297            1,
298            0,
299            sfmsmd::Sfmoex,
300            sfmsmd::Sfmoex,
301            Sfmsmd_SPEC,
302            crate::common::RW,
303        >::from_register(self, 0)
304    }
305
306    #[doc = "SPI mode selection. An initial value is determined by input to CFGMD3."]
307    #[inline(always)]
308    pub fn sfmmd3(
309        self,
310    ) -> crate::common::RegisterField<
311        8,
312        0x1,
313        1,
314        0,
315        sfmsmd::Sfmmd3,
316        sfmsmd::Sfmmd3,
317        Sfmsmd_SPEC,
318        crate::common::RW,
319    > {
320        crate::common::RegisterField::<
321            8,
322            0x1,
323            1,
324            0,
325            sfmsmd::Sfmmd3,
326            sfmsmd::Sfmmd3,
327            Sfmsmd_SPEC,
328            crate::common::RW,
329        >::from_register(self, 0)
330    }
331
332    #[doc = "Selection of the function for stopping prefetch at locations other than on byte boundaries"]
333    #[inline(always)]
334    pub fn sfmpae(
335        self,
336    ) -> crate::common::RegisterField<
337        7,
338        0x1,
339        1,
340        0,
341        sfmsmd::Sfmpae,
342        sfmsmd::Sfmpae,
343        Sfmsmd_SPEC,
344        crate::common::RW,
345    > {
346        crate::common::RegisterField::<
347            7,
348            0x1,
349            1,
350            0,
351            sfmsmd::Sfmpae,
352            sfmsmd::Sfmpae,
353            Sfmsmd_SPEC,
354            crate::common::RW,
355        >::from_register(self, 0)
356    }
357
358    #[doc = "Selection of the prefetch function"]
359    #[inline(always)]
360    pub fn sfmpfe(
361        self,
362    ) -> crate::common::RegisterField<
363        6,
364        0x1,
365        1,
366        0,
367        sfmsmd::Sfmpfe,
368        sfmsmd::Sfmpfe,
369        Sfmsmd_SPEC,
370        crate::common::RW,
371    > {
372        crate::common::RegisterField::<
373            6,
374            0x1,
375            1,
376            0,
377            sfmsmd::Sfmpfe,
378            sfmsmd::Sfmpfe,
379            Sfmsmd_SPEC,
380            crate::common::RW,
381        >::from_register(self, 0)
382    }
383
384    #[doc = "Selection of the prefetch function"]
385    #[inline(always)]
386    pub fn sfmse(
387        self,
388    ) -> crate::common::RegisterField<
389        4,
390        0x3,
391        1,
392        0,
393        sfmsmd::Sfmse,
394        sfmsmd::Sfmse,
395        Sfmsmd_SPEC,
396        crate::common::RW,
397    > {
398        crate::common::RegisterField::<
399            4,
400            0x3,
401            1,
402            0,
403            sfmsmd::Sfmse,
404            sfmsmd::Sfmse,
405            Sfmsmd_SPEC,
406            crate::common::RW,
407        >::from_register(self, 0)
408    }
409
410    #[doc = "Serial interface read mode selection"]
411    #[inline(always)]
412    pub fn sfmrm(
413        self,
414    ) -> crate::common::RegisterField<
415        0,
416        0x7,
417        1,
418        0,
419        sfmsmd::Sfmrm,
420        sfmsmd::Sfmrm,
421        Sfmsmd_SPEC,
422        crate::common::RW,
423    > {
424        crate::common::RegisterField::<
425            0,
426            0x7,
427            1,
428            0,
429            sfmsmd::Sfmrm,
430            sfmsmd::Sfmrm,
431            Sfmsmd_SPEC,
432            crate::common::RW,
433        >::from_register(self, 0)
434    }
435}
436impl ::core::default::Default for Sfmsmd {
437    #[inline(always)]
438    fn default() -> Sfmsmd {
439        <crate::RegValueT<Sfmsmd_SPEC> as RegisterValue<_>>::new(0)
440    }
441}
442pub mod sfmsmd {
443
444    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
445    pub struct Sfmcce_SPEC;
446    pub type Sfmcce = crate::EnumBitfieldStruct<u8, Sfmcce_SPEC>;
447    impl Sfmcce {
448        #[doc = "Default instruction code set for each instruction"]
449        pub const _0: Self = Self::new(0);
450
451        #[doc = "Instruction code written in the SFMSIC register"]
452        pub const _1: Self = Self::new(1);
453    }
454    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
455    pub struct Sfmosw_SPEC;
456    pub type Sfmosw = crate::EnumBitfieldStruct<u8, Sfmosw_SPEC>;
457    impl Sfmosw {
458        #[doc = "Does not extend the low-level width of SCK at transmission time"]
459        pub const _0: Self = Self::new(0);
460
461        #[doc = "Extends the low-level width of SCK by 1*PCLKA at transmission time"]
462        pub const _1: Self = Self::new(1);
463    }
464    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
465    pub struct Sfmohw_SPEC;
466    pub type Sfmohw = crate::EnumBitfieldStruct<u8, Sfmohw_SPEC>;
467    impl Sfmohw {
468        #[doc = "Does not extend the high-level width of SCK at transmission time"]
469        pub const _0: Self = Self::new(0);
470
471        #[doc = "Extends the high-level width of SCK by 1*PCLKA at transmission time"]
472        pub const _1: Self = Self::new(1);
473    }
474    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
475    pub struct Sfmoex_SPEC;
476    pub type Sfmoex = crate::EnumBitfieldStruct<u8, Sfmoex_SPEC>;
477    impl Sfmoex {
478        #[doc = "Does not extend the output enable signal"]
479        pub const _0: Self = Self::new(0);
480
481        #[doc = "Extends the output enable signal by 1*QSPCLK"]
482        pub const _1: Self = Self::new(1);
483    }
484    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
485    pub struct Sfmmd3_SPEC;
486    pub type Sfmmd3 = crate::EnumBitfieldStruct<u8, Sfmmd3_SPEC>;
487    impl Sfmmd3 {
488        #[doc = "SPI mode 0"]
489        pub const _0: Self = Self::new(0);
490
491        #[doc = "SPI mode 3"]
492        pub const _1: Self = Self::new(1);
493    }
494    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
495    pub struct Sfmpae_SPEC;
496    pub type Sfmpae = crate::EnumBitfieldStruct<u8, Sfmpae_SPEC>;
497    impl Sfmpae {
498        #[doc = "Disables prefetch stopping at locations other than on byte boundaries"]
499        pub const _0: Self = Self::new(0);
500
501        #[doc = "Enables prefetch stopping at locations other than on byte boundaries"]
502        pub const _1: Self = Self::new(1);
503    }
504    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
505    pub struct Sfmpfe_SPEC;
506    pub type Sfmpfe = crate::EnumBitfieldStruct<u8, Sfmpfe_SPEC>;
507    impl Sfmpfe {
508        #[doc = "Disables prefetch"]
509        pub const _0: Self = Self::new(0);
510
511        #[doc = "Enables prefetch"]
512        pub const _1: Self = Self::new(1);
513    }
514    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
515    pub struct Sfmse_SPEC;
516    pub type Sfmse = crate::EnumBitfieldStruct<u8, Sfmse_SPEC>;
517    impl Sfmse {
518        #[doc = "Does not extend QSSL"]
519        pub const _00: Self = Self::new(0);
520
521        #[doc = "Extends QSSL by 33*QSPCLK"]
522        pub const _01: Self = Self::new(1);
523
524        #[doc = "Extends QSSL by 129*QSPCLK"]
525        pub const _10: Self = Self::new(2);
526
527        #[doc = "Extends QSSL infinitely"]
528        pub const _11: Self = Self::new(3);
529    }
530    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
531    pub struct Sfmrm_SPEC;
532    pub type Sfmrm = crate::EnumBitfieldStruct<u8, Sfmrm_SPEC>;
533    impl Sfmrm {
534        #[doc = "Standard Read"]
535        pub const _000: Self = Self::new(0);
536
537        #[doc = "Fast Read"]
538        pub const _001: Self = Self::new(1);
539
540        #[doc = "Fast Read Dual Output"]
541        pub const _010: Self = Self::new(2);
542
543        #[doc = "Fast Read Dual I/O"]
544        pub const _011: Self = Self::new(3);
545
546        #[doc = "Fast Read Quad Output"]
547        pub const _100: Self = Self::new(4);
548
549        #[doc = "Fast Read Quad I/O"]
550        pub const _101: Self = Self::new(5);
551
552        #[doc = "Setting prohibited"]
553        pub const _110: Self = Self::new(6);
554
555        #[doc = "Setting prohibited"]
556        pub const _111: Self = Self::new(7);
557    }
558}
559#[doc(hidden)]
560#[derive(Copy, Clone, Eq, PartialEq)]
561pub struct Sfmssc_SPEC;
562impl crate::sealed::RegSpec for Sfmssc_SPEC {
563    type DataType = u32;
564}
565
566#[doc = "Chip Selection Control Register"]
567pub type Sfmssc = crate::RegValueT<Sfmssc_SPEC>;
568
569impl Sfmssc {
570    #[doc = "QSSL signal output timing selection"]
571    #[inline(always)]
572    pub fn sfmsld(
573        self,
574    ) -> crate::common::RegisterField<
575        5,
576        0x1,
577        1,
578        0,
579        sfmssc::Sfmsld,
580        sfmssc::Sfmsld,
581        Sfmssc_SPEC,
582        crate::common::RW,
583    > {
584        crate::common::RegisterField::<
585            5,
586            0x1,
587            1,
588            0,
589            sfmssc::Sfmsld,
590            sfmssc::Sfmsld,
591            Sfmssc_SPEC,
592            crate::common::RW,
593        >::from_register(self, 0)
594    }
595
596    #[doc = "QSSL signal release timing selection"]
597    #[inline(always)]
598    pub fn sfmshd(
599        self,
600    ) -> crate::common::RegisterField<
601        4,
602        0x1,
603        1,
604        0,
605        sfmssc::Sfmshd,
606        sfmssc::Sfmshd,
607        Sfmssc_SPEC,
608        crate::common::RW,
609    > {
610        crate::common::RegisterField::<
611            4,
612            0x1,
613            1,
614            0,
615            sfmssc::Sfmshd,
616            sfmssc::Sfmshd,
617            Sfmssc_SPEC,
618            crate::common::RW,
619        >::from_register(self, 0)
620    }
621
622    #[doc = "Selection of a minimum high-level width of the QSSL signal"]
623    #[inline(always)]
624    pub fn sfmsw(
625        self,
626    ) -> crate::common::RegisterField<
627        0,
628        0xf,
629        1,
630        0,
631        sfmssc::Sfmsw,
632        sfmssc::Sfmsw,
633        Sfmssc_SPEC,
634        crate::common::RW,
635    > {
636        crate::common::RegisterField::<
637            0,
638            0xf,
639            1,
640            0,
641            sfmssc::Sfmsw,
642            sfmssc::Sfmsw,
643            Sfmssc_SPEC,
644            crate::common::RW,
645        >::from_register(self, 0)
646    }
647}
648impl ::core::default::Default for Sfmssc {
649    #[inline(always)]
650    fn default() -> Sfmssc {
651        <crate::RegValueT<Sfmssc_SPEC> as RegisterValue<_>>::new(55)
652    }
653}
654pub mod sfmssc {
655
656    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
657    pub struct Sfmsld_SPEC;
658    pub type Sfmsld = crate::EnumBitfieldStruct<u8, Sfmsld_SPEC>;
659    impl Sfmsld {
660        #[doc = "Outputs QSSL 0.5*SCK before the first rising edge of QSPCLK"]
661        pub const _0: Self = Self::new(0);
662
663        #[doc = "Outputs QSSL 1.5*SCK before the first rising edge of QSPCLK"]
664        pub const _1: Self = Self::new(1);
665    }
666    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
667    pub struct Sfmshd_SPEC;
668    pub type Sfmshd = crate::EnumBitfieldStruct<u8, Sfmshd_SPEC>;
669    impl Sfmshd {
670        #[doc = "Releases QSSL 0.5*SCK after the last rising edge of QSPCLK"]
671        pub const _0: Self = Self::new(0);
672
673        #[doc = "Releases QSSL 1.5*SCK after the last rising edge of QSPCLK"]
674        pub const _1: Self = Self::new(1);
675    }
676    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
677    pub struct Sfmsw_SPEC;
678    pub type Sfmsw = crate::EnumBitfieldStruct<u8, Sfmsw_SPEC>;
679    impl Sfmsw {
680        #[doc = "1 x QSPCLK"]
681        pub const _0000: Self = Self::new(0);
682
683        #[doc = "2 x QSPCLK"]
684        pub const _0001: Self = Self::new(1);
685
686        #[doc = "3 x QSPCLK"]
687        pub const _0010: Self = Self::new(2);
688
689        #[doc = "4 x QSPCLK"]
690        pub const _0011: Self = Self::new(3);
691
692        #[doc = "5 x QSPCLK"]
693        pub const _0100: Self = Self::new(4);
694
695        #[doc = "6 x QSPCLK"]
696        pub const _0101: Self = Self::new(5);
697
698        #[doc = "7 x QSPCLK"]
699        pub const _0110: Self = Self::new(6);
700
701        #[doc = "8 x QSPCLK"]
702        pub const _0111: Self = Self::new(7);
703
704        #[doc = "9 x QSPCLK"]
705        pub const _1000: Self = Self::new(8);
706
707        #[doc = "10 x QSPCLK"]
708        pub const _1001: Self = Self::new(9);
709
710        #[doc = "11 x QSPCLK"]
711        pub const _1010: Self = Self::new(10);
712
713        #[doc = "12 x QSPCLK"]
714        pub const _1011: Self = Self::new(11);
715
716        #[doc = "13 x QSPCLK"]
717        pub const _1100: Self = Self::new(12);
718
719        #[doc = "14 x QSPCLK"]
720        pub const _1101: Self = Self::new(13);
721
722        #[doc = "15 x QSPCLK"]
723        pub const _1110: Self = Self::new(14);
724
725        #[doc = "16 x QSPCLK"]
726        pub const _1111: Self = Self::new(15);
727    }
728}
729#[doc(hidden)]
730#[derive(Copy, Clone, Eq, PartialEq)]
731pub struct Sfmskc_SPEC;
732impl crate::sealed::RegSpec for Sfmskc_SPEC {
733    type DataType = u32;
734}
735
736#[doc = "Clock Control Register"]
737pub type Sfmskc = crate::RegValueT<Sfmskc_SPEC>;
738
739impl Sfmskc {
740    #[doc = "Selection of a duty ratio correction function for the SCK signal"]
741    #[inline(always)]
742    pub fn sfmdty(
743        self,
744    ) -> crate::common::RegisterField<
745        5,
746        0x1,
747        1,
748        0,
749        sfmskc::Sfmdty,
750        sfmskc::Sfmdty,
751        Sfmskc_SPEC,
752        crate::common::RW,
753    > {
754        crate::common::RegisterField::<
755            5,
756            0x1,
757            1,
758            0,
759            sfmskc::Sfmdty,
760            sfmskc::Sfmdty,
761            Sfmskc_SPEC,
762            crate::common::RW,
763        >::from_register(self, 0)
764    }
765
766    #[doc = "Serial interface reference cycle selection (* Pay attention to the irregularity.)NOTE: When PCLKA multiplied by an odd number is selected, the high-level width of the SCK signal is longer than the low-level width by 1 x PCLKA before duty ratio correction."]
767    #[inline(always)]
768    pub fn sfmdv(
769        self,
770    ) -> crate::common::RegisterField<
771        0,
772        0x1f,
773        1,
774        0,
775        sfmskc::Sfmdv,
776        sfmskc::Sfmdv,
777        Sfmskc_SPEC,
778        crate::common::RW,
779    > {
780        crate::common::RegisterField::<
781            0,
782            0x1f,
783            1,
784            0,
785            sfmskc::Sfmdv,
786            sfmskc::Sfmdv,
787            Sfmskc_SPEC,
788            crate::common::RW,
789        >::from_register(self, 0)
790    }
791}
792impl ::core::default::Default for Sfmskc {
793    #[inline(always)]
794    fn default() -> Sfmskc {
795        <crate::RegValueT<Sfmskc_SPEC> as RegisterValue<_>>::new(8)
796    }
797}
798pub mod sfmskc {
799
800    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
801    pub struct Sfmdty_SPEC;
802    pub type Sfmdty = crate::EnumBitfieldStruct<u8, Sfmdty_SPEC>;
803    impl Sfmdty {
804        #[doc = "Serial interface reference cycle selection (* Pay attention to the irregularity.)"]
805        pub const _0: Self = Self::new(0);
806
807        #[doc = "Delays the rising of the SCK signal by 0.5*PCLKA.(* Valid with PCLKA multiplied by an odd number)"]
808        pub const _1: Self = Self::new(1);
809    }
810    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
811    pub struct Sfmdv_SPEC;
812    pub type Sfmdv = crate::EnumBitfieldStruct<u8, Sfmdv_SPEC>;
813    impl Sfmdv {
814        #[doc = "18 x PCLKA"]
815        pub const _10000: Self = Self::new(16);
816
817        #[doc = "20 x PCLKA"]
818        pub const _10001: Self = Self::new(17);
819
820        #[doc = "22 x PCLKA"]
821        pub const _10010: Self = Self::new(18);
822
823        #[doc = "24 x PCLKA"]
824        pub const _10011: Self = Self::new(19);
825
826        #[doc = "26 x PCLKA"]
827        pub const _10100: Self = Self::new(20);
828
829        #[doc = "28 x PCLKA"]
830        pub const _10101: Self = Self::new(21);
831
832        #[doc = "30 x PCLKA"]
833        pub const _10110: Self = Self::new(22);
834
835        #[doc = "32 x PCLKA"]
836        pub const _10111: Self = Self::new(23);
837
838        #[doc = "34 x PCLKA"]
839        pub const _11000: Self = Self::new(24);
840
841        #[doc = "36 x PCLKA"]
842        pub const _11001: Self = Self::new(25);
843
844        #[doc = "38 x PCLKA"]
845        pub const _11010: Self = Self::new(26);
846
847        #[doc = "40 x PCLKA"]
848        pub const _11011: Self = Self::new(27);
849
850        #[doc = "42 x PCLKA"]
851        pub const _11100: Self = Self::new(28);
852
853        #[doc = "44 x PCLKA"]
854        pub const _11101: Self = Self::new(29);
855
856        #[doc = "46 x PCLKA"]
857        pub const _11110: Self = Self::new(30);
858
859        #[doc = "48 x PCLKA"]
860        pub const _11111: Self = Self::new(31);
861    }
862}
863#[doc(hidden)]
864#[derive(Copy, Clone, Eq, PartialEq)]
865pub struct Sfmsst_SPEC;
866impl crate::sealed::RegSpec for Sfmsst_SPEC {
867    type DataType = u32;
868}
869
870#[doc = "Status Register"]
871pub type Sfmsst = crate::RegValueT<Sfmsst_SPEC>;
872
873impl Sfmsst {
874    #[doc = "Prefetch function operation state"]
875    #[inline(always)]
876    pub fn pfoff(
877        self,
878    ) -> crate::common::RegisterField<
879        7,
880        0x1,
881        1,
882        0,
883        sfmsst::Pfoff,
884        sfmsst::Pfoff,
885        Sfmsst_SPEC,
886        crate::common::R,
887    > {
888        crate::common::RegisterField::<
889            7,
890            0x1,
891            1,
892            0,
893            sfmsst::Pfoff,
894            sfmsst::Pfoff,
895            Sfmsst_SPEC,
896            crate::common::R,
897        >::from_register(self, 0)
898    }
899
900    #[doc = "Prefetch buffer state"]
901    #[inline(always)]
902    pub fn pfful(
903        self,
904    ) -> crate::common::RegisterField<
905        6,
906        0x1,
907        1,
908        0,
909        sfmsst::Pfful,
910        sfmsst::Pfful,
911        Sfmsst_SPEC,
912        crate::common::R,
913    > {
914        crate::common::RegisterField::<
915            6,
916            0x1,
917            1,
918            0,
919            sfmsst::Pfful,
920            sfmsst::Pfful,
921            Sfmsst_SPEC,
922            crate::common::R,
923        >::from_register(self, 0)
924    }
925
926    #[doc = "Number of bytes of prefetched dataRange: 00000 - 10010  (No combination other than the above is available.)"]
927    #[inline(always)]
928    pub fn pfcnt(
929        self,
930    ) -> crate::common::RegisterField<
931        0,
932        0x1f,
933        1,
934        0,
935        sfmsst::Pfcnt,
936        sfmsst::Pfcnt,
937        Sfmsst_SPEC,
938        crate::common::R,
939    > {
940        crate::common::RegisterField::<
941            0,
942            0x1f,
943            1,
944            0,
945            sfmsst::Pfcnt,
946            sfmsst::Pfcnt,
947            Sfmsst_SPEC,
948            crate::common::R,
949        >::from_register(self, 0)
950    }
951}
952impl ::core::default::Default for Sfmsst {
953    #[inline(always)]
954    fn default() -> Sfmsst {
955        <crate::RegValueT<Sfmsst_SPEC> as RegisterValue<_>>::new(128)
956    }
957}
958pub mod sfmsst {
959
960    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
961    pub struct Pfoff_SPEC;
962    pub type Pfoff = crate::EnumBitfieldStruct<u8, Pfoff_SPEC>;
963    impl Pfoff {
964        #[doc = "The prefetch function is operating."]
965        pub const _0: Self = Self::new(0);
966
967        #[doc = "The prefetch function is not enabled or is not operating."]
968        pub const _1: Self = Self::new(1);
969    }
970    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
971    pub struct Pfful_SPEC;
972    pub type Pfful = crate::EnumBitfieldStruct<u8, Pfful_SPEC>;
973    impl Pfful {
974        #[doc = "The prefetch buffer has a free space."]
975        pub const _0: Self = Self::new(0);
976
977        #[doc = "The prefetch buffer is full."]
978        pub const _1: Self = Self::new(1);
979    }
980    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
981    pub struct Pfcnt_SPEC;
982    pub type Pfcnt = crate::EnumBitfieldStruct<u8, Pfcnt_SPEC>;
983    impl Pfcnt {
984        #[doc = "Nodata has been prefetched."]
985        pub const _00000: Self = Self::new(0);
986    }
987}
988#[doc(hidden)]
989#[derive(Copy, Clone, Eq, PartialEq)]
990pub struct Sfmcom_SPEC;
991impl crate::sealed::RegSpec for Sfmcom_SPEC {
992    type DataType = u32;
993}
994
995#[doc = "Communication Port Register"]
996pub type Sfmcom = crate::RegValueT<Sfmcom_SPEC>;
997
998impl Sfmcom {
999    #[doc = "Port for direct communication with the SPI bus.Input/output to and from this port is converted to an SPI bus cycle. This port is accessible in the direct communication mode (DCOM=1) only.Access to this port is ignored in the ROM access mode."]
1000    #[inline(always)]
1001    pub fn sfmd(
1002        self,
1003    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Sfmcom_SPEC, crate::common::RW> {
1004        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Sfmcom_SPEC,crate::common::RW>::from_register(self,0)
1005    }
1006}
1007impl ::core::default::Default for Sfmcom {
1008    #[inline(always)]
1009    fn default() -> Sfmcom {
1010        <crate::RegValueT<Sfmcom_SPEC> as RegisterValue<_>>::new(0)
1011    }
1012}
1013
1014#[doc(hidden)]
1015#[derive(Copy, Clone, Eq, PartialEq)]
1016pub struct Sfmcmd_SPEC;
1017impl crate::sealed::RegSpec for Sfmcmd_SPEC {
1018    type DataType = u32;
1019}
1020
1021#[doc = "Communication Mode Control Register"]
1022pub type Sfmcmd = crate::RegValueT<Sfmcmd_SPEC>;
1023
1024impl Sfmcmd {
1025    #[doc = "Selection of a mode of communication with the SPI bus"]
1026    #[inline(always)]
1027    pub fn dcom(
1028        self,
1029    ) -> crate::common::RegisterField<
1030        0,
1031        0x1,
1032        1,
1033        0,
1034        sfmcmd::Dcom,
1035        sfmcmd::Dcom,
1036        Sfmcmd_SPEC,
1037        crate::common::RW,
1038    > {
1039        crate::common::RegisterField::<
1040            0,
1041            0x1,
1042            1,
1043            0,
1044            sfmcmd::Dcom,
1045            sfmcmd::Dcom,
1046            Sfmcmd_SPEC,
1047            crate::common::RW,
1048        >::from_register(self, 0)
1049    }
1050}
1051impl ::core::default::Default for Sfmcmd {
1052    #[inline(always)]
1053    fn default() -> Sfmcmd {
1054        <crate::RegValueT<Sfmcmd_SPEC> as RegisterValue<_>>::new(0)
1055    }
1056}
1057pub mod sfmcmd {
1058
1059    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1060    pub struct Dcom_SPEC;
1061    pub type Dcom = crate::EnumBitfieldStruct<u8, Dcom_SPEC>;
1062    impl Dcom {
1063        #[doc = "ROM access mode"]
1064        pub const _0: Self = Self::new(0);
1065
1066        #[doc = "Direct communication mode"]
1067        pub const _1: Self = Self::new(1);
1068    }
1069}
1070#[doc(hidden)]
1071#[derive(Copy, Clone, Eq, PartialEq)]
1072pub struct Sfmcst_SPEC;
1073impl crate::sealed::RegSpec for Sfmcst_SPEC {
1074    type DataType = u32;
1075}
1076
1077#[doc = "Communication Status Register"]
1078pub type Sfmcst = crate::RegValueT<Sfmcst_SPEC>;
1079
1080impl Sfmcst {
1081    #[doc = "Status of ROM access detection in the direct communication modeNOTE: Writing of 0 only is possible. Writing of 1 is ignored."]
1082    #[inline(always)]
1083    pub fn eromr(
1084        self,
1085    ) -> crate::common::RegisterField<
1086        7,
1087        0x1,
1088        1,
1089        0,
1090        sfmcst::Eromr,
1091        sfmcst::Eromr,
1092        Sfmcst_SPEC,
1093        crate::common::R,
1094    > {
1095        crate::common::RegisterField::<
1096            7,
1097            0x1,
1098            1,
1099            0,
1100            sfmcst::Eromr,
1101            sfmcst::Eromr,
1102            Sfmcst_SPEC,
1103            crate::common::R,
1104        >::from_register(self, 0)
1105    }
1106
1107    #[doc = "SPI bus cycle completion state in direct communication"]
1108    #[inline(always)]
1109    pub fn combsy(
1110        self,
1111    ) -> crate::common::RegisterField<
1112        0,
1113        0x1,
1114        1,
1115        0,
1116        sfmcst::Combsy,
1117        sfmcst::Combsy,
1118        Sfmcst_SPEC,
1119        crate::common::R,
1120    > {
1121        crate::common::RegisterField::<
1122            0,
1123            0x1,
1124            1,
1125            0,
1126            sfmcst::Combsy,
1127            sfmcst::Combsy,
1128            Sfmcst_SPEC,
1129            crate::common::R,
1130        >::from_register(self, 0)
1131    }
1132}
1133impl ::core::default::Default for Sfmcst {
1134    #[inline(always)]
1135    fn default() -> Sfmcst {
1136        <crate::RegValueT<Sfmcst_SPEC> as RegisterValue<_>>::new(0)
1137    }
1138}
1139pub mod sfmcst {
1140
1141    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1142    pub struct Eromr_SPEC;
1143    pub type Eromr = crate::EnumBitfieldStruct<u8, Eromr_SPEC>;
1144    impl Eromr {
1145        #[doc = "ROM access is not detected in direct communication mode"]
1146        pub const _0: Self = Self::new(0);
1147
1148        #[doc = "ROM access is detected in direct communication mode"]
1149        pub const _1: Self = Self::new(1);
1150    }
1151    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1152    pub struct Combsy_SPEC;
1153    pub type Combsy = crate::EnumBitfieldStruct<u8, Combsy_SPEC>;
1154    impl Combsy {
1155        #[doc = "There is no serial transfer being processed."]
1156        pub const _0: Self = Self::new(0);
1157
1158        #[doc = "There is a serial transfer being processed."]
1159        pub const _1: Self = Self::new(1);
1160    }
1161}
1162#[doc(hidden)]
1163#[derive(Copy, Clone, Eq, PartialEq)]
1164pub struct Sfmsic_SPEC;
1165impl crate::sealed::RegSpec for Sfmsic_SPEC {
1166    type DataType = u32;
1167}
1168
1169#[doc = "Instruction Code Register"]
1170pub type Sfmsic = crate::RegValueT<Sfmsic_SPEC>;
1171
1172impl Sfmsic {
1173    #[doc = "Serial ROM instruction code to substitute"]
1174    #[inline(always)]
1175    pub fn sfmcic(
1176        self,
1177    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Sfmsic_SPEC, crate::common::RW> {
1178        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Sfmsic_SPEC,crate::common::RW>::from_register(self,0)
1179    }
1180}
1181impl ::core::default::Default for Sfmsic {
1182    #[inline(always)]
1183    fn default() -> Sfmsic {
1184        <crate::RegValueT<Sfmsic_SPEC> as RegisterValue<_>>::new(0)
1185    }
1186}
1187
1188#[doc(hidden)]
1189#[derive(Copy, Clone, Eq, PartialEq)]
1190pub struct Sfmsac_SPEC;
1191impl crate::sealed::RegSpec for Sfmsac_SPEC {
1192    type DataType = u32;
1193}
1194
1195#[doc = "Address Mode Control Register"]
1196pub type Sfmsac = crate::RegValueT<Sfmsac_SPEC>;
1197
1198impl Sfmsac {
1199    #[doc = "Selection of a default instruction code, when Serial Interface address width is selected 4 bytes."]
1200    #[inline(always)]
1201    pub fn sfm4bc(
1202        self,
1203    ) -> crate::common::RegisterField<
1204        4,
1205        0x1,
1206        1,
1207        0,
1208        sfmsac::Sfm4Bc,
1209        sfmsac::Sfm4Bc,
1210        Sfmsac_SPEC,
1211        crate::common::RW,
1212    > {
1213        crate::common::RegisterField::<
1214            4,
1215            0x1,
1216            1,
1217            0,
1218            sfmsac::Sfm4Bc,
1219            sfmsac::Sfm4Bc,
1220            Sfmsac_SPEC,
1221            crate::common::RW,
1222        >::from_register(self, 0)
1223    }
1224
1225    #[doc = "Selection the number of address bits of the serial interface"]
1226    #[inline(always)]
1227    pub fn sfmas(
1228        self,
1229    ) -> crate::common::RegisterField<
1230        0,
1231        0x3,
1232        1,
1233        0,
1234        sfmsac::Sfmas,
1235        sfmsac::Sfmas,
1236        Sfmsac_SPEC,
1237        crate::common::RW,
1238    > {
1239        crate::common::RegisterField::<
1240            0,
1241            0x3,
1242            1,
1243            0,
1244            sfmsac::Sfmas,
1245            sfmsac::Sfmas,
1246            Sfmsac_SPEC,
1247            crate::common::RW,
1248        >::from_register(self, 0)
1249    }
1250}
1251impl ::core::default::Default for Sfmsac {
1252    #[inline(always)]
1253    fn default() -> Sfmsac {
1254        <crate::RegValueT<Sfmsac_SPEC> as RegisterValue<_>>::new(2)
1255    }
1256}
1257pub mod sfmsac {
1258
1259    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1260    pub struct Sfm4Bc_SPEC;
1261    pub type Sfm4Bc = crate::EnumBitfieldStruct<u8, Sfm4Bc_SPEC>;
1262    impl Sfm4Bc {
1263        #[doc = "Does not use 4 Byte address read Instruction code"]
1264        pub const _0: Self = Self::new(0);
1265
1266        #[doc = "Use 4 Byte address read Instruction code"]
1267        pub const _1: Self = Self::new(1);
1268    }
1269    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1270    pub struct Sfmas_SPEC;
1271    pub type Sfmas = crate::EnumBitfieldStruct<u8, Sfmas_SPEC>;
1272    impl Sfmas {
1273        #[doc = "1byte"]
1274        pub const _00: Self = Self::new(0);
1275
1276        #[doc = "2bytes"]
1277        pub const _01: Self = Self::new(1);
1278
1279        #[doc = "3bytes"]
1280        pub const _10: Self = Self::new(2);
1281
1282        #[doc = "4 bytes"]
1283        pub const _11: Self = Self::new(3);
1284    }
1285}
1286#[doc(hidden)]
1287#[derive(Copy, Clone, Eq, PartialEq)]
1288pub struct Sfmsdc_SPEC;
1289impl crate::sealed::RegSpec for Sfmsdc_SPEC {
1290    type DataType = u32;
1291}
1292
1293#[doc = "Dummy Cycle Control Register"]
1294pub type Sfmsdc = crate::RegValueT<Sfmsdc_SPEC>;
1295
1296impl Sfmsdc {
1297    #[doc = "Mode data for serial ROM. (Control XIP mode)"]
1298    #[inline(always)]
1299    pub fn sfmxd(
1300        self,
1301    ) -> crate::common::RegisterField<
1302        8,
1303        0xff,
1304        1,
1305        0,
1306        sfmsdc::Sfmxd,
1307        sfmsdc::Sfmxd,
1308        Sfmsdc_SPEC,
1309        crate::common::RW,
1310    > {
1311        crate::common::RegisterField::<
1312            8,
1313            0xff,
1314            1,
1315            0,
1316            sfmsdc::Sfmxd,
1317            sfmsdc::Sfmxd,
1318            Sfmsdc_SPEC,
1319            crate::common::RW,
1320        >::from_register(self, 0)
1321    }
1322
1323    #[doc = "XIP mode permission"]
1324    #[inline(always)]
1325    pub fn sfmxen(
1326        self,
1327    ) -> crate::common::RegisterField<
1328        7,
1329        0x1,
1330        1,
1331        0,
1332        sfmsdc::Sfmxen,
1333        sfmsdc::Sfmxen,
1334        Sfmsdc_SPEC,
1335        crate::common::RW,
1336    > {
1337        crate::common::RegisterField::<
1338            7,
1339            0x1,
1340            1,
1341            0,
1342            sfmsdc::Sfmxen,
1343            sfmsdc::Sfmxen,
1344            Sfmsdc_SPEC,
1345            crate::common::RW,
1346        >::from_register(self, 0)
1347    }
1348
1349    #[doc = "XIP mode status"]
1350    #[inline(always)]
1351    pub fn sfmxst(
1352        self,
1353    ) -> crate::common::RegisterField<
1354        6,
1355        0x1,
1356        1,
1357        0,
1358        sfmsdc::Sfmxst,
1359        sfmsdc::Sfmxst,
1360        Sfmsdc_SPEC,
1361        crate::common::R,
1362    > {
1363        crate::common::RegisterField::<
1364            6,
1365            0x1,
1366            1,
1367            0,
1368            sfmsdc::Sfmxst,
1369            sfmsdc::Sfmxst,
1370            Sfmsdc_SPEC,
1371            crate::common::R,
1372        >::from_register(self, 0)
1373    }
1374
1375    #[doc = "Selection of the number of dummy cycles of Fast Read instructions"]
1376    #[inline(always)]
1377    pub fn sfmdn(
1378        self,
1379    ) -> crate::common::RegisterField<
1380        0,
1381        0xf,
1382        1,
1383        0,
1384        sfmsdc::Sfmdn,
1385        sfmsdc::Sfmdn,
1386        Sfmsdc_SPEC,
1387        crate::common::RW,
1388    > {
1389        crate::common::RegisterField::<
1390            0,
1391            0xf,
1392            1,
1393            0,
1394            sfmsdc::Sfmdn,
1395            sfmsdc::Sfmdn,
1396            Sfmsdc_SPEC,
1397            crate::common::RW,
1398        >::from_register(self, 0)
1399    }
1400}
1401impl ::core::default::Default for Sfmsdc {
1402    #[inline(always)]
1403    fn default() -> Sfmsdc {
1404        <crate::RegValueT<Sfmsdc_SPEC> as RegisterValue<_>>::new(65280)
1405    }
1406}
1407pub mod sfmsdc {
1408
1409    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1410    pub struct Sfmxd_SPEC;
1411    pub type Sfmxd = crate::EnumBitfieldStruct<u8, Sfmxd_SPEC>;
1412    impl Sfmxd {
1413        #[doc = "XIP mode is prohibited"]
1414        pub const _0: Self = Self::new(0);
1415
1416        #[doc = "XIP mode is permitted"]
1417        pub const _1: Self = Self::new(1);
1418    }
1419    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1420    pub struct Sfmxen_SPEC;
1421    pub type Sfmxen = crate::EnumBitfieldStruct<u8, Sfmxen_SPEC>;
1422    impl Sfmxen {
1423        #[doc = "XIP mode is prohibited"]
1424        pub const _0: Self = Self::new(0);
1425
1426        #[doc = "XIP mode is permitted"]
1427        pub const _1: Self = Self::new(1);
1428    }
1429    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1430    pub struct Sfmxst_SPEC;
1431    pub type Sfmxst = crate::EnumBitfieldStruct<u8, Sfmxst_SPEC>;
1432    impl Sfmxst {
1433        #[doc = "Normal (non-XIP) mode is operating"]
1434        pub const _0: Self = Self::new(0);
1435
1436        #[doc = "XIP mode is operating"]
1437        pub const _1: Self = Self::new(1);
1438    }
1439    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1440    pub struct Sfmdn_SPEC;
1441    pub type Sfmdn = crate::EnumBitfieldStruct<u8, Sfmdn_SPEC>;
1442    impl Sfmdn {
1443        #[doc = "Default dummy cycles of each instruction."]
1444        pub const _0000: Self = Self::new(0);
1445    }
1446}
1447#[doc(hidden)]
1448#[derive(Copy, Clone, Eq, PartialEq)]
1449pub struct Sfmspc_SPEC;
1450impl crate::sealed::RegSpec for Sfmspc_SPEC {
1451    type DataType = u32;
1452}
1453
1454#[doc = "SPI Protocol Control Register"]
1455pub type Sfmspc = crate::RegValueT<Sfmspc_SPEC>;
1456
1457impl Sfmspc {
1458    #[doc = "Selection of the minimum time of input output switch, when Dual SPI protocol or Quad SPI protocol is selected."]
1459    #[inline(always)]
1460    pub fn sfmsde(
1461        self,
1462    ) -> crate::common::RegisterField<
1463        4,
1464        0x1,
1465        1,
1466        0,
1467        sfmspc::Sfmsde,
1468        sfmspc::Sfmsde,
1469        Sfmspc_SPEC,
1470        crate::common::RW,
1471    > {
1472        crate::common::RegisterField::<
1473            4,
1474            0x1,
1475            1,
1476            0,
1477            sfmspc::Sfmsde,
1478            sfmspc::Sfmsde,
1479            Sfmspc_SPEC,
1480            crate::common::RW,
1481        >::from_register(self, 0)
1482    }
1483
1484    #[doc = "Selection of SPI protocolNOTE: Serial ROM\'s SPI protocol is required to be set by software separately."]
1485    #[inline(always)]
1486    pub fn sfmspi(
1487        self,
1488    ) -> crate::common::RegisterField<
1489        0,
1490        0x3,
1491        1,
1492        0,
1493        sfmspc::Sfmspi,
1494        sfmspc::Sfmspi,
1495        Sfmspc_SPEC,
1496        crate::common::RW,
1497    > {
1498        crate::common::RegisterField::<
1499            0,
1500            0x3,
1501            1,
1502            0,
1503            sfmspc::Sfmspi,
1504            sfmspc::Sfmspi,
1505            Sfmspc_SPEC,
1506            crate::common::RW,
1507        >::from_register(self, 0)
1508    }
1509}
1510impl ::core::default::Default for Sfmspc {
1511    #[inline(always)]
1512    fn default() -> Sfmspc {
1513        <crate::RegValueT<Sfmspc_SPEC> as RegisterValue<_>>::new(16)
1514    }
1515}
1516pub mod sfmspc {
1517
1518    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1519    pub struct Sfmsde_SPEC;
1520    pub type Sfmsde = crate::EnumBitfieldStruct<u8, Sfmsde_SPEC>;
1521    impl Sfmsde {
1522        #[doc = "Does not allocate minimum switch time"]
1523        pub const _0: Self = Self::new(0);
1524
1525        #[doc = "Allocate the minimum switch time equivalent to 1*QSPXLK"]
1526        pub const _1: Self = Self::new(1);
1527    }
1528    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1529    pub struct Sfmspi_SPEC;
1530    pub type Sfmspi = crate::EnumBitfieldStruct<u8, Sfmspi_SPEC>;
1531    impl Sfmspi {
1532        #[doc = "Extended SPI protocol"]
1533        pub const _00: Self = Self::new(0);
1534
1535        #[doc = "Dual SPI protocol"]
1536        pub const _01: Self = Self::new(1);
1537
1538        #[doc = "Quad SPI protocol"]
1539        pub const _10: Self = Self::new(2);
1540
1541        #[doc = "Setting prohibited."]
1542        pub const _11: Self = Self::new(3);
1543    }
1544}
1545#[doc(hidden)]
1546#[derive(Copy, Clone, Eq, PartialEq)]
1547pub struct Sfmpmd_SPEC;
1548impl crate::sealed::RegSpec for Sfmpmd_SPEC {
1549    type DataType = u32;
1550}
1551
1552#[doc = "Port Control Register"]
1553pub type Sfmpmd = crate::RegValueT<Sfmpmd_SPEC>;
1554
1555impl Sfmpmd {
1556    #[doc = "Specify level of WP pin"]
1557    #[inline(always)]
1558    pub fn sfmwpl(
1559        self,
1560    ) -> crate::common::RegisterField<
1561        2,
1562        0x1,
1563        1,
1564        0,
1565        sfmpmd::Sfmwpl,
1566        sfmpmd::Sfmwpl,
1567        Sfmpmd_SPEC,
1568        crate::common::RW,
1569    > {
1570        crate::common::RegisterField::<
1571            2,
1572            0x1,
1573            1,
1574            0,
1575            sfmpmd::Sfmwpl,
1576            sfmpmd::Sfmwpl,
1577            Sfmpmd_SPEC,
1578            crate::common::RW,
1579        >::from_register(self, 0)
1580    }
1581}
1582impl ::core::default::Default for Sfmpmd {
1583    #[inline(always)]
1584    fn default() -> Sfmpmd {
1585        <crate::RegValueT<Sfmpmd_SPEC> as RegisterValue<_>>::new(0)
1586    }
1587}
1588pub mod sfmpmd {
1589
1590    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1591    pub struct Sfmwpl_SPEC;
1592    pub type Sfmwpl = crate::EnumBitfieldStruct<u8, Sfmwpl_SPEC>;
1593    impl Sfmwpl {
1594        #[doc = "Low level"]
1595        pub const _0: Self = Self::new(0);
1596
1597        #[doc = "High level"]
1598        pub const _1: Self = Self::new(1);
1599    }
1600}
1601#[doc(hidden)]
1602#[derive(Copy, Clone, Eq, PartialEq)]
1603pub struct Sfmcnt1_SPEC;
1604impl crate::sealed::RegSpec for Sfmcnt1_SPEC {
1605    type DataType = u32;
1606}
1607
1608#[doc = "External QSPI Address Register 1"]
1609pub type Sfmcnt1 = crate::RegValueT<Sfmcnt1_SPEC>;
1610
1611impl Sfmcnt1 {
1612    #[doc = "BANK Switching AddressWhen accessing from 0x6000_0000 to 0x63FF_FFFF, Addres bus is Set QSPI_EXT\\[5:0\\] to high-order 6bits of SHADDR\\[31:0\\]NOTE: Setting 6\'h3F is prihibited."]
1613    #[inline(always)]
1614    pub fn qspi_ext(
1615        self,
1616    ) -> crate::common::RegisterField<26, 0x3f, 1, 0, u8, u8, Sfmcnt1_SPEC, crate::common::RW> {
1617        crate::common::RegisterField::<26,0x3f,1,0,u8,u8,Sfmcnt1_SPEC,crate::common::RW>::from_register(self,0)
1618    }
1619}
1620impl ::core::default::Default for Sfmcnt1 {
1621    #[inline(always)]
1622    fn default() -> Sfmcnt1 {
1623        <crate::RegValueT<Sfmcnt1_SPEC> as RegisterValue<_>>::new(0)
1624    }
1625}
ra6m2_pac/qspi.rs

ra6m2_pac/
qspi.rs
