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ra6m2_pac/
usbfs.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:11:44 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"USB 2.0 FS Module"]
28unsafe impl ::core::marker::Send for super::Usbfs {}
29unsafe impl ::core::marker::Sync for super::Usbfs {}
30impl super::Usbfs {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "System Configuration Control Register"]
38    #[inline(always)]
39    pub const fn syscfg(
40        &self,
41    ) -> &'static crate::common::Reg<self::Syscfg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::Syscfg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(0usize),
45            )
46        }
47    }
48
49    #[doc = "System Configuration Status Register 0"]
50    #[inline(always)]
51    pub const fn syssts0(
52        &self,
53    ) -> &'static crate::common::Reg<self::Syssts0_SPEC, crate::common::R> {
54        unsafe {
55            crate::common::Reg::<self::Syssts0_SPEC, crate::common::R>::from_ptr(
56                self._svd2pac_as_ptr().add(4usize),
57            )
58        }
59    }
60
61    #[doc = "Device State Control Register 0"]
62    #[inline(always)]
63    pub const fn dvstctr0(
64        &self,
65    ) -> &'static crate::common::Reg<self::Dvstctr0_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::Dvstctr0_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(8usize),
69            )
70        }
71    }
72
73    #[doc = "CFIFO Port Register"]
74    #[inline(always)]
75    pub const fn cfifo(&self) -> &'static crate::common::Reg<self::Cfifo_SPEC, crate::common::RW> {
76        unsafe {
77            crate::common::Reg::<self::Cfifo_SPEC, crate::common::RW>::from_ptr(
78                self._svd2pac_as_ptr().add(20usize),
79            )
80        }
81    }
82
83    #[doc = "CFIFO Port Register L"]
84    #[inline(always)]
85    pub const fn cfifol(
86        &self,
87    ) -> &'static crate::common::Reg<self::Cfifol_SPEC, crate::common::RW> {
88        unsafe {
89            crate::common::Reg::<self::Cfifol_SPEC, crate::common::RW>::from_ptr(
90                self._svd2pac_as_ptr().add(20usize),
91            )
92        }
93    }
94
95    #[doc = "D0FIFO Port Register"]
96    #[inline(always)]
97    pub const fn d0fifo(
98        &self,
99    ) -> &'static crate::common::Reg<self::D0Fifo_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::D0Fifo_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(24usize),
103            )
104        }
105    }
106
107    #[doc = "D0FIFO Port Register L"]
108    #[inline(always)]
109    pub const fn d0fifol(
110        &self,
111    ) -> &'static crate::common::Reg<self::D0Fifol_SPEC, crate::common::RW> {
112        unsafe {
113            crate::common::Reg::<self::D0Fifol_SPEC, crate::common::RW>::from_ptr(
114                self._svd2pac_as_ptr().add(24usize),
115            )
116        }
117    }
118
119    #[doc = "D1FIFO Port Register"]
120    #[inline(always)]
121    pub const fn d1fifo(
122        &self,
123    ) -> &'static crate::common::Reg<self::D1Fifo_SPEC, crate::common::RW> {
124        unsafe {
125            crate::common::Reg::<self::D1Fifo_SPEC, crate::common::RW>::from_ptr(
126                self._svd2pac_as_ptr().add(28usize),
127            )
128        }
129    }
130
131    #[doc = "D1FIFO Port Register L"]
132    #[inline(always)]
133    pub const fn d1fifol(
134        &self,
135    ) -> &'static crate::common::Reg<self::D1Fifol_SPEC, crate::common::RW> {
136        unsafe {
137            crate::common::Reg::<self::D1Fifol_SPEC, crate::common::RW>::from_ptr(
138                self._svd2pac_as_ptr().add(28usize),
139            )
140        }
141    }
142
143    #[doc = "CFIFO Port Select Register"]
144    #[inline(always)]
145    pub const fn cfifosel(
146        &self,
147    ) -> &'static crate::common::Reg<self::Cfifosel_SPEC, crate::common::RW> {
148        unsafe {
149            crate::common::Reg::<self::Cfifosel_SPEC, crate::common::RW>::from_ptr(
150                self._svd2pac_as_ptr().add(32usize),
151            )
152        }
153    }
154
155    #[doc = "CFIFO Port Control Register"]
156    #[inline(always)]
157    pub const fn cfifoctr(
158        &self,
159    ) -> &'static crate::common::Reg<self::Cfifoctr_SPEC, crate::common::RW> {
160        unsafe {
161            crate::common::Reg::<self::Cfifoctr_SPEC, crate::common::RW>::from_ptr(
162                self._svd2pac_as_ptr().add(34usize),
163            )
164        }
165    }
166
167    #[doc = "D0FIFO Port Select Register"]
168    #[inline(always)]
169    pub const fn d0fifosel(
170        &self,
171    ) -> &'static crate::common::Reg<self::D0Fifosel_SPEC, crate::common::RW> {
172        unsafe {
173            crate::common::Reg::<self::D0Fifosel_SPEC, crate::common::RW>::from_ptr(
174                self._svd2pac_as_ptr().add(40usize),
175            )
176        }
177    }
178
179    #[doc = "D0FIFO Port Control Register"]
180    #[inline(always)]
181    pub const fn d0fifoctr(
182        &self,
183    ) -> &'static crate::common::Reg<self::D0Fifoctr_SPEC, crate::common::RW> {
184        unsafe {
185            crate::common::Reg::<self::D0Fifoctr_SPEC, crate::common::RW>::from_ptr(
186                self._svd2pac_as_ptr().add(42usize),
187            )
188        }
189    }
190
191    #[doc = "D1FIFO Port Select Register"]
192    #[inline(always)]
193    pub const fn d1fifosel(
194        &self,
195    ) -> &'static crate::common::Reg<self::D1Fifosel_SPEC, crate::common::RW> {
196        unsafe {
197            crate::common::Reg::<self::D1Fifosel_SPEC, crate::common::RW>::from_ptr(
198                self._svd2pac_as_ptr().add(44usize),
199            )
200        }
201    }
202
203    #[doc = "D1FIFO Port Control Register"]
204    #[inline(always)]
205    pub const fn d1fifoctr(
206        &self,
207    ) -> &'static crate::common::Reg<self::D1Fifoctr_SPEC, crate::common::RW> {
208        unsafe {
209            crate::common::Reg::<self::D1Fifoctr_SPEC, crate::common::RW>::from_ptr(
210                self._svd2pac_as_ptr().add(46usize),
211            )
212        }
213    }
214
215    #[doc = "Interrupt Enable Register 0"]
216    #[inline(always)]
217    pub const fn intenb0(
218        &self,
219    ) -> &'static crate::common::Reg<self::Intenb0_SPEC, crate::common::RW> {
220        unsafe {
221            crate::common::Reg::<self::Intenb0_SPEC, crate::common::RW>::from_ptr(
222                self._svd2pac_as_ptr().add(48usize),
223            )
224        }
225    }
226
227    #[doc = "Interrupt Enable Register 1"]
228    #[inline(always)]
229    pub const fn intenb1(
230        &self,
231    ) -> &'static crate::common::Reg<self::Intenb1_SPEC, crate::common::RW> {
232        unsafe {
233            crate::common::Reg::<self::Intenb1_SPEC, crate::common::RW>::from_ptr(
234                self._svd2pac_as_ptr().add(50usize),
235            )
236        }
237    }
238
239    #[doc = "BRDY Interrupt Enable Register"]
240    #[inline(always)]
241    pub const fn brdyenb(
242        &self,
243    ) -> &'static crate::common::Reg<self::Brdyenb_SPEC, crate::common::RW> {
244        unsafe {
245            crate::common::Reg::<self::Brdyenb_SPEC, crate::common::RW>::from_ptr(
246                self._svd2pac_as_ptr().add(54usize),
247            )
248        }
249    }
250
251    #[doc = "NRDY Interrupt Enable Register"]
252    #[inline(always)]
253    pub const fn nrdyenb(
254        &self,
255    ) -> &'static crate::common::Reg<self::Nrdyenb_SPEC, crate::common::RW> {
256        unsafe {
257            crate::common::Reg::<self::Nrdyenb_SPEC, crate::common::RW>::from_ptr(
258                self._svd2pac_as_ptr().add(56usize),
259            )
260        }
261    }
262
263    #[doc = "BEMP Interrupt Enable Register"]
264    #[inline(always)]
265    pub const fn bempenb(
266        &self,
267    ) -> &'static crate::common::Reg<self::Bempenb_SPEC, crate::common::RW> {
268        unsafe {
269            crate::common::Reg::<self::Bempenb_SPEC, crate::common::RW>::from_ptr(
270                self._svd2pac_as_ptr().add(58usize),
271            )
272        }
273    }
274
275    #[doc = "SOF Output Configuration Register"]
276    #[inline(always)]
277    pub const fn sofcfg(
278        &self,
279    ) -> &'static crate::common::Reg<self::Sofcfg_SPEC, crate::common::RW> {
280        unsafe {
281            crate::common::Reg::<self::Sofcfg_SPEC, crate::common::RW>::from_ptr(
282                self._svd2pac_as_ptr().add(60usize),
283            )
284        }
285    }
286
287    #[doc = "Interrupt Status Register 0"]
288    #[inline(always)]
289    pub const fn intsts0(
290        &self,
291    ) -> &'static crate::common::Reg<self::Intsts0_SPEC, crate::common::RW> {
292        unsafe {
293            crate::common::Reg::<self::Intsts0_SPEC, crate::common::RW>::from_ptr(
294                self._svd2pac_as_ptr().add(64usize),
295            )
296        }
297    }
298
299    #[doc = "Interrupt Status Register 1"]
300    #[inline(always)]
301    pub const fn intsts1(
302        &self,
303    ) -> &'static crate::common::Reg<self::Intsts1_SPEC, crate::common::RW> {
304        unsafe {
305            crate::common::Reg::<self::Intsts1_SPEC, crate::common::RW>::from_ptr(
306                self._svd2pac_as_ptr().add(66usize),
307            )
308        }
309    }
310
311    #[doc = "BRDY Interrupt Status Register"]
312    #[inline(always)]
313    pub const fn brdysts(
314        &self,
315    ) -> &'static crate::common::Reg<self::Brdysts_SPEC, crate::common::RW> {
316        unsafe {
317            crate::common::Reg::<self::Brdysts_SPEC, crate::common::RW>::from_ptr(
318                self._svd2pac_as_ptr().add(70usize),
319            )
320        }
321    }
322
323    #[doc = "NRDY Interrupt Status Register"]
324    #[inline(always)]
325    pub const fn nrdysts(
326        &self,
327    ) -> &'static crate::common::Reg<self::Nrdysts_SPEC, crate::common::RW> {
328        unsafe {
329            crate::common::Reg::<self::Nrdysts_SPEC, crate::common::RW>::from_ptr(
330                self._svd2pac_as_ptr().add(72usize),
331            )
332        }
333    }
334
335    #[doc = "BEMP Interrupt Status Register"]
336    #[inline(always)]
337    pub const fn bempsts(
338        &self,
339    ) -> &'static crate::common::Reg<self::Bempsts_SPEC, crate::common::RW> {
340        unsafe {
341            crate::common::Reg::<self::Bempsts_SPEC, crate::common::RW>::from_ptr(
342                self._svd2pac_as_ptr().add(74usize),
343            )
344        }
345    }
346
347    #[doc = "Frame Number Register"]
348    #[inline(always)]
349    pub const fn frmnum(
350        &self,
351    ) -> &'static crate::common::Reg<self::Frmnum_SPEC, crate::common::RW> {
352        unsafe {
353            crate::common::Reg::<self::Frmnum_SPEC, crate::common::RW>::from_ptr(
354                self._svd2pac_as_ptr().add(76usize),
355            )
356        }
357    }
358
359    #[doc = "Device State Change Register"]
360    #[inline(always)]
361    pub const fn dvchgr(
362        &self,
363    ) -> &'static crate::common::Reg<self::Dvchgr_SPEC, crate::common::RW> {
364        unsafe {
365            crate::common::Reg::<self::Dvchgr_SPEC, crate::common::RW>::from_ptr(
366                self._svd2pac_as_ptr().add(78usize),
367            )
368        }
369    }
370
371    #[doc = "USB Address Register"]
372    #[inline(always)]
373    pub const fn usbaddr(
374        &self,
375    ) -> &'static crate::common::Reg<self::Usbaddr_SPEC, crate::common::RW> {
376        unsafe {
377            crate::common::Reg::<self::Usbaddr_SPEC, crate::common::RW>::from_ptr(
378                self._svd2pac_as_ptr().add(80usize),
379            )
380        }
381    }
382
383    #[doc = "USB Request Type Register"]
384    #[inline(always)]
385    pub const fn usbreq(
386        &self,
387    ) -> &'static crate::common::Reg<self::Usbreq_SPEC, crate::common::RW> {
388        unsafe {
389            crate::common::Reg::<self::Usbreq_SPEC, crate::common::RW>::from_ptr(
390                self._svd2pac_as_ptr().add(84usize),
391            )
392        }
393    }
394
395    #[doc = "USB Request Value Register"]
396    #[inline(always)]
397    pub const fn usbval(
398        &self,
399    ) -> &'static crate::common::Reg<self::Usbval_SPEC, crate::common::RW> {
400        unsafe {
401            crate::common::Reg::<self::Usbval_SPEC, crate::common::RW>::from_ptr(
402                self._svd2pac_as_ptr().add(86usize),
403            )
404        }
405    }
406
407    #[doc = "USB Request Index Register"]
408    #[inline(always)]
409    pub const fn usbindx(
410        &self,
411    ) -> &'static crate::common::Reg<self::Usbindx_SPEC, crate::common::RW> {
412        unsafe {
413            crate::common::Reg::<self::Usbindx_SPEC, crate::common::RW>::from_ptr(
414                self._svd2pac_as_ptr().add(88usize),
415            )
416        }
417    }
418
419    #[doc = "USB Request Length Register"]
420    #[inline(always)]
421    pub const fn usbleng(
422        &self,
423    ) -> &'static crate::common::Reg<self::Usbleng_SPEC, crate::common::RW> {
424        unsafe {
425            crate::common::Reg::<self::Usbleng_SPEC, crate::common::RW>::from_ptr(
426                self._svd2pac_as_ptr().add(90usize),
427            )
428        }
429    }
430
431    #[doc = "DCP Configuration Register"]
432    #[inline(always)]
433    pub const fn dcpcfg(
434        &self,
435    ) -> &'static crate::common::Reg<self::Dcpcfg_SPEC, crate::common::RW> {
436        unsafe {
437            crate::common::Reg::<self::Dcpcfg_SPEC, crate::common::RW>::from_ptr(
438                self._svd2pac_as_ptr().add(92usize),
439            )
440        }
441    }
442
443    #[doc = "DCP Maximum Packet Size Register"]
444    #[inline(always)]
445    pub const fn dcpmaxp(
446        &self,
447    ) -> &'static crate::common::Reg<self::Dcpmaxp_SPEC, crate::common::RW> {
448        unsafe {
449            crate::common::Reg::<self::Dcpmaxp_SPEC, crate::common::RW>::from_ptr(
450                self._svd2pac_as_ptr().add(94usize),
451            )
452        }
453    }
454
455    #[doc = "DCP Control Register"]
456    #[inline(always)]
457    pub const fn dcpctr(
458        &self,
459    ) -> &'static crate::common::Reg<self::Dcpctr_SPEC, crate::common::RW> {
460        unsafe {
461            crate::common::Reg::<self::Dcpctr_SPEC, crate::common::RW>::from_ptr(
462                self._svd2pac_as_ptr().add(96usize),
463            )
464        }
465    }
466
467    #[doc = "Pipe Window Select Register"]
468    #[inline(always)]
469    pub const fn pipesel(
470        &self,
471    ) -> &'static crate::common::Reg<self::Pipesel_SPEC, crate::common::RW> {
472        unsafe {
473            crate::common::Reg::<self::Pipesel_SPEC, crate::common::RW>::from_ptr(
474                self._svd2pac_as_ptr().add(100usize),
475            )
476        }
477    }
478
479    #[doc = "Pipe Configuration Register"]
480    #[inline(always)]
481    pub const fn pipecfg(
482        &self,
483    ) -> &'static crate::common::Reg<self::Pipecfg_SPEC, crate::common::RW> {
484        unsafe {
485            crate::common::Reg::<self::Pipecfg_SPEC, crate::common::RW>::from_ptr(
486                self._svd2pac_as_ptr().add(104usize),
487            )
488        }
489    }
490
491    #[doc = "Pipe Maximum Packet Size Register"]
492    #[inline(always)]
493    pub const fn pipemaxp(
494        &self,
495    ) -> &'static crate::common::Reg<self::Pipemaxp_SPEC, crate::common::RW> {
496        unsafe {
497            crate::common::Reg::<self::Pipemaxp_SPEC, crate::common::RW>::from_ptr(
498                self._svd2pac_as_ptr().add(108usize),
499            )
500        }
501    }
502
503    #[doc = "Pipe Cycle Control Register"]
504    #[inline(always)]
505    pub const fn pipeperi(
506        &self,
507    ) -> &'static crate::common::Reg<self::Pipeperi_SPEC, crate::common::RW> {
508        unsafe {
509            crate::common::Reg::<self::Pipeperi_SPEC, crate::common::RW>::from_ptr(
510                self._svd2pac_as_ptr().add(110usize),
511            )
512        }
513    }
514
515    #[doc = "Pipe %s Control Register"]
516    #[inline(always)]
517    pub const fn pipectr(
518        &self,
519    ) -> &'static crate::common::ClusterRegisterArray<
520        crate::common::Reg<self::Pipectr_SPEC, crate::common::RW>,
521        4,
522        0x2,
523    > {
524        unsafe {
525            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x7ausize))
526        }
527    }
528    #[inline(always)]
529    pub const fn pipe6ctr(
530        &self,
531    ) -> &'static crate::common::Reg<self::Pipectr_SPEC, crate::common::RW> {
532        unsafe {
533            crate::common::Reg::<self::Pipectr_SPEC, crate::common::RW>::from_ptr(
534                self._svd2pac_as_ptr().add(0x7ausize),
535            )
536        }
537    }
538    #[inline(always)]
539    pub const fn pipe7ctr(
540        &self,
541    ) -> &'static crate::common::Reg<self::Pipectr_SPEC, crate::common::RW> {
542        unsafe {
543            crate::common::Reg::<self::Pipectr_SPEC, crate::common::RW>::from_ptr(
544                self._svd2pac_as_ptr().add(0x7cusize),
545            )
546        }
547    }
548    #[inline(always)]
549    pub const fn pipe8ctr(
550        &self,
551    ) -> &'static crate::common::Reg<self::Pipectr_SPEC, crate::common::RW> {
552        unsafe {
553            crate::common::Reg::<self::Pipectr_SPEC, crate::common::RW>::from_ptr(
554                self._svd2pac_as_ptr().add(0x7eusize),
555            )
556        }
557    }
558    #[inline(always)]
559    pub const fn pipe9ctr(
560        &self,
561    ) -> &'static crate::common::Reg<self::Pipectr_SPEC, crate::common::RW> {
562        unsafe {
563            crate::common::Reg::<self::Pipectr_SPEC, crate::common::RW>::from_ptr(
564                self._svd2pac_as_ptr().add(0x80usize),
565            )
566        }
567    }
568
569    #[doc = "Pipe %s Transaction Counter Enable Register"]
570    #[inline(always)]
571    pub const fn pipetre(
572        &self,
573    ) -> &'static crate::common::ClusterRegisterArray<
574        crate::common::Reg<self::Pipetre_SPEC, crate::common::RW>,
575        5,
576        0x4,
577    > {
578        unsafe {
579            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x90usize))
580        }
581    }
582    #[inline(always)]
583    pub const fn pipe1tre(
584        &self,
585    ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
586        unsafe {
587            crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
588                self._svd2pac_as_ptr().add(0x90usize),
589            )
590        }
591    }
592    #[inline(always)]
593    pub const fn pipe2tre(
594        &self,
595    ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
596        unsafe {
597            crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
598                self._svd2pac_as_ptr().add(0x94usize),
599            )
600        }
601    }
602    #[inline(always)]
603    pub const fn pipe3tre(
604        &self,
605    ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
606        unsafe {
607            crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
608                self._svd2pac_as_ptr().add(0x98usize),
609            )
610        }
611    }
612    #[inline(always)]
613    pub const fn pipe4tre(
614        &self,
615    ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
616        unsafe {
617            crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
618                self._svd2pac_as_ptr().add(0x9cusize),
619            )
620        }
621    }
622    #[inline(always)]
623    pub const fn pipe5tre(
624        &self,
625    ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
626        unsafe {
627            crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
628                self._svd2pac_as_ptr().add(0xa0usize),
629            )
630        }
631    }
632
633    #[doc = "Pipe %s Transaction Counter Register"]
634    #[inline(always)]
635    pub const fn pipetrn(
636        &self,
637    ) -> &'static crate::common::ClusterRegisterArray<
638        crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW>,
639        5,
640        0x4,
641    > {
642        unsafe {
643            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x92usize))
644        }
645    }
646    #[inline(always)]
647    pub const fn pipe1trn(
648        &self,
649    ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
650        unsafe {
651            crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
652                self._svd2pac_as_ptr().add(0x92usize),
653            )
654        }
655    }
656    #[inline(always)]
657    pub const fn pipe2trn(
658        &self,
659    ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
660        unsafe {
661            crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
662                self._svd2pac_as_ptr().add(0x96usize),
663            )
664        }
665    }
666    #[inline(always)]
667    pub const fn pipe3trn(
668        &self,
669    ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
670        unsafe {
671            crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
672                self._svd2pac_as_ptr().add(0x9ausize),
673            )
674        }
675    }
676    #[inline(always)]
677    pub const fn pipe4trn(
678        &self,
679    ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
680        unsafe {
681            crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
682                self._svd2pac_as_ptr().add(0x9eusize),
683            )
684        }
685    }
686    #[inline(always)]
687    pub const fn pipe5trn(
688        &self,
689    ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
690        unsafe {
691            crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
692                self._svd2pac_as_ptr().add(0xa2usize),
693            )
694        }
695    }
696
697    #[doc = "Device Address %s Configuration Register"]
698    #[inline(always)]
699    pub const fn devadd(
700        &self,
701    ) -> &'static crate::common::ClusterRegisterArray<
702        crate::common::Reg<self::Devadd_SPEC, crate::common::RW>,
703        6,
704        0x2,
705    > {
706        unsafe {
707            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xd0usize))
708        }
709    }
710    #[inline(always)]
711    pub const fn devadd0(
712        &self,
713    ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
714        unsafe {
715            crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
716                self._svd2pac_as_ptr().add(0xd0usize),
717            )
718        }
719    }
720    #[inline(always)]
721    pub const fn devadd1(
722        &self,
723    ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
724        unsafe {
725            crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
726                self._svd2pac_as_ptr().add(0xd2usize),
727            )
728        }
729    }
730    #[inline(always)]
731    pub const fn devadd2(
732        &self,
733    ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
734        unsafe {
735            crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
736                self._svd2pac_as_ptr().add(0xd4usize),
737            )
738        }
739    }
740    #[inline(always)]
741    pub const fn devadd3(
742        &self,
743    ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
744        unsafe {
745            crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
746                self._svd2pac_as_ptr().add(0xd6usize),
747            )
748        }
749    }
750    #[inline(always)]
751    pub const fn devadd4(
752        &self,
753    ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
754        unsafe {
755            crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
756                self._svd2pac_as_ptr().add(0xd8usize),
757            )
758        }
759    }
760    #[inline(always)]
761    pub const fn devadd5(
762        &self,
763    ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
764        unsafe {
765            crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
766                self._svd2pac_as_ptr().add(0xdausize),
767            )
768        }
769    }
770
771    #[doc = "PHY Cross Point Adjustment Register"]
772    #[inline(always)]
773    pub const fn physlew(
774        &self,
775    ) -> &'static crate::common::Reg<self::Physlew_SPEC, crate::common::RW> {
776        unsafe {
777            crate::common::Reg::<self::Physlew_SPEC, crate::common::RW>::from_ptr(
778                self._svd2pac_as_ptr().add(240usize),
779            )
780        }
781    }
782
783    #[doc = "Deep Software Standby USB Transceiver Control/Pin Monitor Register"]
784    #[inline(always)]
785    pub const fn dpusr0r(
786        &self,
787    ) -> &'static crate::common::Reg<self::Dpusr0R_SPEC, crate::common::RW> {
788        unsafe {
789            crate::common::Reg::<self::Dpusr0R_SPEC, crate::common::RW>::from_ptr(
790                self._svd2pac_as_ptr().add(1024usize),
791            )
792        }
793    }
794
795    #[doc = "Deep Software Standby USB Suspend/Resume Interrupt Register"]
796    #[inline(always)]
797    pub const fn dpusr1r(
798        &self,
799    ) -> &'static crate::common::Reg<self::Dpusr1R_SPEC, crate::common::RW> {
800        unsafe {
801            crate::common::Reg::<self::Dpusr1R_SPEC, crate::common::RW>::from_ptr(
802                self._svd2pac_as_ptr().add(1028usize),
803            )
804        }
805    }
806}
807#[doc(hidden)]
808#[derive(Copy, Clone, Eq, PartialEq)]
809pub struct Syscfg_SPEC;
810impl crate::sealed::RegSpec for Syscfg_SPEC {
811    type DataType = u16;
812}
813
814#[doc = "System Configuration Control Register"]
815pub type Syscfg = crate::RegValueT<Syscfg_SPEC>;
816
817impl Syscfg {
818    #[doc = "USB Clock Enable"]
819    #[inline(always)]
820    pub fn scke(
821        self,
822    ) -> crate::common::RegisterField<
823        10,
824        0x1,
825        1,
826        0,
827        syscfg::Scke,
828        syscfg::Scke,
829        Syscfg_SPEC,
830        crate::common::RW,
831    > {
832        crate::common::RegisterField::<
833            10,
834            0x1,
835            1,
836            0,
837            syscfg::Scke,
838            syscfg::Scke,
839            Syscfg_SPEC,
840            crate::common::RW,
841        >::from_register(self, 0)
842    }
843
844    #[doc = "Controller Function Select"]
845    #[inline(always)]
846    pub fn dcfm(
847        self,
848    ) -> crate::common::RegisterField<
849        6,
850        0x1,
851        1,
852        0,
853        syscfg::Dcfm,
854        syscfg::Dcfm,
855        Syscfg_SPEC,
856        crate::common::RW,
857    > {
858        crate::common::RegisterField::<
859            6,
860            0x1,
861            1,
862            0,
863            syscfg::Dcfm,
864            syscfg::Dcfm,
865            Syscfg_SPEC,
866            crate::common::RW,
867        >::from_register(self, 0)
868    }
869
870    #[doc = "D+/D- Line Resistor Control"]
871    #[inline(always)]
872    pub fn drpd(
873        self,
874    ) -> crate::common::RegisterField<
875        5,
876        0x1,
877        1,
878        0,
879        syscfg::Drpd,
880        syscfg::Drpd,
881        Syscfg_SPEC,
882        crate::common::RW,
883    > {
884        crate::common::RegisterField::<
885            5,
886            0x1,
887            1,
888            0,
889            syscfg::Drpd,
890            syscfg::Drpd,
891            Syscfg_SPEC,
892            crate::common::RW,
893        >::from_register(self, 0)
894    }
895
896    #[doc = "D+ Line Resistor Control"]
897    #[inline(always)]
898    pub fn dprpu(
899        self,
900    ) -> crate::common::RegisterField<
901        4,
902        0x1,
903        1,
904        0,
905        syscfg::Dprpu,
906        syscfg::Dprpu,
907        Syscfg_SPEC,
908        crate::common::RW,
909    > {
910        crate::common::RegisterField::<
911            4,
912            0x1,
913            1,
914            0,
915            syscfg::Dprpu,
916            syscfg::Dprpu,
917            Syscfg_SPEC,
918            crate::common::RW,
919        >::from_register(self, 0)
920    }
921
922    #[doc = "USB Operation Enable"]
923    #[inline(always)]
924    pub fn usbe(
925        self,
926    ) -> crate::common::RegisterField<
927        0,
928        0x1,
929        1,
930        0,
931        syscfg::Usbe,
932        syscfg::Usbe,
933        Syscfg_SPEC,
934        crate::common::RW,
935    > {
936        crate::common::RegisterField::<
937            0,
938            0x1,
939            1,
940            0,
941            syscfg::Usbe,
942            syscfg::Usbe,
943            Syscfg_SPEC,
944            crate::common::RW,
945        >::from_register(self, 0)
946    }
947}
948impl ::core::default::Default for Syscfg {
949    #[inline(always)]
950    fn default() -> Syscfg {
951        <crate::RegValueT<Syscfg_SPEC> as RegisterValue<_>>::new(0)
952    }
953}
954pub mod syscfg {
955
956    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
957    pub struct Scke_SPEC;
958    pub type Scke = crate::EnumBitfieldStruct<u8, Scke_SPEC>;
959    impl Scke {
960        #[doc = "Stops supplying the clock signal to the USB."]
961        pub const _0: Self = Self::new(0);
962
963        #[doc = "Enables supplying the clock signal to the USB."]
964        pub const _1: Self = Self::new(1);
965    }
966    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
967    pub struct Dcfm_SPEC;
968    pub type Dcfm = crate::EnumBitfieldStruct<u8, Dcfm_SPEC>;
969    impl Dcfm {
970        #[doc = "Function controller is selected."]
971        pub const _0: Self = Self::new(0);
972
973        #[doc = "Host controller is selected."]
974        pub const _1: Self = Self::new(1);
975    }
976    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
977    pub struct Drpd_SPEC;
978    pub type Drpd = crate::EnumBitfieldStruct<u8, Drpd_SPEC>;
979    impl Drpd {
980        #[doc = "Pulling down the lines is disabled."]
981        pub const _0: Self = Self::new(0);
982
983        #[doc = "Pulling down the lines is enabled."]
984        pub const _1: Self = Self::new(1);
985    }
986    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
987    pub struct Dprpu_SPEC;
988    pub type Dprpu = crate::EnumBitfieldStruct<u8, Dprpu_SPEC>;
989    impl Dprpu {
990        #[doc = "Pulling up the line is disabled."]
991        pub const _0: Self = Self::new(0);
992
993        #[doc = "Pulling up the line is enabled."]
994        pub const _1: Self = Self::new(1);
995    }
996    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
997    pub struct Usbe_SPEC;
998    pub type Usbe = crate::EnumBitfieldStruct<u8, Usbe_SPEC>;
999    impl Usbe {
1000        #[doc = "USB operation is disabled."]
1001        pub const _0: Self = Self::new(0);
1002
1003        #[doc = "USB operation is enabled."]
1004        pub const _1: Self = Self::new(1);
1005    }
1006}
1007#[doc(hidden)]
1008#[derive(Copy, Clone, Eq, PartialEq)]
1009pub struct Syssts0_SPEC;
1010impl crate::sealed::RegSpec for Syssts0_SPEC {
1011    type DataType = u16;
1012}
1013
1014#[doc = "System Configuration Status Register 0"]
1015pub type Syssts0 = crate::RegValueT<Syssts0_SPEC>;
1016
1017impl Syssts0 {
1018    #[doc = "External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON\\[1\\] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON\\[0\\] bit indicates the status of the USBHS_OVRCURB pin."]
1019    #[inline(always)]
1020    pub fn ovcmon(
1021        self,
1022    ) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, Syssts0_SPEC, crate::common::R> {
1023        crate::common::RegisterField::<14,0x3,1,0,u8,u8,Syssts0_SPEC,crate::common::R>::from_register(self,0)
1024    }
1025
1026    #[doc = "USB Host Sequencer Status Monitor"]
1027    #[inline(always)]
1028    pub fn htact(
1029        self,
1030    ) -> crate::common::RegisterField<
1031        6,
1032        0x1,
1033        1,
1034        0,
1035        syssts0::Htact,
1036        syssts0::Htact,
1037        Syssts0_SPEC,
1038        crate::common::R,
1039    > {
1040        crate::common::RegisterField::<
1041            6,
1042            0x1,
1043            1,
1044            0,
1045            syssts0::Htact,
1046            syssts0::Htact,
1047            Syssts0_SPEC,
1048            crate::common::R,
1049        >::from_register(self, 0)
1050    }
1051
1052    #[doc = "Active Monitor When the Host Controller is Selected."]
1053    #[inline(always)]
1054    pub fn sofea(
1055        self,
1056    ) -> crate::common::RegisterField<
1057        5,
1058        0x1,
1059        1,
1060        0,
1061        syssts0::Sofea,
1062        syssts0::Sofea,
1063        Syssts0_SPEC,
1064        crate::common::R,
1065    > {
1066        crate::common::RegisterField::<
1067            5,
1068            0x1,
1069            1,
1070            0,
1071            syssts0::Sofea,
1072            syssts0::Sofea,
1073            Syssts0_SPEC,
1074            crate::common::R,
1075        >::from_register(self, 0)
1076    }
1077
1078    #[doc = "External ID0 Input Pin Monitor"]
1079    #[inline(always)]
1080    pub fn idmon(
1081        self,
1082    ) -> crate::common::RegisterField<
1083        2,
1084        0x1,
1085        1,
1086        0,
1087        syssts0::Idmon,
1088        syssts0::Idmon,
1089        Syssts0_SPEC,
1090        crate::common::R,
1091    > {
1092        crate::common::RegisterField::<
1093            2,
1094            0x1,
1095            1,
1096            0,
1097            syssts0::Idmon,
1098            syssts0::Idmon,
1099            Syssts0_SPEC,
1100            crate::common::R,
1101        >::from_register(self, 0)
1102    }
1103
1104    #[doc = "USB Data Line Status Monitor"]
1105    #[inline(always)]
1106    pub fn lnst(
1107        self,
1108    ) -> crate::common::RegisterField<
1109        0,
1110        0x3,
1111        1,
1112        0,
1113        syssts0::Lnst,
1114        syssts0::Lnst,
1115        Syssts0_SPEC,
1116        crate::common::R,
1117    > {
1118        crate::common::RegisterField::<
1119            0,
1120            0x3,
1121            1,
1122            0,
1123            syssts0::Lnst,
1124            syssts0::Lnst,
1125            Syssts0_SPEC,
1126            crate::common::R,
1127        >::from_register(self, 0)
1128    }
1129}
1130impl ::core::default::Default for Syssts0 {
1131    #[inline(always)]
1132    fn default() -> Syssts0 {
1133        <crate::RegValueT<Syssts0_SPEC> as RegisterValue<_>>::new(0)
1134    }
1135}
1136pub mod syssts0 {
1137
1138    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1139    pub struct Htact_SPEC;
1140    pub type Htact = crate::EnumBitfieldStruct<u8, Htact_SPEC>;
1141    impl Htact {
1142        #[doc = "Host sequencer of the USB is completely stopped."]
1143        pub const _0: Self = Self::new(0);
1144
1145        #[doc = "Host sequencer of the USB is not completely stopped."]
1146        pub const _1: Self = Self::new(1);
1147    }
1148    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1149    pub struct Sofea_SPEC;
1150    pub type Sofea = crate::EnumBitfieldStruct<u8, Sofea_SPEC>;
1151    impl Sofea {
1152        #[doc = "SOF output is stopped."]
1153        pub const _0: Self = Self::new(0);
1154
1155        #[doc = "SOF output is operating."]
1156        pub const _1: Self = Self::new(1);
1157    }
1158    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1159    pub struct Idmon_SPEC;
1160    pub type Idmon = crate::EnumBitfieldStruct<u8, Idmon_SPEC>;
1161    impl Idmon {
1162        #[doc = "USB0_ID pin is low"]
1163        pub const _0: Self = Self::new(0);
1164
1165        #[doc = "USB0_ID pin is high"]
1166        pub const _1: Self = Self::new(1);
1167    }
1168    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1169    pub struct Lnst_SPEC;
1170    pub type Lnst = crate::EnumBitfieldStruct<u8, Lnst_SPEC>;
1171    impl Lnst {
1172        #[doc = "SE0"]
1173        pub const _00: Self = Self::new(0);
1174
1175        #[doc = "J-State"]
1176        pub const _01: Self = Self::new(1);
1177
1178        #[doc = "K-State"]
1179        pub const _10: Self = Self::new(2);
1180
1181        #[doc = "SE1"]
1182        pub const _11: Self = Self::new(3);
1183    }
1184}
1185#[doc(hidden)]
1186#[derive(Copy, Clone, Eq, PartialEq)]
1187pub struct Dvstctr0_SPEC;
1188impl crate::sealed::RegSpec for Dvstctr0_SPEC {
1189    type DataType = u16;
1190}
1191
1192#[doc = "Device State Control Register 0"]
1193pub type Dvstctr0 = crate::RegValueT<Dvstctr0_SPEC>;
1194
1195impl Dvstctr0 {
1196    #[doc = "Host Negotiation Protocol (HNP) Control     This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even  though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set."]
1197    #[inline(always)]
1198    pub fn hnpbtoa(
1199        self,
1200    ) -> crate::common::RegisterField<
1201        11,
1202        0x1,
1203        1,
1204        0,
1205        dvstctr0::Hnpbtoa,
1206        dvstctr0::Hnpbtoa,
1207        Dvstctr0_SPEC,
1208        crate::common::RW,
1209    > {
1210        crate::common::RegisterField::<
1211            11,
1212            0x1,
1213            1,
1214            0,
1215            dvstctr0::Hnpbtoa,
1216            dvstctr0::Hnpbtoa,
1217            Dvstctr0_SPEC,
1218            crate::common::RW,
1219        >::from_register(self, 0)
1220    }
1221
1222    #[doc = "USB0_EXICEN Output Pin Control"]
1223    #[inline(always)]
1224    pub fn exicen(
1225        self,
1226    ) -> crate::common::RegisterField<
1227        10,
1228        0x1,
1229        1,
1230        0,
1231        dvstctr0::Exicen,
1232        dvstctr0::Exicen,
1233        Dvstctr0_SPEC,
1234        crate::common::RW,
1235    > {
1236        crate::common::RegisterField::<
1237            10,
1238            0x1,
1239            1,
1240            0,
1241            dvstctr0::Exicen,
1242            dvstctr0::Exicen,
1243            Dvstctr0_SPEC,
1244            crate::common::RW,
1245        >::from_register(self, 0)
1246    }
1247
1248    #[doc = "USB0_VBUSEN Output Pin Control"]
1249    #[inline(always)]
1250    pub fn vbusen(
1251        self,
1252    ) -> crate::common::RegisterField<
1253        9,
1254        0x1,
1255        1,
1256        0,
1257        dvstctr0::Vbusen,
1258        dvstctr0::Vbusen,
1259        Dvstctr0_SPEC,
1260        crate::common::RW,
1261    > {
1262        crate::common::RegisterField::<
1263            9,
1264            0x1,
1265            1,
1266            0,
1267            dvstctr0::Vbusen,
1268            dvstctr0::Vbusen,
1269            Dvstctr0_SPEC,
1270            crate::common::RW,
1271        >::from_register(self, 0)
1272    }
1273
1274    #[doc = "Wakeup Output"]
1275    #[inline(always)]
1276    pub fn wkup(
1277        self,
1278    ) -> crate::common::RegisterField<
1279        8,
1280        0x1,
1281        1,
1282        0,
1283        dvstctr0::Wkup,
1284        dvstctr0::Wkup,
1285        Dvstctr0_SPEC,
1286        crate::common::RW,
1287    > {
1288        crate::common::RegisterField::<
1289            8,
1290            0x1,
1291            1,
1292            0,
1293            dvstctr0::Wkup,
1294            dvstctr0::Wkup,
1295            Dvstctr0_SPEC,
1296            crate::common::RW,
1297        >::from_register(self, 0)
1298    }
1299
1300    #[doc = "Wakeup Detection Enable"]
1301    #[inline(always)]
1302    pub fn rwupe(
1303        self,
1304    ) -> crate::common::RegisterField<
1305        7,
1306        0x1,
1307        1,
1308        0,
1309        dvstctr0::Rwupe,
1310        dvstctr0::Rwupe,
1311        Dvstctr0_SPEC,
1312        crate::common::RW,
1313    > {
1314        crate::common::RegisterField::<
1315            7,
1316            0x1,
1317            1,
1318            0,
1319            dvstctr0::Rwupe,
1320            dvstctr0::Rwupe,
1321            Dvstctr0_SPEC,
1322            crate::common::RW,
1323        >::from_register(self, 0)
1324    }
1325
1326    #[doc = "USB Bus Reset Output"]
1327    #[inline(always)]
1328    pub fn usbrst(
1329        self,
1330    ) -> crate::common::RegisterField<
1331        6,
1332        0x1,
1333        1,
1334        0,
1335        dvstctr0::Usbrst,
1336        dvstctr0::Usbrst,
1337        Dvstctr0_SPEC,
1338        crate::common::RW,
1339    > {
1340        crate::common::RegisterField::<
1341            6,
1342            0x1,
1343            1,
1344            0,
1345            dvstctr0::Usbrst,
1346            dvstctr0::Usbrst,
1347            Dvstctr0_SPEC,
1348            crate::common::RW,
1349        >::from_register(self, 0)
1350    }
1351
1352    #[doc = "Resume Output"]
1353    #[inline(always)]
1354    pub fn resume(
1355        self,
1356    ) -> crate::common::RegisterField<
1357        5,
1358        0x1,
1359        1,
1360        0,
1361        dvstctr0::Resume,
1362        dvstctr0::Resume,
1363        Dvstctr0_SPEC,
1364        crate::common::RW,
1365    > {
1366        crate::common::RegisterField::<
1367            5,
1368            0x1,
1369            1,
1370            0,
1371            dvstctr0::Resume,
1372            dvstctr0::Resume,
1373            Dvstctr0_SPEC,
1374            crate::common::RW,
1375        >::from_register(self, 0)
1376    }
1377
1378    #[doc = "USB Bus Enable"]
1379    #[inline(always)]
1380    pub fn uact(
1381        self,
1382    ) -> crate::common::RegisterField<
1383        4,
1384        0x1,
1385        1,
1386        0,
1387        dvstctr0::Uact,
1388        dvstctr0::Uact,
1389        Dvstctr0_SPEC,
1390        crate::common::RW,
1391    > {
1392        crate::common::RegisterField::<
1393            4,
1394            0x1,
1395            1,
1396            0,
1397            dvstctr0::Uact,
1398            dvstctr0::Uact,
1399            Dvstctr0_SPEC,
1400            crate::common::RW,
1401        >::from_register(self, 0)
1402    }
1403
1404    #[doc = "USB Bus Reset Status"]
1405    #[inline(always)]
1406    pub fn rhst(
1407        self,
1408    ) -> crate::common::RegisterField<
1409        0,
1410        0x7,
1411        1,
1412        0,
1413        dvstctr0::Rhst,
1414        dvstctr0::Rhst,
1415        Dvstctr0_SPEC,
1416        crate::common::R,
1417    > {
1418        crate::common::RegisterField::<
1419            0,
1420            0x7,
1421            1,
1422            0,
1423            dvstctr0::Rhst,
1424            dvstctr0::Rhst,
1425            Dvstctr0_SPEC,
1426            crate::common::R,
1427        >::from_register(self, 0)
1428    }
1429}
1430impl ::core::default::Default for Dvstctr0 {
1431    #[inline(always)]
1432    fn default() -> Dvstctr0 {
1433        <crate::RegValueT<Dvstctr0_SPEC> as RegisterValue<_>>::new(0)
1434    }
1435}
1436pub mod dvstctr0 {
1437
1438    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1439    pub struct Hnpbtoa_SPEC;
1440    pub type Hnpbtoa = crate::EnumBitfieldStruct<u8, Hnpbtoa_SPEC>;
1441    impl Hnpbtoa {
1442        #[doc = "Normal Operation"]
1443        pub const _0: Self = Self::new(0);
1444
1445        #[doc = "Switching from device B to device A is enabled"]
1446        pub const _1: Self = Self::new(1);
1447    }
1448    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1449    pub struct Exicen_SPEC;
1450    pub type Exicen = crate::EnumBitfieldStruct<u8, Exicen_SPEC>;
1451    impl Exicen {
1452        #[doc = "External USB0_EXICEN pin outputs low"]
1453        pub const _0: Self = Self::new(0);
1454
1455        #[doc = "External USB0_EXICEN pin outputs high"]
1456        pub const _1: Self = Self::new(1);
1457    }
1458    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1459    pub struct Vbusen_SPEC;
1460    pub type Vbusen = crate::EnumBitfieldStruct<u8, Vbusen_SPEC>;
1461    impl Vbusen {
1462        #[doc = "External USB0_VBUSEN pin outputs low"]
1463        pub const _0: Self = Self::new(0);
1464
1465        #[doc = "External USB0_VBUSEN pin outputs high"]
1466        pub const _1: Self = Self::new(1);
1467    }
1468    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1469    pub struct Wkup_SPEC;
1470    pub type Wkup = crate::EnumBitfieldStruct<u8, Wkup_SPEC>;
1471    impl Wkup {
1472        #[doc = "Remote wakeup signal is not output."]
1473        pub const _0: Self = Self::new(0);
1474
1475        #[doc = "Remote wakeup signal is output."]
1476        pub const _1: Self = Self::new(1);
1477    }
1478    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1479    pub struct Rwupe_SPEC;
1480    pub type Rwupe = crate::EnumBitfieldStruct<u8, Rwupe_SPEC>;
1481    impl Rwupe {
1482        #[doc = "Downstream port wakeup is disabled."]
1483        pub const _0: Self = Self::new(0);
1484
1485        #[doc = "Downstream port wakeup is enabled."]
1486        pub const _1: Self = Self::new(1);
1487    }
1488    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1489    pub struct Usbrst_SPEC;
1490    pub type Usbrst = crate::EnumBitfieldStruct<u8, Usbrst_SPEC>;
1491    impl Usbrst {
1492        #[doc = "USB bus reset signal is not output."]
1493        pub const _0: Self = Self::new(0);
1494
1495        #[doc = "USB bus reset signal is output."]
1496        pub const _1: Self = Self::new(1);
1497    }
1498    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1499    pub struct Resume_SPEC;
1500    pub type Resume = crate::EnumBitfieldStruct<u8, Resume_SPEC>;
1501    impl Resume {
1502        #[doc = "Resume signal is not output."]
1503        pub const _0: Self = Self::new(0);
1504
1505        #[doc = "Resume signal is output."]
1506        pub const _1: Self = Self::new(1);
1507    }
1508    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1509    pub struct Uact_SPEC;
1510    pub type Uact = crate::EnumBitfieldStruct<u8, Uact_SPEC>;
1511    impl Uact {
1512        #[doc = "Downstream port is disabled (SOF transmission is disabled)."]
1513        pub const _0: Self = Self::new(0);
1514
1515        #[doc = "Downstream port is enabled (SOF transmission is enabled)."]
1516        pub const _1: Self = Self::new(1);
1517    }
1518    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1519    pub struct Rhst_SPEC;
1520    pub type Rhst = crate::EnumBitfieldStruct<u8, Rhst_SPEC>;
1521    impl Rhst {
1522        #[doc = "Communication speed not determined"]
1523        pub const _000: Self = Self::new(0);
1524
1525        #[doc = "Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected)"]
1526        pub const _001: Self = Self::new(1);
1527
1528        #[doc = "Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected)"]
1529        pub const _010: Self = Self::new(2);
1530
1531        #[doc = "Setting prohibited"]
1532        pub const _011: Self = Self::new(3);
1533    }
1534}
1535#[doc(hidden)]
1536#[derive(Copy, Clone, Eq, PartialEq)]
1537pub struct Cfifo_SPEC;
1538impl crate::sealed::RegSpec for Cfifo_SPEC {
1539    type DataType = u16;
1540}
1541
1542#[doc = "CFIFO Port Register"]
1543pub type Cfifo = crate::RegValueT<Cfifo_SPEC>;
1544
1545impl Cfifo {
1546    #[doc = "FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits."]
1547    #[inline(always)]
1548    pub fn fifoport(
1549        self,
1550    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Cfifo_SPEC, crate::common::RW>
1551    {
1552        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Cfifo_SPEC,crate::common::RW>::from_register(self,0)
1553    }
1554}
1555impl ::core::default::Default for Cfifo {
1556    #[inline(always)]
1557    fn default() -> Cfifo {
1558        <crate::RegValueT<Cfifo_SPEC> as RegisterValue<_>>::new(0)
1559    }
1560}
1561
1562#[doc(hidden)]
1563#[derive(Copy, Clone, Eq, PartialEq)]
1564pub struct Cfifol_SPEC;
1565impl crate::sealed::RegSpec for Cfifol_SPEC {
1566    type DataType = u8;
1567}
1568
1569#[doc = "CFIFO Port Register L"]
1570pub type Cfifol = crate::RegValueT<Cfifol_SPEC>;
1571
1572impl NoBitfieldReg<Cfifol_SPEC> for Cfifol {}
1573impl ::core::default::Default for Cfifol {
1574    #[inline(always)]
1575    fn default() -> Cfifol {
1576        <crate::RegValueT<Cfifol_SPEC> as RegisterValue<_>>::new(0)
1577    }
1578}
1579
1580#[doc(hidden)]
1581#[derive(Copy, Clone, Eq, PartialEq)]
1582pub struct D0Fifo_SPEC;
1583impl crate::sealed::RegSpec for D0Fifo_SPEC {
1584    type DataType = u16;
1585}
1586
1587#[doc = "D0FIFO Port Register"]
1588pub type D0Fifo = crate::RegValueT<D0Fifo_SPEC>;
1589
1590impl D0Fifo {
1591    #[doc = "FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits."]
1592    #[inline(always)]
1593    pub fn fifoport(
1594        self,
1595    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, D0Fifo_SPEC, crate::common::RW>
1596    {
1597        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,D0Fifo_SPEC,crate::common::RW>::from_register(self,0)
1598    }
1599}
1600impl ::core::default::Default for D0Fifo {
1601    #[inline(always)]
1602    fn default() -> D0Fifo {
1603        <crate::RegValueT<D0Fifo_SPEC> as RegisterValue<_>>::new(0)
1604    }
1605}
1606
1607#[doc(hidden)]
1608#[derive(Copy, Clone, Eq, PartialEq)]
1609pub struct D0Fifol_SPEC;
1610impl crate::sealed::RegSpec for D0Fifol_SPEC {
1611    type DataType = u8;
1612}
1613
1614#[doc = "D0FIFO Port Register L"]
1615pub type D0Fifol = crate::RegValueT<D0Fifol_SPEC>;
1616
1617impl NoBitfieldReg<D0Fifol_SPEC> for D0Fifol {}
1618impl ::core::default::Default for D0Fifol {
1619    #[inline(always)]
1620    fn default() -> D0Fifol {
1621        <crate::RegValueT<D0Fifol_SPEC> as RegisterValue<_>>::new(0)
1622    }
1623}
1624
1625#[doc(hidden)]
1626#[derive(Copy, Clone, Eq, PartialEq)]
1627pub struct D1Fifo_SPEC;
1628impl crate::sealed::RegSpec for D1Fifo_SPEC {
1629    type DataType = u16;
1630}
1631
1632#[doc = "D1FIFO Port Register"]
1633pub type D1Fifo = crate::RegValueT<D1Fifo_SPEC>;
1634
1635impl D1Fifo {
1636    #[doc = "FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits."]
1637    #[inline(always)]
1638    pub fn fifoport(
1639        self,
1640    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, D1Fifo_SPEC, crate::common::RW>
1641    {
1642        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,D1Fifo_SPEC,crate::common::RW>::from_register(self,0)
1643    }
1644}
1645impl ::core::default::Default for D1Fifo {
1646    #[inline(always)]
1647    fn default() -> D1Fifo {
1648        <crate::RegValueT<D1Fifo_SPEC> as RegisterValue<_>>::new(0)
1649    }
1650}
1651
1652#[doc(hidden)]
1653#[derive(Copy, Clone, Eq, PartialEq)]
1654pub struct D1Fifol_SPEC;
1655impl crate::sealed::RegSpec for D1Fifol_SPEC {
1656    type DataType = u8;
1657}
1658
1659#[doc = "D1FIFO Port Register L"]
1660pub type D1Fifol = crate::RegValueT<D1Fifol_SPEC>;
1661
1662impl NoBitfieldReg<D1Fifol_SPEC> for D1Fifol {}
1663impl ::core::default::Default for D1Fifol {
1664    #[inline(always)]
1665    fn default() -> D1Fifol {
1666        <crate::RegValueT<D1Fifol_SPEC> as RegisterValue<_>>::new(0)
1667    }
1668}
1669
1670#[doc(hidden)]
1671#[derive(Copy, Clone, Eq, PartialEq)]
1672pub struct Cfifosel_SPEC;
1673impl crate::sealed::RegSpec for Cfifosel_SPEC {
1674    type DataType = u16;
1675}
1676
1677#[doc = "CFIFO Port Select Register"]
1678pub type Cfifosel = crate::RegValueT<Cfifosel_SPEC>;
1679
1680impl Cfifosel {
1681    #[doc = "Read Count Mode"]
1682    #[inline(always)]
1683    pub fn rcnt(
1684        self,
1685    ) -> crate::common::RegisterField<
1686        15,
1687        0x1,
1688        1,
1689        0,
1690        cfifosel::Rcnt,
1691        cfifosel::Rcnt,
1692        Cfifosel_SPEC,
1693        crate::common::RW,
1694    > {
1695        crate::common::RegisterField::<
1696            15,
1697            0x1,
1698            1,
1699            0,
1700            cfifosel::Rcnt,
1701            cfifosel::Rcnt,
1702            Cfifosel_SPEC,
1703            crate::common::RW,
1704        >::from_register(self, 0)
1705    }
1706
1707    #[doc = "Buffer Pointer Rewind"]
1708    #[inline(always)]
1709    pub fn rew(
1710        self,
1711    ) -> crate::common::RegisterField<
1712        14,
1713        0x1,
1714        1,
1715        0,
1716        cfifosel::Rew,
1717        cfifosel::Rew,
1718        Cfifosel_SPEC,
1719        crate::common::R,
1720    > {
1721        crate::common::RegisterField::<
1722            14,
1723            0x1,
1724            1,
1725            0,
1726            cfifosel::Rew,
1727            cfifosel::Rew,
1728            Cfifosel_SPEC,
1729            crate::common::R,
1730        >::from_register(self, 0)
1731    }
1732
1733    #[doc = "CFIFO Port Access Bit Width"]
1734    #[inline(always)]
1735    pub fn mbw(
1736        self,
1737    ) -> crate::common::RegisterField<
1738        10,
1739        0x1,
1740        1,
1741        0,
1742        cfifosel::Mbw,
1743        cfifosel::Mbw,
1744        Cfifosel_SPEC,
1745        crate::common::RW,
1746    > {
1747        crate::common::RegisterField::<
1748            10,
1749            0x1,
1750            1,
1751            0,
1752            cfifosel::Mbw,
1753            cfifosel::Mbw,
1754            Cfifosel_SPEC,
1755            crate::common::RW,
1756        >::from_register(self, 0)
1757    }
1758
1759    #[doc = "CFIFO Port Endian Control"]
1760    #[inline(always)]
1761    pub fn bigend(
1762        self,
1763    ) -> crate::common::RegisterField<
1764        8,
1765        0x1,
1766        1,
1767        0,
1768        cfifosel::Bigend,
1769        cfifosel::Bigend,
1770        Cfifosel_SPEC,
1771        crate::common::RW,
1772    > {
1773        crate::common::RegisterField::<
1774            8,
1775            0x1,
1776            1,
1777            0,
1778            cfifosel::Bigend,
1779            cfifosel::Bigend,
1780            Cfifosel_SPEC,
1781            crate::common::RW,
1782        >::from_register(self, 0)
1783    }
1784
1785    #[doc = "CFIFO Port Access Direction When DCP is Selected"]
1786    #[inline(always)]
1787    pub fn isel(
1788        self,
1789    ) -> crate::common::RegisterField<
1790        5,
1791        0x1,
1792        1,
1793        0,
1794        cfifosel::Isel,
1795        cfifosel::Isel,
1796        Cfifosel_SPEC,
1797        crate::common::RW,
1798    > {
1799        crate::common::RegisterField::<
1800            5,
1801            0x1,
1802            1,
1803            0,
1804            cfifosel::Isel,
1805            cfifosel::Isel,
1806            Cfifosel_SPEC,
1807            crate::common::RW,
1808        >::from_register(self, 0)
1809    }
1810
1811    #[doc = "CFIFO Port Access Pipe Specification"]
1812    #[inline(always)]
1813    pub fn curpipe(
1814        self,
1815    ) -> crate::common::RegisterField<
1816        0,
1817        0xf,
1818        1,
1819        0,
1820        cfifosel::Curpipe,
1821        cfifosel::Curpipe,
1822        Cfifosel_SPEC,
1823        crate::common::RW,
1824    > {
1825        crate::common::RegisterField::<
1826            0,
1827            0xf,
1828            1,
1829            0,
1830            cfifosel::Curpipe,
1831            cfifosel::Curpipe,
1832            Cfifosel_SPEC,
1833            crate::common::RW,
1834        >::from_register(self, 0)
1835    }
1836}
1837impl ::core::default::Default for Cfifosel {
1838    #[inline(always)]
1839    fn default() -> Cfifosel {
1840        <crate::RegValueT<Cfifosel_SPEC> as RegisterValue<_>>::new(0)
1841    }
1842}
1843pub mod cfifosel {
1844
1845    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1846    pub struct Rcnt_SPEC;
1847    pub type Rcnt = crate::EnumBitfieldStruct<u8, Rcnt_SPEC>;
1848    impl Rcnt {
1849        #[doc = "The DTLN\\[8:0\\] bits (CFIFOCRT.DTLN\\[8:0\\], D0FIFOCRT.DTLN\\[8:0\\], D1FIFOCRT.DTLN\\[8:0\\]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN\\[8:0\\] bit value is cleared when all the data has been read from only a single plane.)"]
1850        pub const _0: Self = Self::new(0);
1851
1852        #[doc = "The DTLN\\[8:0\\] bits are decremented each time the receive data is read from the CFIFO."]
1853        pub const _1: Self = Self::new(1);
1854    }
1855    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1856    pub struct Rew_SPEC;
1857    pub type Rew = crate::EnumBitfieldStruct<u8, Rew_SPEC>;
1858    impl Rew {
1859        #[doc = "The buffer pointer is not rewound."]
1860        pub const _0: Self = Self::new(0);
1861
1862        #[doc = "The buffer pointer is rewound."]
1863        pub const _1: Self = Self::new(1);
1864    }
1865    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1866    pub struct Mbw_SPEC;
1867    pub type Mbw = crate::EnumBitfieldStruct<u8, Mbw_SPEC>;
1868    impl Mbw {
1869        #[doc = "8-bit width"]
1870        pub const _0: Self = Self::new(0);
1871
1872        #[doc = "16-bit width"]
1873        pub const _1: Self = Self::new(1);
1874    }
1875    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1876    pub struct Bigend_SPEC;
1877    pub type Bigend = crate::EnumBitfieldStruct<u8, Bigend_SPEC>;
1878    impl Bigend {
1879        #[doc = "Little endian"]
1880        pub const _0: Self = Self::new(0);
1881
1882        #[doc = "Big endian"]
1883        pub const _1: Self = Self::new(1);
1884    }
1885    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1886    pub struct Isel_SPEC;
1887    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
1888    impl Isel {
1889        #[doc = "Reading from the buffer memory is selected"]
1890        pub const _0: Self = Self::new(0);
1891
1892        #[doc = "Writing to the buffer memory is selected"]
1893        pub const _1: Self = Self::new(1);
1894    }
1895    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1896    pub struct Curpipe_SPEC;
1897    pub type Curpipe = crate::EnumBitfieldStruct<u8, Curpipe_SPEC>;
1898    impl Curpipe {
1899        #[doc = "DCP (Default control pipe)"]
1900        pub const _0000: Self = Self::new(0);
1901
1902        #[doc = "Pipe 1"]
1903        pub const _0001: Self = Self::new(1);
1904
1905        #[doc = "Pipe 2"]
1906        pub const _0010: Self = Self::new(2);
1907
1908        #[doc = "Pipe 3"]
1909        pub const _0011: Self = Self::new(3);
1910
1911        #[doc = "Pipe 4"]
1912        pub const _0100: Self = Self::new(4);
1913
1914        #[doc = "Pipe 5"]
1915        pub const _0101: Self = Self::new(5);
1916
1917        #[doc = "Pipe 6"]
1918        pub const _0110: Self = Self::new(6);
1919
1920        #[doc = "Pipe 7"]
1921        pub const _0111: Self = Self::new(7);
1922
1923        #[doc = "Pipe 8"]
1924        pub const _1000: Self = Self::new(8);
1925
1926        #[doc = "Pipe 9"]
1927        pub const _1001: Self = Self::new(9);
1928    }
1929}
1930#[doc(hidden)]
1931#[derive(Copy, Clone, Eq, PartialEq)]
1932pub struct Cfifoctr_SPEC;
1933impl crate::sealed::RegSpec for Cfifoctr_SPEC {
1934    type DataType = u16;
1935}
1936
1937#[doc = "CFIFO Port Control Register"]
1938pub type Cfifoctr = crate::RegValueT<Cfifoctr_SPEC>;
1939
1940impl Cfifoctr {
1941    #[doc = "Buffer Memory Valid Flag"]
1942    #[inline(always)]
1943    pub fn bval(
1944        self,
1945    ) -> crate::common::RegisterField<
1946        15,
1947        0x1,
1948        1,
1949        0,
1950        cfifoctr::Bval,
1951        cfifoctr::Bval,
1952        Cfifoctr_SPEC,
1953        crate::common::RW,
1954    > {
1955        crate::common::RegisterField::<
1956            15,
1957            0x1,
1958            1,
1959            0,
1960            cfifoctr::Bval,
1961            cfifoctr::Bval,
1962            Cfifoctr_SPEC,
1963            crate::common::RW,
1964        >::from_register(self, 0)
1965    }
1966
1967    #[doc = "CPU Buffer Clear"]
1968    #[inline(always)]
1969    pub fn bclr(
1970        self,
1971    ) -> crate::common::RegisterField<
1972        14,
1973        0x1,
1974        1,
1975        0,
1976        cfifoctr::Bclr,
1977        cfifoctr::Bclr,
1978        Cfifoctr_SPEC,
1979        crate::common::R,
1980    > {
1981        crate::common::RegisterField::<
1982            14,
1983            0x1,
1984            1,
1985            0,
1986            cfifoctr::Bclr,
1987            cfifoctr::Bclr,
1988            Cfifoctr_SPEC,
1989            crate::common::R,
1990        >::from_register(self, 0)
1991    }
1992
1993    #[doc = "FIFO Port Ready"]
1994    #[inline(always)]
1995    pub fn frdy(
1996        self,
1997    ) -> crate::common::RegisterField<
1998        13,
1999        0x1,
2000        1,
2001        0,
2002        cfifoctr::Frdy,
2003        cfifoctr::Frdy,
2004        Cfifoctr_SPEC,
2005        crate::common::R,
2006    > {
2007        crate::common::RegisterField::<
2008            13,
2009            0x1,
2010            1,
2011            0,
2012            cfifoctr::Frdy,
2013            cfifoctr::Frdy,
2014            Cfifoctr_SPEC,
2015            crate::common::R,
2016        >::from_register(self, 0)
2017    }
2018
2019    #[doc = "Receive Data LengthIndicates the length of the receive data."]
2020    #[inline(always)]
2021    pub fn dtln(
2022        self,
2023    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Cfifoctr_SPEC, crate::common::R>
2024    {
2025        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Cfifoctr_SPEC,crate::common::R>::from_register(self,0)
2026    }
2027}
2028impl ::core::default::Default for Cfifoctr {
2029    #[inline(always)]
2030    fn default() -> Cfifoctr {
2031        <crate::RegValueT<Cfifoctr_SPEC> as RegisterValue<_>>::new(0)
2032    }
2033}
2034pub mod cfifoctr {
2035
2036    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2037    pub struct Bval_SPEC;
2038    pub type Bval = crate::EnumBitfieldStruct<u8, Bval_SPEC>;
2039    impl Bval {
2040        #[doc = "Invalid"]
2041        pub const _0: Self = Self::new(0);
2042
2043        #[doc = "Writing ended"]
2044        pub const _1: Self = Self::new(1);
2045    }
2046    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2047    pub struct Bclr_SPEC;
2048    pub type Bclr = crate::EnumBitfieldStruct<u8, Bclr_SPEC>;
2049    impl Bclr {
2050        #[doc = "Invalid"]
2051        pub const _0: Self = Self::new(0);
2052
2053        #[doc = "Clears the buffer memory on the CPU side"]
2054        pub const _1: Self = Self::new(1);
2055    }
2056    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2057    pub struct Frdy_SPEC;
2058    pub type Frdy = crate::EnumBitfieldStruct<u8, Frdy_SPEC>;
2059    impl Frdy {
2060        #[doc = "FIFO port access is disabled."]
2061        pub const _0: Self = Self::new(0);
2062
2063        #[doc = "FIFO port access is enabled."]
2064        pub const _1: Self = Self::new(1);
2065    }
2066}
2067#[doc(hidden)]
2068#[derive(Copy, Clone, Eq, PartialEq)]
2069pub struct D0Fifosel_SPEC;
2070impl crate::sealed::RegSpec for D0Fifosel_SPEC {
2071    type DataType = u16;
2072}
2073
2074#[doc = "D0FIFO Port Select Register"]
2075pub type D0Fifosel = crate::RegValueT<D0Fifosel_SPEC>;
2076
2077impl D0Fifosel {
2078    #[doc = "Read Count Mode"]
2079    #[inline(always)]
2080    pub fn rcnt(
2081        self,
2082    ) -> crate::common::RegisterField<
2083        15,
2084        0x1,
2085        1,
2086        0,
2087        d0fifosel::Rcnt,
2088        d0fifosel::Rcnt,
2089        D0Fifosel_SPEC,
2090        crate::common::RW,
2091    > {
2092        crate::common::RegisterField::<
2093            15,
2094            0x1,
2095            1,
2096            0,
2097            d0fifosel::Rcnt,
2098            d0fifosel::Rcnt,
2099            D0Fifosel_SPEC,
2100            crate::common::RW,
2101        >::from_register(self, 0)
2102    }
2103
2104    #[doc = "Buffer Pointer Rewind"]
2105    #[inline(always)]
2106    pub fn rew(
2107        self,
2108    ) -> crate::common::RegisterField<
2109        14,
2110        0x1,
2111        1,
2112        0,
2113        d0fifosel::Rew,
2114        d0fifosel::Rew,
2115        D0Fifosel_SPEC,
2116        crate::common::R,
2117    > {
2118        crate::common::RegisterField::<
2119            14,
2120            0x1,
2121            1,
2122            0,
2123            d0fifosel::Rew,
2124            d0fifosel::Rew,
2125            D0Fifosel_SPEC,
2126            crate::common::R,
2127        >::from_register(self, 0)
2128    }
2129
2130    #[doc = "Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read"]
2131    #[inline(always)]
2132    pub fn dclrm(
2133        self,
2134    ) -> crate::common::RegisterField<
2135        13,
2136        0x1,
2137        1,
2138        0,
2139        d0fifosel::Dclrm,
2140        d0fifosel::Dclrm,
2141        D0Fifosel_SPEC,
2142        crate::common::RW,
2143    > {
2144        crate::common::RegisterField::<
2145            13,
2146            0x1,
2147            1,
2148            0,
2149            d0fifosel::Dclrm,
2150            d0fifosel::Dclrm,
2151            D0Fifosel_SPEC,
2152            crate::common::RW,
2153        >::from_register(self, 0)
2154    }
2155
2156    #[doc = "DMA/DTC Transfer Request Enable"]
2157    #[inline(always)]
2158    pub fn dreqe(
2159        self,
2160    ) -> crate::common::RegisterField<
2161        12,
2162        0x1,
2163        1,
2164        0,
2165        d0fifosel::Dreqe,
2166        d0fifosel::Dreqe,
2167        D0Fifosel_SPEC,
2168        crate::common::RW,
2169    > {
2170        crate::common::RegisterField::<
2171            12,
2172            0x1,
2173            1,
2174            0,
2175            d0fifosel::Dreqe,
2176            d0fifosel::Dreqe,
2177            D0Fifosel_SPEC,
2178            crate::common::RW,
2179        >::from_register(self, 0)
2180    }
2181
2182    #[doc = "FIFO Port Access Bit Width"]
2183    #[inline(always)]
2184    pub fn mbw(
2185        self,
2186    ) -> crate::common::RegisterField<
2187        10,
2188        0x1,
2189        1,
2190        0,
2191        d0fifosel::Mbw,
2192        d0fifosel::Mbw,
2193        D0Fifosel_SPEC,
2194        crate::common::RW,
2195    > {
2196        crate::common::RegisterField::<
2197            10,
2198            0x1,
2199            1,
2200            0,
2201            d0fifosel::Mbw,
2202            d0fifosel::Mbw,
2203            D0Fifosel_SPEC,
2204            crate::common::RW,
2205        >::from_register(self, 0)
2206    }
2207
2208    #[doc = "FIFO Port Endian Control"]
2209    #[inline(always)]
2210    pub fn bigend(
2211        self,
2212    ) -> crate::common::RegisterField<
2213        8,
2214        0x1,
2215        1,
2216        0,
2217        d0fifosel::Bigend,
2218        d0fifosel::Bigend,
2219        D0Fifosel_SPEC,
2220        crate::common::RW,
2221    > {
2222        crate::common::RegisterField::<
2223            8,
2224            0x1,
2225            1,
2226            0,
2227            d0fifosel::Bigend,
2228            d0fifosel::Bigend,
2229            D0Fifosel_SPEC,
2230            crate::common::RW,
2231        >::from_register(self, 0)
2232    }
2233
2234    #[doc = "FIFO Port Access Pipe Specification"]
2235    #[inline(always)]
2236    pub fn curpipe(
2237        self,
2238    ) -> crate::common::RegisterField<
2239        0,
2240        0xf,
2241        1,
2242        0,
2243        d0fifosel::Curpipe,
2244        d0fifosel::Curpipe,
2245        D0Fifosel_SPEC,
2246        crate::common::RW,
2247    > {
2248        crate::common::RegisterField::<
2249            0,
2250            0xf,
2251            1,
2252            0,
2253            d0fifosel::Curpipe,
2254            d0fifosel::Curpipe,
2255            D0Fifosel_SPEC,
2256            crate::common::RW,
2257        >::from_register(self, 0)
2258    }
2259}
2260impl ::core::default::Default for D0Fifosel {
2261    #[inline(always)]
2262    fn default() -> D0Fifosel {
2263        <crate::RegValueT<D0Fifosel_SPEC> as RegisterValue<_>>::new(0)
2264    }
2265}
2266pub mod d0fifosel {
2267
2268    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2269    pub struct Rcnt_SPEC;
2270    pub type Rcnt = crate::EnumBitfieldStruct<u8, Rcnt_SPEC>;
2271    impl Rcnt {
2272        #[doc = "The DTLN\\[8:0\\] bits (CFIFOCRT.DTLN\\[8:0\\], D0FIFOCRT.DTLN\\[8:0\\], D1FIFOCRT.DTLN\\[8:0\\]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)"]
2273        pub const _0: Self = Self::new(0);
2274
2275        #[doc = "The DTLN\\[8:0\\] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)"]
2276        pub const _1: Self = Self::new(1);
2277    }
2278    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2279    pub struct Rew_SPEC;
2280    pub type Rew = crate::EnumBitfieldStruct<u8, Rew_SPEC>;
2281    impl Rew {
2282        #[doc = "The buffer pointer is not rewound."]
2283        pub const _0: Self = Self::new(0);
2284
2285        #[doc = "The buffer pointer is rewound."]
2286        pub const _1: Self = Self::new(1);
2287    }
2288    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2289    pub struct Dclrm_SPEC;
2290    pub type Dclrm = crate::EnumBitfieldStruct<u8, Dclrm_SPEC>;
2291    impl Dclrm {
2292        #[doc = "Auto buffer clear mode is disabled."]
2293        pub const _0: Self = Self::new(0);
2294
2295        #[doc = "Auto buffer clear mode is enabled."]
2296        pub const _1: Self = Self::new(1);
2297    }
2298    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2299    pub struct Dreqe_SPEC;
2300    pub type Dreqe = crate::EnumBitfieldStruct<u8, Dreqe_SPEC>;
2301    impl Dreqe {
2302        #[doc = "DMA/DTC transfer request is disabled."]
2303        pub const _0: Self = Self::new(0);
2304
2305        #[doc = "DMA/DTC transfer request is enabled."]
2306        pub const _1: Self = Self::new(1);
2307    }
2308    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2309    pub struct Mbw_SPEC;
2310    pub type Mbw = crate::EnumBitfieldStruct<u8, Mbw_SPEC>;
2311    impl Mbw {
2312        #[doc = "8-bit width"]
2313        pub const _0: Self = Self::new(0);
2314
2315        #[doc = "16-bit width"]
2316        pub const _1: Self = Self::new(1);
2317    }
2318    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2319    pub struct Bigend_SPEC;
2320    pub type Bigend = crate::EnumBitfieldStruct<u8, Bigend_SPEC>;
2321    impl Bigend {
2322        #[doc = "Little endian"]
2323        pub const _0: Self = Self::new(0);
2324
2325        #[doc = "Big endian"]
2326        pub const _1: Self = Self::new(1);
2327    }
2328    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2329    pub struct Curpipe_SPEC;
2330    pub type Curpipe = crate::EnumBitfieldStruct<u8, Curpipe_SPEC>;
2331    impl Curpipe {
2332        #[doc = "DCP (Default control pipe)"]
2333        pub const _0000: Self = Self::new(0);
2334
2335        #[doc = "Pipe 1"]
2336        pub const _0001: Self = Self::new(1);
2337
2338        #[doc = "Pipe 2"]
2339        pub const _0010: Self = Self::new(2);
2340
2341        #[doc = "Pipe 3"]
2342        pub const _0011: Self = Self::new(3);
2343
2344        #[doc = "Pipe 4"]
2345        pub const _0100: Self = Self::new(4);
2346
2347        #[doc = "Pipe 5"]
2348        pub const _0101: Self = Self::new(5);
2349
2350        #[doc = "Pipe 6"]
2351        pub const _0110: Self = Self::new(6);
2352
2353        #[doc = "Pipe 7"]
2354        pub const _0111: Self = Self::new(7);
2355
2356        #[doc = "Pipe 8"]
2357        pub const _1000: Self = Self::new(8);
2358
2359        #[doc = "Pipe 9"]
2360        pub const _1001: Self = Self::new(9);
2361    }
2362}
2363#[doc(hidden)]
2364#[derive(Copy, Clone, Eq, PartialEq)]
2365pub struct D0Fifoctr_SPEC;
2366impl crate::sealed::RegSpec for D0Fifoctr_SPEC {
2367    type DataType = u16;
2368}
2369
2370#[doc = "D0FIFO Port Control Register"]
2371pub type D0Fifoctr = crate::RegValueT<D0Fifoctr_SPEC>;
2372
2373impl D0Fifoctr {
2374    #[doc = "Buffer Memory Valid Flag"]
2375    #[inline(always)]
2376    pub fn bval(
2377        self,
2378    ) -> crate::common::RegisterField<
2379        15,
2380        0x1,
2381        1,
2382        0,
2383        d0fifoctr::Bval,
2384        d0fifoctr::Bval,
2385        D0Fifoctr_SPEC,
2386        crate::common::RW,
2387    > {
2388        crate::common::RegisterField::<
2389            15,
2390            0x1,
2391            1,
2392            0,
2393            d0fifoctr::Bval,
2394            d0fifoctr::Bval,
2395            D0Fifoctr_SPEC,
2396            crate::common::RW,
2397        >::from_register(self, 0)
2398    }
2399
2400    #[doc = "CPU Buffer Clear"]
2401    #[inline(always)]
2402    pub fn bclr(
2403        self,
2404    ) -> crate::common::RegisterField<
2405        14,
2406        0x1,
2407        1,
2408        0,
2409        d0fifoctr::Bclr,
2410        d0fifoctr::Bclr,
2411        D0Fifoctr_SPEC,
2412        crate::common::R,
2413    > {
2414        crate::common::RegisterField::<
2415            14,
2416            0x1,
2417            1,
2418            0,
2419            d0fifoctr::Bclr,
2420            d0fifoctr::Bclr,
2421            D0Fifoctr_SPEC,
2422            crate::common::R,
2423        >::from_register(self, 0)
2424    }
2425
2426    #[doc = "FIFO Port Ready"]
2427    #[inline(always)]
2428    pub fn frdy(
2429        self,
2430    ) -> crate::common::RegisterField<
2431        13,
2432        0x1,
2433        1,
2434        0,
2435        d0fifoctr::Frdy,
2436        d0fifoctr::Frdy,
2437        D0Fifoctr_SPEC,
2438        crate::common::R,
2439    > {
2440        crate::common::RegisterField::<
2441            13,
2442            0x1,
2443            1,
2444            0,
2445            d0fifoctr::Frdy,
2446            d0fifoctr::Frdy,
2447            D0Fifoctr_SPEC,
2448            crate::common::R,
2449        >::from_register(self, 0)
2450    }
2451
2452    #[doc = "Receive Data LengthIndicates the length of the receive data."]
2453    #[inline(always)]
2454    pub fn dtln(
2455        self,
2456    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, D0Fifoctr_SPEC, crate::common::R>
2457    {
2458        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,D0Fifoctr_SPEC,crate::common::R>::from_register(self,0)
2459    }
2460}
2461impl ::core::default::Default for D0Fifoctr {
2462    #[inline(always)]
2463    fn default() -> D0Fifoctr {
2464        <crate::RegValueT<D0Fifoctr_SPEC> as RegisterValue<_>>::new(0)
2465    }
2466}
2467pub mod d0fifoctr {
2468
2469    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2470    pub struct Bval_SPEC;
2471    pub type Bval = crate::EnumBitfieldStruct<u8, Bval_SPEC>;
2472    impl Bval {
2473        #[doc = "Invalid"]
2474        pub const _0: Self = Self::new(0);
2475
2476        #[doc = "Writing ended"]
2477        pub const _1: Self = Self::new(1);
2478    }
2479    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2480    pub struct Bclr_SPEC;
2481    pub type Bclr = crate::EnumBitfieldStruct<u8, Bclr_SPEC>;
2482    impl Bclr {
2483        #[doc = "Invalid"]
2484        pub const _0: Self = Self::new(0);
2485
2486        #[doc = "Clears the buffer memory on the CPU side"]
2487        pub const _1: Self = Self::new(1);
2488    }
2489    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2490    pub struct Frdy_SPEC;
2491    pub type Frdy = crate::EnumBitfieldStruct<u8, Frdy_SPEC>;
2492    impl Frdy {
2493        #[doc = "FIFO port access is disabled."]
2494        pub const _0: Self = Self::new(0);
2495
2496        #[doc = "FIFO port access is enabled."]
2497        pub const _1: Self = Self::new(1);
2498    }
2499}
2500#[doc(hidden)]
2501#[derive(Copy, Clone, Eq, PartialEq)]
2502pub struct D1Fifosel_SPEC;
2503impl crate::sealed::RegSpec for D1Fifosel_SPEC {
2504    type DataType = u16;
2505}
2506
2507#[doc = "D1FIFO Port Select Register"]
2508pub type D1Fifosel = crate::RegValueT<D1Fifosel_SPEC>;
2509
2510impl D1Fifosel {
2511    #[doc = "Read Count Mode"]
2512    #[inline(always)]
2513    pub fn rcnt(
2514        self,
2515    ) -> crate::common::RegisterField<
2516        15,
2517        0x1,
2518        1,
2519        0,
2520        d1fifosel::Rcnt,
2521        d1fifosel::Rcnt,
2522        D1Fifosel_SPEC,
2523        crate::common::RW,
2524    > {
2525        crate::common::RegisterField::<
2526            15,
2527            0x1,
2528            1,
2529            0,
2530            d1fifosel::Rcnt,
2531            d1fifosel::Rcnt,
2532            D1Fifosel_SPEC,
2533            crate::common::RW,
2534        >::from_register(self, 0)
2535    }
2536
2537    #[doc = "Buffer Pointer Rewind"]
2538    #[inline(always)]
2539    pub fn rew(
2540        self,
2541    ) -> crate::common::RegisterField<
2542        14,
2543        0x1,
2544        1,
2545        0,
2546        d1fifosel::Rew,
2547        d1fifosel::Rew,
2548        D1Fifosel_SPEC,
2549        crate::common::R,
2550    > {
2551        crate::common::RegisterField::<
2552            14,
2553            0x1,
2554            1,
2555            0,
2556            d1fifosel::Rew,
2557            d1fifosel::Rew,
2558            D1Fifosel_SPEC,
2559            crate::common::R,
2560        >::from_register(self, 0)
2561    }
2562
2563    #[doc = "Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read"]
2564    #[inline(always)]
2565    pub fn dclrm(
2566        self,
2567    ) -> crate::common::RegisterField<
2568        13,
2569        0x1,
2570        1,
2571        0,
2572        d1fifosel::Dclrm,
2573        d1fifosel::Dclrm,
2574        D1Fifosel_SPEC,
2575        crate::common::RW,
2576    > {
2577        crate::common::RegisterField::<
2578            13,
2579            0x1,
2580            1,
2581            0,
2582            d1fifosel::Dclrm,
2583            d1fifosel::Dclrm,
2584            D1Fifosel_SPEC,
2585            crate::common::RW,
2586        >::from_register(self, 0)
2587    }
2588
2589    #[doc = "DMA/DTC Transfer Request Enable"]
2590    #[inline(always)]
2591    pub fn dreqe(
2592        self,
2593    ) -> crate::common::RegisterField<
2594        12,
2595        0x1,
2596        1,
2597        0,
2598        d1fifosel::Dreqe,
2599        d1fifosel::Dreqe,
2600        D1Fifosel_SPEC,
2601        crate::common::RW,
2602    > {
2603        crate::common::RegisterField::<
2604            12,
2605            0x1,
2606            1,
2607            0,
2608            d1fifosel::Dreqe,
2609            d1fifosel::Dreqe,
2610            D1Fifosel_SPEC,
2611            crate::common::RW,
2612        >::from_register(self, 0)
2613    }
2614
2615    #[doc = "FIFO Port Access Bit Width"]
2616    #[inline(always)]
2617    pub fn mbw(
2618        self,
2619    ) -> crate::common::RegisterField<
2620        10,
2621        0x1,
2622        1,
2623        0,
2624        d1fifosel::Mbw,
2625        d1fifosel::Mbw,
2626        D1Fifosel_SPEC,
2627        crate::common::RW,
2628    > {
2629        crate::common::RegisterField::<
2630            10,
2631            0x1,
2632            1,
2633            0,
2634            d1fifosel::Mbw,
2635            d1fifosel::Mbw,
2636            D1Fifosel_SPEC,
2637            crate::common::RW,
2638        >::from_register(self, 0)
2639    }
2640
2641    #[doc = "FIFO Port Endian Control"]
2642    #[inline(always)]
2643    pub fn bigend(
2644        self,
2645    ) -> crate::common::RegisterField<
2646        8,
2647        0x1,
2648        1,
2649        0,
2650        d1fifosel::Bigend,
2651        d1fifosel::Bigend,
2652        D1Fifosel_SPEC,
2653        crate::common::RW,
2654    > {
2655        crate::common::RegisterField::<
2656            8,
2657            0x1,
2658            1,
2659            0,
2660            d1fifosel::Bigend,
2661            d1fifosel::Bigend,
2662            D1Fifosel_SPEC,
2663            crate::common::RW,
2664        >::from_register(self, 0)
2665    }
2666
2667    #[doc = "FIFO Port Access Pipe Specification"]
2668    #[inline(always)]
2669    pub fn curpipe(
2670        self,
2671    ) -> crate::common::RegisterField<
2672        0,
2673        0xf,
2674        1,
2675        0,
2676        d1fifosel::Curpipe,
2677        d1fifosel::Curpipe,
2678        D1Fifosel_SPEC,
2679        crate::common::RW,
2680    > {
2681        crate::common::RegisterField::<
2682            0,
2683            0xf,
2684            1,
2685            0,
2686            d1fifosel::Curpipe,
2687            d1fifosel::Curpipe,
2688            D1Fifosel_SPEC,
2689            crate::common::RW,
2690        >::from_register(self, 0)
2691    }
2692}
2693impl ::core::default::Default for D1Fifosel {
2694    #[inline(always)]
2695    fn default() -> D1Fifosel {
2696        <crate::RegValueT<D1Fifosel_SPEC> as RegisterValue<_>>::new(0)
2697    }
2698}
2699pub mod d1fifosel {
2700
2701    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2702    pub struct Rcnt_SPEC;
2703    pub type Rcnt = crate::EnumBitfieldStruct<u8, Rcnt_SPEC>;
2704    impl Rcnt {
2705        #[doc = "The DTLN\\[8:0\\] bits (CFIFOCRT.DTLN\\[8:0\\], D0FIFOCRT.DTLN\\[8:0\\], D1FIFOCRT.DTLN\\[8:0\\]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)"]
2706        pub const _0: Self = Self::new(0);
2707
2708        #[doc = "The DTLN\\[8:0\\] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)"]
2709        pub const _1: Self = Self::new(1);
2710    }
2711    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2712    pub struct Rew_SPEC;
2713    pub type Rew = crate::EnumBitfieldStruct<u8, Rew_SPEC>;
2714    impl Rew {
2715        #[doc = "The buffer pointer is not rewound."]
2716        pub const _0: Self = Self::new(0);
2717
2718        #[doc = "The buffer pointer is rewound."]
2719        pub const _1: Self = Self::new(1);
2720    }
2721    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2722    pub struct Dclrm_SPEC;
2723    pub type Dclrm = crate::EnumBitfieldStruct<u8, Dclrm_SPEC>;
2724    impl Dclrm {
2725        #[doc = "Auto buffer clear mode is disabled."]
2726        pub const _0: Self = Self::new(0);
2727
2728        #[doc = "Auto buffer clear mode is enabled."]
2729        pub const _1: Self = Self::new(1);
2730    }
2731    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2732    pub struct Dreqe_SPEC;
2733    pub type Dreqe = crate::EnumBitfieldStruct<u8, Dreqe_SPEC>;
2734    impl Dreqe {
2735        #[doc = "DMA/DTC transfer request is disabled."]
2736        pub const _0: Self = Self::new(0);
2737
2738        #[doc = "DMA/DTC transfer request is enabled."]
2739        pub const _1: Self = Self::new(1);
2740    }
2741    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2742    pub struct Mbw_SPEC;
2743    pub type Mbw = crate::EnumBitfieldStruct<u8, Mbw_SPEC>;
2744    impl Mbw {
2745        #[doc = "8-bit width"]
2746        pub const _0: Self = Self::new(0);
2747
2748        #[doc = "16-bit width"]
2749        pub const _1: Self = Self::new(1);
2750    }
2751    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2752    pub struct Bigend_SPEC;
2753    pub type Bigend = crate::EnumBitfieldStruct<u8, Bigend_SPEC>;
2754    impl Bigend {
2755        #[doc = "Little endian"]
2756        pub const _0: Self = Self::new(0);
2757
2758        #[doc = "Big endian"]
2759        pub const _1: Self = Self::new(1);
2760    }
2761    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2762    pub struct Curpipe_SPEC;
2763    pub type Curpipe = crate::EnumBitfieldStruct<u8, Curpipe_SPEC>;
2764    impl Curpipe {
2765        #[doc = "DCP (Default control pipe)"]
2766        pub const _0000: Self = Self::new(0);
2767
2768        #[doc = "Pipe 1"]
2769        pub const _0001: Self = Self::new(1);
2770
2771        #[doc = "Pipe 2"]
2772        pub const _0010: Self = Self::new(2);
2773
2774        #[doc = "Pipe 3"]
2775        pub const _0011: Self = Self::new(3);
2776
2777        #[doc = "Pipe 4"]
2778        pub const _0100: Self = Self::new(4);
2779
2780        #[doc = "Pipe 5"]
2781        pub const _0101: Self = Self::new(5);
2782
2783        #[doc = "Pipe 6"]
2784        pub const _0110: Self = Self::new(6);
2785
2786        #[doc = "Pipe 7"]
2787        pub const _0111: Self = Self::new(7);
2788
2789        #[doc = "Pipe 8"]
2790        pub const _1000: Self = Self::new(8);
2791
2792        #[doc = "Pipe 9"]
2793        pub const _1001: Self = Self::new(9);
2794    }
2795}
2796#[doc(hidden)]
2797#[derive(Copy, Clone, Eq, PartialEq)]
2798pub struct D1Fifoctr_SPEC;
2799impl crate::sealed::RegSpec for D1Fifoctr_SPEC {
2800    type DataType = u16;
2801}
2802
2803#[doc = "D1FIFO Port Control Register"]
2804pub type D1Fifoctr = crate::RegValueT<D1Fifoctr_SPEC>;
2805
2806impl D1Fifoctr {
2807    #[doc = "Buffer Memory Valid Flag"]
2808    #[inline(always)]
2809    pub fn bval(
2810        self,
2811    ) -> crate::common::RegisterField<
2812        15,
2813        0x1,
2814        1,
2815        0,
2816        d1fifoctr::Bval,
2817        d1fifoctr::Bval,
2818        D1Fifoctr_SPEC,
2819        crate::common::RW,
2820    > {
2821        crate::common::RegisterField::<
2822            15,
2823            0x1,
2824            1,
2825            0,
2826            d1fifoctr::Bval,
2827            d1fifoctr::Bval,
2828            D1Fifoctr_SPEC,
2829            crate::common::RW,
2830        >::from_register(self, 0)
2831    }
2832
2833    #[doc = "CPU Buffer Clear"]
2834    #[inline(always)]
2835    pub fn bclr(
2836        self,
2837    ) -> crate::common::RegisterField<
2838        14,
2839        0x1,
2840        1,
2841        0,
2842        d1fifoctr::Bclr,
2843        d1fifoctr::Bclr,
2844        D1Fifoctr_SPEC,
2845        crate::common::R,
2846    > {
2847        crate::common::RegisterField::<
2848            14,
2849            0x1,
2850            1,
2851            0,
2852            d1fifoctr::Bclr,
2853            d1fifoctr::Bclr,
2854            D1Fifoctr_SPEC,
2855            crate::common::R,
2856        >::from_register(self, 0)
2857    }
2858
2859    #[doc = "FIFO Port Ready"]
2860    #[inline(always)]
2861    pub fn frdy(
2862        self,
2863    ) -> crate::common::RegisterField<
2864        13,
2865        0x1,
2866        1,
2867        0,
2868        d1fifoctr::Frdy,
2869        d1fifoctr::Frdy,
2870        D1Fifoctr_SPEC,
2871        crate::common::R,
2872    > {
2873        crate::common::RegisterField::<
2874            13,
2875            0x1,
2876            1,
2877            0,
2878            d1fifoctr::Frdy,
2879            d1fifoctr::Frdy,
2880            D1Fifoctr_SPEC,
2881            crate::common::R,
2882        >::from_register(self, 0)
2883    }
2884
2885    #[doc = "Receive Data LengthIndicates the length of the receive data."]
2886    #[inline(always)]
2887    pub fn dtln(
2888        self,
2889    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, D1Fifoctr_SPEC, crate::common::R>
2890    {
2891        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,D1Fifoctr_SPEC,crate::common::R>::from_register(self,0)
2892    }
2893}
2894impl ::core::default::Default for D1Fifoctr {
2895    #[inline(always)]
2896    fn default() -> D1Fifoctr {
2897        <crate::RegValueT<D1Fifoctr_SPEC> as RegisterValue<_>>::new(0)
2898    }
2899}
2900pub mod d1fifoctr {
2901
2902    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2903    pub struct Bval_SPEC;
2904    pub type Bval = crate::EnumBitfieldStruct<u8, Bval_SPEC>;
2905    impl Bval {
2906        #[doc = "Invalid"]
2907        pub const _0: Self = Self::new(0);
2908
2909        #[doc = "Writing ended"]
2910        pub const _1: Self = Self::new(1);
2911    }
2912    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2913    pub struct Bclr_SPEC;
2914    pub type Bclr = crate::EnumBitfieldStruct<u8, Bclr_SPEC>;
2915    impl Bclr {
2916        #[doc = "Invalid"]
2917        pub const _0: Self = Self::new(0);
2918
2919        #[doc = "Clears the buffer memory on the CPU side"]
2920        pub const _1: Self = Self::new(1);
2921    }
2922    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2923    pub struct Frdy_SPEC;
2924    pub type Frdy = crate::EnumBitfieldStruct<u8, Frdy_SPEC>;
2925    impl Frdy {
2926        #[doc = "FIFO port access is disabled."]
2927        pub const _0: Self = Self::new(0);
2928
2929        #[doc = "FIFO port access is enabled."]
2930        pub const _1: Self = Self::new(1);
2931    }
2932}
2933#[doc(hidden)]
2934#[derive(Copy, Clone, Eq, PartialEq)]
2935pub struct Intenb0_SPEC;
2936impl crate::sealed::RegSpec for Intenb0_SPEC {
2937    type DataType = u16;
2938}
2939
2940#[doc = "Interrupt Enable Register 0"]
2941pub type Intenb0 = crate::RegValueT<Intenb0_SPEC>;
2942
2943impl Intenb0 {
2944    #[doc = "VBUS Interrupt Enable"]
2945    #[inline(always)]
2946    pub fn vbse(
2947        self,
2948    ) -> crate::common::RegisterField<
2949        15,
2950        0x1,
2951        1,
2952        0,
2953        intenb0::Vbse,
2954        intenb0::Vbse,
2955        Intenb0_SPEC,
2956        crate::common::RW,
2957    > {
2958        crate::common::RegisterField::<
2959            15,
2960            0x1,
2961            1,
2962            0,
2963            intenb0::Vbse,
2964            intenb0::Vbse,
2965            Intenb0_SPEC,
2966            crate::common::RW,
2967        >::from_register(self, 0)
2968    }
2969
2970    #[doc = "Resume Interrupt Enable"]
2971    #[inline(always)]
2972    pub fn rsme(
2973        self,
2974    ) -> crate::common::RegisterField<
2975        14,
2976        0x1,
2977        1,
2978        0,
2979        intenb0::Rsme,
2980        intenb0::Rsme,
2981        Intenb0_SPEC,
2982        crate::common::RW,
2983    > {
2984        crate::common::RegisterField::<
2985            14,
2986            0x1,
2987            1,
2988            0,
2989            intenb0::Rsme,
2990            intenb0::Rsme,
2991            Intenb0_SPEC,
2992            crate::common::RW,
2993        >::from_register(self, 0)
2994    }
2995
2996    #[doc = "Frame Number Update Interrupt Enable"]
2997    #[inline(always)]
2998    pub fn sofe(
2999        self,
3000    ) -> crate::common::RegisterField<
3001        13,
3002        0x1,
3003        1,
3004        0,
3005        intenb0::Sofe,
3006        intenb0::Sofe,
3007        Intenb0_SPEC,
3008        crate::common::RW,
3009    > {
3010        crate::common::RegisterField::<
3011            13,
3012            0x1,
3013            1,
3014            0,
3015            intenb0::Sofe,
3016            intenb0::Sofe,
3017            Intenb0_SPEC,
3018            crate::common::RW,
3019        >::from_register(self, 0)
3020    }
3021
3022    #[doc = "Device State Transition Interrupt Enable"]
3023    #[inline(always)]
3024    pub fn dvse(
3025        self,
3026    ) -> crate::common::RegisterField<
3027        12,
3028        0x1,
3029        1,
3030        0,
3031        intenb0::Dvse,
3032        intenb0::Dvse,
3033        Intenb0_SPEC,
3034        crate::common::RW,
3035    > {
3036        crate::common::RegisterField::<
3037            12,
3038            0x1,
3039            1,
3040            0,
3041            intenb0::Dvse,
3042            intenb0::Dvse,
3043            Intenb0_SPEC,
3044            crate::common::RW,
3045        >::from_register(self, 0)
3046    }
3047
3048    #[doc = "Control Transfer Stage Transition Interrupt Enable"]
3049    #[inline(always)]
3050    pub fn ctre(
3051        self,
3052    ) -> crate::common::RegisterField<
3053        11,
3054        0x1,
3055        1,
3056        0,
3057        intenb0::Ctre,
3058        intenb0::Ctre,
3059        Intenb0_SPEC,
3060        crate::common::RW,
3061    > {
3062        crate::common::RegisterField::<
3063            11,
3064            0x1,
3065            1,
3066            0,
3067            intenb0::Ctre,
3068            intenb0::Ctre,
3069            Intenb0_SPEC,
3070            crate::common::RW,
3071        >::from_register(self, 0)
3072    }
3073
3074    #[doc = "Buffer Empty Interrupt Enable"]
3075    #[inline(always)]
3076    pub fn bempe(
3077        self,
3078    ) -> crate::common::RegisterField<
3079        10,
3080        0x1,
3081        1,
3082        0,
3083        intenb0::Bempe,
3084        intenb0::Bempe,
3085        Intenb0_SPEC,
3086        crate::common::RW,
3087    > {
3088        crate::common::RegisterField::<
3089            10,
3090            0x1,
3091            1,
3092            0,
3093            intenb0::Bempe,
3094            intenb0::Bempe,
3095            Intenb0_SPEC,
3096            crate::common::RW,
3097        >::from_register(self, 0)
3098    }
3099
3100    #[doc = "Buffer Not Ready Response Interrupt Enable"]
3101    #[inline(always)]
3102    pub fn nrdye(
3103        self,
3104    ) -> crate::common::RegisterField<
3105        9,
3106        0x1,
3107        1,
3108        0,
3109        intenb0::Nrdye,
3110        intenb0::Nrdye,
3111        Intenb0_SPEC,
3112        crate::common::RW,
3113    > {
3114        crate::common::RegisterField::<
3115            9,
3116            0x1,
3117            1,
3118            0,
3119            intenb0::Nrdye,
3120            intenb0::Nrdye,
3121            Intenb0_SPEC,
3122            crate::common::RW,
3123        >::from_register(self, 0)
3124    }
3125
3126    #[doc = "Buffer Ready Interrupt Enable"]
3127    #[inline(always)]
3128    pub fn brdye(
3129        self,
3130    ) -> crate::common::RegisterField<
3131        8,
3132        0x1,
3133        1,
3134        0,
3135        intenb0::Brdye,
3136        intenb0::Brdye,
3137        Intenb0_SPEC,
3138        crate::common::RW,
3139    > {
3140        crate::common::RegisterField::<
3141            8,
3142            0x1,
3143            1,
3144            0,
3145            intenb0::Brdye,
3146            intenb0::Brdye,
3147            Intenb0_SPEC,
3148            crate::common::RW,
3149        >::from_register(self, 0)
3150    }
3151}
3152impl ::core::default::Default for Intenb0 {
3153    #[inline(always)]
3154    fn default() -> Intenb0 {
3155        <crate::RegValueT<Intenb0_SPEC> as RegisterValue<_>>::new(0)
3156    }
3157}
3158pub mod intenb0 {
3159
3160    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3161    pub struct Vbse_SPEC;
3162    pub type Vbse = crate::EnumBitfieldStruct<u8, Vbse_SPEC>;
3163    impl Vbse {
3164        #[doc = "Interrupt output disabled"]
3165        pub const _0: Self = Self::new(0);
3166
3167        #[doc = "Interrupt output enabled"]
3168        pub const _1: Self = Self::new(1);
3169    }
3170    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3171    pub struct Rsme_SPEC;
3172    pub type Rsme = crate::EnumBitfieldStruct<u8, Rsme_SPEC>;
3173    impl Rsme {
3174        #[doc = "Interrupt output disabled"]
3175        pub const _0: Self = Self::new(0);
3176
3177        #[doc = "Interrupt output enabled"]
3178        pub const _1: Self = Self::new(1);
3179    }
3180    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3181    pub struct Sofe_SPEC;
3182    pub type Sofe = crate::EnumBitfieldStruct<u8, Sofe_SPEC>;
3183    impl Sofe {
3184        #[doc = "Interrupt output disabled"]
3185        pub const _0: Self = Self::new(0);
3186
3187        #[doc = "Interrupt output enabled"]
3188        pub const _1: Self = Self::new(1);
3189    }
3190    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3191    pub struct Dvse_SPEC;
3192    pub type Dvse = crate::EnumBitfieldStruct<u8, Dvse_SPEC>;
3193    impl Dvse {
3194        #[doc = "Interrupt output disabled"]
3195        pub const _0: Self = Self::new(0);
3196
3197        #[doc = "Interrupt output enabled"]
3198        pub const _1: Self = Self::new(1);
3199    }
3200    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3201    pub struct Ctre_SPEC;
3202    pub type Ctre = crate::EnumBitfieldStruct<u8, Ctre_SPEC>;
3203    impl Ctre {
3204        #[doc = "Interrupt output disabled"]
3205        pub const _0: Self = Self::new(0);
3206
3207        #[doc = "Interrupt output enabled"]
3208        pub const _1: Self = Self::new(1);
3209    }
3210    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3211    pub struct Bempe_SPEC;
3212    pub type Bempe = crate::EnumBitfieldStruct<u8, Bempe_SPEC>;
3213    impl Bempe {
3214        #[doc = "Interrupt output disabled"]
3215        pub const _0: Self = Self::new(0);
3216
3217        #[doc = "Interrupt output enabled"]
3218        pub const _1: Self = Self::new(1);
3219    }
3220    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3221    pub struct Nrdye_SPEC;
3222    pub type Nrdye = crate::EnumBitfieldStruct<u8, Nrdye_SPEC>;
3223    impl Nrdye {
3224        #[doc = "Interrupt output disabled"]
3225        pub const _0: Self = Self::new(0);
3226
3227        #[doc = "Interrupt output enabled"]
3228        pub const _1: Self = Self::new(1);
3229    }
3230    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3231    pub struct Brdye_SPEC;
3232    pub type Brdye = crate::EnumBitfieldStruct<u8, Brdye_SPEC>;
3233    impl Brdye {
3234        #[doc = "Interrupt output disabled"]
3235        pub const _0: Self = Self::new(0);
3236
3237        #[doc = "Interrupt output enabled"]
3238        pub const _1: Self = Self::new(1);
3239    }
3240}
3241#[doc(hidden)]
3242#[derive(Copy, Clone, Eq, PartialEq)]
3243pub struct Intenb1_SPEC;
3244impl crate::sealed::RegSpec for Intenb1_SPEC {
3245    type DataType = u16;
3246}
3247
3248#[doc = "Interrupt Enable Register 1"]
3249pub type Intenb1 = crate::RegValueT<Intenb1_SPEC>;
3250
3251impl Intenb1 {
3252    #[doc = "Overcurrent Input Change Interrupt Enable"]
3253    #[inline(always)]
3254    pub fn ovrcre(
3255        self,
3256    ) -> crate::common::RegisterField<
3257        15,
3258        0x1,
3259        1,
3260        0,
3261        intenb1::Ovrcre,
3262        intenb1::Ovrcre,
3263        Intenb1_SPEC,
3264        crate::common::RW,
3265    > {
3266        crate::common::RegisterField::<
3267            15,
3268            0x1,
3269            1,
3270            0,
3271            intenb1::Ovrcre,
3272            intenb1::Ovrcre,
3273            Intenb1_SPEC,
3274            crate::common::RW,
3275        >::from_register(self, 0)
3276    }
3277
3278    #[doc = "USB Bus Change Interrupt Enable"]
3279    #[inline(always)]
3280    pub fn bchge(
3281        self,
3282    ) -> crate::common::RegisterField<
3283        14,
3284        0x1,
3285        1,
3286        0,
3287        intenb1::Bchge,
3288        intenb1::Bchge,
3289        Intenb1_SPEC,
3290        crate::common::RW,
3291    > {
3292        crate::common::RegisterField::<
3293            14,
3294            0x1,
3295            1,
3296            0,
3297            intenb1::Bchge,
3298            intenb1::Bchge,
3299            Intenb1_SPEC,
3300            crate::common::RW,
3301        >::from_register(self, 0)
3302    }
3303
3304    #[doc = "Disconnection Detection Interrupt Enable"]
3305    #[inline(always)]
3306    pub fn dtche(
3307        self,
3308    ) -> crate::common::RegisterField<
3309        12,
3310        0x1,
3311        1,
3312        0,
3313        intenb1::Dtche,
3314        intenb1::Dtche,
3315        Intenb1_SPEC,
3316        crate::common::RW,
3317    > {
3318        crate::common::RegisterField::<
3319            12,
3320            0x1,
3321            1,
3322            0,
3323            intenb1::Dtche,
3324            intenb1::Dtche,
3325            Intenb1_SPEC,
3326            crate::common::RW,
3327        >::from_register(self, 0)
3328    }
3329
3330    #[doc = "Connection Detection Interrupt Enable"]
3331    #[inline(always)]
3332    pub fn attche(
3333        self,
3334    ) -> crate::common::RegisterField<
3335        11,
3336        0x1,
3337        1,
3338        0,
3339        intenb1::Attche,
3340        intenb1::Attche,
3341        Intenb1_SPEC,
3342        crate::common::RW,
3343    > {
3344        crate::common::RegisterField::<
3345            11,
3346            0x1,
3347            1,
3348            0,
3349            intenb1::Attche,
3350            intenb1::Attche,
3351            Intenb1_SPEC,
3352            crate::common::RW,
3353        >::from_register(self, 0)
3354    }
3355
3356    #[doc = "EOF Error Detection Interrupt Enable"]
3357    #[inline(always)]
3358    pub fn eoferre(
3359        self,
3360    ) -> crate::common::RegisterField<
3361        6,
3362        0x1,
3363        1,
3364        0,
3365        intenb1::Eoferre,
3366        intenb1::Eoferre,
3367        Intenb1_SPEC,
3368        crate::common::RW,
3369    > {
3370        crate::common::RegisterField::<
3371            6,
3372            0x1,
3373            1,
3374            0,
3375            intenb1::Eoferre,
3376            intenb1::Eoferre,
3377            Intenb1_SPEC,
3378            crate::common::RW,
3379        >::from_register(self, 0)
3380    }
3381
3382    #[doc = "Setup Transaction Error Interrupt Enable"]
3383    #[inline(always)]
3384    pub fn signe(
3385        self,
3386    ) -> crate::common::RegisterField<
3387        5,
3388        0x1,
3389        1,
3390        0,
3391        intenb1::Signe,
3392        intenb1::Signe,
3393        Intenb1_SPEC,
3394        crate::common::RW,
3395    > {
3396        crate::common::RegisterField::<
3397            5,
3398            0x1,
3399            1,
3400            0,
3401            intenb1::Signe,
3402            intenb1::Signe,
3403            Intenb1_SPEC,
3404            crate::common::RW,
3405        >::from_register(self, 0)
3406    }
3407
3408    #[doc = "Setup Transaction Normal Response Interrupt Enable"]
3409    #[inline(always)]
3410    pub fn sacke(
3411        self,
3412    ) -> crate::common::RegisterField<
3413        4,
3414        0x1,
3415        1,
3416        0,
3417        intenb1::Sacke,
3418        intenb1::Sacke,
3419        Intenb1_SPEC,
3420        crate::common::RW,
3421    > {
3422        crate::common::RegisterField::<
3423            4,
3424            0x1,
3425            1,
3426            0,
3427            intenb1::Sacke,
3428            intenb1::Sacke,
3429            Intenb1_SPEC,
3430            crate::common::RW,
3431        >::from_register(self, 0)
3432    }
3433}
3434impl ::core::default::Default for Intenb1 {
3435    #[inline(always)]
3436    fn default() -> Intenb1 {
3437        <crate::RegValueT<Intenb1_SPEC> as RegisterValue<_>>::new(0)
3438    }
3439}
3440pub mod intenb1 {
3441
3442    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3443    pub struct Ovrcre_SPEC;
3444    pub type Ovrcre = crate::EnumBitfieldStruct<u8, Ovrcre_SPEC>;
3445    impl Ovrcre {
3446        #[doc = "Interrupt output disabled"]
3447        pub const _0: Self = Self::new(0);
3448
3449        #[doc = "Interrupt output enabled"]
3450        pub const _1: Self = Self::new(1);
3451    }
3452    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3453    pub struct Bchge_SPEC;
3454    pub type Bchge = crate::EnumBitfieldStruct<u8, Bchge_SPEC>;
3455    impl Bchge {
3456        #[doc = "Interrupt output disabled"]
3457        pub const _0: Self = Self::new(0);
3458
3459        #[doc = "Interrupt output enabled"]
3460        pub const _1: Self = Self::new(1);
3461    }
3462    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3463    pub struct Dtche_SPEC;
3464    pub type Dtche = crate::EnumBitfieldStruct<u8, Dtche_SPEC>;
3465    impl Dtche {
3466        #[doc = "Interrupt output disabled"]
3467        pub const _0: Self = Self::new(0);
3468
3469        #[doc = "Interrupt output enabled"]
3470        pub const _1: Self = Self::new(1);
3471    }
3472    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3473    pub struct Attche_SPEC;
3474    pub type Attche = crate::EnumBitfieldStruct<u8, Attche_SPEC>;
3475    impl Attche {
3476        #[doc = "Interrupt output disabled"]
3477        pub const _0: Self = Self::new(0);
3478
3479        #[doc = "Interrupt output enabled"]
3480        pub const _1: Self = Self::new(1);
3481    }
3482    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3483    pub struct Eoferre_SPEC;
3484    pub type Eoferre = crate::EnumBitfieldStruct<u8, Eoferre_SPEC>;
3485    impl Eoferre {
3486        #[doc = "Interrupt output disabled"]
3487        pub const _0: Self = Self::new(0);
3488
3489        #[doc = "Interrupt output enabled"]
3490        pub const _1: Self = Self::new(1);
3491    }
3492    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3493    pub struct Signe_SPEC;
3494    pub type Signe = crate::EnumBitfieldStruct<u8, Signe_SPEC>;
3495    impl Signe {
3496        #[doc = "Interrupt output disabled"]
3497        pub const _0: Self = Self::new(0);
3498
3499        #[doc = "Interrupt output enabled"]
3500        pub const _1: Self = Self::new(1);
3501    }
3502    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3503    pub struct Sacke_SPEC;
3504    pub type Sacke = crate::EnumBitfieldStruct<u8, Sacke_SPEC>;
3505    impl Sacke {
3506        #[doc = "Interrupt output disabled"]
3507        pub const _0: Self = Self::new(0);
3508
3509        #[doc = "Interrupt output enabled"]
3510        pub const _1: Self = Self::new(1);
3511    }
3512}
3513#[doc(hidden)]
3514#[derive(Copy, Clone, Eq, PartialEq)]
3515pub struct Brdyenb_SPEC;
3516impl crate::sealed::RegSpec for Brdyenb_SPEC {
3517    type DataType = u16;
3518}
3519
3520#[doc = "BRDY Interrupt Enable Register"]
3521pub type Brdyenb = crate::RegValueT<Brdyenb_SPEC>;
3522
3523impl Brdyenb {
3524    #[doc = "BRDY Interrupt Enable for PIPE9"]
3525    #[inline(always)]
3526    pub fn pipe9brdye(
3527        self,
3528    ) -> crate::common::RegisterField<
3529        9,
3530        0x1,
3531        1,
3532        0,
3533        brdyenb::Pipe9Brdye,
3534        brdyenb::Pipe9Brdye,
3535        Brdyenb_SPEC,
3536        crate::common::RW,
3537    > {
3538        crate::common::RegisterField::<
3539            9,
3540            0x1,
3541            1,
3542            0,
3543            brdyenb::Pipe9Brdye,
3544            brdyenb::Pipe9Brdye,
3545            Brdyenb_SPEC,
3546            crate::common::RW,
3547        >::from_register(self, 0)
3548    }
3549
3550    #[doc = "BRDY Interrupt Enable for PIPE8"]
3551    #[inline(always)]
3552    pub fn pipe8brdye(
3553        self,
3554    ) -> crate::common::RegisterField<
3555        8,
3556        0x1,
3557        1,
3558        0,
3559        brdyenb::Pipe8Brdye,
3560        brdyenb::Pipe8Brdye,
3561        Brdyenb_SPEC,
3562        crate::common::RW,
3563    > {
3564        crate::common::RegisterField::<
3565            8,
3566            0x1,
3567            1,
3568            0,
3569            brdyenb::Pipe8Brdye,
3570            brdyenb::Pipe8Brdye,
3571            Brdyenb_SPEC,
3572            crate::common::RW,
3573        >::from_register(self, 0)
3574    }
3575
3576    #[doc = "BRDY Interrupt Enable for PIPE7"]
3577    #[inline(always)]
3578    pub fn pipe7brdye(
3579        self,
3580    ) -> crate::common::RegisterField<
3581        7,
3582        0x1,
3583        1,
3584        0,
3585        brdyenb::Pipe7Brdye,
3586        brdyenb::Pipe7Brdye,
3587        Brdyenb_SPEC,
3588        crate::common::RW,
3589    > {
3590        crate::common::RegisterField::<
3591            7,
3592            0x1,
3593            1,
3594            0,
3595            brdyenb::Pipe7Brdye,
3596            brdyenb::Pipe7Brdye,
3597            Brdyenb_SPEC,
3598            crate::common::RW,
3599        >::from_register(self, 0)
3600    }
3601
3602    #[doc = "BRDY Interrupt Enable for PIPE6"]
3603    #[inline(always)]
3604    pub fn pipe6brdye(
3605        self,
3606    ) -> crate::common::RegisterField<
3607        6,
3608        0x1,
3609        1,
3610        0,
3611        brdyenb::Pipe6Brdye,
3612        brdyenb::Pipe6Brdye,
3613        Brdyenb_SPEC,
3614        crate::common::RW,
3615    > {
3616        crate::common::RegisterField::<
3617            6,
3618            0x1,
3619            1,
3620            0,
3621            brdyenb::Pipe6Brdye,
3622            brdyenb::Pipe6Brdye,
3623            Brdyenb_SPEC,
3624            crate::common::RW,
3625        >::from_register(self, 0)
3626    }
3627
3628    #[doc = "BRDY Interrupt Enable for PIPE5"]
3629    #[inline(always)]
3630    pub fn pipe5brdye(
3631        self,
3632    ) -> crate::common::RegisterField<
3633        5,
3634        0x1,
3635        1,
3636        0,
3637        brdyenb::Pipe5Brdye,
3638        brdyenb::Pipe5Brdye,
3639        Brdyenb_SPEC,
3640        crate::common::RW,
3641    > {
3642        crate::common::RegisterField::<
3643            5,
3644            0x1,
3645            1,
3646            0,
3647            brdyenb::Pipe5Brdye,
3648            brdyenb::Pipe5Brdye,
3649            Brdyenb_SPEC,
3650            crate::common::RW,
3651        >::from_register(self, 0)
3652    }
3653
3654    #[doc = "BRDY Interrupt Enable for PIPE4"]
3655    #[inline(always)]
3656    pub fn pipe4brdye(
3657        self,
3658    ) -> crate::common::RegisterField<
3659        4,
3660        0x1,
3661        1,
3662        0,
3663        brdyenb::Pipe4Brdye,
3664        brdyenb::Pipe4Brdye,
3665        Brdyenb_SPEC,
3666        crate::common::RW,
3667    > {
3668        crate::common::RegisterField::<
3669            4,
3670            0x1,
3671            1,
3672            0,
3673            brdyenb::Pipe4Brdye,
3674            brdyenb::Pipe4Brdye,
3675            Brdyenb_SPEC,
3676            crate::common::RW,
3677        >::from_register(self, 0)
3678    }
3679
3680    #[doc = "BRDY Interrupt Enable for PIPE3"]
3681    #[inline(always)]
3682    pub fn pipe3brdye(
3683        self,
3684    ) -> crate::common::RegisterField<
3685        3,
3686        0x1,
3687        1,
3688        0,
3689        brdyenb::Pipe3Brdye,
3690        brdyenb::Pipe3Brdye,
3691        Brdyenb_SPEC,
3692        crate::common::RW,
3693    > {
3694        crate::common::RegisterField::<
3695            3,
3696            0x1,
3697            1,
3698            0,
3699            brdyenb::Pipe3Brdye,
3700            brdyenb::Pipe3Brdye,
3701            Brdyenb_SPEC,
3702            crate::common::RW,
3703        >::from_register(self, 0)
3704    }
3705
3706    #[doc = "BRDY Interrupt Enable for PIPE2"]
3707    #[inline(always)]
3708    pub fn pipe2brdye(
3709        self,
3710    ) -> crate::common::RegisterField<
3711        2,
3712        0x1,
3713        1,
3714        0,
3715        brdyenb::Pipe2Brdye,
3716        brdyenb::Pipe2Brdye,
3717        Brdyenb_SPEC,
3718        crate::common::RW,
3719    > {
3720        crate::common::RegisterField::<
3721            2,
3722            0x1,
3723            1,
3724            0,
3725            brdyenb::Pipe2Brdye,
3726            brdyenb::Pipe2Brdye,
3727            Brdyenb_SPEC,
3728            crate::common::RW,
3729        >::from_register(self, 0)
3730    }
3731
3732    #[doc = "BRDY Interrupt Enable for PIPE1"]
3733    #[inline(always)]
3734    pub fn pipe1brdye(
3735        self,
3736    ) -> crate::common::RegisterField<
3737        1,
3738        0x1,
3739        1,
3740        0,
3741        brdyenb::Pipe1Brdye,
3742        brdyenb::Pipe1Brdye,
3743        Brdyenb_SPEC,
3744        crate::common::RW,
3745    > {
3746        crate::common::RegisterField::<
3747            1,
3748            0x1,
3749            1,
3750            0,
3751            brdyenb::Pipe1Brdye,
3752            brdyenb::Pipe1Brdye,
3753            Brdyenb_SPEC,
3754            crate::common::RW,
3755        >::from_register(self, 0)
3756    }
3757
3758    #[doc = "BRDY Interrupt Enable for PIPE0"]
3759    #[inline(always)]
3760    pub fn pipe0brdye(
3761        self,
3762    ) -> crate::common::RegisterField<
3763        0,
3764        0x1,
3765        1,
3766        0,
3767        brdyenb::Pipe0Brdye,
3768        brdyenb::Pipe0Brdye,
3769        Brdyenb_SPEC,
3770        crate::common::RW,
3771    > {
3772        crate::common::RegisterField::<
3773            0,
3774            0x1,
3775            1,
3776            0,
3777            brdyenb::Pipe0Brdye,
3778            brdyenb::Pipe0Brdye,
3779            Brdyenb_SPEC,
3780            crate::common::RW,
3781        >::from_register(self, 0)
3782    }
3783}
3784impl ::core::default::Default for Brdyenb {
3785    #[inline(always)]
3786    fn default() -> Brdyenb {
3787        <crate::RegValueT<Brdyenb_SPEC> as RegisterValue<_>>::new(0)
3788    }
3789}
3790pub mod brdyenb {
3791
3792    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3793    pub struct Pipe9Brdye_SPEC;
3794    pub type Pipe9Brdye = crate::EnumBitfieldStruct<u8, Pipe9Brdye_SPEC>;
3795    impl Pipe9Brdye {
3796        #[doc = "Interrupt output disabled"]
3797        pub const _0: Self = Self::new(0);
3798
3799        #[doc = "Interrupt output enabled"]
3800        pub const _1: Self = Self::new(1);
3801    }
3802    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3803    pub struct Pipe8Brdye_SPEC;
3804    pub type Pipe8Brdye = crate::EnumBitfieldStruct<u8, Pipe8Brdye_SPEC>;
3805    impl Pipe8Brdye {
3806        #[doc = "Interrupt output disabled"]
3807        pub const _0: Self = Self::new(0);
3808
3809        #[doc = "Interrupt output enabled"]
3810        pub const _1: Self = Self::new(1);
3811    }
3812    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3813    pub struct Pipe7Brdye_SPEC;
3814    pub type Pipe7Brdye = crate::EnumBitfieldStruct<u8, Pipe7Brdye_SPEC>;
3815    impl Pipe7Brdye {
3816        #[doc = "Interrupt output disabled"]
3817        pub const _0: Self = Self::new(0);
3818
3819        #[doc = "Interrupt output enabled"]
3820        pub const _1: Self = Self::new(1);
3821    }
3822    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3823    pub struct Pipe6Brdye_SPEC;
3824    pub type Pipe6Brdye = crate::EnumBitfieldStruct<u8, Pipe6Brdye_SPEC>;
3825    impl Pipe6Brdye {
3826        #[doc = "Interrupt output disabled"]
3827        pub const _0: Self = Self::new(0);
3828
3829        #[doc = "Interrupt output enabled"]
3830        pub const _1: Self = Self::new(1);
3831    }
3832    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3833    pub struct Pipe5Brdye_SPEC;
3834    pub type Pipe5Brdye = crate::EnumBitfieldStruct<u8, Pipe5Brdye_SPEC>;
3835    impl Pipe5Brdye {
3836        #[doc = "Interrupt output disabled"]
3837        pub const _0: Self = Self::new(0);
3838
3839        #[doc = "Interrupt output enabled"]
3840        pub const _1: Self = Self::new(1);
3841    }
3842    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3843    pub struct Pipe4Brdye_SPEC;
3844    pub type Pipe4Brdye = crate::EnumBitfieldStruct<u8, Pipe4Brdye_SPEC>;
3845    impl Pipe4Brdye {
3846        #[doc = "Interrupt output disabled"]
3847        pub const _0: Self = Self::new(0);
3848
3849        #[doc = "Interrupt output enabled"]
3850        pub const _1: Self = Self::new(1);
3851    }
3852    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3853    pub struct Pipe3Brdye_SPEC;
3854    pub type Pipe3Brdye = crate::EnumBitfieldStruct<u8, Pipe3Brdye_SPEC>;
3855    impl Pipe3Brdye {
3856        #[doc = "Interrupt output disabled"]
3857        pub const _0: Self = Self::new(0);
3858
3859        #[doc = "Interrupt output enabled"]
3860        pub const _1: Self = Self::new(1);
3861    }
3862    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3863    pub struct Pipe2Brdye_SPEC;
3864    pub type Pipe2Brdye = crate::EnumBitfieldStruct<u8, Pipe2Brdye_SPEC>;
3865    impl Pipe2Brdye {
3866        #[doc = "Interrupt output disabled"]
3867        pub const _0: Self = Self::new(0);
3868
3869        #[doc = "Interrupt output enabled"]
3870        pub const _1: Self = Self::new(1);
3871    }
3872    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3873    pub struct Pipe1Brdye_SPEC;
3874    pub type Pipe1Brdye = crate::EnumBitfieldStruct<u8, Pipe1Brdye_SPEC>;
3875    impl Pipe1Brdye {
3876        #[doc = "Interrupt output disabled"]
3877        pub const _0: Self = Self::new(0);
3878
3879        #[doc = "Interrupt output enabled"]
3880        pub const _1: Self = Self::new(1);
3881    }
3882    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3883    pub struct Pipe0Brdye_SPEC;
3884    pub type Pipe0Brdye = crate::EnumBitfieldStruct<u8, Pipe0Brdye_SPEC>;
3885    impl Pipe0Brdye {
3886        #[doc = "Interrupt output disabled"]
3887        pub const _0: Self = Self::new(0);
3888
3889        #[doc = "Interrupt output enabled"]
3890        pub const _1: Self = Self::new(1);
3891    }
3892}
3893#[doc(hidden)]
3894#[derive(Copy, Clone, Eq, PartialEq)]
3895pub struct Nrdyenb_SPEC;
3896impl crate::sealed::RegSpec for Nrdyenb_SPEC {
3897    type DataType = u16;
3898}
3899
3900#[doc = "NRDY Interrupt Enable Register"]
3901pub type Nrdyenb = crate::RegValueT<Nrdyenb_SPEC>;
3902
3903impl Nrdyenb {
3904    #[doc = "NRDY Interrupt Enable for PIPE9"]
3905    #[inline(always)]
3906    pub fn pipe9nrdye(
3907        self,
3908    ) -> crate::common::RegisterField<
3909        9,
3910        0x1,
3911        1,
3912        0,
3913        nrdyenb::Pipe9Nrdye,
3914        nrdyenb::Pipe9Nrdye,
3915        Nrdyenb_SPEC,
3916        crate::common::RW,
3917    > {
3918        crate::common::RegisterField::<
3919            9,
3920            0x1,
3921            1,
3922            0,
3923            nrdyenb::Pipe9Nrdye,
3924            nrdyenb::Pipe9Nrdye,
3925            Nrdyenb_SPEC,
3926            crate::common::RW,
3927        >::from_register(self, 0)
3928    }
3929
3930    #[doc = "NRDY Interrupt Enable for PIPE8"]
3931    #[inline(always)]
3932    pub fn pipe8nrdye(
3933        self,
3934    ) -> crate::common::RegisterField<
3935        8,
3936        0x1,
3937        1,
3938        0,
3939        nrdyenb::Pipe8Nrdye,
3940        nrdyenb::Pipe8Nrdye,
3941        Nrdyenb_SPEC,
3942        crate::common::RW,
3943    > {
3944        crate::common::RegisterField::<
3945            8,
3946            0x1,
3947            1,
3948            0,
3949            nrdyenb::Pipe8Nrdye,
3950            nrdyenb::Pipe8Nrdye,
3951            Nrdyenb_SPEC,
3952            crate::common::RW,
3953        >::from_register(self, 0)
3954    }
3955
3956    #[doc = "NRDY Interrupt Enable for PIPE7"]
3957    #[inline(always)]
3958    pub fn pipe7nrdye(
3959        self,
3960    ) -> crate::common::RegisterField<
3961        7,
3962        0x1,
3963        1,
3964        0,
3965        nrdyenb::Pipe7Nrdye,
3966        nrdyenb::Pipe7Nrdye,
3967        Nrdyenb_SPEC,
3968        crate::common::RW,
3969    > {
3970        crate::common::RegisterField::<
3971            7,
3972            0x1,
3973            1,
3974            0,
3975            nrdyenb::Pipe7Nrdye,
3976            nrdyenb::Pipe7Nrdye,
3977            Nrdyenb_SPEC,
3978            crate::common::RW,
3979        >::from_register(self, 0)
3980    }
3981
3982    #[doc = "NRDY Interrupt Enable for PIPE6"]
3983    #[inline(always)]
3984    pub fn pipe6nrdye(
3985        self,
3986    ) -> crate::common::RegisterField<
3987        6,
3988        0x1,
3989        1,
3990        0,
3991        nrdyenb::Pipe6Nrdye,
3992        nrdyenb::Pipe6Nrdye,
3993        Nrdyenb_SPEC,
3994        crate::common::RW,
3995    > {
3996        crate::common::RegisterField::<
3997            6,
3998            0x1,
3999            1,
4000            0,
4001            nrdyenb::Pipe6Nrdye,
4002            nrdyenb::Pipe6Nrdye,
4003            Nrdyenb_SPEC,
4004            crate::common::RW,
4005        >::from_register(self, 0)
4006    }
4007
4008    #[doc = "NRDY Interrupt Enable for PIPE5"]
4009    #[inline(always)]
4010    pub fn pipe5nrdye(
4011        self,
4012    ) -> crate::common::RegisterField<
4013        5,
4014        0x1,
4015        1,
4016        0,
4017        nrdyenb::Pipe5Nrdye,
4018        nrdyenb::Pipe5Nrdye,
4019        Nrdyenb_SPEC,
4020        crate::common::RW,
4021    > {
4022        crate::common::RegisterField::<
4023            5,
4024            0x1,
4025            1,
4026            0,
4027            nrdyenb::Pipe5Nrdye,
4028            nrdyenb::Pipe5Nrdye,
4029            Nrdyenb_SPEC,
4030            crate::common::RW,
4031        >::from_register(self, 0)
4032    }
4033
4034    #[doc = "NRDY Interrupt Enable for PIPE4"]
4035    #[inline(always)]
4036    pub fn pipe4nrdye(
4037        self,
4038    ) -> crate::common::RegisterField<
4039        4,
4040        0x1,
4041        1,
4042        0,
4043        nrdyenb::Pipe4Nrdye,
4044        nrdyenb::Pipe4Nrdye,
4045        Nrdyenb_SPEC,
4046        crate::common::RW,
4047    > {
4048        crate::common::RegisterField::<
4049            4,
4050            0x1,
4051            1,
4052            0,
4053            nrdyenb::Pipe4Nrdye,
4054            nrdyenb::Pipe4Nrdye,
4055            Nrdyenb_SPEC,
4056            crate::common::RW,
4057        >::from_register(self, 0)
4058    }
4059
4060    #[doc = "NRDY Interrupt Enable for PIPE3"]
4061    #[inline(always)]
4062    pub fn pipe3nrdye(
4063        self,
4064    ) -> crate::common::RegisterField<
4065        3,
4066        0x1,
4067        1,
4068        0,
4069        nrdyenb::Pipe3Nrdye,
4070        nrdyenb::Pipe3Nrdye,
4071        Nrdyenb_SPEC,
4072        crate::common::RW,
4073    > {
4074        crate::common::RegisterField::<
4075            3,
4076            0x1,
4077            1,
4078            0,
4079            nrdyenb::Pipe3Nrdye,
4080            nrdyenb::Pipe3Nrdye,
4081            Nrdyenb_SPEC,
4082            crate::common::RW,
4083        >::from_register(self, 0)
4084    }
4085
4086    #[doc = "NRDY Interrupt Enable for PIPE2"]
4087    #[inline(always)]
4088    pub fn pipe2nrdye(
4089        self,
4090    ) -> crate::common::RegisterField<
4091        2,
4092        0x1,
4093        1,
4094        0,
4095        nrdyenb::Pipe2Nrdye,
4096        nrdyenb::Pipe2Nrdye,
4097        Nrdyenb_SPEC,
4098        crate::common::RW,
4099    > {
4100        crate::common::RegisterField::<
4101            2,
4102            0x1,
4103            1,
4104            0,
4105            nrdyenb::Pipe2Nrdye,
4106            nrdyenb::Pipe2Nrdye,
4107            Nrdyenb_SPEC,
4108            crate::common::RW,
4109        >::from_register(self, 0)
4110    }
4111
4112    #[doc = "NRDY Interrupt Enable for PIPE1"]
4113    #[inline(always)]
4114    pub fn pipe1nrdye(
4115        self,
4116    ) -> crate::common::RegisterField<
4117        1,
4118        0x1,
4119        1,
4120        0,
4121        nrdyenb::Pipe1Nrdye,
4122        nrdyenb::Pipe1Nrdye,
4123        Nrdyenb_SPEC,
4124        crate::common::RW,
4125    > {
4126        crate::common::RegisterField::<
4127            1,
4128            0x1,
4129            1,
4130            0,
4131            nrdyenb::Pipe1Nrdye,
4132            nrdyenb::Pipe1Nrdye,
4133            Nrdyenb_SPEC,
4134            crate::common::RW,
4135        >::from_register(self, 0)
4136    }
4137
4138    #[doc = "NRDY Interrupt Enable for PIPE0"]
4139    #[inline(always)]
4140    pub fn pipe0nrdye(
4141        self,
4142    ) -> crate::common::RegisterField<
4143        0,
4144        0x1,
4145        1,
4146        0,
4147        nrdyenb::Pipe0Nrdye,
4148        nrdyenb::Pipe0Nrdye,
4149        Nrdyenb_SPEC,
4150        crate::common::RW,
4151    > {
4152        crate::common::RegisterField::<
4153            0,
4154            0x1,
4155            1,
4156            0,
4157            nrdyenb::Pipe0Nrdye,
4158            nrdyenb::Pipe0Nrdye,
4159            Nrdyenb_SPEC,
4160            crate::common::RW,
4161        >::from_register(self, 0)
4162    }
4163}
4164impl ::core::default::Default for Nrdyenb {
4165    #[inline(always)]
4166    fn default() -> Nrdyenb {
4167        <crate::RegValueT<Nrdyenb_SPEC> as RegisterValue<_>>::new(0)
4168    }
4169}
4170pub mod nrdyenb {
4171
4172    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4173    pub struct Pipe9Nrdye_SPEC;
4174    pub type Pipe9Nrdye = crate::EnumBitfieldStruct<u8, Pipe9Nrdye_SPEC>;
4175    impl Pipe9Nrdye {
4176        #[doc = "Interrupt output disabled"]
4177        pub const _0: Self = Self::new(0);
4178
4179        #[doc = "Interrupt output enabled"]
4180        pub const _1: Self = Self::new(1);
4181    }
4182    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4183    pub struct Pipe8Nrdye_SPEC;
4184    pub type Pipe8Nrdye = crate::EnumBitfieldStruct<u8, Pipe8Nrdye_SPEC>;
4185    impl Pipe8Nrdye {
4186        #[doc = "Interrupt output disabled"]
4187        pub const _0: Self = Self::new(0);
4188
4189        #[doc = "Interrupt output enabled"]
4190        pub const _1: Self = Self::new(1);
4191    }
4192    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4193    pub struct Pipe7Nrdye_SPEC;
4194    pub type Pipe7Nrdye = crate::EnumBitfieldStruct<u8, Pipe7Nrdye_SPEC>;
4195    impl Pipe7Nrdye {
4196        #[doc = "Interrupt output disabled"]
4197        pub const _0: Self = Self::new(0);
4198
4199        #[doc = "Interrupt output enabled"]
4200        pub const _1: Self = Self::new(1);
4201    }
4202    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4203    pub struct Pipe6Nrdye_SPEC;
4204    pub type Pipe6Nrdye = crate::EnumBitfieldStruct<u8, Pipe6Nrdye_SPEC>;
4205    impl Pipe6Nrdye {
4206        #[doc = "Interrupt output disabled"]
4207        pub const _0: Self = Self::new(0);
4208
4209        #[doc = "Interrupt output enabled"]
4210        pub const _1: Self = Self::new(1);
4211    }
4212    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4213    pub struct Pipe5Nrdye_SPEC;
4214    pub type Pipe5Nrdye = crate::EnumBitfieldStruct<u8, Pipe5Nrdye_SPEC>;
4215    impl Pipe5Nrdye {
4216        #[doc = "Interrupt output disabled"]
4217        pub const _0: Self = Self::new(0);
4218
4219        #[doc = "Interrupt output enabled"]
4220        pub const _1: Self = Self::new(1);
4221    }
4222    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4223    pub struct Pipe4Nrdye_SPEC;
4224    pub type Pipe4Nrdye = crate::EnumBitfieldStruct<u8, Pipe4Nrdye_SPEC>;
4225    impl Pipe4Nrdye {
4226        #[doc = "Interrupt output disabled"]
4227        pub const _0: Self = Self::new(0);
4228
4229        #[doc = "Interrupt output enabled"]
4230        pub const _1: Self = Self::new(1);
4231    }
4232    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4233    pub struct Pipe3Nrdye_SPEC;
4234    pub type Pipe3Nrdye = crate::EnumBitfieldStruct<u8, Pipe3Nrdye_SPEC>;
4235    impl Pipe3Nrdye {
4236        #[doc = "Interrupt output disabled"]
4237        pub const _0: Self = Self::new(0);
4238
4239        #[doc = "Interrupt output enabled"]
4240        pub const _1: Self = Self::new(1);
4241    }
4242    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4243    pub struct Pipe2Nrdye_SPEC;
4244    pub type Pipe2Nrdye = crate::EnumBitfieldStruct<u8, Pipe2Nrdye_SPEC>;
4245    impl Pipe2Nrdye {
4246        #[doc = "Interrupt output disabled"]
4247        pub const _0: Self = Self::new(0);
4248
4249        #[doc = "Interrupt output enabled"]
4250        pub const _1: Self = Self::new(1);
4251    }
4252    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4253    pub struct Pipe1Nrdye_SPEC;
4254    pub type Pipe1Nrdye = crate::EnumBitfieldStruct<u8, Pipe1Nrdye_SPEC>;
4255    impl Pipe1Nrdye {
4256        #[doc = "Interrupt output disabled"]
4257        pub const _0: Self = Self::new(0);
4258
4259        #[doc = "Interrupt output enabled"]
4260        pub const _1: Self = Self::new(1);
4261    }
4262    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4263    pub struct Pipe0Nrdye_SPEC;
4264    pub type Pipe0Nrdye = crate::EnumBitfieldStruct<u8, Pipe0Nrdye_SPEC>;
4265    impl Pipe0Nrdye {
4266        #[doc = "Interrupt output disabled"]
4267        pub const _0: Self = Self::new(0);
4268
4269        #[doc = "Interrupt output enabled"]
4270        pub const _1: Self = Self::new(1);
4271    }
4272}
4273#[doc(hidden)]
4274#[derive(Copy, Clone, Eq, PartialEq)]
4275pub struct Bempenb_SPEC;
4276impl crate::sealed::RegSpec for Bempenb_SPEC {
4277    type DataType = u16;
4278}
4279
4280#[doc = "BEMP Interrupt Enable Register"]
4281pub type Bempenb = crate::RegValueT<Bempenb_SPEC>;
4282
4283impl Bempenb {
4284    #[doc = "BEMP Interrupt Enable for PIPE9"]
4285    #[inline(always)]
4286    pub fn pipe9bempe(
4287        self,
4288    ) -> crate::common::RegisterField<
4289        9,
4290        0x1,
4291        1,
4292        0,
4293        bempenb::Pipe9Bempe,
4294        bempenb::Pipe9Bempe,
4295        Bempenb_SPEC,
4296        crate::common::RW,
4297    > {
4298        crate::common::RegisterField::<
4299            9,
4300            0x1,
4301            1,
4302            0,
4303            bempenb::Pipe9Bempe,
4304            bempenb::Pipe9Bempe,
4305            Bempenb_SPEC,
4306            crate::common::RW,
4307        >::from_register(self, 0)
4308    }
4309
4310    #[doc = "BEMP Interrupt Enable for PIPE8"]
4311    #[inline(always)]
4312    pub fn pipe8bempe(
4313        self,
4314    ) -> crate::common::RegisterField<
4315        8,
4316        0x1,
4317        1,
4318        0,
4319        bempenb::Pipe8Bempe,
4320        bempenb::Pipe8Bempe,
4321        Bempenb_SPEC,
4322        crate::common::RW,
4323    > {
4324        crate::common::RegisterField::<
4325            8,
4326            0x1,
4327            1,
4328            0,
4329            bempenb::Pipe8Bempe,
4330            bempenb::Pipe8Bempe,
4331            Bempenb_SPEC,
4332            crate::common::RW,
4333        >::from_register(self, 0)
4334    }
4335
4336    #[doc = "BEMP Interrupt Enable for PIPE7"]
4337    #[inline(always)]
4338    pub fn pipe7bempe(
4339        self,
4340    ) -> crate::common::RegisterField<
4341        7,
4342        0x1,
4343        1,
4344        0,
4345        bempenb::Pipe7Bempe,
4346        bempenb::Pipe7Bempe,
4347        Bempenb_SPEC,
4348        crate::common::RW,
4349    > {
4350        crate::common::RegisterField::<
4351            7,
4352            0x1,
4353            1,
4354            0,
4355            bempenb::Pipe7Bempe,
4356            bempenb::Pipe7Bempe,
4357            Bempenb_SPEC,
4358            crate::common::RW,
4359        >::from_register(self, 0)
4360    }
4361
4362    #[doc = "BEMP Interrupt Enable for PIPE6"]
4363    #[inline(always)]
4364    pub fn pipe6bempe(
4365        self,
4366    ) -> crate::common::RegisterField<
4367        6,
4368        0x1,
4369        1,
4370        0,
4371        bempenb::Pipe6Bempe,
4372        bempenb::Pipe6Bempe,
4373        Bempenb_SPEC,
4374        crate::common::RW,
4375    > {
4376        crate::common::RegisterField::<
4377            6,
4378            0x1,
4379            1,
4380            0,
4381            bempenb::Pipe6Bempe,
4382            bempenb::Pipe6Bempe,
4383            Bempenb_SPEC,
4384            crate::common::RW,
4385        >::from_register(self, 0)
4386    }
4387
4388    #[doc = "BEMP Interrupt Enable for PIPE5"]
4389    #[inline(always)]
4390    pub fn pipe5bempe(
4391        self,
4392    ) -> crate::common::RegisterField<
4393        5,
4394        0x1,
4395        1,
4396        0,
4397        bempenb::Pipe5Bempe,
4398        bempenb::Pipe5Bempe,
4399        Bempenb_SPEC,
4400        crate::common::RW,
4401    > {
4402        crate::common::RegisterField::<
4403            5,
4404            0x1,
4405            1,
4406            0,
4407            bempenb::Pipe5Bempe,
4408            bempenb::Pipe5Bempe,
4409            Bempenb_SPEC,
4410            crate::common::RW,
4411        >::from_register(self, 0)
4412    }
4413
4414    #[doc = "BEMP Interrupt Enable for PIPE4"]
4415    #[inline(always)]
4416    pub fn pipe4bempe(
4417        self,
4418    ) -> crate::common::RegisterField<
4419        4,
4420        0x1,
4421        1,
4422        0,
4423        bempenb::Pipe4Bempe,
4424        bempenb::Pipe4Bempe,
4425        Bempenb_SPEC,
4426        crate::common::RW,
4427    > {
4428        crate::common::RegisterField::<
4429            4,
4430            0x1,
4431            1,
4432            0,
4433            bempenb::Pipe4Bempe,
4434            bempenb::Pipe4Bempe,
4435            Bempenb_SPEC,
4436            crate::common::RW,
4437        >::from_register(self, 0)
4438    }
4439
4440    #[doc = "BEMP Interrupt Enable for PIPE3"]
4441    #[inline(always)]
4442    pub fn pipe3bempe(
4443        self,
4444    ) -> crate::common::RegisterField<
4445        3,
4446        0x1,
4447        1,
4448        0,
4449        bempenb::Pipe3Bempe,
4450        bempenb::Pipe3Bempe,
4451        Bempenb_SPEC,
4452        crate::common::RW,
4453    > {
4454        crate::common::RegisterField::<
4455            3,
4456            0x1,
4457            1,
4458            0,
4459            bempenb::Pipe3Bempe,
4460            bempenb::Pipe3Bempe,
4461            Bempenb_SPEC,
4462            crate::common::RW,
4463        >::from_register(self, 0)
4464    }
4465
4466    #[doc = "BEMP Interrupt Enable for PIPE2"]
4467    #[inline(always)]
4468    pub fn pipe2bempe(
4469        self,
4470    ) -> crate::common::RegisterField<
4471        2,
4472        0x1,
4473        1,
4474        0,
4475        bempenb::Pipe2Bempe,
4476        bempenb::Pipe2Bempe,
4477        Bempenb_SPEC,
4478        crate::common::RW,
4479    > {
4480        crate::common::RegisterField::<
4481            2,
4482            0x1,
4483            1,
4484            0,
4485            bempenb::Pipe2Bempe,
4486            bempenb::Pipe2Bempe,
4487            Bempenb_SPEC,
4488            crate::common::RW,
4489        >::from_register(self, 0)
4490    }
4491
4492    #[doc = "BEMP Interrupt Enable for PIPE1"]
4493    #[inline(always)]
4494    pub fn pipe1bempe(
4495        self,
4496    ) -> crate::common::RegisterField<
4497        1,
4498        0x1,
4499        1,
4500        0,
4501        bempenb::Pipe1Bempe,
4502        bempenb::Pipe1Bempe,
4503        Bempenb_SPEC,
4504        crate::common::RW,
4505    > {
4506        crate::common::RegisterField::<
4507            1,
4508            0x1,
4509            1,
4510            0,
4511            bempenb::Pipe1Bempe,
4512            bempenb::Pipe1Bempe,
4513            Bempenb_SPEC,
4514            crate::common::RW,
4515        >::from_register(self, 0)
4516    }
4517
4518    #[doc = "BEMP Interrupt Enable for PIPE0"]
4519    #[inline(always)]
4520    pub fn pipe0bempe(
4521        self,
4522    ) -> crate::common::RegisterField<
4523        0,
4524        0x1,
4525        1,
4526        0,
4527        bempenb::Pipe0Bempe,
4528        bempenb::Pipe0Bempe,
4529        Bempenb_SPEC,
4530        crate::common::RW,
4531    > {
4532        crate::common::RegisterField::<
4533            0,
4534            0x1,
4535            1,
4536            0,
4537            bempenb::Pipe0Bempe,
4538            bempenb::Pipe0Bempe,
4539            Bempenb_SPEC,
4540            crate::common::RW,
4541        >::from_register(self, 0)
4542    }
4543}
4544impl ::core::default::Default for Bempenb {
4545    #[inline(always)]
4546    fn default() -> Bempenb {
4547        <crate::RegValueT<Bempenb_SPEC> as RegisterValue<_>>::new(0)
4548    }
4549}
4550pub mod bempenb {
4551
4552    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4553    pub struct Pipe9Bempe_SPEC;
4554    pub type Pipe9Bempe = crate::EnumBitfieldStruct<u8, Pipe9Bempe_SPEC>;
4555    impl Pipe9Bempe {
4556        #[doc = "Interrupt output disabled"]
4557        pub const _0: Self = Self::new(0);
4558
4559        #[doc = "Interrupt output enabled"]
4560        pub const _1: Self = Self::new(1);
4561    }
4562    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4563    pub struct Pipe8Bempe_SPEC;
4564    pub type Pipe8Bempe = crate::EnumBitfieldStruct<u8, Pipe8Bempe_SPEC>;
4565    impl Pipe8Bempe {
4566        #[doc = "Interrupt output disabled"]
4567        pub const _0: Self = Self::new(0);
4568
4569        #[doc = "Interrupt output enabled"]
4570        pub const _1: Self = Self::new(1);
4571    }
4572    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4573    pub struct Pipe7Bempe_SPEC;
4574    pub type Pipe7Bempe = crate::EnumBitfieldStruct<u8, Pipe7Bempe_SPEC>;
4575    impl Pipe7Bempe {
4576        #[doc = "Interrupt output disabled"]
4577        pub const _0: Self = Self::new(0);
4578
4579        #[doc = "Interrupt output enabled"]
4580        pub const _1: Self = Self::new(1);
4581    }
4582    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4583    pub struct Pipe6Bempe_SPEC;
4584    pub type Pipe6Bempe = crate::EnumBitfieldStruct<u8, Pipe6Bempe_SPEC>;
4585    impl Pipe6Bempe {
4586        #[doc = "Interrupt output disabled"]
4587        pub const _0: Self = Self::new(0);
4588
4589        #[doc = "Interrupt output enabled"]
4590        pub const _1: Self = Self::new(1);
4591    }
4592    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4593    pub struct Pipe5Bempe_SPEC;
4594    pub type Pipe5Bempe = crate::EnumBitfieldStruct<u8, Pipe5Bempe_SPEC>;
4595    impl Pipe5Bempe {
4596        #[doc = "Interrupt output disabled"]
4597        pub const _0: Self = Self::new(0);
4598
4599        #[doc = "Interrupt output enabled"]
4600        pub const _1: Self = Self::new(1);
4601    }
4602    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4603    pub struct Pipe4Bempe_SPEC;
4604    pub type Pipe4Bempe = crate::EnumBitfieldStruct<u8, Pipe4Bempe_SPEC>;
4605    impl Pipe4Bempe {
4606        #[doc = "Interrupt output disabled"]
4607        pub const _0: Self = Self::new(0);
4608
4609        #[doc = "Interrupt output enabled"]
4610        pub const _1: Self = Self::new(1);
4611    }
4612    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4613    pub struct Pipe3Bempe_SPEC;
4614    pub type Pipe3Bempe = crate::EnumBitfieldStruct<u8, Pipe3Bempe_SPEC>;
4615    impl Pipe3Bempe {
4616        #[doc = "Interrupt output disabled"]
4617        pub const _0: Self = Self::new(0);
4618
4619        #[doc = "Interrupt output enabled"]
4620        pub const _1: Self = Self::new(1);
4621    }
4622    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4623    pub struct Pipe2Bempe_SPEC;
4624    pub type Pipe2Bempe = crate::EnumBitfieldStruct<u8, Pipe2Bempe_SPEC>;
4625    impl Pipe2Bempe {
4626        #[doc = "Interrupt output disabled"]
4627        pub const _0: Self = Self::new(0);
4628
4629        #[doc = "Interrupt output enabled"]
4630        pub const _1: Self = Self::new(1);
4631    }
4632    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4633    pub struct Pipe1Bempe_SPEC;
4634    pub type Pipe1Bempe = crate::EnumBitfieldStruct<u8, Pipe1Bempe_SPEC>;
4635    impl Pipe1Bempe {
4636        #[doc = "Interrupt output disabled"]
4637        pub const _0: Self = Self::new(0);
4638
4639        #[doc = "Interrupt output enabled"]
4640        pub const _1: Self = Self::new(1);
4641    }
4642    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4643    pub struct Pipe0Bempe_SPEC;
4644    pub type Pipe0Bempe = crate::EnumBitfieldStruct<u8, Pipe0Bempe_SPEC>;
4645    impl Pipe0Bempe {
4646        #[doc = "Interrupt output disabled"]
4647        pub const _0: Self = Self::new(0);
4648
4649        #[doc = "Interrupt output enabled"]
4650        pub const _1: Self = Self::new(1);
4651    }
4652}
4653#[doc(hidden)]
4654#[derive(Copy, Clone, Eq, PartialEq)]
4655pub struct Sofcfg_SPEC;
4656impl crate::sealed::RegSpec for Sofcfg_SPEC {
4657    type DataType = u16;
4658}
4659
4660#[doc = "SOF Output Configuration Register"]
4661pub type Sofcfg = crate::RegValueT<Sofcfg_SPEC>;
4662
4663impl Sofcfg {
4664    #[doc = "Transaction-Enabled Time Select"]
4665    #[inline(always)]
4666    pub fn trnensel(
4667        self,
4668    ) -> crate::common::RegisterField<
4669        8,
4670        0x1,
4671        1,
4672        0,
4673        sofcfg::Trnensel,
4674        sofcfg::Trnensel,
4675        Sofcfg_SPEC,
4676        crate::common::RW,
4677    > {
4678        crate::common::RegisterField::<
4679            8,
4680            0x1,
4681            1,
4682            0,
4683            sofcfg::Trnensel,
4684            sofcfg::Trnensel,
4685            Sofcfg_SPEC,
4686            crate::common::RW,
4687        >::from_register(self, 0)
4688    }
4689
4690    #[doc = "BRDY Interrupt Status Clear Timing"]
4691    #[inline(always)]
4692    pub fn brdym(
4693        self,
4694    ) -> crate::common::RegisterField<
4695        6,
4696        0x1,
4697        1,
4698        0,
4699        sofcfg::Brdym,
4700        sofcfg::Brdym,
4701        Sofcfg_SPEC,
4702        crate::common::RW,
4703    > {
4704        crate::common::RegisterField::<
4705            6,
4706            0x1,
4707            1,
4708            0,
4709            sofcfg::Brdym,
4710            sofcfg::Brdym,
4711            Sofcfg_SPEC,
4712            crate::common::RW,
4713        >::from_register(self, 0)
4714    }
4715
4716    #[doc = "Edge Interrupt Output Status Monitor"]
4717    #[inline(always)]
4718    pub fn edgests(
4719        self,
4720    ) -> crate::common::RegisterField<
4721        4,
4722        0x1,
4723        1,
4724        0,
4725        sofcfg::Edgests,
4726        sofcfg::Edgests,
4727        Sofcfg_SPEC,
4728        crate::common::R,
4729    > {
4730        crate::common::RegisterField::<
4731            4,
4732            0x1,
4733            1,
4734            0,
4735            sofcfg::Edgests,
4736            sofcfg::Edgests,
4737            Sofcfg_SPEC,
4738            crate::common::R,
4739        >::from_register(self, 0)
4740    }
4741}
4742impl ::core::default::Default for Sofcfg {
4743    #[inline(always)]
4744    fn default() -> Sofcfg {
4745        <crate::RegValueT<Sofcfg_SPEC> as RegisterValue<_>>::new(0)
4746    }
4747}
4748pub mod sofcfg {
4749
4750    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4751    pub struct Trnensel_SPEC;
4752    pub type Trnensel = crate::EnumBitfieldStruct<u8, Trnensel_SPEC>;
4753    impl Trnensel {
4754        #[doc = "For non-low-speed communication"]
4755        pub const _0: Self = Self::new(0);
4756
4757        #[doc = "For low-speed communication"]
4758        pub const _1: Self = Self::new(1);
4759    }
4760    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4761    pub struct Brdym_SPEC;
4762    pub type Brdym = crate::EnumBitfieldStruct<u8, Brdym_SPEC>;
4763    impl Brdym {
4764        #[doc = "Software clears the status."]
4765        pub const _0: Self = Self::new(0);
4766
4767        #[doc = "The USB clears the status when data has been read from the FIFO buffer or data has been written to the FIFO buffer."]
4768        pub const _1: Self = Self::new(1);
4769    }
4770    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4771    pub struct Edgests_SPEC;
4772    pub type Edgests = crate::EnumBitfieldStruct<u8, Edgests_SPEC>;
4773    impl Edgests {
4774        #[doc = "before stopping the clock supply to the USB module"]
4775        pub const _0: Self = Self::new(0);
4776
4777        #[doc = "the edge interrupt output signal is in the middle of the edge processing"]
4778        pub const _1: Self = Self::new(1);
4779    }
4780}
4781#[doc(hidden)]
4782#[derive(Copy, Clone, Eq, PartialEq)]
4783pub struct Intsts0_SPEC;
4784impl crate::sealed::RegSpec for Intsts0_SPEC {
4785    type DataType = u16;
4786}
4787
4788#[doc = "Interrupt Status Register 0"]
4789pub type Intsts0 = crate::RegValueT<Intsts0_SPEC>;
4790
4791impl Intsts0 {
4792    #[doc = "VBUS Interrupt Status"]
4793    #[inline(always)]
4794    pub fn vbint(
4795        self,
4796    ) -> crate::common::RegisterField<
4797        15,
4798        0x1,
4799        1,
4800        0,
4801        intsts0::Vbint,
4802        intsts0::Vbint,
4803        Intsts0_SPEC,
4804        crate::common::RW,
4805    > {
4806        crate::common::RegisterField::<
4807            15,
4808            0x1,
4809            1,
4810            0,
4811            intsts0::Vbint,
4812            intsts0::Vbint,
4813            Intsts0_SPEC,
4814            crate::common::RW,
4815        >::from_register(self, 0)
4816    }
4817
4818    #[doc = "Resume Interrupt Status"]
4819    #[inline(always)]
4820    pub fn resm(
4821        self,
4822    ) -> crate::common::RegisterField<
4823        14,
4824        0x1,
4825        1,
4826        0,
4827        intsts0::Resm,
4828        intsts0::Resm,
4829        Intsts0_SPEC,
4830        crate::common::RW,
4831    > {
4832        crate::common::RegisterField::<
4833            14,
4834            0x1,
4835            1,
4836            0,
4837            intsts0::Resm,
4838            intsts0::Resm,
4839            Intsts0_SPEC,
4840            crate::common::RW,
4841        >::from_register(self, 0)
4842    }
4843
4844    #[doc = "Frame Number Refresh Interrupt Status"]
4845    #[inline(always)]
4846    pub fn sofr(
4847        self,
4848    ) -> crate::common::RegisterField<
4849        13,
4850        0x1,
4851        1,
4852        0,
4853        intsts0::Sofr,
4854        intsts0::Sofr,
4855        Intsts0_SPEC,
4856        crate::common::RW,
4857    > {
4858        crate::common::RegisterField::<
4859            13,
4860            0x1,
4861            1,
4862            0,
4863            intsts0::Sofr,
4864            intsts0::Sofr,
4865            Intsts0_SPEC,
4866            crate::common::RW,
4867        >::from_register(self, 0)
4868    }
4869
4870    #[doc = "Device State Transition Interrupt Status"]
4871    #[inline(always)]
4872    pub fn dvst(
4873        self,
4874    ) -> crate::common::RegisterField<
4875        12,
4876        0x1,
4877        1,
4878        0,
4879        intsts0::Dvst,
4880        intsts0::Dvst,
4881        Intsts0_SPEC,
4882        crate::common::RW,
4883    > {
4884        crate::common::RegisterField::<
4885            12,
4886            0x1,
4887            1,
4888            0,
4889            intsts0::Dvst,
4890            intsts0::Dvst,
4891            Intsts0_SPEC,
4892            crate::common::RW,
4893        >::from_register(self, 0)
4894    }
4895
4896    #[doc = "Control Transfer Stage Transition Interrupt Status"]
4897    #[inline(always)]
4898    pub fn ctrt(
4899        self,
4900    ) -> crate::common::RegisterField<
4901        11,
4902        0x1,
4903        1,
4904        0,
4905        intsts0::Ctrt,
4906        intsts0::Ctrt,
4907        Intsts0_SPEC,
4908        crate::common::RW,
4909    > {
4910        crate::common::RegisterField::<
4911            11,
4912            0x1,
4913            1,
4914            0,
4915            intsts0::Ctrt,
4916            intsts0::Ctrt,
4917            Intsts0_SPEC,
4918            crate::common::RW,
4919        >::from_register(self, 0)
4920    }
4921
4922    #[doc = "Buffer Empty Interrupt Status"]
4923    #[inline(always)]
4924    pub fn bemp(
4925        self,
4926    ) -> crate::common::RegisterField<
4927        10,
4928        0x1,
4929        1,
4930        0,
4931        intsts0::Bemp,
4932        intsts0::Bemp,
4933        Intsts0_SPEC,
4934        crate::common::R,
4935    > {
4936        crate::common::RegisterField::<
4937            10,
4938            0x1,
4939            1,
4940            0,
4941            intsts0::Bemp,
4942            intsts0::Bemp,
4943            Intsts0_SPEC,
4944            crate::common::R,
4945        >::from_register(self, 0)
4946    }
4947
4948    #[doc = "Buffer Not Ready Interrupt Status"]
4949    #[inline(always)]
4950    pub fn nrdy(
4951        self,
4952    ) -> crate::common::RegisterField<
4953        9,
4954        0x1,
4955        1,
4956        0,
4957        intsts0::Nrdy,
4958        intsts0::Nrdy,
4959        Intsts0_SPEC,
4960        crate::common::R,
4961    > {
4962        crate::common::RegisterField::<
4963            9,
4964            0x1,
4965            1,
4966            0,
4967            intsts0::Nrdy,
4968            intsts0::Nrdy,
4969            Intsts0_SPEC,
4970            crate::common::R,
4971        >::from_register(self, 0)
4972    }
4973
4974    #[doc = "Buffer Ready Interrupt Status"]
4975    #[inline(always)]
4976    pub fn brdy(
4977        self,
4978    ) -> crate::common::RegisterField<
4979        8,
4980        0x1,
4981        1,
4982        0,
4983        intsts0::Brdy,
4984        intsts0::Brdy,
4985        Intsts0_SPEC,
4986        crate::common::R,
4987    > {
4988        crate::common::RegisterField::<
4989            8,
4990            0x1,
4991            1,
4992            0,
4993            intsts0::Brdy,
4994            intsts0::Brdy,
4995            Intsts0_SPEC,
4996            crate::common::R,
4997        >::from_register(self, 0)
4998    }
4999
5000    #[doc = "VBUS Input Status"]
5001    #[inline(always)]
5002    pub fn vbsts(
5003        self,
5004    ) -> crate::common::RegisterField<
5005        7,
5006        0x1,
5007        1,
5008        0,
5009        intsts0::Vbsts,
5010        intsts0::Vbsts,
5011        Intsts0_SPEC,
5012        crate::common::R,
5013    > {
5014        crate::common::RegisterField::<
5015            7,
5016            0x1,
5017            1,
5018            0,
5019            intsts0::Vbsts,
5020            intsts0::Vbsts,
5021            Intsts0_SPEC,
5022            crate::common::R,
5023        >::from_register(self, 0)
5024    }
5025
5026    #[doc = "Device State"]
5027    #[inline(always)]
5028    pub fn dvsq(
5029        self,
5030    ) -> crate::common::RegisterField<
5031        4,
5032        0x7,
5033        1,
5034        0,
5035        intsts0::Dvsq,
5036        intsts0::Dvsq,
5037        Intsts0_SPEC,
5038        crate::common::R,
5039    > {
5040        crate::common::RegisterField::<
5041            4,
5042            0x7,
5043            1,
5044            0,
5045            intsts0::Dvsq,
5046            intsts0::Dvsq,
5047            Intsts0_SPEC,
5048            crate::common::R,
5049        >::from_register(self, 0)
5050    }
5051
5052    #[doc = "USB Request Reception"]
5053    #[inline(always)]
5054    pub fn valid(
5055        self,
5056    ) -> crate::common::RegisterField<
5057        3,
5058        0x1,
5059        1,
5060        0,
5061        intsts0::Valid,
5062        intsts0::Valid,
5063        Intsts0_SPEC,
5064        crate::common::RW,
5065    > {
5066        crate::common::RegisterField::<
5067            3,
5068            0x1,
5069            1,
5070            0,
5071            intsts0::Valid,
5072            intsts0::Valid,
5073            Intsts0_SPEC,
5074            crate::common::RW,
5075        >::from_register(self, 0)
5076    }
5077
5078    #[doc = "Control Transfer Stage"]
5079    #[inline(always)]
5080    pub fn ctsq(
5081        self,
5082    ) -> crate::common::RegisterField<
5083        0,
5084        0x7,
5085        1,
5086        0,
5087        intsts0::Ctsq,
5088        intsts0::Ctsq,
5089        Intsts0_SPEC,
5090        crate::common::R,
5091    > {
5092        crate::common::RegisterField::<
5093            0,
5094            0x7,
5095            1,
5096            0,
5097            intsts0::Ctsq,
5098            intsts0::Ctsq,
5099            Intsts0_SPEC,
5100            crate::common::R,
5101        >::from_register(self, 0)
5102    }
5103}
5104impl ::core::default::Default for Intsts0 {
5105    #[inline(always)]
5106    fn default() -> Intsts0 {
5107        <crate::RegValueT<Intsts0_SPEC> as RegisterValue<_>>::new(0)
5108    }
5109}
5110pub mod intsts0 {
5111
5112    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5113    pub struct Vbint_SPEC;
5114    pub type Vbint = crate::EnumBitfieldStruct<u8, Vbint_SPEC>;
5115    impl Vbint {
5116        #[doc = "VBUS interrupts are not generated."]
5117        pub const _0: Self = Self::new(0);
5118
5119        #[doc = "VBUS interrupts are generated."]
5120        pub const _1: Self = Self::new(1);
5121    }
5122    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5123    pub struct Resm_SPEC;
5124    pub type Resm = crate::EnumBitfieldStruct<u8, Resm_SPEC>;
5125    impl Resm {
5126        #[doc = "Resume interrupts are not generated."]
5127        pub const _0: Self = Self::new(0);
5128
5129        #[doc = "Resume interrupts are generated."]
5130        pub const _1: Self = Self::new(1);
5131    }
5132    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5133    pub struct Sofr_SPEC;
5134    pub type Sofr = crate::EnumBitfieldStruct<u8, Sofr_SPEC>;
5135    impl Sofr {
5136        #[doc = "SOF interrupts are not generated."]
5137        pub const _0: Self = Self::new(0);
5138
5139        #[doc = "SOF interrupts are generated."]
5140        pub const _1: Self = Self::new(1);
5141    }
5142    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5143    pub struct Dvst_SPEC;
5144    pub type Dvst = crate::EnumBitfieldStruct<u8, Dvst_SPEC>;
5145    impl Dvst {
5146        #[doc = "Device state transition interrupts are not generated."]
5147        pub const _0: Self = Self::new(0);
5148
5149        #[doc = "Device state transition interrupts are generated."]
5150        pub const _1: Self = Self::new(1);
5151    }
5152    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5153    pub struct Ctrt_SPEC;
5154    pub type Ctrt = crate::EnumBitfieldStruct<u8, Ctrt_SPEC>;
5155    impl Ctrt {
5156        #[doc = "Control transfer stage transition interrupts are not generated."]
5157        pub const _0: Self = Self::new(0);
5158
5159        #[doc = "Control transfer stage transition interrupts are generated."]
5160        pub const _1: Self = Self::new(1);
5161    }
5162    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5163    pub struct Bemp_SPEC;
5164    pub type Bemp = crate::EnumBitfieldStruct<u8, Bemp_SPEC>;
5165    impl Bemp {
5166        #[doc = "BEMP interrupts are not generated."]
5167        pub const _0: Self = Self::new(0);
5168
5169        #[doc = "BEMP interrupts are generated."]
5170        pub const _1: Self = Self::new(1);
5171    }
5172    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5173    pub struct Nrdy_SPEC;
5174    pub type Nrdy = crate::EnumBitfieldStruct<u8, Nrdy_SPEC>;
5175    impl Nrdy {
5176        #[doc = "NRDY interrupts are not generated."]
5177        pub const _0: Self = Self::new(0);
5178
5179        #[doc = "NRDY interrupts are generated."]
5180        pub const _1: Self = Self::new(1);
5181    }
5182    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5183    pub struct Brdy_SPEC;
5184    pub type Brdy = crate::EnumBitfieldStruct<u8, Brdy_SPEC>;
5185    impl Brdy {
5186        #[doc = "BRDY interrupts are not generated."]
5187        pub const _0: Self = Self::new(0);
5188
5189        #[doc = "BRDY interrupts are generated."]
5190        pub const _1: Self = Self::new(1);
5191    }
5192    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5193    pub struct Vbsts_SPEC;
5194    pub type Vbsts = crate::EnumBitfieldStruct<u8, Vbsts_SPEC>;
5195    impl Vbsts {
5196        #[doc = "USB0_VBUS pin is low."]
5197        pub const _0: Self = Self::new(0);
5198
5199        #[doc = "USB0_VBUS pin is high."]
5200        pub const _1: Self = Self::new(1);
5201    }
5202    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5203    pub struct Dvsq_SPEC;
5204    pub type Dvsq = crate::EnumBitfieldStruct<u8, Dvsq_SPEC>;
5205    impl Dvsq {
5206        #[doc = "Powered state"]
5207        pub const _000: Self = Self::new(0);
5208
5209        #[doc = "Default state"]
5210        pub const _001: Self = Self::new(1);
5211
5212        #[doc = "Address state"]
5213        pub const _010: Self = Self::new(2);
5214
5215        #[doc = "Configured state"]
5216        pub const _011: Self = Self::new(3);
5217    }
5218    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5219    pub struct Valid_SPEC;
5220    pub type Valid = crate::EnumBitfieldStruct<u8, Valid_SPEC>;
5221    impl Valid {
5222        #[doc = "Setup packet is not received"]
5223        pub const _0: Self = Self::new(0);
5224
5225        #[doc = "Setup packet is received"]
5226        pub const _1: Self = Self::new(1);
5227    }
5228    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5229    pub struct Ctsq_SPEC;
5230    pub type Ctsq = crate::EnumBitfieldStruct<u8, Ctsq_SPEC>;
5231    impl Ctsq {
5232        #[doc = "Idle or setup stage"]
5233        pub const _000: Self = Self::new(0);
5234
5235        #[doc = "Control read data stage"]
5236        pub const _001: Self = Self::new(1);
5237
5238        #[doc = "Control read status stage"]
5239        pub const _010: Self = Self::new(2);
5240
5241        #[doc = "Control write data stage"]
5242        pub const _011: Self = Self::new(3);
5243
5244        #[doc = "Control write status stage"]
5245        pub const _100: Self = Self::new(4);
5246
5247        #[doc = "Control write (no data) status stage"]
5248        pub const _101: Self = Self::new(5);
5249
5250        #[doc = "Control transfer sequence error"]
5251        pub const _110: Self = Self::new(6);
5252    }
5253}
5254#[doc(hidden)]
5255#[derive(Copy, Clone, Eq, PartialEq)]
5256pub struct Intsts1_SPEC;
5257impl crate::sealed::RegSpec for Intsts1_SPEC {
5258    type DataType = u16;
5259}
5260
5261#[doc = "Interrupt Status Register 1"]
5262pub type Intsts1 = crate::RegValueT<Intsts1_SPEC>;
5263
5264impl Intsts1 {
5265    #[doc = "Overcurrent Input Change Interrupt Status"]
5266    #[inline(always)]
5267    pub fn ovrcr(
5268        self,
5269    ) -> crate::common::RegisterField<
5270        15,
5271        0x1,
5272        1,
5273        0,
5274        intsts1::Ovrcr,
5275        intsts1::Ovrcr,
5276        Intsts1_SPEC,
5277        crate::common::RW,
5278    > {
5279        crate::common::RegisterField::<
5280            15,
5281            0x1,
5282            1,
5283            0,
5284            intsts1::Ovrcr,
5285            intsts1::Ovrcr,
5286            Intsts1_SPEC,
5287            crate::common::RW,
5288        >::from_register(self, 0)
5289    }
5290
5291    #[doc = "USB Bus Change Interrupt Status"]
5292    #[inline(always)]
5293    pub fn bchg(
5294        self,
5295    ) -> crate::common::RegisterField<
5296        14,
5297        0x1,
5298        1,
5299        0,
5300        intsts1::Bchg,
5301        intsts1::Bchg,
5302        Intsts1_SPEC,
5303        crate::common::RW,
5304    > {
5305        crate::common::RegisterField::<
5306            14,
5307            0x1,
5308            1,
5309            0,
5310            intsts1::Bchg,
5311            intsts1::Bchg,
5312            Intsts1_SPEC,
5313            crate::common::RW,
5314        >::from_register(self, 0)
5315    }
5316
5317    #[doc = "USB Disconnection Detection Interrupt Status"]
5318    #[inline(always)]
5319    pub fn dtch(
5320        self,
5321    ) -> crate::common::RegisterField<
5322        12,
5323        0x1,
5324        1,
5325        0,
5326        intsts1::Dtch,
5327        intsts1::Dtch,
5328        Intsts1_SPEC,
5329        crate::common::RW,
5330    > {
5331        crate::common::RegisterField::<
5332            12,
5333            0x1,
5334            1,
5335            0,
5336            intsts1::Dtch,
5337            intsts1::Dtch,
5338            Intsts1_SPEC,
5339            crate::common::RW,
5340        >::from_register(self, 0)
5341    }
5342
5343    #[doc = "ATTCH Interrupt Status"]
5344    #[inline(always)]
5345    pub fn attch(
5346        self,
5347    ) -> crate::common::RegisterField<
5348        11,
5349        0x1,
5350        1,
5351        0,
5352        intsts1::Attch,
5353        intsts1::Attch,
5354        Intsts1_SPEC,
5355        crate::common::RW,
5356    > {
5357        crate::common::RegisterField::<
5358            11,
5359            0x1,
5360            1,
5361            0,
5362            intsts1::Attch,
5363            intsts1::Attch,
5364            Intsts1_SPEC,
5365            crate::common::RW,
5366        >::from_register(self, 0)
5367    }
5368
5369    #[doc = "EOF Error Detection Interrupt Status"]
5370    #[inline(always)]
5371    pub fn eoferr(
5372        self,
5373    ) -> crate::common::RegisterField<
5374        6,
5375        0x1,
5376        1,
5377        0,
5378        intsts1::Eoferr,
5379        intsts1::Eoferr,
5380        Intsts1_SPEC,
5381        crate::common::RW,
5382    > {
5383        crate::common::RegisterField::<
5384            6,
5385            0x1,
5386            1,
5387            0,
5388            intsts1::Eoferr,
5389            intsts1::Eoferr,
5390            Intsts1_SPEC,
5391            crate::common::RW,
5392        >::from_register(self, 0)
5393    }
5394
5395    #[doc = "Setup Transaction Error Interrupt Status"]
5396    #[inline(always)]
5397    pub fn sign(
5398        self,
5399    ) -> crate::common::RegisterField<
5400        5,
5401        0x1,
5402        1,
5403        0,
5404        intsts1::Sign,
5405        intsts1::Sign,
5406        Intsts1_SPEC,
5407        crate::common::RW,
5408    > {
5409        crate::common::RegisterField::<
5410            5,
5411            0x1,
5412            1,
5413            0,
5414            intsts1::Sign,
5415            intsts1::Sign,
5416            Intsts1_SPEC,
5417            crate::common::RW,
5418        >::from_register(self, 0)
5419    }
5420
5421    #[doc = "Setup Transaction Normal Response Interrupt Status"]
5422    #[inline(always)]
5423    pub fn sack(
5424        self,
5425    ) -> crate::common::RegisterField<
5426        4,
5427        0x1,
5428        1,
5429        0,
5430        intsts1::Sack,
5431        intsts1::Sack,
5432        Intsts1_SPEC,
5433        crate::common::RW,
5434    > {
5435        crate::common::RegisterField::<
5436            4,
5437            0x1,
5438            1,
5439            0,
5440            intsts1::Sack,
5441            intsts1::Sack,
5442            Intsts1_SPEC,
5443            crate::common::RW,
5444        >::from_register(self, 0)
5445    }
5446}
5447impl ::core::default::Default for Intsts1 {
5448    #[inline(always)]
5449    fn default() -> Intsts1 {
5450        <crate::RegValueT<Intsts1_SPEC> as RegisterValue<_>>::new(0)
5451    }
5452}
5453pub mod intsts1 {
5454
5455    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5456    pub struct Ovrcr_SPEC;
5457    pub type Ovrcr = crate::EnumBitfieldStruct<u8, Ovrcr_SPEC>;
5458    impl Ovrcr {
5459        #[doc = "OVRCR interrupts are not generated."]
5460        pub const _0: Self = Self::new(0);
5461
5462        #[doc = "OVRCR interrupts are generated."]
5463        pub const _1: Self = Self::new(1);
5464    }
5465    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5466    pub struct Bchg_SPEC;
5467    pub type Bchg = crate::EnumBitfieldStruct<u8, Bchg_SPEC>;
5468    impl Bchg {
5469        #[doc = "BCHG interrupts are not generated."]
5470        pub const _0: Self = Self::new(0);
5471
5472        #[doc = "BCHG interrupts are generated."]
5473        pub const _1: Self = Self::new(1);
5474    }
5475    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5476    pub struct Dtch_SPEC;
5477    pub type Dtch = crate::EnumBitfieldStruct<u8, Dtch_SPEC>;
5478    impl Dtch {
5479        #[doc = "DTCH interrupts are not generated."]
5480        pub const _0: Self = Self::new(0);
5481
5482        #[doc = "DTCH interrupts are generated."]
5483        pub const _1: Self = Self::new(1);
5484    }
5485    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5486    pub struct Attch_SPEC;
5487    pub type Attch = crate::EnumBitfieldStruct<u8, Attch_SPEC>;
5488    impl Attch {
5489        #[doc = "ATTCH interrupts are not generated."]
5490        pub const _0: Self = Self::new(0);
5491
5492        #[doc = "ATTCH interrupts are generated."]
5493        pub const _1: Self = Self::new(1);
5494    }
5495    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5496    pub struct Eoferr_SPEC;
5497    pub type Eoferr = crate::EnumBitfieldStruct<u8, Eoferr_SPEC>;
5498    impl Eoferr {
5499        #[doc = "EOFERR interrupts are not generated."]
5500        pub const _0: Self = Self::new(0);
5501
5502        #[doc = "EOFERR interrupts are generated."]
5503        pub const _1: Self = Self::new(1);
5504    }
5505    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5506    pub struct Sign_SPEC;
5507    pub type Sign = crate::EnumBitfieldStruct<u8, Sign_SPEC>;
5508    impl Sign {
5509        #[doc = "SIGN interrupts are not generated."]
5510        pub const _0: Self = Self::new(0);
5511
5512        #[doc = "SIGN interrupts are generated."]
5513        pub const _1: Self = Self::new(1);
5514    }
5515    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5516    pub struct Sack_SPEC;
5517    pub type Sack = crate::EnumBitfieldStruct<u8, Sack_SPEC>;
5518    impl Sack {
5519        #[doc = "SACK interrupts are not generated."]
5520        pub const _0: Self = Self::new(0);
5521
5522        #[doc = "SACK interrupts are generated."]
5523        pub const _1: Self = Self::new(1);
5524    }
5525}
5526#[doc(hidden)]
5527#[derive(Copy, Clone, Eq, PartialEq)]
5528pub struct Brdysts_SPEC;
5529impl crate::sealed::RegSpec for Brdysts_SPEC {
5530    type DataType = u16;
5531}
5532
5533#[doc = "BRDY Interrupt Status Register"]
5534pub type Brdysts = crate::RegValueT<Brdysts_SPEC>;
5535
5536impl Brdysts {
5537    #[doc = "BRDY Interrupt Status for PIPE9"]
5538    #[inline(always)]
5539    pub fn pipe9brdy(
5540        self,
5541    ) -> crate::common::RegisterField<
5542        9,
5543        0x1,
5544        1,
5545        0,
5546        brdysts::Pipe9Brdy,
5547        brdysts::Pipe9Brdy,
5548        Brdysts_SPEC,
5549        crate::common::RW,
5550    > {
5551        crate::common::RegisterField::<
5552            9,
5553            0x1,
5554            1,
5555            0,
5556            brdysts::Pipe9Brdy,
5557            brdysts::Pipe9Brdy,
5558            Brdysts_SPEC,
5559            crate::common::RW,
5560        >::from_register(self, 0)
5561    }
5562
5563    #[doc = "BRDY Interrupt Status for PIPE8"]
5564    #[inline(always)]
5565    pub fn pipe8brdy(
5566        self,
5567    ) -> crate::common::RegisterField<
5568        8,
5569        0x1,
5570        1,
5571        0,
5572        brdysts::Pipe8Brdy,
5573        brdysts::Pipe8Brdy,
5574        Brdysts_SPEC,
5575        crate::common::RW,
5576    > {
5577        crate::common::RegisterField::<
5578            8,
5579            0x1,
5580            1,
5581            0,
5582            brdysts::Pipe8Brdy,
5583            brdysts::Pipe8Brdy,
5584            Brdysts_SPEC,
5585            crate::common::RW,
5586        >::from_register(self, 0)
5587    }
5588
5589    #[doc = "BRDY Interrupt Status for PIPE7"]
5590    #[inline(always)]
5591    pub fn pipe7brdy(
5592        self,
5593    ) -> crate::common::RegisterField<
5594        7,
5595        0x1,
5596        1,
5597        0,
5598        brdysts::Pipe7Brdy,
5599        brdysts::Pipe7Brdy,
5600        Brdysts_SPEC,
5601        crate::common::RW,
5602    > {
5603        crate::common::RegisterField::<
5604            7,
5605            0x1,
5606            1,
5607            0,
5608            brdysts::Pipe7Brdy,
5609            brdysts::Pipe7Brdy,
5610            Brdysts_SPEC,
5611            crate::common::RW,
5612        >::from_register(self, 0)
5613    }
5614
5615    #[doc = "BRDY Interrupt Status for PIPE6"]
5616    #[inline(always)]
5617    pub fn pipe6brdy(
5618        self,
5619    ) -> crate::common::RegisterField<
5620        6,
5621        0x1,
5622        1,
5623        0,
5624        brdysts::Pipe6Brdy,
5625        brdysts::Pipe6Brdy,
5626        Brdysts_SPEC,
5627        crate::common::RW,
5628    > {
5629        crate::common::RegisterField::<
5630            6,
5631            0x1,
5632            1,
5633            0,
5634            brdysts::Pipe6Brdy,
5635            brdysts::Pipe6Brdy,
5636            Brdysts_SPEC,
5637            crate::common::RW,
5638        >::from_register(self, 0)
5639    }
5640
5641    #[doc = "BRDY Interrupt Status for PIPE5"]
5642    #[inline(always)]
5643    pub fn pipe5brdy(
5644        self,
5645    ) -> crate::common::RegisterField<
5646        5,
5647        0x1,
5648        1,
5649        0,
5650        brdysts::Pipe5Brdy,
5651        brdysts::Pipe5Brdy,
5652        Brdysts_SPEC,
5653        crate::common::RW,
5654    > {
5655        crate::common::RegisterField::<
5656            5,
5657            0x1,
5658            1,
5659            0,
5660            brdysts::Pipe5Brdy,
5661            brdysts::Pipe5Brdy,
5662            Brdysts_SPEC,
5663            crate::common::RW,
5664        >::from_register(self, 0)
5665    }
5666
5667    #[doc = "BRDY Interrupt Status for PIPE4"]
5668    #[inline(always)]
5669    pub fn pipe4brdy(
5670        self,
5671    ) -> crate::common::RegisterField<
5672        4,
5673        0x1,
5674        1,
5675        0,
5676        brdysts::Pipe4Brdy,
5677        brdysts::Pipe4Brdy,
5678        Brdysts_SPEC,
5679        crate::common::RW,
5680    > {
5681        crate::common::RegisterField::<
5682            4,
5683            0x1,
5684            1,
5685            0,
5686            brdysts::Pipe4Brdy,
5687            brdysts::Pipe4Brdy,
5688            Brdysts_SPEC,
5689            crate::common::RW,
5690        >::from_register(self, 0)
5691    }
5692
5693    #[doc = "BRDY Interrupt Status for PIPE3"]
5694    #[inline(always)]
5695    pub fn pipe3brdy(
5696        self,
5697    ) -> crate::common::RegisterField<
5698        3,
5699        0x1,
5700        1,
5701        0,
5702        brdysts::Pipe3Brdy,
5703        brdysts::Pipe3Brdy,
5704        Brdysts_SPEC,
5705        crate::common::RW,
5706    > {
5707        crate::common::RegisterField::<
5708            3,
5709            0x1,
5710            1,
5711            0,
5712            brdysts::Pipe3Brdy,
5713            brdysts::Pipe3Brdy,
5714            Brdysts_SPEC,
5715            crate::common::RW,
5716        >::from_register(self, 0)
5717    }
5718
5719    #[doc = "BRDY Interrupt Status for PIPE2"]
5720    #[inline(always)]
5721    pub fn pipe2brdy(
5722        self,
5723    ) -> crate::common::RegisterField<
5724        2,
5725        0x1,
5726        1,
5727        0,
5728        brdysts::Pipe2Brdy,
5729        brdysts::Pipe2Brdy,
5730        Brdysts_SPEC,
5731        crate::common::RW,
5732    > {
5733        crate::common::RegisterField::<
5734            2,
5735            0x1,
5736            1,
5737            0,
5738            brdysts::Pipe2Brdy,
5739            brdysts::Pipe2Brdy,
5740            Brdysts_SPEC,
5741            crate::common::RW,
5742        >::from_register(self, 0)
5743    }
5744
5745    #[doc = "BRDY Interrupt Status for PIPE1"]
5746    #[inline(always)]
5747    pub fn pipe1brdy(
5748        self,
5749    ) -> crate::common::RegisterField<
5750        1,
5751        0x1,
5752        1,
5753        0,
5754        brdysts::Pipe1Brdy,
5755        brdysts::Pipe1Brdy,
5756        Brdysts_SPEC,
5757        crate::common::RW,
5758    > {
5759        crate::common::RegisterField::<
5760            1,
5761            0x1,
5762            1,
5763            0,
5764            brdysts::Pipe1Brdy,
5765            brdysts::Pipe1Brdy,
5766            Brdysts_SPEC,
5767            crate::common::RW,
5768        >::from_register(self, 0)
5769    }
5770
5771    #[doc = "BRDY Interrupt Status for PIPE0"]
5772    #[inline(always)]
5773    pub fn pipe0brdy(
5774        self,
5775    ) -> crate::common::RegisterField<
5776        0,
5777        0x1,
5778        1,
5779        0,
5780        brdysts::Pipe0Brdy,
5781        brdysts::Pipe0Brdy,
5782        Brdysts_SPEC,
5783        crate::common::RW,
5784    > {
5785        crate::common::RegisterField::<
5786            0,
5787            0x1,
5788            1,
5789            0,
5790            brdysts::Pipe0Brdy,
5791            brdysts::Pipe0Brdy,
5792            Brdysts_SPEC,
5793            crate::common::RW,
5794        >::from_register(self, 0)
5795    }
5796}
5797impl ::core::default::Default for Brdysts {
5798    #[inline(always)]
5799    fn default() -> Brdysts {
5800        <crate::RegValueT<Brdysts_SPEC> as RegisterValue<_>>::new(0)
5801    }
5802}
5803pub mod brdysts {
5804
5805    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5806    pub struct Pipe9Brdy_SPEC;
5807    pub type Pipe9Brdy = crate::EnumBitfieldStruct<u8, Pipe9Brdy_SPEC>;
5808    impl Pipe9Brdy {
5809        #[doc = "Interrupts are not generated."]
5810        pub const _0: Self = Self::new(0);
5811
5812        #[doc = "Interrupts are generated."]
5813        pub const _1: Self = Self::new(1);
5814    }
5815    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5816    pub struct Pipe8Brdy_SPEC;
5817    pub type Pipe8Brdy = crate::EnumBitfieldStruct<u8, Pipe8Brdy_SPEC>;
5818    impl Pipe8Brdy {
5819        #[doc = "Interrupts are not generated."]
5820        pub const _0: Self = Self::new(0);
5821
5822        #[doc = "Interrupts are generated."]
5823        pub const _1: Self = Self::new(1);
5824    }
5825    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5826    pub struct Pipe7Brdy_SPEC;
5827    pub type Pipe7Brdy = crate::EnumBitfieldStruct<u8, Pipe7Brdy_SPEC>;
5828    impl Pipe7Brdy {
5829        #[doc = "Interrupts are not generated."]
5830        pub const _0: Self = Self::new(0);
5831
5832        #[doc = "Interrupts are generated."]
5833        pub const _1: Self = Self::new(1);
5834    }
5835    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5836    pub struct Pipe6Brdy_SPEC;
5837    pub type Pipe6Brdy = crate::EnumBitfieldStruct<u8, Pipe6Brdy_SPEC>;
5838    impl Pipe6Brdy {
5839        #[doc = "Interrupts are not generated."]
5840        pub const _0: Self = Self::new(0);
5841
5842        #[doc = "Interrupts are generated."]
5843        pub const _1: Self = Self::new(1);
5844    }
5845    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5846    pub struct Pipe5Brdy_SPEC;
5847    pub type Pipe5Brdy = crate::EnumBitfieldStruct<u8, Pipe5Brdy_SPEC>;
5848    impl Pipe5Brdy {
5849        #[doc = "Interrupts are not generated."]
5850        pub const _0: Self = Self::new(0);
5851
5852        #[doc = "Interrupts are generated."]
5853        pub const _1: Self = Self::new(1);
5854    }
5855    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5856    pub struct Pipe4Brdy_SPEC;
5857    pub type Pipe4Brdy = crate::EnumBitfieldStruct<u8, Pipe4Brdy_SPEC>;
5858    impl Pipe4Brdy {
5859        #[doc = "Interrupts are not generated."]
5860        pub const _0: Self = Self::new(0);
5861
5862        #[doc = "Interrupts are generated."]
5863        pub const _1: Self = Self::new(1);
5864    }
5865    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5866    pub struct Pipe3Brdy_SPEC;
5867    pub type Pipe3Brdy = crate::EnumBitfieldStruct<u8, Pipe3Brdy_SPEC>;
5868    impl Pipe3Brdy {
5869        #[doc = "Interrupts are not generated."]
5870        pub const _0: Self = Self::new(0);
5871
5872        #[doc = "Interrupts are generated."]
5873        pub const _1: Self = Self::new(1);
5874    }
5875    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5876    pub struct Pipe2Brdy_SPEC;
5877    pub type Pipe2Brdy = crate::EnumBitfieldStruct<u8, Pipe2Brdy_SPEC>;
5878    impl Pipe2Brdy {
5879        #[doc = "Interrupts are not generated."]
5880        pub const _0: Self = Self::new(0);
5881
5882        #[doc = "Interrupts are generated."]
5883        pub const _1: Self = Self::new(1);
5884    }
5885    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5886    pub struct Pipe1Brdy_SPEC;
5887    pub type Pipe1Brdy = crate::EnumBitfieldStruct<u8, Pipe1Brdy_SPEC>;
5888    impl Pipe1Brdy {
5889        #[doc = "Interrupts are not generated."]
5890        pub const _0: Self = Self::new(0);
5891
5892        #[doc = "Interrupts are generated."]
5893        pub const _1: Self = Self::new(1);
5894    }
5895    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5896    pub struct Pipe0Brdy_SPEC;
5897    pub type Pipe0Brdy = crate::EnumBitfieldStruct<u8, Pipe0Brdy_SPEC>;
5898    impl Pipe0Brdy {
5899        #[doc = "Interrupts are not generated."]
5900        pub const _0: Self = Self::new(0);
5901
5902        #[doc = "Interrupts are generated."]
5903        pub const _1: Self = Self::new(1);
5904    }
5905}
5906#[doc(hidden)]
5907#[derive(Copy, Clone, Eq, PartialEq)]
5908pub struct Nrdysts_SPEC;
5909impl crate::sealed::RegSpec for Nrdysts_SPEC {
5910    type DataType = u16;
5911}
5912
5913#[doc = "NRDY Interrupt Status Register"]
5914pub type Nrdysts = crate::RegValueT<Nrdysts_SPEC>;
5915
5916impl Nrdysts {
5917    #[doc = "NRDY Interrupt Status for PIPE9"]
5918    #[inline(always)]
5919    pub fn pipe9nrdy(
5920        self,
5921    ) -> crate::common::RegisterField<
5922        9,
5923        0x1,
5924        1,
5925        0,
5926        nrdysts::Pipe9Nrdy,
5927        nrdysts::Pipe9Nrdy,
5928        Nrdysts_SPEC,
5929        crate::common::RW,
5930    > {
5931        crate::common::RegisterField::<
5932            9,
5933            0x1,
5934            1,
5935            0,
5936            nrdysts::Pipe9Nrdy,
5937            nrdysts::Pipe9Nrdy,
5938            Nrdysts_SPEC,
5939            crate::common::RW,
5940        >::from_register(self, 0)
5941    }
5942
5943    #[doc = "NRDY Interrupt Status for PIPE8"]
5944    #[inline(always)]
5945    pub fn pipe8nrdy(
5946        self,
5947    ) -> crate::common::RegisterField<
5948        8,
5949        0x1,
5950        1,
5951        0,
5952        nrdysts::Pipe8Nrdy,
5953        nrdysts::Pipe8Nrdy,
5954        Nrdysts_SPEC,
5955        crate::common::RW,
5956    > {
5957        crate::common::RegisterField::<
5958            8,
5959            0x1,
5960            1,
5961            0,
5962            nrdysts::Pipe8Nrdy,
5963            nrdysts::Pipe8Nrdy,
5964            Nrdysts_SPEC,
5965            crate::common::RW,
5966        >::from_register(self, 0)
5967    }
5968
5969    #[doc = "NRDY Interrupt Status for PIPE7"]
5970    #[inline(always)]
5971    pub fn pipe7nrdy(
5972        self,
5973    ) -> crate::common::RegisterField<
5974        7,
5975        0x1,
5976        1,
5977        0,
5978        nrdysts::Pipe7Nrdy,
5979        nrdysts::Pipe7Nrdy,
5980        Nrdysts_SPEC,
5981        crate::common::RW,
5982    > {
5983        crate::common::RegisterField::<
5984            7,
5985            0x1,
5986            1,
5987            0,
5988            nrdysts::Pipe7Nrdy,
5989            nrdysts::Pipe7Nrdy,
5990            Nrdysts_SPEC,
5991            crate::common::RW,
5992        >::from_register(self, 0)
5993    }
5994
5995    #[doc = "NRDY Interrupt Status for PIPE6"]
5996    #[inline(always)]
5997    pub fn pipe6nrdy(
5998        self,
5999    ) -> crate::common::RegisterField<
6000        6,
6001        0x1,
6002        1,
6003        0,
6004        nrdysts::Pipe6Nrdy,
6005        nrdysts::Pipe6Nrdy,
6006        Nrdysts_SPEC,
6007        crate::common::RW,
6008    > {
6009        crate::common::RegisterField::<
6010            6,
6011            0x1,
6012            1,
6013            0,
6014            nrdysts::Pipe6Nrdy,
6015            nrdysts::Pipe6Nrdy,
6016            Nrdysts_SPEC,
6017            crate::common::RW,
6018        >::from_register(self, 0)
6019    }
6020
6021    #[doc = "NRDY Interrupt Status for PIPE5"]
6022    #[inline(always)]
6023    pub fn pipe5nrdy(
6024        self,
6025    ) -> crate::common::RegisterField<
6026        5,
6027        0x1,
6028        1,
6029        0,
6030        nrdysts::Pipe5Nrdy,
6031        nrdysts::Pipe5Nrdy,
6032        Nrdysts_SPEC,
6033        crate::common::RW,
6034    > {
6035        crate::common::RegisterField::<
6036            5,
6037            0x1,
6038            1,
6039            0,
6040            nrdysts::Pipe5Nrdy,
6041            nrdysts::Pipe5Nrdy,
6042            Nrdysts_SPEC,
6043            crate::common::RW,
6044        >::from_register(self, 0)
6045    }
6046
6047    #[doc = "NRDY Interrupt Status for PIPE4"]
6048    #[inline(always)]
6049    pub fn pipe4nrdy(
6050        self,
6051    ) -> crate::common::RegisterField<
6052        4,
6053        0x1,
6054        1,
6055        0,
6056        nrdysts::Pipe4Nrdy,
6057        nrdysts::Pipe4Nrdy,
6058        Nrdysts_SPEC,
6059        crate::common::RW,
6060    > {
6061        crate::common::RegisterField::<
6062            4,
6063            0x1,
6064            1,
6065            0,
6066            nrdysts::Pipe4Nrdy,
6067            nrdysts::Pipe4Nrdy,
6068            Nrdysts_SPEC,
6069            crate::common::RW,
6070        >::from_register(self, 0)
6071    }
6072
6073    #[doc = "NRDY Interrupt Status for PIPE3"]
6074    #[inline(always)]
6075    pub fn pipe3nrdy(
6076        self,
6077    ) -> crate::common::RegisterField<
6078        3,
6079        0x1,
6080        1,
6081        0,
6082        nrdysts::Pipe3Nrdy,
6083        nrdysts::Pipe3Nrdy,
6084        Nrdysts_SPEC,
6085        crate::common::RW,
6086    > {
6087        crate::common::RegisterField::<
6088            3,
6089            0x1,
6090            1,
6091            0,
6092            nrdysts::Pipe3Nrdy,
6093            nrdysts::Pipe3Nrdy,
6094            Nrdysts_SPEC,
6095            crate::common::RW,
6096        >::from_register(self, 0)
6097    }
6098
6099    #[doc = "NRDY Interrupt Status for PIPE2"]
6100    #[inline(always)]
6101    pub fn pipe2nrdy(
6102        self,
6103    ) -> crate::common::RegisterField<
6104        2,
6105        0x1,
6106        1,
6107        0,
6108        nrdysts::Pipe2Nrdy,
6109        nrdysts::Pipe2Nrdy,
6110        Nrdysts_SPEC,
6111        crate::common::RW,
6112    > {
6113        crate::common::RegisterField::<
6114            2,
6115            0x1,
6116            1,
6117            0,
6118            nrdysts::Pipe2Nrdy,
6119            nrdysts::Pipe2Nrdy,
6120            Nrdysts_SPEC,
6121            crate::common::RW,
6122        >::from_register(self, 0)
6123    }
6124
6125    #[doc = "NRDY Interrupt Status for PIPE1"]
6126    #[inline(always)]
6127    pub fn pipe1nrdy(
6128        self,
6129    ) -> crate::common::RegisterField<
6130        1,
6131        0x1,
6132        1,
6133        0,
6134        nrdysts::Pipe1Nrdy,
6135        nrdysts::Pipe1Nrdy,
6136        Nrdysts_SPEC,
6137        crate::common::RW,
6138    > {
6139        crate::common::RegisterField::<
6140            1,
6141            0x1,
6142            1,
6143            0,
6144            nrdysts::Pipe1Nrdy,
6145            nrdysts::Pipe1Nrdy,
6146            Nrdysts_SPEC,
6147            crate::common::RW,
6148        >::from_register(self, 0)
6149    }
6150
6151    #[doc = "NRDY Interrupt Status for PIPE0"]
6152    #[inline(always)]
6153    pub fn pipe0nrdy(
6154        self,
6155    ) -> crate::common::RegisterField<
6156        0,
6157        0x1,
6158        1,
6159        0,
6160        nrdysts::Pipe0Nrdy,
6161        nrdysts::Pipe0Nrdy,
6162        Nrdysts_SPEC,
6163        crate::common::RW,
6164    > {
6165        crate::common::RegisterField::<
6166            0,
6167            0x1,
6168            1,
6169            0,
6170            nrdysts::Pipe0Nrdy,
6171            nrdysts::Pipe0Nrdy,
6172            Nrdysts_SPEC,
6173            crate::common::RW,
6174        >::from_register(self, 0)
6175    }
6176}
6177impl ::core::default::Default for Nrdysts {
6178    #[inline(always)]
6179    fn default() -> Nrdysts {
6180        <crate::RegValueT<Nrdysts_SPEC> as RegisterValue<_>>::new(0)
6181    }
6182}
6183pub mod nrdysts {
6184
6185    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6186    pub struct Pipe9Nrdy_SPEC;
6187    pub type Pipe9Nrdy = crate::EnumBitfieldStruct<u8, Pipe9Nrdy_SPEC>;
6188    impl Pipe9Nrdy {
6189        #[doc = "Interrupts are not generated."]
6190        pub const _0: Self = Self::new(0);
6191
6192        #[doc = "Interrupts are generated."]
6193        pub const _1: Self = Self::new(1);
6194    }
6195    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6196    pub struct Pipe8Nrdy_SPEC;
6197    pub type Pipe8Nrdy = crate::EnumBitfieldStruct<u8, Pipe8Nrdy_SPEC>;
6198    impl Pipe8Nrdy {
6199        #[doc = "Interrupts are not generated."]
6200        pub const _0: Self = Self::new(0);
6201
6202        #[doc = "Interrupts are generated."]
6203        pub const _1: Self = Self::new(1);
6204    }
6205    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6206    pub struct Pipe7Nrdy_SPEC;
6207    pub type Pipe7Nrdy = crate::EnumBitfieldStruct<u8, Pipe7Nrdy_SPEC>;
6208    impl Pipe7Nrdy {
6209        #[doc = "Interrupts are not generated."]
6210        pub const _0: Self = Self::new(0);
6211
6212        #[doc = "Interrupts are generated."]
6213        pub const _1: Self = Self::new(1);
6214    }
6215    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6216    pub struct Pipe6Nrdy_SPEC;
6217    pub type Pipe6Nrdy = crate::EnumBitfieldStruct<u8, Pipe6Nrdy_SPEC>;
6218    impl Pipe6Nrdy {
6219        #[doc = "Interrupts are not generated."]
6220        pub const _0: Self = Self::new(0);
6221
6222        #[doc = "Interrupts are generated."]
6223        pub const _1: Self = Self::new(1);
6224    }
6225    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6226    pub struct Pipe5Nrdy_SPEC;
6227    pub type Pipe5Nrdy = crate::EnumBitfieldStruct<u8, Pipe5Nrdy_SPEC>;
6228    impl Pipe5Nrdy {
6229        #[doc = "Interrupts are not generated."]
6230        pub const _0: Self = Self::new(0);
6231
6232        #[doc = "Interrupts are generated."]
6233        pub const _1: Self = Self::new(1);
6234    }
6235    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6236    pub struct Pipe4Nrdy_SPEC;
6237    pub type Pipe4Nrdy = crate::EnumBitfieldStruct<u8, Pipe4Nrdy_SPEC>;
6238    impl Pipe4Nrdy {
6239        #[doc = "Interrupts are not generated."]
6240        pub const _0: Self = Self::new(0);
6241
6242        #[doc = "Interrupts are generated."]
6243        pub const _1: Self = Self::new(1);
6244    }
6245    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6246    pub struct Pipe3Nrdy_SPEC;
6247    pub type Pipe3Nrdy = crate::EnumBitfieldStruct<u8, Pipe3Nrdy_SPEC>;
6248    impl Pipe3Nrdy {
6249        #[doc = "Interrupts are not generated."]
6250        pub const _0: Self = Self::new(0);
6251
6252        #[doc = "Interrupts are generated."]
6253        pub const _1: Self = Self::new(1);
6254    }
6255    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6256    pub struct Pipe2Nrdy_SPEC;
6257    pub type Pipe2Nrdy = crate::EnumBitfieldStruct<u8, Pipe2Nrdy_SPEC>;
6258    impl Pipe2Nrdy {
6259        #[doc = "Interrupts are not generated."]
6260        pub const _0: Self = Self::new(0);
6261
6262        #[doc = "Interrupts are generated."]
6263        pub const _1: Self = Self::new(1);
6264    }
6265    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6266    pub struct Pipe1Nrdy_SPEC;
6267    pub type Pipe1Nrdy = crate::EnumBitfieldStruct<u8, Pipe1Nrdy_SPEC>;
6268    impl Pipe1Nrdy {
6269        #[doc = "Interrupts are not generated."]
6270        pub const _0: Self = Self::new(0);
6271
6272        #[doc = "Interrupts are generated."]
6273        pub const _1: Self = Self::new(1);
6274    }
6275    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6276    pub struct Pipe0Nrdy_SPEC;
6277    pub type Pipe0Nrdy = crate::EnumBitfieldStruct<u8, Pipe0Nrdy_SPEC>;
6278    impl Pipe0Nrdy {
6279        #[doc = "Interrupts are not generated."]
6280        pub const _0: Self = Self::new(0);
6281
6282        #[doc = "Interrupts are generated."]
6283        pub const _1: Self = Self::new(1);
6284    }
6285}
6286#[doc(hidden)]
6287#[derive(Copy, Clone, Eq, PartialEq)]
6288pub struct Bempsts_SPEC;
6289impl crate::sealed::RegSpec for Bempsts_SPEC {
6290    type DataType = u16;
6291}
6292
6293#[doc = "BEMP Interrupt Status Register"]
6294pub type Bempsts = crate::RegValueT<Bempsts_SPEC>;
6295
6296impl Bempsts {
6297    #[doc = "BEMP Interrupt Status for PIPE9"]
6298    #[inline(always)]
6299    pub fn pipe9bemp(
6300        self,
6301    ) -> crate::common::RegisterField<
6302        9,
6303        0x1,
6304        1,
6305        0,
6306        bempsts::Pipe9Bemp,
6307        bempsts::Pipe9Bemp,
6308        Bempsts_SPEC,
6309        crate::common::RW,
6310    > {
6311        crate::common::RegisterField::<
6312            9,
6313            0x1,
6314            1,
6315            0,
6316            bempsts::Pipe9Bemp,
6317            bempsts::Pipe9Bemp,
6318            Bempsts_SPEC,
6319            crate::common::RW,
6320        >::from_register(self, 0)
6321    }
6322
6323    #[doc = "BEMP Interrupt Status for PIPE8"]
6324    #[inline(always)]
6325    pub fn pipe8bemp(
6326        self,
6327    ) -> crate::common::RegisterField<
6328        8,
6329        0x1,
6330        1,
6331        0,
6332        bempsts::Pipe8Bemp,
6333        bempsts::Pipe8Bemp,
6334        Bempsts_SPEC,
6335        crate::common::RW,
6336    > {
6337        crate::common::RegisterField::<
6338            8,
6339            0x1,
6340            1,
6341            0,
6342            bempsts::Pipe8Bemp,
6343            bempsts::Pipe8Bemp,
6344            Bempsts_SPEC,
6345            crate::common::RW,
6346        >::from_register(self, 0)
6347    }
6348
6349    #[doc = "BEMP Interrupt Status for PIPE7"]
6350    #[inline(always)]
6351    pub fn pipe7bemp(
6352        self,
6353    ) -> crate::common::RegisterField<
6354        7,
6355        0x1,
6356        1,
6357        0,
6358        bempsts::Pipe7Bemp,
6359        bempsts::Pipe7Bemp,
6360        Bempsts_SPEC,
6361        crate::common::RW,
6362    > {
6363        crate::common::RegisterField::<
6364            7,
6365            0x1,
6366            1,
6367            0,
6368            bempsts::Pipe7Bemp,
6369            bempsts::Pipe7Bemp,
6370            Bempsts_SPEC,
6371            crate::common::RW,
6372        >::from_register(self, 0)
6373    }
6374
6375    #[doc = "BEMP Interrupt Status for PIPE6"]
6376    #[inline(always)]
6377    pub fn pipe6bemp(
6378        self,
6379    ) -> crate::common::RegisterField<
6380        6,
6381        0x1,
6382        1,
6383        0,
6384        bempsts::Pipe6Bemp,
6385        bempsts::Pipe6Bemp,
6386        Bempsts_SPEC,
6387        crate::common::RW,
6388    > {
6389        crate::common::RegisterField::<
6390            6,
6391            0x1,
6392            1,
6393            0,
6394            bempsts::Pipe6Bemp,
6395            bempsts::Pipe6Bemp,
6396            Bempsts_SPEC,
6397            crate::common::RW,
6398        >::from_register(self, 0)
6399    }
6400
6401    #[doc = "BEMP Interrupt Status for PIPE5"]
6402    #[inline(always)]
6403    pub fn pipe5bemp(
6404        self,
6405    ) -> crate::common::RegisterField<
6406        5,
6407        0x1,
6408        1,
6409        0,
6410        bempsts::Pipe5Bemp,
6411        bempsts::Pipe5Bemp,
6412        Bempsts_SPEC,
6413        crate::common::RW,
6414    > {
6415        crate::common::RegisterField::<
6416            5,
6417            0x1,
6418            1,
6419            0,
6420            bempsts::Pipe5Bemp,
6421            bempsts::Pipe5Bemp,
6422            Bempsts_SPEC,
6423            crate::common::RW,
6424        >::from_register(self, 0)
6425    }
6426
6427    #[doc = "BEMP Interrupt Status for PIPE4"]
6428    #[inline(always)]
6429    pub fn pipe4bemp(
6430        self,
6431    ) -> crate::common::RegisterField<
6432        4,
6433        0x1,
6434        1,
6435        0,
6436        bempsts::Pipe4Bemp,
6437        bempsts::Pipe4Bemp,
6438        Bempsts_SPEC,
6439        crate::common::RW,
6440    > {
6441        crate::common::RegisterField::<
6442            4,
6443            0x1,
6444            1,
6445            0,
6446            bempsts::Pipe4Bemp,
6447            bempsts::Pipe4Bemp,
6448            Bempsts_SPEC,
6449            crate::common::RW,
6450        >::from_register(self, 0)
6451    }
6452
6453    #[doc = "BEMP Interrupt Status for PIPE3"]
6454    #[inline(always)]
6455    pub fn pipe3bemp(
6456        self,
6457    ) -> crate::common::RegisterField<
6458        3,
6459        0x1,
6460        1,
6461        0,
6462        bempsts::Pipe3Bemp,
6463        bempsts::Pipe3Bemp,
6464        Bempsts_SPEC,
6465        crate::common::RW,
6466    > {
6467        crate::common::RegisterField::<
6468            3,
6469            0x1,
6470            1,
6471            0,
6472            bempsts::Pipe3Bemp,
6473            bempsts::Pipe3Bemp,
6474            Bempsts_SPEC,
6475            crate::common::RW,
6476        >::from_register(self, 0)
6477    }
6478
6479    #[doc = "BEMP Interrupt Status for PIPE2"]
6480    #[inline(always)]
6481    pub fn pipe2bemp(
6482        self,
6483    ) -> crate::common::RegisterField<
6484        2,
6485        0x1,
6486        1,
6487        0,
6488        bempsts::Pipe2Bemp,
6489        bempsts::Pipe2Bemp,
6490        Bempsts_SPEC,
6491        crate::common::RW,
6492    > {
6493        crate::common::RegisterField::<
6494            2,
6495            0x1,
6496            1,
6497            0,
6498            bempsts::Pipe2Bemp,
6499            bempsts::Pipe2Bemp,
6500            Bempsts_SPEC,
6501            crate::common::RW,
6502        >::from_register(self, 0)
6503    }
6504
6505    #[doc = "BEMP Interrupt Status for PIPE1"]
6506    #[inline(always)]
6507    pub fn pipe1bemp(
6508        self,
6509    ) -> crate::common::RegisterField<
6510        1,
6511        0x1,
6512        1,
6513        0,
6514        bempsts::Pipe1Bemp,
6515        bempsts::Pipe1Bemp,
6516        Bempsts_SPEC,
6517        crate::common::RW,
6518    > {
6519        crate::common::RegisterField::<
6520            1,
6521            0x1,
6522            1,
6523            0,
6524            bempsts::Pipe1Bemp,
6525            bempsts::Pipe1Bemp,
6526            Bempsts_SPEC,
6527            crate::common::RW,
6528        >::from_register(self, 0)
6529    }
6530
6531    #[doc = "BEMP Interrupt Status for PIPE0"]
6532    #[inline(always)]
6533    pub fn pipe0bemp(
6534        self,
6535    ) -> crate::common::RegisterField<
6536        0,
6537        0x1,
6538        1,
6539        0,
6540        bempsts::Pipe0Bemp,
6541        bempsts::Pipe0Bemp,
6542        Bempsts_SPEC,
6543        crate::common::RW,
6544    > {
6545        crate::common::RegisterField::<
6546            0,
6547            0x1,
6548            1,
6549            0,
6550            bempsts::Pipe0Bemp,
6551            bempsts::Pipe0Bemp,
6552            Bempsts_SPEC,
6553            crate::common::RW,
6554        >::from_register(self, 0)
6555    }
6556}
6557impl ::core::default::Default for Bempsts {
6558    #[inline(always)]
6559    fn default() -> Bempsts {
6560        <crate::RegValueT<Bempsts_SPEC> as RegisterValue<_>>::new(0)
6561    }
6562}
6563pub mod bempsts {
6564
6565    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6566    pub struct Pipe9Bemp_SPEC;
6567    pub type Pipe9Bemp = crate::EnumBitfieldStruct<u8, Pipe9Bemp_SPEC>;
6568    impl Pipe9Bemp {
6569        #[doc = "Interrupts are not generated."]
6570        pub const _0: Self = Self::new(0);
6571
6572        #[doc = "Interrupts are generated."]
6573        pub const _1: Self = Self::new(1);
6574    }
6575    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6576    pub struct Pipe8Bemp_SPEC;
6577    pub type Pipe8Bemp = crate::EnumBitfieldStruct<u8, Pipe8Bemp_SPEC>;
6578    impl Pipe8Bemp {
6579        #[doc = "Interrupts are not generated."]
6580        pub const _0: Self = Self::new(0);
6581
6582        #[doc = "Interrupts are generated."]
6583        pub const _1: Self = Self::new(1);
6584    }
6585    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6586    pub struct Pipe7Bemp_SPEC;
6587    pub type Pipe7Bemp = crate::EnumBitfieldStruct<u8, Pipe7Bemp_SPEC>;
6588    impl Pipe7Bemp {
6589        #[doc = "Interrupts are not generated."]
6590        pub const _0: Self = Self::new(0);
6591
6592        #[doc = "Interrupts are generated."]
6593        pub const _1: Self = Self::new(1);
6594    }
6595    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6596    pub struct Pipe6Bemp_SPEC;
6597    pub type Pipe6Bemp = crate::EnumBitfieldStruct<u8, Pipe6Bemp_SPEC>;
6598    impl Pipe6Bemp {
6599        #[doc = "Interrupts are not generated."]
6600        pub const _0: Self = Self::new(0);
6601
6602        #[doc = "Interrupts are generated."]
6603        pub const _1: Self = Self::new(1);
6604    }
6605    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6606    pub struct Pipe5Bemp_SPEC;
6607    pub type Pipe5Bemp = crate::EnumBitfieldStruct<u8, Pipe5Bemp_SPEC>;
6608    impl Pipe5Bemp {
6609        #[doc = "Interrupts are not generated."]
6610        pub const _0: Self = Self::new(0);
6611
6612        #[doc = "Interrupts are generated."]
6613        pub const _1: Self = Self::new(1);
6614    }
6615    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6616    pub struct Pipe4Bemp_SPEC;
6617    pub type Pipe4Bemp = crate::EnumBitfieldStruct<u8, Pipe4Bemp_SPEC>;
6618    impl Pipe4Bemp {
6619        #[doc = "Interrupts are not generated."]
6620        pub const _0: Self = Self::new(0);
6621
6622        #[doc = "Interrupts are generated."]
6623        pub const _1: Self = Self::new(1);
6624    }
6625    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6626    pub struct Pipe3Bemp_SPEC;
6627    pub type Pipe3Bemp = crate::EnumBitfieldStruct<u8, Pipe3Bemp_SPEC>;
6628    impl Pipe3Bemp {
6629        #[doc = "Interrupts are not generated."]
6630        pub const _0: Self = Self::new(0);
6631
6632        #[doc = "Interrupts are generated."]
6633        pub const _1: Self = Self::new(1);
6634    }
6635    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6636    pub struct Pipe2Bemp_SPEC;
6637    pub type Pipe2Bemp = crate::EnumBitfieldStruct<u8, Pipe2Bemp_SPEC>;
6638    impl Pipe2Bemp {
6639        #[doc = "Interrupts are not generated."]
6640        pub const _0: Self = Self::new(0);
6641
6642        #[doc = "Interrupts are generated."]
6643        pub const _1: Self = Self::new(1);
6644    }
6645    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6646    pub struct Pipe1Bemp_SPEC;
6647    pub type Pipe1Bemp = crate::EnumBitfieldStruct<u8, Pipe1Bemp_SPEC>;
6648    impl Pipe1Bemp {
6649        #[doc = "Interrupts are not generated."]
6650        pub const _0: Self = Self::new(0);
6651
6652        #[doc = "Interrupts are generated."]
6653        pub const _1: Self = Self::new(1);
6654    }
6655    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6656    pub struct Pipe0Bemp_SPEC;
6657    pub type Pipe0Bemp = crate::EnumBitfieldStruct<u8, Pipe0Bemp_SPEC>;
6658    impl Pipe0Bemp {
6659        #[doc = "Interrupts are not generated."]
6660        pub const _0: Self = Self::new(0);
6661
6662        #[doc = "Interrupts are generated."]
6663        pub const _1: Self = Self::new(1);
6664    }
6665}
6666#[doc(hidden)]
6667#[derive(Copy, Clone, Eq, PartialEq)]
6668pub struct Frmnum_SPEC;
6669impl crate::sealed::RegSpec for Frmnum_SPEC {
6670    type DataType = u16;
6671}
6672
6673#[doc = "Frame Number Register"]
6674pub type Frmnum = crate::RegValueT<Frmnum_SPEC>;
6675
6676impl Frmnum {
6677    #[doc = "Overrun/Underrun Detection Status"]
6678    #[inline(always)]
6679    pub fn ovrn(
6680        self,
6681    ) -> crate::common::RegisterField<
6682        15,
6683        0x1,
6684        1,
6685        0,
6686        frmnum::Ovrn,
6687        frmnum::Ovrn,
6688        Frmnum_SPEC,
6689        crate::common::RW,
6690    > {
6691        crate::common::RegisterField::<
6692            15,
6693            0x1,
6694            1,
6695            0,
6696            frmnum::Ovrn,
6697            frmnum::Ovrn,
6698            Frmnum_SPEC,
6699            crate::common::RW,
6700        >::from_register(self, 0)
6701    }
6702
6703    #[doc = "Receive Data Error"]
6704    #[inline(always)]
6705    pub fn crce(
6706        self,
6707    ) -> crate::common::RegisterField<
6708        14,
6709        0x1,
6710        1,
6711        0,
6712        frmnum::Crce,
6713        frmnum::Crce,
6714        Frmnum_SPEC,
6715        crate::common::RW,
6716    > {
6717        crate::common::RegisterField::<
6718            14,
6719            0x1,
6720            1,
6721            0,
6722            frmnum::Crce,
6723            frmnum::Crce,
6724            Frmnum_SPEC,
6725            crate::common::RW,
6726        >::from_register(self, 0)
6727    }
6728
6729    #[doc = "Frame NumberLatest frame number"]
6730    #[inline(always)]
6731    pub fn frnm(
6732        self,
6733    ) -> crate::common::RegisterField<0, 0x7ff, 1, 0, u16, u16, Frmnum_SPEC, crate::common::R> {
6734        crate::common::RegisterField::<0,0x7ff,1,0,u16,u16,Frmnum_SPEC,crate::common::R>::from_register(self,0)
6735    }
6736}
6737impl ::core::default::Default for Frmnum {
6738    #[inline(always)]
6739    fn default() -> Frmnum {
6740        <crate::RegValueT<Frmnum_SPEC> as RegisterValue<_>>::new(0)
6741    }
6742}
6743pub mod frmnum {
6744
6745    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6746    pub struct Ovrn_SPEC;
6747    pub type Ovrn = crate::EnumBitfieldStruct<u8, Ovrn_SPEC>;
6748    impl Ovrn {
6749        #[doc = "No error"]
6750        pub const _0: Self = Self::new(0);
6751
6752        #[doc = "An error occurred"]
6753        pub const _1: Self = Self::new(1);
6754    }
6755    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6756    pub struct Crce_SPEC;
6757    pub type Crce = crate::EnumBitfieldStruct<u8, Crce_SPEC>;
6758    impl Crce {
6759        #[doc = "No error"]
6760        pub const _0: Self = Self::new(0);
6761
6762        #[doc = "An error occurred"]
6763        pub const _1: Self = Self::new(1);
6764    }
6765}
6766#[doc(hidden)]
6767#[derive(Copy, Clone, Eq, PartialEq)]
6768pub struct Dvchgr_SPEC;
6769impl crate::sealed::RegSpec for Dvchgr_SPEC {
6770    type DataType = u16;
6771}
6772
6773#[doc = "Device State Change Register"]
6774pub type Dvchgr = crate::RegValueT<Dvchgr_SPEC>;
6775
6776impl Dvchgr {
6777    #[doc = "Device State Change"]
6778    #[inline(always)]
6779    pub fn dvchg(
6780        self,
6781    ) -> crate::common::RegisterField<
6782        15,
6783        0x1,
6784        1,
6785        0,
6786        dvchgr::Dvchg,
6787        dvchgr::Dvchg,
6788        Dvchgr_SPEC,
6789        crate::common::RW,
6790    > {
6791        crate::common::RegisterField::<
6792            15,
6793            0x1,
6794            1,
6795            0,
6796            dvchgr::Dvchg,
6797            dvchgr::Dvchg,
6798            Dvchgr_SPEC,
6799            crate::common::RW,
6800        >::from_register(self, 0)
6801    }
6802}
6803impl ::core::default::Default for Dvchgr {
6804    #[inline(always)]
6805    fn default() -> Dvchgr {
6806        <crate::RegValueT<Dvchgr_SPEC> as RegisterValue<_>>::new(0)
6807    }
6808}
6809pub mod dvchgr {
6810
6811    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6812    pub struct Dvchg_SPEC;
6813    pub type Dvchg = crate::EnumBitfieldStruct<u8, Dvchg_SPEC>;
6814    impl Dvchg {
6815        #[doc = "Disables the writing to the USBADDR.STSRECOV\\[3:0\\] bits and USBADDR.USBADDR\\[6:0\\]."]
6816        pub const _0: Self = Self::new(0);
6817
6818        #[doc = "Enables the writing to the USBADDR.STSRECOV\\[3:0\\] bits and USBADDR.USBADDR\\[6:0\\]."]
6819        pub const _1: Self = Self::new(1);
6820    }
6821}
6822#[doc(hidden)]
6823#[derive(Copy, Clone, Eq, PartialEq)]
6824pub struct Usbaddr_SPEC;
6825impl crate::sealed::RegSpec for Usbaddr_SPEC {
6826    type DataType = u16;
6827}
6828
6829#[doc = "USB Address Register"]
6830pub type Usbaddr = crate::RegValueT<Usbaddr_SPEC>;
6831
6832impl Usbaddr {
6833    #[doc = "Status Recovery"]
6834    #[inline(always)]
6835    pub fn stsrecov(
6836        self,
6837    ) -> crate::common::RegisterField<
6838        8,
6839        0xf,
6840        1,
6841        0,
6842        usbaddr::Stsrecov,
6843        usbaddr::Stsrecov,
6844        Usbaddr_SPEC,
6845        crate::common::RW,
6846    > {
6847        crate::common::RegisterField::<
6848            8,
6849            0xf,
6850            1,
6851            0,
6852            usbaddr::Stsrecov,
6853            usbaddr::Stsrecov,
6854            Usbaddr_SPEC,
6855            crate::common::RW,
6856        >::from_register(self, 0)
6857    }
6858
6859    #[doc = "USB AddressWhen the function controller is selected, these bits indicate the USB address assigned by the host when the SET_ADDRESS request is successfully processed."]
6860    #[inline(always)]
6861    pub fn usbaddr(
6862        self,
6863    ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Usbaddr_SPEC, crate::common::RW> {
6864        crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Usbaddr_SPEC,crate::common::RW>::from_register(self,0)
6865    }
6866}
6867impl ::core::default::Default for Usbaddr {
6868    #[inline(always)]
6869    fn default() -> Usbaddr {
6870        <crate::RegValueT<Usbaddr_SPEC> as RegisterValue<_>>::new(0)
6871    }
6872}
6873pub mod usbaddr {
6874
6875    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6876    pub struct Stsrecov_SPEC;
6877    pub type Stsrecov = crate::EnumBitfieldStruct<u8, Stsrecov_SPEC>;
6878    impl Stsrecov {
6879        #[doc = "Return to the low-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 001b;(Recovery when the host controller is selected))"]
6880        pub const _0100: Self = Self::new(4);
6881
6882        #[doc = "Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b;(Recovery when the host controller is selected))"]
6883        pub const _1000: Self = Self::new(8);
6884
6885        #[doc = "Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 001b (Default state);(Recovery when the function controller is selected)"]
6886        pub const _1001: Self = Self::new(9);
6887
6888        #[doc = "Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 010b (Address state);(Recovery when the function controller is selected)"]
6889        pub const _1010: Self = Self::new(10);
6890
6891        #[doc = "Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 011b (Configured state);(Recovery when the function controller is selected)"]
6892        pub const _1011: Self = Self::new(11);
6893    }
6894}
6895#[doc(hidden)]
6896#[derive(Copy, Clone, Eq, PartialEq)]
6897pub struct Usbreq_SPEC;
6898impl crate::sealed::RegSpec for Usbreq_SPEC {
6899    type DataType = u16;
6900}
6901
6902#[doc = "USB Request Type Register"]
6903pub type Usbreq = crate::RegValueT<Usbreq_SPEC>;
6904
6905impl Usbreq {
6906    #[doc = "RequestThese bits store the USB request bRequest value."]
6907    #[inline(always)]
6908    pub fn brequest(
6909        self,
6910    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Usbreq_SPEC, crate::common::RW> {
6911        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Usbreq_SPEC,crate::common::RW>::from_register(self,0)
6912    }
6913
6914    #[doc = "Request TypeThese bits store the USB request bmRequestType value."]
6915    #[inline(always)]
6916    pub fn bmrequesttype(
6917        self,
6918    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Usbreq_SPEC, crate::common::RW> {
6919        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Usbreq_SPEC,crate::common::RW>::from_register(self,0)
6920    }
6921}
6922impl ::core::default::Default for Usbreq {
6923    #[inline(always)]
6924    fn default() -> Usbreq {
6925        <crate::RegValueT<Usbreq_SPEC> as RegisterValue<_>>::new(0)
6926    }
6927}
6928
6929#[doc(hidden)]
6930#[derive(Copy, Clone, Eq, PartialEq)]
6931pub struct Usbval_SPEC;
6932impl crate::sealed::RegSpec for Usbval_SPEC {
6933    type DataType = u16;
6934}
6935
6936#[doc = "USB Request Value Register"]
6937pub type Usbval = crate::RegValueT<Usbval_SPEC>;
6938
6939impl Usbval {
6940    #[doc = "ValueThese bits store the USB request wValue value."]
6941    #[inline(always)]
6942    pub fn wvalue(
6943        self,
6944    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Usbval_SPEC, crate::common::RW>
6945    {
6946        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Usbval_SPEC,crate::common::RW>::from_register(self,0)
6947    }
6948}
6949impl ::core::default::Default for Usbval {
6950    #[inline(always)]
6951    fn default() -> Usbval {
6952        <crate::RegValueT<Usbval_SPEC> as RegisterValue<_>>::new(0)
6953    }
6954}
6955
6956#[doc(hidden)]
6957#[derive(Copy, Clone, Eq, PartialEq)]
6958pub struct Usbindx_SPEC;
6959impl crate::sealed::RegSpec for Usbindx_SPEC {
6960    type DataType = u16;
6961}
6962
6963#[doc = "USB Request Index Register"]
6964pub type Usbindx = crate::RegValueT<Usbindx_SPEC>;
6965
6966impl Usbindx {
6967    #[doc = "IndexThese bits store the USB request wIndex value."]
6968    #[inline(always)]
6969    pub fn windex(
6970        self,
6971    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Usbindx_SPEC, crate::common::RW>
6972    {
6973        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Usbindx_SPEC,crate::common::RW>::from_register(self,0)
6974    }
6975}
6976impl ::core::default::Default for Usbindx {
6977    #[inline(always)]
6978    fn default() -> Usbindx {
6979        <crate::RegValueT<Usbindx_SPEC> as RegisterValue<_>>::new(0)
6980    }
6981}
6982
6983#[doc(hidden)]
6984#[derive(Copy, Clone, Eq, PartialEq)]
6985pub struct Usbleng_SPEC;
6986impl crate::sealed::RegSpec for Usbleng_SPEC {
6987    type DataType = u16;
6988}
6989
6990#[doc = "USB Request Length Register"]
6991pub type Usbleng = crate::RegValueT<Usbleng_SPEC>;
6992
6993impl Usbleng {
6994    #[doc = "LengthThese bits store the USB request wLength value."]
6995    #[inline(always)]
6996    pub fn wlength(
6997        self,
6998    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Usbleng_SPEC, crate::common::RW>
6999    {
7000        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Usbleng_SPEC,crate::common::RW>::from_register(self,0)
7001    }
7002}
7003impl ::core::default::Default for Usbleng {
7004    #[inline(always)]
7005    fn default() -> Usbleng {
7006        <crate::RegValueT<Usbleng_SPEC> as RegisterValue<_>>::new(0)
7007    }
7008}
7009
7010#[doc(hidden)]
7011#[derive(Copy, Clone, Eq, PartialEq)]
7012pub struct Dcpcfg_SPEC;
7013impl crate::sealed::RegSpec for Dcpcfg_SPEC {
7014    type DataType = u16;
7015}
7016
7017#[doc = "DCP Configuration Register"]
7018pub type Dcpcfg = crate::RegValueT<Dcpcfg_SPEC>;
7019
7020impl Dcpcfg {
7021    #[doc = "Pipe Disabled at End of Transfer"]
7022    #[inline(always)]
7023    pub fn shtnak(
7024        self,
7025    ) -> crate::common::RegisterField<
7026        7,
7027        0x1,
7028        1,
7029        0,
7030        dcpcfg::Shtnak,
7031        dcpcfg::Shtnak,
7032        Dcpcfg_SPEC,
7033        crate::common::RW,
7034    > {
7035        crate::common::RegisterField::<
7036            7,
7037            0x1,
7038            1,
7039            0,
7040            dcpcfg::Shtnak,
7041            dcpcfg::Shtnak,
7042            Dcpcfg_SPEC,
7043            crate::common::RW,
7044        >::from_register(self, 0)
7045    }
7046
7047    #[doc = "Transfer Direction"]
7048    #[inline(always)]
7049    pub fn dir(
7050        self,
7051    ) -> crate::common::RegisterField<
7052        4,
7053        0x1,
7054        1,
7055        0,
7056        dcpcfg::Dir,
7057        dcpcfg::Dir,
7058        Dcpcfg_SPEC,
7059        crate::common::RW,
7060    > {
7061        crate::common::RegisterField::<
7062            4,
7063            0x1,
7064            1,
7065            0,
7066            dcpcfg::Dir,
7067            dcpcfg::Dir,
7068            Dcpcfg_SPEC,
7069            crate::common::RW,
7070        >::from_register(self, 0)
7071    }
7072}
7073impl ::core::default::Default for Dcpcfg {
7074    #[inline(always)]
7075    fn default() -> Dcpcfg {
7076        <crate::RegValueT<Dcpcfg_SPEC> as RegisterValue<_>>::new(0)
7077    }
7078}
7079pub mod dcpcfg {
7080
7081    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7082    pub struct Shtnak_SPEC;
7083    pub type Shtnak = crate::EnumBitfieldStruct<u8, Shtnak_SPEC>;
7084    impl Shtnak {
7085        #[doc = "Pipe continued at the end of transfer"]
7086        pub const _0: Self = Self::new(0);
7087
7088        #[doc = "Pipe disabled at the end of transfer"]
7089        pub const _1: Self = Self::new(1);
7090    }
7091    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7092    pub struct Dir_SPEC;
7093    pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
7094    impl Dir {
7095        #[doc = "Data receiving direction"]
7096        pub const _0: Self = Self::new(0);
7097
7098        #[doc = "Data transmitting direction"]
7099        pub const _1: Self = Self::new(1);
7100    }
7101}
7102#[doc(hidden)]
7103#[derive(Copy, Clone, Eq, PartialEq)]
7104pub struct Dcpmaxp_SPEC;
7105impl crate::sealed::RegSpec for Dcpmaxp_SPEC {
7106    type DataType = u16;
7107}
7108
7109#[doc = "DCP Maximum Packet Size Register"]
7110pub type Dcpmaxp = crate::RegValueT<Dcpmaxp_SPEC>;
7111
7112impl Dcpmaxp {
7113    #[doc = "Device Select"]
7114    #[inline(always)]
7115    pub fn devsel(
7116        self,
7117    ) -> crate::common::RegisterField<
7118        12,
7119        0xf,
7120        1,
7121        0,
7122        dcpmaxp::Devsel,
7123        dcpmaxp::Devsel,
7124        Dcpmaxp_SPEC,
7125        crate::common::RW,
7126    > {
7127        crate::common::RegisterField::<
7128            12,
7129            0xf,
7130            1,
7131            0,
7132            dcpmaxp::Devsel,
7133            dcpmaxp::Devsel,
7134            Dcpmaxp_SPEC,
7135            crate::common::RW,
7136        >::from_register(self, 0)
7137    }
7138
7139    #[doc = "Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP."]
7140    #[inline(always)]
7141    pub fn mxps(
7142        self,
7143    ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Dcpmaxp_SPEC, crate::common::RW> {
7144        crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Dcpmaxp_SPEC,crate::common::RW>::from_register(self,0)
7145    }
7146}
7147impl ::core::default::Default for Dcpmaxp {
7148    #[inline(always)]
7149    fn default() -> Dcpmaxp {
7150        <crate::RegValueT<Dcpmaxp_SPEC> as RegisterValue<_>>::new(64)
7151    }
7152}
7153pub mod dcpmaxp {
7154
7155    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7156    pub struct Devsel_SPEC;
7157    pub type Devsel = crate::EnumBitfieldStruct<u8, Devsel_SPEC>;
7158    impl Devsel {
7159        #[doc = "Address 0000"]
7160        pub const _0000: Self = Self::new(0);
7161
7162        #[doc = "Address 0001"]
7163        pub const _0001: Self = Self::new(1);
7164
7165        #[doc = "Address 0010"]
7166        pub const _0010: Self = Self::new(2);
7167
7168        #[doc = "Address 0011"]
7169        pub const _0011: Self = Self::new(3);
7170
7171        #[doc = "Address 0100"]
7172        pub const _0100: Self = Self::new(4);
7173
7174        #[doc = "Address 0101"]
7175        pub const _0101: Self = Self::new(5);
7176    }
7177}
7178#[doc(hidden)]
7179#[derive(Copy, Clone, Eq, PartialEq)]
7180pub struct Dcpctr_SPEC;
7181impl crate::sealed::RegSpec for Dcpctr_SPEC {
7182    type DataType = u16;
7183}
7184
7185#[doc = "DCP Control Register"]
7186pub type Dcpctr = crate::RegValueT<Dcpctr_SPEC>;
7187
7188impl Dcpctr {
7189    #[doc = "Buffer Status"]
7190    #[inline(always)]
7191    pub fn bsts(
7192        self,
7193    ) -> crate::common::RegisterField<
7194        15,
7195        0x1,
7196        1,
7197        0,
7198        dcpctr::Bsts,
7199        dcpctr::Bsts,
7200        Dcpctr_SPEC,
7201        crate::common::R,
7202    > {
7203        crate::common::RegisterField::<
7204            15,
7205            0x1,
7206            1,
7207            0,
7208            dcpctr::Bsts,
7209            dcpctr::Bsts,
7210            Dcpctr_SPEC,
7211            crate::common::R,
7212        >::from_register(self, 0)
7213    }
7214
7215    #[doc = "Setup Token Transmission"]
7216    #[inline(always)]
7217    pub fn sureq(
7218        self,
7219    ) -> crate::common::RegisterField<
7220        14,
7221        0x1,
7222        1,
7223        0,
7224        dcpctr::Sureq,
7225        dcpctr::Sureq,
7226        Dcpctr_SPEC,
7227        crate::common::RW,
7228    > {
7229        crate::common::RegisterField::<
7230            14,
7231            0x1,
7232            1,
7233            0,
7234            dcpctr::Sureq,
7235            dcpctr::Sureq,
7236            Dcpctr_SPEC,
7237            crate::common::RW,
7238        >::from_register(self, 0)
7239    }
7240
7241    #[doc = "SUREQ Bit Clear"]
7242    #[inline(always)]
7243    pub fn sureqclr(
7244        self,
7245    ) -> crate::common::RegisterField<
7246        11,
7247        0x1,
7248        1,
7249        0,
7250        dcpctr::Sureqclr,
7251        dcpctr::Sureqclr,
7252        Dcpctr_SPEC,
7253        crate::common::RW,
7254    > {
7255        crate::common::RegisterField::<
7256            11,
7257            0x1,
7258            1,
7259            0,
7260            dcpctr::Sureqclr,
7261            dcpctr::Sureqclr,
7262            Dcpctr_SPEC,
7263            crate::common::RW,
7264        >::from_register(self, 0)
7265    }
7266
7267    #[doc = "Sequence Toggle Bit Clear"]
7268    #[inline(always)]
7269    pub fn sqclr(
7270        self,
7271    ) -> crate::common::RegisterField<
7272        8,
7273        0x1,
7274        1,
7275        0,
7276        dcpctr::Sqclr,
7277        dcpctr::Sqclr,
7278        Dcpctr_SPEC,
7279        crate::common::RW,
7280    > {
7281        crate::common::RegisterField::<
7282            8,
7283            0x1,
7284            1,
7285            0,
7286            dcpctr::Sqclr,
7287            dcpctr::Sqclr,
7288            Dcpctr_SPEC,
7289            crate::common::RW,
7290        >::from_register(self, 0)
7291    }
7292
7293    #[doc = "Sequence Toggle Bit Set"]
7294    #[inline(always)]
7295    pub fn sqset(
7296        self,
7297    ) -> crate::common::RegisterField<
7298        7,
7299        0x1,
7300        1,
7301        0,
7302        dcpctr::Sqset,
7303        dcpctr::Sqset,
7304        Dcpctr_SPEC,
7305        crate::common::RW,
7306    > {
7307        crate::common::RegisterField::<
7308            7,
7309            0x1,
7310            1,
7311            0,
7312            dcpctr::Sqset,
7313            dcpctr::Sqset,
7314            Dcpctr_SPEC,
7315            crate::common::RW,
7316        >::from_register(self, 0)
7317    }
7318
7319    #[doc = "Sequence Toggle Bit Monitor"]
7320    #[inline(always)]
7321    pub fn sqmon(
7322        self,
7323    ) -> crate::common::RegisterField<
7324        6,
7325        0x1,
7326        1,
7327        0,
7328        dcpctr::Sqmon,
7329        dcpctr::Sqmon,
7330        Dcpctr_SPEC,
7331        crate::common::R,
7332    > {
7333        crate::common::RegisterField::<
7334            6,
7335            0x1,
7336            1,
7337            0,
7338            dcpctr::Sqmon,
7339            dcpctr::Sqmon,
7340            Dcpctr_SPEC,
7341            crate::common::R,
7342        >::from_register(self, 0)
7343    }
7344
7345    #[doc = "Pipe Busy"]
7346    #[inline(always)]
7347    pub fn pbusy(
7348        self,
7349    ) -> crate::common::RegisterField<
7350        5,
7351        0x1,
7352        1,
7353        0,
7354        dcpctr::Pbusy,
7355        dcpctr::Pbusy,
7356        Dcpctr_SPEC,
7357        crate::common::R,
7358    > {
7359        crate::common::RegisterField::<
7360            5,
7361            0x1,
7362            1,
7363            0,
7364            dcpctr::Pbusy,
7365            dcpctr::Pbusy,
7366            Dcpctr_SPEC,
7367            crate::common::R,
7368        >::from_register(self, 0)
7369    }
7370
7371    #[doc = "Control Transfer End Enable"]
7372    #[inline(always)]
7373    pub fn ccpl(
7374        self,
7375    ) -> crate::common::RegisterField<
7376        2,
7377        0x1,
7378        1,
7379        0,
7380        dcpctr::Ccpl,
7381        dcpctr::Ccpl,
7382        Dcpctr_SPEC,
7383        crate::common::RW,
7384    > {
7385        crate::common::RegisterField::<
7386            2,
7387            0x1,
7388            1,
7389            0,
7390            dcpctr::Ccpl,
7391            dcpctr::Ccpl,
7392            Dcpctr_SPEC,
7393            crate::common::RW,
7394        >::from_register(self, 0)
7395    }
7396
7397    #[doc = "Response PID"]
7398    #[inline(always)]
7399    pub fn pid(
7400        self,
7401    ) -> crate::common::RegisterField<
7402        0,
7403        0x3,
7404        1,
7405        0,
7406        dcpctr::Pid,
7407        dcpctr::Pid,
7408        Dcpctr_SPEC,
7409        crate::common::RW,
7410    > {
7411        crate::common::RegisterField::<
7412            0,
7413            0x3,
7414            1,
7415            0,
7416            dcpctr::Pid,
7417            dcpctr::Pid,
7418            Dcpctr_SPEC,
7419            crate::common::RW,
7420        >::from_register(self, 0)
7421    }
7422}
7423impl ::core::default::Default for Dcpctr {
7424    #[inline(always)]
7425    fn default() -> Dcpctr {
7426        <crate::RegValueT<Dcpctr_SPEC> as RegisterValue<_>>::new(64)
7427    }
7428}
7429pub mod dcpctr {
7430
7431    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7432    pub struct Bsts_SPEC;
7433    pub type Bsts = crate::EnumBitfieldStruct<u8, Bsts_SPEC>;
7434    impl Bsts {
7435        #[doc = "Buffer access is disabled."]
7436        pub const _0: Self = Self::new(0);
7437
7438        #[doc = "Buffer access is enabled."]
7439        pub const _1: Self = Self::new(1);
7440    }
7441    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7442    pub struct Sureq_SPEC;
7443    pub type Sureq = crate::EnumBitfieldStruct<u8, Sureq_SPEC>;
7444    impl Sureq {
7445        #[doc = "Invalid"]
7446        pub const _0: Self = Self::new(0);
7447
7448        #[doc = "Transmits the setup packet."]
7449        pub const _1: Self = Self::new(1);
7450    }
7451    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7452    pub struct Sureqclr_SPEC;
7453    pub type Sureqclr = crate::EnumBitfieldStruct<u8, Sureqclr_SPEC>;
7454    impl Sureqclr {
7455        #[doc = "Invalid"]
7456        pub const _0: Self = Self::new(0);
7457
7458        #[doc = "Clears the SUREQ bit to 0."]
7459        pub const _1: Self = Self::new(1);
7460    }
7461    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7462    pub struct Sqclr_SPEC;
7463    pub type Sqclr = crate::EnumBitfieldStruct<u8, Sqclr_SPEC>;
7464    impl Sqclr {
7465        #[doc = "Invalid"]
7466        pub const _0: Self = Self::new(0);
7467
7468        #[doc = "Specifies DATA0."]
7469        pub const _1: Self = Self::new(1);
7470    }
7471    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7472    pub struct Sqset_SPEC;
7473    pub type Sqset = crate::EnumBitfieldStruct<u8, Sqset_SPEC>;
7474    impl Sqset {
7475        #[doc = "Invalid"]
7476        pub const _0: Self = Self::new(0);
7477
7478        #[doc = "Specifies DATA1."]
7479        pub const _1: Self = Self::new(1);
7480    }
7481    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7482    pub struct Sqmon_SPEC;
7483    pub type Sqmon = crate::EnumBitfieldStruct<u8, Sqmon_SPEC>;
7484    impl Sqmon {
7485        #[doc = "DATA0"]
7486        pub const _0: Self = Self::new(0);
7487
7488        #[doc = "DATA1"]
7489        pub const _1: Self = Self::new(1);
7490    }
7491    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7492    pub struct Pbusy_SPEC;
7493    pub type Pbusy = crate::EnumBitfieldStruct<u8, Pbusy_SPEC>;
7494    impl Pbusy {
7495        #[doc = "DCP is not used for the transaction."]
7496        pub const _0: Self = Self::new(0);
7497
7498        #[doc = "DCP is used for the transaction."]
7499        pub const _1: Self = Self::new(1);
7500    }
7501    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7502    pub struct Ccpl_SPEC;
7503    pub type Ccpl = crate::EnumBitfieldStruct<u8, Ccpl_SPEC>;
7504    impl Ccpl {
7505        #[doc = "Invalid"]
7506        pub const _0: Self = Self::new(0);
7507
7508        #[doc = "Completion of control transfer is enabled."]
7509        pub const _1: Self = Self::new(1);
7510    }
7511    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7512    pub struct Pid_SPEC;
7513    pub type Pid = crate::EnumBitfieldStruct<u8, Pid_SPEC>;
7514    impl Pid {
7515        #[doc = "NAK response"]
7516        pub const _00: Self = Self::new(0);
7517
7518        #[doc = "BUF response (depending on the buffer state)"]
7519        pub const _01: Self = Self::new(1);
7520
7521        #[doc = "STALL response"]
7522        pub const _10: Self = Self::new(2);
7523
7524        #[doc = "STALL response"]
7525        pub const _11: Self = Self::new(3);
7526    }
7527}
7528#[doc(hidden)]
7529#[derive(Copy, Clone, Eq, PartialEq)]
7530pub struct Pipesel_SPEC;
7531impl crate::sealed::RegSpec for Pipesel_SPEC {
7532    type DataType = u16;
7533}
7534
7535#[doc = "Pipe Window Select Register"]
7536pub type Pipesel = crate::RegValueT<Pipesel_SPEC>;
7537
7538impl Pipesel {
7539    #[doc = "Pipe Window Select"]
7540    #[inline(always)]
7541    pub fn pipesel(
7542        self,
7543    ) -> crate::common::RegisterField<
7544        0,
7545        0xf,
7546        1,
7547        0,
7548        pipesel::Pipesel,
7549        pipesel::Pipesel,
7550        Pipesel_SPEC,
7551        crate::common::RW,
7552    > {
7553        crate::common::RegisterField::<
7554            0,
7555            0xf,
7556            1,
7557            0,
7558            pipesel::Pipesel,
7559            pipesel::Pipesel,
7560            Pipesel_SPEC,
7561            crate::common::RW,
7562        >::from_register(self, 0)
7563    }
7564}
7565impl ::core::default::Default for Pipesel {
7566    #[inline(always)]
7567    fn default() -> Pipesel {
7568        <crate::RegValueT<Pipesel_SPEC> as RegisterValue<_>>::new(0)
7569    }
7570}
7571pub mod pipesel {
7572
7573    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7574    pub struct Pipesel_SPEC;
7575    pub type Pipesel = crate::EnumBitfieldStruct<u8, Pipesel_SPEC>;
7576    impl Pipesel {
7577        #[doc = "No pipe selected"]
7578        pub const _0000: Self = Self::new(0);
7579
7580        #[doc = "PIPE1"]
7581        pub const _0001: Self = Self::new(1);
7582
7583        #[doc = "PIPE2"]
7584        pub const _0010: Self = Self::new(2);
7585
7586        #[doc = "PIPE3"]
7587        pub const _0011: Self = Self::new(3);
7588
7589        #[doc = "PIPE4"]
7590        pub const _0100: Self = Self::new(4);
7591
7592        #[doc = "PIPE5"]
7593        pub const _0101: Self = Self::new(5);
7594
7595        #[doc = "PIPE6"]
7596        pub const _0110: Self = Self::new(6);
7597
7598        #[doc = "PIPE7"]
7599        pub const _0111: Self = Self::new(7);
7600
7601        #[doc = "PIPE8"]
7602        pub const _1000: Self = Self::new(8);
7603
7604        #[doc = "PIPE9"]
7605        pub const _1001: Self = Self::new(9);
7606    }
7607}
7608#[doc(hidden)]
7609#[derive(Copy, Clone, Eq, PartialEq)]
7610pub struct Pipecfg_SPEC;
7611impl crate::sealed::RegSpec for Pipecfg_SPEC {
7612    type DataType = u16;
7613}
7614
7615#[doc = "Pipe Configuration Register"]
7616pub type Pipecfg = crate::RegValueT<Pipecfg_SPEC>;
7617
7618impl Pipecfg {
7619    #[doc = "Transfer Type"]
7620    #[inline(always)]
7621    pub fn r#type(
7622        self,
7623    ) -> crate::common::RegisterField<
7624        14,
7625        0x3,
7626        1,
7627        0,
7628        pipecfg::Type,
7629        pipecfg::Type,
7630        Pipecfg_SPEC,
7631        crate::common::RW,
7632    > {
7633        crate::common::RegisterField::<
7634            14,
7635            0x3,
7636            1,
7637            0,
7638            pipecfg::Type,
7639            pipecfg::Type,
7640            Pipecfg_SPEC,
7641            crate::common::RW,
7642        >::from_register(self, 0)
7643    }
7644
7645    #[doc = "BRDY Interrupt Operation Specification"]
7646    #[inline(always)]
7647    pub fn bfre(
7648        self,
7649    ) -> crate::common::RegisterField<
7650        10,
7651        0x1,
7652        1,
7653        0,
7654        pipecfg::Bfre,
7655        pipecfg::Bfre,
7656        Pipecfg_SPEC,
7657        crate::common::RW,
7658    > {
7659        crate::common::RegisterField::<
7660            10,
7661            0x1,
7662            1,
7663            0,
7664            pipecfg::Bfre,
7665            pipecfg::Bfre,
7666            Pipecfg_SPEC,
7667            crate::common::RW,
7668        >::from_register(self, 0)
7669    }
7670
7671    #[doc = "Double Buffer Mode"]
7672    #[inline(always)]
7673    pub fn dblb(
7674        self,
7675    ) -> crate::common::RegisterField<
7676        9,
7677        0x1,
7678        1,
7679        0,
7680        pipecfg::Dblb,
7681        pipecfg::Dblb,
7682        Pipecfg_SPEC,
7683        crate::common::RW,
7684    > {
7685        crate::common::RegisterField::<
7686            9,
7687            0x1,
7688            1,
7689            0,
7690            pipecfg::Dblb,
7691            pipecfg::Dblb,
7692            Pipecfg_SPEC,
7693            crate::common::RW,
7694        >::from_register(self, 0)
7695    }
7696
7697    #[doc = "Pipe Disabled at End of Transfer"]
7698    #[inline(always)]
7699    pub fn shtnak(
7700        self,
7701    ) -> crate::common::RegisterField<
7702        7,
7703        0x1,
7704        1,
7705        0,
7706        pipecfg::Shtnak,
7707        pipecfg::Shtnak,
7708        Pipecfg_SPEC,
7709        crate::common::RW,
7710    > {
7711        crate::common::RegisterField::<
7712            7,
7713            0x1,
7714            1,
7715            0,
7716            pipecfg::Shtnak,
7717            pipecfg::Shtnak,
7718            Pipecfg_SPEC,
7719            crate::common::RW,
7720        >::from_register(self, 0)
7721    }
7722
7723    #[doc = "Transfer Direction"]
7724    #[inline(always)]
7725    pub fn dir(
7726        self,
7727    ) -> crate::common::RegisterField<
7728        4,
7729        0x1,
7730        1,
7731        0,
7732        pipecfg::Dir,
7733        pipecfg::Dir,
7734        Pipecfg_SPEC,
7735        crate::common::RW,
7736    > {
7737        crate::common::RegisterField::<
7738            4,
7739            0x1,
7740            1,
7741            0,
7742            pipecfg::Dir,
7743            pipecfg::Dir,
7744            Pipecfg_SPEC,
7745            crate::common::RW,
7746        >::from_register(self, 0)
7747    }
7748
7749    #[doc = "Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe."]
7750    #[inline(always)]
7751    pub fn epnum(
7752        self,
7753    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, Pipecfg_SPEC, crate::common::RW> {
7754        crate::common::RegisterField::<0,0xf,1,0,u8,u8,Pipecfg_SPEC,crate::common::RW>::from_register(self,0)
7755    }
7756}
7757impl ::core::default::Default for Pipecfg {
7758    #[inline(always)]
7759    fn default() -> Pipecfg {
7760        <crate::RegValueT<Pipecfg_SPEC> as RegisterValue<_>>::new(0)
7761    }
7762}
7763pub mod pipecfg {
7764
7765    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7766    pub struct Type_SPEC;
7767    pub type Type = crate::EnumBitfieldStruct<u8, Type_SPEC>;
7768    impl Type {
7769        #[doc = "Pipe not used"]
7770        pub const _00: Self = Self::new(0);
7771
7772        #[doc = "Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9)"]
7773        pub const _01: Self = Self::new(1);
7774
7775        #[doc = "Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9)"]
7776        pub const _10: Self = Self::new(2);
7777
7778        #[doc = "Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9)"]
7779        pub const _11: Self = Self::new(3);
7780    }
7781    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7782    pub struct Bfre_SPEC;
7783    pub type Bfre = crate::EnumBitfieldStruct<u8, Bfre_SPEC>;
7784    impl Bfre {
7785        #[doc = "BRDY interrupt upon transmitting or receiving data"]
7786        pub const _0: Self = Self::new(0);
7787
7788        #[doc = "BRDY interrupt upon completion of reading data"]
7789        pub const _1: Self = Self::new(1);
7790    }
7791    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7792    pub struct Dblb_SPEC;
7793    pub type Dblb = crate::EnumBitfieldStruct<u8, Dblb_SPEC>;
7794    impl Dblb {
7795        #[doc = "Single buffer"]
7796        pub const _0: Self = Self::new(0);
7797
7798        #[doc = "Double buffer"]
7799        pub const _1: Self = Self::new(1);
7800    }
7801    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7802    pub struct Shtnak_SPEC;
7803    pub type Shtnak = crate::EnumBitfieldStruct<u8, Shtnak_SPEC>;
7804    impl Shtnak {
7805        #[doc = "Pipe assignment continued at the end of transfer"]
7806        pub const _0: Self = Self::new(0);
7807
7808        #[doc = "Pipe assignment disabled at the end of transfer"]
7809        pub const _1: Self = Self::new(1);
7810    }
7811    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7812    pub struct Dir_SPEC;
7813    pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
7814    impl Dir {
7815        #[doc = "Receiving direction"]
7816        pub const _0: Self = Self::new(0);
7817
7818        #[doc = "Transmitting direction"]
7819        pub const _1: Self = Self::new(1);
7820    }
7821}
7822#[doc(hidden)]
7823#[derive(Copy, Clone, Eq, PartialEq)]
7824pub struct Pipemaxp_SPEC;
7825impl crate::sealed::RegSpec for Pipemaxp_SPEC {
7826    type DataType = u16;
7827}
7828
7829#[doc = "Pipe Maximum Packet Size Register"]
7830pub type Pipemaxp = crate::RegValueT<Pipemaxp_SPEC>;
7831
7832impl Pipemaxp {
7833    #[doc = "Device Select"]
7834    #[inline(always)]
7835    pub fn devsel(
7836        self,
7837    ) -> crate::common::RegisterField<
7838        12,
7839        0xf,
7840        1,
7841        0,
7842        pipemaxp::Devsel,
7843        pipemaxp::Devsel,
7844        Pipemaxp_SPEC,
7845        crate::common::RW,
7846    > {
7847        crate::common::RegisterField::<
7848            12,
7849            0xf,
7850            1,
7851            0,
7852            pipemaxp::Devsel,
7853            pipemaxp::Devsel,
7854            Pipemaxp_SPEC,
7855            crate::common::RW,
7856        >::from_register(self, 0)
7857    }
7858
7859    #[doc = "Maximum Packet SizePIPE1 and PIPE2:  1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5:   8 bytes (008h), 16 bytes (010h),  32 bytes (020h), 64 bytes (040h)   (Bits \\[8:7\\] and \\[2:0\\] are not provided.)PIPE6 to PIPE9:  1 byte (001h) to 64 bytes (040h)  (Bits \\[8:7\\] are not provided.)"]
7860    #[inline(always)]
7861    pub fn mxps(
7862        self,
7863    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Pipemaxp_SPEC, crate::common::RW>
7864    {
7865        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Pipemaxp_SPEC,crate::common::RW>::from_register(self,0)
7866    }
7867}
7868impl ::core::default::Default for Pipemaxp {
7869    #[inline(always)]
7870    fn default() -> Pipemaxp {
7871        <crate::RegValueT<Pipemaxp_SPEC> as RegisterValue<_>>::new(0)
7872    }
7873}
7874pub mod pipemaxp {
7875
7876    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7877    pub struct Devsel_SPEC;
7878    pub type Devsel = crate::EnumBitfieldStruct<u8, Devsel_SPEC>;
7879    impl Devsel {
7880        #[doc = "Address 0000"]
7881        pub const _0000: Self = Self::new(0);
7882
7883        #[doc = "Address 0001"]
7884        pub const _0001: Self = Self::new(1);
7885
7886        #[doc = "Address 0010"]
7887        pub const _0010: Self = Self::new(2);
7888
7889        #[doc = "Address 0011"]
7890        pub const _0011: Self = Self::new(3);
7891
7892        #[doc = "Address 0100"]
7893        pub const _0100: Self = Self::new(4);
7894
7895        #[doc = "Address 0101"]
7896        pub const _0101: Self = Self::new(5);
7897    }
7898}
7899#[doc(hidden)]
7900#[derive(Copy, Clone, Eq, PartialEq)]
7901pub struct Pipeperi_SPEC;
7902impl crate::sealed::RegSpec for Pipeperi_SPEC {
7903    type DataType = u16;
7904}
7905
7906#[doc = "Pipe Cycle Control Register"]
7907pub type Pipeperi = crate::RegValueT<Pipeperi_SPEC>;
7908
7909impl Pipeperi {
7910    #[doc = "Isochronous IN Buffer Flush"]
7911    #[inline(always)]
7912    pub fn ifis(
7913        self,
7914    ) -> crate::common::RegisterField<
7915        12,
7916        0x1,
7917        1,
7918        0,
7919        pipeperi::Ifis,
7920        pipeperi::Ifis,
7921        Pipeperi_SPEC,
7922        crate::common::RW,
7923    > {
7924        crate::common::RegisterField::<
7925            12,
7926            0x1,
7927            1,
7928            0,
7929            pipeperi::Ifis,
7930            pipeperi::Ifis,
7931            Pipeperi_SPEC,
7932            crate::common::RW,
7933        >::from_register(self, 0)
7934    }
7935
7936    #[doc = "Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2."]
7937    #[inline(always)]
7938    pub fn iitv(
7939        self,
7940    ) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, Pipeperi_SPEC, crate::common::RW> {
7941        crate::common::RegisterField::<0,0x7,1,0,u8,u8,Pipeperi_SPEC,crate::common::RW>::from_register(self,0)
7942    }
7943}
7944impl ::core::default::Default for Pipeperi {
7945    #[inline(always)]
7946    fn default() -> Pipeperi {
7947        <crate::RegValueT<Pipeperi_SPEC> as RegisterValue<_>>::new(0)
7948    }
7949}
7950pub mod pipeperi {
7951
7952    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7953    pub struct Ifis_SPEC;
7954    pub type Ifis = crate::EnumBitfieldStruct<u8, Ifis_SPEC>;
7955    impl Ifis {
7956        #[doc = "The buffer is not flushed."]
7957        pub const _0: Self = Self::new(0);
7958
7959        #[doc = "The buffer is flushed."]
7960        pub const _1: Self = Self::new(1);
7961    }
7962}
7963#[doc(hidden)]
7964#[derive(Copy, Clone, Eq, PartialEq)]
7965pub struct Pipectr_SPEC;
7966impl crate::sealed::RegSpec for Pipectr_SPEC {
7967    type DataType = u16;
7968}
7969
7970#[doc = "Pipe %s Control Register"]
7971pub type Pipectr = crate::RegValueT<Pipectr_SPEC>;
7972
7973impl Pipectr {
7974    #[doc = "Buffer Status"]
7975    #[inline(always)]
7976    pub fn bsts(
7977        self,
7978    ) -> crate::common::RegisterField<
7979        15,
7980        0x1,
7981        1,
7982        0,
7983        pipectr::Bsts,
7984        pipectr::Bsts,
7985        Pipectr_SPEC,
7986        crate::common::R,
7987    > {
7988        crate::common::RegisterField::<
7989            15,
7990            0x1,
7991            1,
7992            0,
7993            pipectr::Bsts,
7994            pipectr::Bsts,
7995            Pipectr_SPEC,
7996            crate::common::R,
7997        >::from_register(self, 0)
7998    }
7999
8000    #[doc = "Auto Buffer Clear Mode"]
8001    #[inline(always)]
8002    pub fn aclrm(
8003        self,
8004    ) -> crate::common::RegisterField<
8005        9,
8006        0x1,
8007        1,
8008        0,
8009        pipectr::Aclrm,
8010        pipectr::Aclrm,
8011        Pipectr_SPEC,
8012        crate::common::RW,
8013    > {
8014        crate::common::RegisterField::<
8015            9,
8016            0x1,
8017            1,
8018            0,
8019            pipectr::Aclrm,
8020            pipectr::Aclrm,
8021            Pipectr_SPEC,
8022            crate::common::RW,
8023        >::from_register(self, 0)
8024    }
8025
8026    #[doc = "Sequence Toggle Bit Clear"]
8027    #[inline(always)]
8028    pub fn sqclr(
8029        self,
8030    ) -> crate::common::RegisterField<
8031        8,
8032        0x1,
8033        1,
8034        0,
8035        pipectr::Sqclr,
8036        pipectr::Sqclr,
8037        Pipectr_SPEC,
8038        crate::common::W,
8039    > {
8040        crate::common::RegisterField::<
8041            8,
8042            0x1,
8043            1,
8044            0,
8045            pipectr::Sqclr,
8046            pipectr::Sqclr,
8047            Pipectr_SPEC,
8048            crate::common::W,
8049        >::from_register(self, 0)
8050    }
8051
8052    #[doc = "Sequence Toggle Bit Set"]
8053    #[inline(always)]
8054    pub fn sqset(
8055        self,
8056    ) -> crate::common::RegisterField<
8057        7,
8058        0x1,
8059        1,
8060        0,
8061        pipectr::Sqset,
8062        pipectr::Sqset,
8063        Pipectr_SPEC,
8064        crate::common::W,
8065    > {
8066        crate::common::RegisterField::<
8067            7,
8068            0x1,
8069            1,
8070            0,
8071            pipectr::Sqset,
8072            pipectr::Sqset,
8073            Pipectr_SPEC,
8074            crate::common::W,
8075        >::from_register(self, 0)
8076    }
8077
8078    #[doc = "Sequence Toggle Bit Confirmation"]
8079    #[inline(always)]
8080    pub fn sqmon(
8081        self,
8082    ) -> crate::common::RegisterField<
8083        6,
8084        0x1,
8085        1,
8086        0,
8087        pipectr::Sqmon,
8088        pipectr::Sqmon,
8089        Pipectr_SPEC,
8090        crate::common::R,
8091    > {
8092        crate::common::RegisterField::<
8093            6,
8094            0x1,
8095            1,
8096            0,
8097            pipectr::Sqmon,
8098            pipectr::Sqmon,
8099            Pipectr_SPEC,
8100            crate::common::R,
8101        >::from_register(self, 0)
8102    }
8103
8104    #[doc = "Pipe Busy"]
8105    #[inline(always)]
8106    pub fn pbusy(
8107        self,
8108    ) -> crate::common::RegisterField<
8109        5,
8110        0x1,
8111        1,
8112        0,
8113        pipectr::Pbusy,
8114        pipectr::Pbusy,
8115        Pipectr_SPEC,
8116        crate::common::R,
8117    > {
8118        crate::common::RegisterField::<
8119            5,
8120            0x1,
8121            1,
8122            0,
8123            pipectr::Pbusy,
8124            pipectr::Pbusy,
8125            Pipectr_SPEC,
8126            crate::common::R,
8127        >::from_register(self, 0)
8128    }
8129
8130    #[doc = "Response PID"]
8131    #[inline(always)]
8132    pub fn pid(
8133        self,
8134    ) -> crate::common::RegisterField<
8135        0,
8136        0x3,
8137        1,
8138        0,
8139        pipectr::Pid,
8140        pipectr::Pid,
8141        Pipectr_SPEC,
8142        crate::common::RW,
8143    > {
8144        crate::common::RegisterField::<
8145            0,
8146            0x3,
8147            1,
8148            0,
8149            pipectr::Pid,
8150            pipectr::Pid,
8151            Pipectr_SPEC,
8152            crate::common::RW,
8153        >::from_register(self, 0)
8154    }
8155}
8156impl ::core::default::Default for Pipectr {
8157    #[inline(always)]
8158    fn default() -> Pipectr {
8159        <crate::RegValueT<Pipectr_SPEC> as RegisterValue<_>>::new(0)
8160    }
8161}
8162pub mod pipectr {
8163
8164    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8165    pub struct Bsts_SPEC;
8166    pub type Bsts = crate::EnumBitfieldStruct<u8, Bsts_SPEC>;
8167    impl Bsts {
8168        #[doc = "Buffer access is disabled."]
8169        pub const _0: Self = Self::new(0);
8170
8171        #[doc = "Buffer access is enabled."]
8172        pub const _1: Self = Self::new(1);
8173    }
8174    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8175    pub struct Aclrm_SPEC;
8176    pub type Aclrm = crate::EnumBitfieldStruct<u8, Aclrm_SPEC>;
8177    impl Aclrm {
8178        #[doc = "Auto buffer clear mode is disabled."]
8179        pub const _0: Self = Self::new(0);
8180
8181        #[doc = "Auto buffer clear mode is enabled (all buffers are initialized)"]
8182        pub const _1: Self = Self::new(1);
8183    }
8184    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8185    pub struct Sqclr_SPEC;
8186    pub type Sqclr = crate::EnumBitfieldStruct<u8, Sqclr_SPEC>;
8187    impl Sqclr {
8188        #[doc = "Invalid"]
8189        pub const _0: Self = Self::new(0);
8190
8191        #[doc = "Specifies DATA0."]
8192        pub const _1: Self = Self::new(1);
8193    }
8194    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8195    pub struct Sqset_SPEC;
8196    pub type Sqset = crate::EnumBitfieldStruct<u8, Sqset_SPEC>;
8197    impl Sqset {
8198        #[doc = "Invalid"]
8199        pub const _0: Self = Self::new(0);
8200
8201        #[doc = "Specifies DATA1."]
8202        pub const _1: Self = Self::new(1);
8203    }
8204    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8205    pub struct Sqmon_SPEC;
8206    pub type Sqmon = crate::EnumBitfieldStruct<u8, Sqmon_SPEC>;
8207    impl Sqmon {
8208        #[doc = "DATA0"]
8209        pub const _0: Self = Self::new(0);
8210
8211        #[doc = "DATA1"]
8212        pub const _1: Self = Self::new(1);
8213    }
8214    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8215    pub struct Pbusy_SPEC;
8216    pub type Pbusy = crate::EnumBitfieldStruct<u8, Pbusy_SPEC>;
8217    impl Pbusy {
8218        #[doc = "The relevant pipe is not used at the USB bus."]
8219        pub const _0: Self = Self::new(0);
8220
8221        #[doc = "The relevant pipe is used at the USB bus."]
8222        pub const _1: Self = Self::new(1);
8223    }
8224    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8225    pub struct Pid_SPEC;
8226    pub type Pid = crate::EnumBitfieldStruct<u8, Pid_SPEC>;
8227    impl Pid {
8228        #[doc = "NAK response"]
8229        pub const _00: Self = Self::new(0);
8230
8231        #[doc = "BUF response (depending on the buffer state)"]
8232        pub const _01: Self = Self::new(1);
8233
8234        #[doc = "STALL response"]
8235        pub const _10: Self = Self::new(2);
8236
8237        #[doc = "STALL response"]
8238        pub const _11: Self = Self::new(3);
8239    }
8240}
8241#[doc(hidden)]
8242#[derive(Copy, Clone, Eq, PartialEq)]
8243pub struct Pipetre_SPEC;
8244impl crate::sealed::RegSpec for Pipetre_SPEC {
8245    type DataType = u16;
8246}
8247
8248#[doc = "Pipe %s Transaction Counter Enable Register"]
8249pub type Pipetre = crate::RegValueT<Pipetre_SPEC>;
8250
8251impl Pipetre {
8252    #[doc = "Transaction Counter Enable"]
8253    #[inline(always)]
8254    pub fn trenb(
8255        self,
8256    ) -> crate::common::RegisterField<
8257        9,
8258        0x1,
8259        1,
8260        0,
8261        pipetre::Trenb,
8262        pipetre::Trenb,
8263        Pipetre_SPEC,
8264        crate::common::RW,
8265    > {
8266        crate::common::RegisterField::<
8267            9,
8268            0x1,
8269            1,
8270            0,
8271            pipetre::Trenb,
8272            pipetre::Trenb,
8273            Pipetre_SPEC,
8274            crate::common::RW,
8275        >::from_register(self, 0)
8276    }
8277
8278    #[doc = "Transaction Counter Clear"]
8279    #[inline(always)]
8280    pub fn trclr(
8281        self,
8282    ) -> crate::common::RegisterField<
8283        8,
8284        0x1,
8285        1,
8286        0,
8287        pipetre::Trclr,
8288        pipetre::Trclr,
8289        Pipetre_SPEC,
8290        crate::common::RW,
8291    > {
8292        crate::common::RegisterField::<
8293            8,
8294            0x1,
8295            1,
8296            0,
8297            pipetre::Trclr,
8298            pipetre::Trclr,
8299            Pipetre_SPEC,
8300            crate::common::RW,
8301        >::from_register(self, 0)
8302    }
8303}
8304impl ::core::default::Default for Pipetre {
8305    #[inline(always)]
8306    fn default() -> Pipetre {
8307        <crate::RegValueT<Pipetre_SPEC> as RegisterValue<_>>::new(0)
8308    }
8309}
8310pub mod pipetre {
8311
8312    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8313    pub struct Trenb_SPEC;
8314    pub type Trenb = crate::EnumBitfieldStruct<u8, Trenb_SPEC>;
8315    impl Trenb {
8316        #[doc = "Transaction counter is disabled."]
8317        pub const _0: Self = Self::new(0);
8318
8319        #[doc = "Transaction counter is enabled."]
8320        pub const _1: Self = Self::new(1);
8321    }
8322    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8323    pub struct Trclr_SPEC;
8324    pub type Trclr = crate::EnumBitfieldStruct<u8, Trclr_SPEC>;
8325    impl Trclr {
8326        #[doc = "Invalid"]
8327        pub const _0: Self = Self::new(0);
8328
8329        #[doc = "The current counter value is cleared."]
8330        pub const _1: Self = Self::new(1);
8331    }
8332}
8333#[doc(hidden)]
8334#[derive(Copy, Clone, Eq, PartialEq)]
8335pub struct Pipetrn_SPEC;
8336impl crate::sealed::RegSpec for Pipetrn_SPEC {
8337    type DataType = u16;
8338}
8339
8340#[doc = "Pipe %s Transaction Counter Register"]
8341pub type Pipetrn = crate::RegValueT<Pipetrn_SPEC>;
8342
8343impl Pipetrn {
8344    #[doc = "Transaction Counter"]
8345    #[inline(always)]
8346    pub fn trncnt(
8347        self,
8348    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Pipetrn_SPEC, crate::common::RW>
8349    {
8350        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Pipetrn_SPEC,crate::common::RW>::from_register(self,0)
8351    }
8352}
8353impl ::core::default::Default for Pipetrn {
8354    #[inline(always)]
8355    fn default() -> Pipetrn {
8356        <crate::RegValueT<Pipetrn_SPEC> as RegisterValue<_>>::new(0)
8357    }
8358}
8359
8360#[doc(hidden)]
8361#[derive(Copy, Clone, Eq, PartialEq)]
8362pub struct Devadd_SPEC;
8363impl crate::sealed::RegSpec for Devadd_SPEC {
8364    type DataType = u16;
8365}
8366
8367#[doc = "Device Address %s Configuration Register"]
8368pub type Devadd = crate::RegValueT<Devadd_SPEC>;
8369
8370impl Devadd {
8371    #[doc = "Transfer Speed of Communication Target Device"]
8372    #[inline(always)]
8373    pub fn usbspd(
8374        self,
8375    ) -> crate::common::RegisterField<
8376        6,
8377        0x3,
8378        1,
8379        0,
8380        devadd::Usbspd,
8381        devadd::Usbspd,
8382        Devadd_SPEC,
8383        crate::common::RW,
8384    > {
8385        crate::common::RegisterField::<
8386            6,
8387            0x3,
8388            1,
8389            0,
8390            devadd::Usbspd,
8391            devadd::Usbspd,
8392            Devadd_SPEC,
8393            crate::common::RW,
8394        >::from_register(self, 0)
8395    }
8396}
8397impl ::core::default::Default for Devadd {
8398    #[inline(always)]
8399    fn default() -> Devadd {
8400        <crate::RegValueT<Devadd_SPEC> as RegisterValue<_>>::new(0)
8401    }
8402}
8403pub mod devadd {
8404
8405    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8406    pub struct Usbspd_SPEC;
8407    pub type Usbspd = crate::EnumBitfieldStruct<u8, Usbspd_SPEC>;
8408    impl Usbspd {
8409        #[doc = "DEVADDn is not used"]
8410        pub const _00: Self = Self::new(0);
8411
8412        #[doc = "Low speed"]
8413        pub const _01: Self = Self::new(1);
8414
8415        #[doc = "Full speed"]
8416        pub const _10: Self = Self::new(2);
8417
8418        #[doc = "Setting prohibited"]
8419        pub const _11: Self = Self::new(3);
8420    }
8421}
8422#[doc(hidden)]
8423#[derive(Copy, Clone, Eq, PartialEq)]
8424pub struct Physlew_SPEC;
8425impl crate::sealed::RegSpec for Physlew_SPEC {
8426    type DataType = u32;
8427}
8428
8429#[doc = "PHY Cross Point Adjustment Register"]
8430pub type Physlew = crate::RegValueT<Physlew_SPEC>;
8431
8432impl Physlew {
8433    #[doc = "Receiver Cross Point Adjustment 01"]
8434    #[inline(always)]
8435    pub fn slewf01(
8436        self,
8437    ) -> crate::common::RegisterField<
8438        3,
8439        0x1,
8440        1,
8441        0,
8442        physlew::Slewf01,
8443        physlew::Slewf01,
8444        Physlew_SPEC,
8445        crate::common::RW,
8446    > {
8447        crate::common::RegisterField::<
8448            3,
8449            0x1,
8450            1,
8451            0,
8452            physlew::Slewf01,
8453            physlew::Slewf01,
8454            Physlew_SPEC,
8455            crate::common::RW,
8456        >::from_register(self, 0)
8457    }
8458
8459    #[doc = "Receiver Cross Point Adjustment 00"]
8460    #[inline(always)]
8461    pub fn slewf00(
8462        self,
8463    ) -> crate::common::RegisterField<
8464        2,
8465        0x1,
8466        1,
8467        0,
8468        physlew::Slewf00,
8469        physlew::Slewf00,
8470        Physlew_SPEC,
8471        crate::common::RW,
8472    > {
8473        crate::common::RegisterField::<
8474            2,
8475            0x1,
8476            1,
8477            0,
8478            physlew::Slewf00,
8479            physlew::Slewf00,
8480            Physlew_SPEC,
8481            crate::common::RW,
8482        >::from_register(self, 0)
8483    }
8484
8485    #[doc = "Receiver Cross Point Adjustment 01"]
8486    #[inline(always)]
8487    pub fn slewr01(
8488        self,
8489    ) -> crate::common::RegisterField<
8490        1,
8491        0x1,
8492        1,
8493        0,
8494        physlew::Slewr01,
8495        physlew::Slewr01,
8496        Physlew_SPEC,
8497        crate::common::RW,
8498    > {
8499        crate::common::RegisterField::<
8500            1,
8501            0x1,
8502            1,
8503            0,
8504            physlew::Slewr01,
8505            physlew::Slewr01,
8506            Physlew_SPEC,
8507            crate::common::RW,
8508        >::from_register(self, 0)
8509    }
8510
8511    #[doc = "Receiver Cross Point Adjustment 00"]
8512    #[inline(always)]
8513    pub fn slewr00(
8514        self,
8515    ) -> crate::common::RegisterField<
8516        0,
8517        0x1,
8518        1,
8519        0,
8520        physlew::Slewr00,
8521        physlew::Slewr00,
8522        Physlew_SPEC,
8523        crate::common::RW,
8524    > {
8525        crate::common::RegisterField::<
8526            0,
8527            0x1,
8528            1,
8529            0,
8530            physlew::Slewr00,
8531            physlew::Slewr00,
8532            Physlew_SPEC,
8533            crate::common::RW,
8534        >::from_register(self, 0)
8535    }
8536}
8537impl ::core::default::Default for Physlew {
8538    #[inline(always)]
8539    fn default() -> Physlew {
8540        <crate::RegValueT<Physlew_SPEC> as RegisterValue<_>>::new(14)
8541    }
8542}
8543pub mod physlew {
8544
8545    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8546    pub struct Slewf01_SPEC;
8547    pub type Slewf01 = crate::EnumBitfieldStruct<u8, Slewf01_SPEC>;
8548    impl Slewf01 {
8549        #[doc = "Reserved"]
8550        pub const _0: Self = Self::new(0);
8551
8552        #[doc = "Host or device controller mode."]
8553        pub const _1: Self = Self::new(1);
8554    }
8555    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8556    pub struct Slewf00_SPEC;
8557    pub type Slewf00 = crate::EnumBitfieldStruct<u8, Slewf00_SPEC>;
8558    impl Slewf00 {
8559        #[doc = "Reserved"]
8560        pub const _0: Self = Self::new(0);
8561
8562        #[doc = "Host or device controller mode."]
8563        pub const _1: Self = Self::new(1);
8564    }
8565    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8566    pub struct Slewr01_SPEC;
8567    pub type Slewr01 = crate::EnumBitfieldStruct<u8, Slewr01_SPEC>;
8568    impl Slewr01 {
8569        #[doc = "Reserved"]
8570        pub const _0: Self = Self::new(0);
8571
8572        #[doc = "Host or device controller mode."]
8573        pub const _1: Self = Self::new(1);
8574    }
8575    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8576    pub struct Slewr00_SPEC;
8577    pub type Slewr00 = crate::EnumBitfieldStruct<u8, Slewr00_SPEC>;
8578    impl Slewr00 {
8579        #[doc = "Reserved"]
8580        pub const _0: Self = Self::new(0);
8581
8582        #[doc = "Host or device controller mode."]
8583        pub const _1: Self = Self::new(1);
8584    }
8585}
8586#[doc(hidden)]
8587#[derive(Copy, Clone, Eq, PartialEq)]
8588pub struct Dpusr0R_SPEC;
8589impl crate::sealed::RegSpec for Dpusr0R_SPEC {
8590    type DataType = u32;
8591}
8592
8593#[doc = "Deep Software Standby USB Transceiver Control/Pin Monitor Register"]
8594pub type Dpusr0R = crate::RegValueT<Dpusr0R_SPEC>;
8595
8596impl Dpusr0R {
8597    #[doc = "USB VBUS InputIndicates the VBUS input signal of the USB."]
8598    #[inline(always)]
8599    pub fn dvbsts0(
8600        self,
8601    ) -> crate::common::RegisterFieldBool<23, 1, 0, Dpusr0R_SPEC, crate::common::R> {
8602        crate::common::RegisterFieldBool::<23, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
8603            self, 0,
8604        )
8605    }
8606
8607    #[doc = "USB OVRCURB InputIndicates the OVRCURB input signal of the USB."]
8608    #[inline(always)]
8609    pub fn dovcb0(
8610        self,
8611    ) -> crate::common::RegisterFieldBool<21, 1, 0, Dpusr0R_SPEC, crate::common::R> {
8612        crate::common::RegisterFieldBool::<21, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
8613            self, 0,
8614        )
8615    }
8616
8617    #[doc = "USB OVRCURA InputIndicates the OVRCURA input signal of the USB."]
8618    #[inline(always)]
8619    pub fn dovca0(
8620        self,
8621    ) -> crate::common::RegisterFieldBool<20, 1, 0, Dpusr0R_SPEC, crate::common::R> {
8622        crate::common::RegisterFieldBool::<20, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
8623            self, 0,
8624        )
8625    }
8626
8627    #[doc = "USB D-InputIndicates the D- input signal of the USB."]
8628    #[inline(always)]
8629    pub fn dm0(self) -> crate::common::RegisterFieldBool<17, 1, 0, Dpusr0R_SPEC, crate::common::R> {
8630        crate::common::RegisterFieldBool::<17, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
8631            self, 0,
8632        )
8633    }
8634
8635    #[doc = "USB0 D+ InputIndicates the D+ input signal of the USB."]
8636    #[inline(always)]
8637    pub fn dp0(self) -> crate::common::RegisterFieldBool<16, 1, 0, Dpusr0R_SPEC, crate::common::R> {
8638        crate::common::RegisterFieldBool::<16, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
8639            self, 0,
8640        )
8641    }
8642
8643    #[doc = "USB Transceiver Output Fix"]
8644    #[inline(always)]
8645    pub fn fixphy0(
8646        self,
8647    ) -> crate::common::RegisterField<
8648        4,
8649        0x1,
8650        1,
8651        0,
8652        dpusr0r::Fixphy0,
8653        dpusr0r::Fixphy0,
8654        Dpusr0R_SPEC,
8655        crate::common::RW,
8656    > {
8657        crate::common::RegisterField::<
8658            4,
8659            0x1,
8660            1,
8661            0,
8662            dpusr0r::Fixphy0,
8663            dpusr0r::Fixphy0,
8664            Dpusr0R_SPEC,
8665            crate::common::RW,
8666        >::from_register(self, 0)
8667    }
8668
8669    #[doc = "D+/D- Pull-Down Resistor Control"]
8670    #[inline(always)]
8671    pub fn drpd0(
8672        self,
8673    ) -> crate::common::RegisterField<
8674        3,
8675        0x1,
8676        1,
8677        0,
8678        dpusr0r::Drpd0,
8679        dpusr0r::Drpd0,
8680        Dpusr0R_SPEC,
8681        crate::common::RW,
8682    > {
8683        crate::common::RegisterField::<
8684            3,
8685            0x1,
8686            1,
8687            0,
8688            dpusr0r::Drpd0,
8689            dpusr0r::Drpd0,
8690            Dpusr0R_SPEC,
8691            crate::common::RW,
8692        >::from_register(self, 0)
8693    }
8694
8695    #[doc = "DP Pull-Up Resistor Control"]
8696    #[inline(always)]
8697    pub fn rpue0(
8698        self,
8699    ) -> crate::common::RegisterField<
8700        1,
8701        0x1,
8702        1,
8703        0,
8704        dpusr0r::Rpue0,
8705        dpusr0r::Rpue0,
8706        Dpusr0R_SPEC,
8707        crate::common::RW,
8708    > {
8709        crate::common::RegisterField::<
8710            1,
8711            0x1,
8712            1,
8713            0,
8714            dpusr0r::Rpue0,
8715            dpusr0r::Rpue0,
8716            Dpusr0R_SPEC,
8717            crate::common::RW,
8718        >::from_register(self, 0)
8719    }
8720
8721    #[doc = "USB Single End Receiver Control"]
8722    #[inline(always)]
8723    pub fn srpc0(
8724        self,
8725    ) -> crate::common::RegisterField<
8726        0,
8727        0x1,
8728        1,
8729        0,
8730        dpusr0r::Srpc0,
8731        dpusr0r::Srpc0,
8732        Dpusr0R_SPEC,
8733        crate::common::RW,
8734    > {
8735        crate::common::RegisterField::<
8736            0,
8737            0x1,
8738            1,
8739            0,
8740            dpusr0r::Srpc0,
8741            dpusr0r::Srpc0,
8742            Dpusr0R_SPEC,
8743            crate::common::RW,
8744        >::from_register(self, 0)
8745    }
8746}
8747impl ::core::default::Default for Dpusr0R {
8748    #[inline(always)]
8749    fn default() -> Dpusr0R {
8750        <crate::RegValueT<Dpusr0R_SPEC> as RegisterValue<_>>::new(0)
8751    }
8752}
8753pub mod dpusr0r {
8754
8755    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8756    pub struct Fixphy0_SPEC;
8757    pub type Fixphy0 = crate::EnumBitfieldStruct<u8, Fixphy0_SPEC>;
8758    impl Fixphy0 {
8759        #[doc = "The outputs are fixed in normal mode and on return from deep software standby mode."]
8760        pub const _0: Self = Self::new(0);
8761
8762        #[doc = "The outputs are fixed on transitions to deep software standby mode."]
8763        pub const _1: Self = Self::new(1);
8764    }
8765    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8766    pub struct Drpd0_SPEC;
8767    pub type Drpd0 = crate::EnumBitfieldStruct<u8, Drpd0_SPEC>;
8768    impl Drpd0 {
8769        #[doc = "Disables DP/DM pull-down resistor."]
8770        pub const _0: Self = Self::new(0);
8771
8772        #[doc = "Enables DP/DM pull-down resistor."]
8773        pub const _1: Self = Self::new(1);
8774    }
8775    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8776    pub struct Rpue0_SPEC;
8777    pub type Rpue0 = crate::EnumBitfieldStruct<u8, Rpue0_SPEC>;
8778    impl Rpue0 {
8779        #[doc = "Disables DP pull-up resistor."]
8780        pub const _0: Self = Self::new(0);
8781
8782        #[doc = "Enables DP pull-up resistor."]
8783        pub const _1: Self = Self::new(1);
8784    }
8785    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8786    pub struct Srpc0_SPEC;
8787    pub type Srpc0 = crate::EnumBitfieldStruct<u8, Srpc0_SPEC>;
8788    impl Srpc0 {
8789        #[doc = "Input through the DP and DM inputs is disabled."]
8790        pub const _0: Self = Self::new(0);
8791
8792        #[doc = "Input through the DP and DM inputs is enabled."]
8793        pub const _1: Self = Self::new(1);
8794    }
8795}
8796#[doc(hidden)]
8797#[derive(Copy, Clone, Eq, PartialEq)]
8798pub struct Dpusr1R_SPEC;
8799impl crate::sealed::RegSpec for Dpusr1R_SPEC {
8800    type DataType = u32;
8801}
8802
8803#[doc = "Deep Software Standby USB Suspend/Resume Interrupt Register"]
8804pub type Dpusr1R = crate::RegValueT<Dpusr1R_SPEC>;
8805
8806impl Dpusr1R {
8807    #[doc = "USB VBUS Interrupt Source Recovery"]
8808    #[inline(always)]
8809    pub fn dvbint0(
8810        self,
8811    ) -> crate::common::RegisterField<
8812        23,
8813        0x1,
8814        1,
8815        0,
8816        dpusr1r::Dvbint0,
8817        dpusr1r::Dvbint0,
8818        Dpusr1R_SPEC,
8819        crate::common::R,
8820    > {
8821        crate::common::RegisterField::<
8822            23,
8823            0x1,
8824            1,
8825            0,
8826            dpusr1r::Dvbint0,
8827            dpusr1r::Dvbint0,
8828            Dpusr1R_SPEC,
8829            crate::common::R,
8830        >::from_register(self, 0)
8831    }
8832
8833    #[doc = "USB OVRCURB Interrupt Source Recovery"]
8834    #[inline(always)]
8835    pub fn dovrcrb0(
8836        self,
8837    ) -> crate::common::RegisterField<
8838        21,
8839        0x1,
8840        1,
8841        0,
8842        dpusr1r::Dovrcrb0,
8843        dpusr1r::Dovrcrb0,
8844        Dpusr1R_SPEC,
8845        crate::common::R,
8846    > {
8847        crate::common::RegisterField::<
8848            21,
8849            0x1,
8850            1,
8851            0,
8852            dpusr1r::Dovrcrb0,
8853            dpusr1r::Dovrcrb0,
8854            Dpusr1R_SPEC,
8855            crate::common::R,
8856        >::from_register(self, 0)
8857    }
8858
8859    #[doc = "USB OVRCURA Interrupt Source Recovery"]
8860    #[inline(always)]
8861    pub fn dovrcra0(
8862        self,
8863    ) -> crate::common::RegisterField<
8864        20,
8865        0x1,
8866        1,
8867        0,
8868        dpusr1r::Dovrcra0,
8869        dpusr1r::Dovrcra0,
8870        Dpusr1R_SPEC,
8871        crate::common::R,
8872    > {
8873        crate::common::RegisterField::<
8874            20,
8875            0x1,
8876            1,
8877            0,
8878            dpusr1r::Dovrcra0,
8879            dpusr1r::Dovrcra0,
8880            Dpusr1R_SPEC,
8881            crate::common::R,
8882        >::from_register(self, 0)
8883    }
8884
8885    #[doc = "USB DM Interrupt Source Recovery"]
8886    #[inline(always)]
8887    pub fn dmint0(
8888        self,
8889    ) -> crate::common::RegisterField<
8890        17,
8891        0x1,
8892        1,
8893        0,
8894        dpusr1r::Dmint0,
8895        dpusr1r::Dmint0,
8896        Dpusr1R_SPEC,
8897        crate::common::R,
8898    > {
8899        crate::common::RegisterField::<
8900            17,
8901            0x1,
8902            1,
8903            0,
8904            dpusr1r::Dmint0,
8905            dpusr1r::Dmint0,
8906            Dpusr1R_SPEC,
8907            crate::common::R,
8908        >::from_register(self, 0)
8909    }
8910
8911    #[doc = "USB DP Interrupt Source Recovery"]
8912    #[inline(always)]
8913    pub fn dpint0(
8914        self,
8915    ) -> crate::common::RegisterField<
8916        16,
8917        0x1,
8918        1,
8919        0,
8920        dpusr1r::Dpint0,
8921        dpusr1r::Dpint0,
8922        Dpusr1R_SPEC,
8923        crate::common::R,
8924    > {
8925        crate::common::RegisterField::<
8926            16,
8927            0x1,
8928            1,
8929            0,
8930            dpusr1r::Dpint0,
8931            dpusr1r::Dpint0,
8932            Dpusr1R_SPEC,
8933            crate::common::R,
8934        >::from_register(self, 0)
8935    }
8936
8937    #[doc = "USB VBUS Interrupt Enable/Clear"]
8938    #[inline(always)]
8939    pub fn dvbse0(
8940        self,
8941    ) -> crate::common::RegisterField<
8942        7,
8943        0x1,
8944        1,
8945        0,
8946        dpusr1r::Dvbse0,
8947        dpusr1r::Dvbse0,
8948        Dpusr1R_SPEC,
8949        crate::common::RW,
8950    > {
8951        crate::common::RegisterField::<
8952            7,
8953            0x1,
8954            1,
8955            0,
8956            dpusr1r::Dvbse0,
8957            dpusr1r::Dvbse0,
8958            Dpusr1R_SPEC,
8959            crate::common::RW,
8960        >::from_register(self, 0)
8961    }
8962
8963    #[doc = "USB OVRCURB Interrupt Enable/Clear"]
8964    #[inline(always)]
8965    pub fn dovrcrbe0(
8966        self,
8967    ) -> crate::common::RegisterField<
8968        5,
8969        0x1,
8970        1,
8971        0,
8972        dpusr1r::Dovrcrbe0,
8973        dpusr1r::Dovrcrbe0,
8974        Dpusr1R_SPEC,
8975        crate::common::RW,
8976    > {
8977        crate::common::RegisterField::<
8978            5,
8979            0x1,
8980            1,
8981            0,
8982            dpusr1r::Dovrcrbe0,
8983            dpusr1r::Dovrcrbe0,
8984            Dpusr1R_SPEC,
8985            crate::common::RW,
8986        >::from_register(self, 0)
8987    }
8988
8989    #[doc = "USB OVRCURA Interrupt Enable/Clear"]
8990    #[inline(always)]
8991    pub fn dovrcrae0(
8992        self,
8993    ) -> crate::common::RegisterField<
8994        4,
8995        0x1,
8996        1,
8997        0,
8998        dpusr1r::Dovrcrae0,
8999        dpusr1r::Dovrcrae0,
9000        Dpusr1R_SPEC,
9001        crate::common::RW,
9002    > {
9003        crate::common::RegisterField::<
9004            4,
9005            0x1,
9006            1,
9007            0,
9008            dpusr1r::Dovrcrae0,
9009            dpusr1r::Dovrcrae0,
9010            Dpusr1R_SPEC,
9011            crate::common::RW,
9012        >::from_register(self, 0)
9013    }
9014
9015    #[doc = "USB DM Interrupt Enable/Clear"]
9016    #[inline(always)]
9017    pub fn dminte0(
9018        self,
9019    ) -> crate::common::RegisterField<
9020        1,
9021        0x1,
9022        1,
9023        0,
9024        dpusr1r::Dminte0,
9025        dpusr1r::Dminte0,
9026        Dpusr1R_SPEC,
9027        crate::common::RW,
9028    > {
9029        crate::common::RegisterField::<
9030            1,
9031            0x1,
9032            1,
9033            0,
9034            dpusr1r::Dminte0,
9035            dpusr1r::Dminte0,
9036            Dpusr1R_SPEC,
9037            crate::common::RW,
9038        >::from_register(self, 0)
9039    }
9040
9041    #[doc = "USB DP Interrupt Enable/Clear"]
9042    #[inline(always)]
9043    pub fn dpinte0(
9044        self,
9045    ) -> crate::common::RegisterField<
9046        0,
9047        0x1,
9048        1,
9049        0,
9050        dpusr1r::Dpinte0,
9051        dpusr1r::Dpinte0,
9052        Dpusr1R_SPEC,
9053        crate::common::RW,
9054    > {
9055        crate::common::RegisterField::<
9056            0,
9057            0x1,
9058            1,
9059            0,
9060            dpusr1r::Dpinte0,
9061            dpusr1r::Dpinte0,
9062            Dpusr1R_SPEC,
9063            crate::common::RW,
9064        >::from_register(self, 0)
9065    }
9066}
9067impl ::core::default::Default for Dpusr1R {
9068    #[inline(always)]
9069    fn default() -> Dpusr1R {
9070        <crate::RegValueT<Dpusr1R_SPEC> as RegisterValue<_>>::new(0)
9071    }
9072}
9073pub mod dpusr1r {
9074
9075    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9076    pub struct Dvbint0_SPEC;
9077    pub type Dvbint0 = crate::EnumBitfieldStruct<u8, Dvbint0_SPEC>;
9078    impl Dvbint0 {
9079        #[doc = "The system has not returned from deep software standby mode."]
9080        pub const _0: Self = Self::new(0);
9081
9082        #[doc = "The system has returned from deep software standby mode."]
9083        pub const _1: Self = Self::new(1);
9084    }
9085    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9086    pub struct Dovrcrb0_SPEC;
9087    pub type Dovrcrb0 = crate::EnumBitfieldStruct<u8, Dovrcrb0_SPEC>;
9088    impl Dovrcrb0 {
9089        #[doc = "The system has not returned from deep software standby mode."]
9090        pub const _0: Self = Self::new(0);
9091
9092        #[doc = "The system has returned from deep software standby mode."]
9093        pub const _1: Self = Self::new(1);
9094    }
9095    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9096    pub struct Dovrcra0_SPEC;
9097    pub type Dovrcra0 = crate::EnumBitfieldStruct<u8, Dovrcra0_SPEC>;
9098    impl Dovrcra0 {
9099        #[doc = "The system has not returned from deep software standby mode."]
9100        pub const _0: Self = Self::new(0);
9101
9102        #[doc = "The system has returned from deep software standby mode."]
9103        pub const _1: Self = Self::new(1);
9104    }
9105    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9106    pub struct Dmint0_SPEC;
9107    pub type Dmint0 = crate::EnumBitfieldStruct<u8, Dmint0_SPEC>;
9108    impl Dmint0 {
9109        #[doc = "The system has not returned from deep software standby mode."]
9110        pub const _0: Self = Self::new(0);
9111
9112        #[doc = "The system has returned from deep software standby mode."]
9113        pub const _1: Self = Self::new(1);
9114    }
9115    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9116    pub struct Dpint0_SPEC;
9117    pub type Dpint0 = crate::EnumBitfieldStruct<u8, Dpint0_SPEC>;
9118    impl Dpint0 {
9119        #[doc = "The system has not returned from deep software standby mode."]
9120        pub const _0: Self = Self::new(0);
9121
9122        #[doc = "The system has returned from deep software standby mode."]
9123        pub const _1: Self = Self::new(1);
9124    }
9125    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9126    pub struct Dvbse0_SPEC;
9127    pub type Dvbse0 = crate::EnumBitfieldStruct<u8, Dvbse0_SPEC>;
9128    impl Dvbse0 {
9129        #[doc = "Recovery from deep software standby mode is disabled."]
9130        pub const _0: Self = Self::new(0);
9131
9132        #[doc = "Recovery from deep software standby mode is enabled."]
9133        pub const _1: Self = Self::new(1);
9134    }
9135    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9136    pub struct Dovrcrbe0_SPEC;
9137    pub type Dovrcrbe0 = crate::EnumBitfieldStruct<u8, Dovrcrbe0_SPEC>;
9138    impl Dovrcrbe0 {
9139        #[doc = "Recovery from deep software standby mode is disabled."]
9140        pub const _0: Self = Self::new(0);
9141
9142        #[doc = "Recovery from deep software standby mode is enabled."]
9143        pub const _1: Self = Self::new(1);
9144    }
9145    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9146    pub struct Dovrcrae0_SPEC;
9147    pub type Dovrcrae0 = crate::EnumBitfieldStruct<u8, Dovrcrae0_SPEC>;
9148    impl Dovrcrae0 {
9149        #[doc = "Recovery from deep software standby mode is disabled."]
9150        pub const _0: Self = Self::new(0);
9151
9152        #[doc = "Recovery from deep software standby mode is enabled."]
9153        pub const _1: Self = Self::new(1);
9154    }
9155    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9156    pub struct Dminte0_SPEC;
9157    pub type Dminte0 = crate::EnumBitfieldStruct<u8, Dminte0_SPEC>;
9158    impl Dminte0 {
9159        #[doc = "Recovery from deep software standby mode is disabled."]
9160        pub const _0: Self = Self::new(0);
9161
9162        #[doc = "Recovery from deep software standby mode is enabled."]
9163        pub const _1: Self = Self::new(1);
9164    }
9165    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9166    pub struct Dpinte0_SPEC;
9167    pub type Dpinte0 = crate::EnumBitfieldStruct<u8, Dpinte0_SPEC>;
9168    impl Dpinte0 {
9169        #[doc = "Recovery from deep software standby mode is disabled."]
9170        pub const _0: Self = Self::new(0);
9171
9172        #[doc = "Recovery from deep software standby mode is enabled."]
9173        pub const _1: Self = Self::new(1);
9174    }
9175}