ra6m2_pac/
iic1.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:11:44 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Inter-Integrated Circuit 1"]
28unsafe impl ::core::marker::Send for super::Iic1 {}
29unsafe impl ::core::marker::Sync for super::Iic1 {}
30impl super::Iic1 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "I2C Bus Control Register 1"]
38    #[inline(always)]
39    pub const fn iccr1(&self) -> &'static crate::common::Reg<self::Iccr1_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Iccr1_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "I2C Bus Control Register 2"]
48    #[inline(always)]
49    pub const fn iccr2(&self) -> &'static crate::common::Reg<self::Iccr2_SPEC, crate::common::RW> {
50        unsafe {
51            crate::common::Reg::<self::Iccr2_SPEC, crate::common::RW>::from_ptr(
52                self._svd2pac_as_ptr().add(1usize),
53            )
54        }
55    }
56
57    #[doc = "I2C Bus Mode Register 1"]
58    #[inline(always)]
59    pub const fn icmr1(&self) -> &'static crate::common::Reg<self::Icmr1_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Icmr1_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(2usize),
63            )
64        }
65    }
66
67    #[doc = "I2C Bus Mode Register 2"]
68    #[inline(always)]
69    pub const fn icmr2(&self) -> &'static crate::common::Reg<self::Icmr2_SPEC, crate::common::RW> {
70        unsafe {
71            crate::common::Reg::<self::Icmr2_SPEC, crate::common::RW>::from_ptr(
72                self._svd2pac_as_ptr().add(3usize),
73            )
74        }
75    }
76
77    #[doc = "I2C Bus Mode Register 3"]
78    #[inline(always)]
79    pub const fn icmr3(&self) -> &'static crate::common::Reg<self::Icmr3_SPEC, crate::common::RW> {
80        unsafe {
81            crate::common::Reg::<self::Icmr3_SPEC, crate::common::RW>::from_ptr(
82                self._svd2pac_as_ptr().add(4usize),
83            )
84        }
85    }
86
87    #[doc = "I2C Bus Function Enable Register"]
88    #[inline(always)]
89    pub const fn icfer(&self) -> &'static crate::common::Reg<self::Icfer_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::Icfer_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(5usize),
93            )
94        }
95    }
96
97    #[doc = "I2C Bus Status Enable Register"]
98    #[inline(always)]
99    pub const fn icser(&self) -> &'static crate::common::Reg<self::Icser_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::Icser_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(6usize),
103            )
104        }
105    }
106
107    #[doc = "I2C Bus Interrupt Enable Register"]
108    #[inline(always)]
109    pub const fn icier(&self) -> &'static crate::common::Reg<self::Icier_SPEC, crate::common::RW> {
110        unsafe {
111            crate::common::Reg::<self::Icier_SPEC, crate::common::RW>::from_ptr(
112                self._svd2pac_as_ptr().add(7usize),
113            )
114        }
115    }
116
117    #[doc = "I2C Bus Status Register 1"]
118    #[inline(always)]
119    pub const fn icsr1(&self) -> &'static crate::common::Reg<self::Icsr1_SPEC, crate::common::RW> {
120        unsafe {
121            crate::common::Reg::<self::Icsr1_SPEC, crate::common::RW>::from_ptr(
122                self._svd2pac_as_ptr().add(8usize),
123            )
124        }
125    }
126
127    #[doc = "I2C Bus Status Register 2"]
128    #[inline(always)]
129    pub const fn icsr2(&self) -> &'static crate::common::Reg<self::Icsr2_SPEC, crate::common::RW> {
130        unsafe {
131            crate::common::Reg::<self::Icsr2_SPEC, crate::common::RW>::from_ptr(
132                self._svd2pac_as_ptr().add(9usize),
133            )
134        }
135    }
136
137    #[doc = "Slave Address Register L%s"]
138    #[inline(always)]
139    pub const fn sarl(
140        &self,
141    ) -> &'static crate::common::ClusterRegisterArray<
142        crate::common::Reg<self::Sarl_SPEC, crate::common::RW>,
143        3,
144        0x2,
145    > {
146        unsafe {
147            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xausize))
148        }
149    }
150    #[inline(always)]
151    pub const fn sarl0(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
152        unsafe {
153            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
154                self._svd2pac_as_ptr().add(0xausize),
155            )
156        }
157    }
158    #[inline(always)]
159    pub const fn sarl1(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
160        unsafe {
161            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
162                self._svd2pac_as_ptr().add(0xcusize),
163            )
164        }
165    }
166    #[inline(always)]
167    pub const fn sarl2(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
168        unsafe {
169            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
170                self._svd2pac_as_ptr().add(0xeusize),
171            )
172        }
173    }
174
175    #[doc = "Slave Address Register U%s"]
176    #[inline(always)]
177    pub const fn saru(
178        &self,
179    ) -> &'static crate::common::ClusterRegisterArray<
180        crate::common::Reg<self::Saru_SPEC, crate::common::RW>,
181        3,
182        0x2,
183    > {
184        unsafe {
185            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xbusize))
186        }
187    }
188    #[inline(always)]
189    pub const fn saru0(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
190        unsafe {
191            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
192                self._svd2pac_as_ptr().add(0xbusize),
193            )
194        }
195    }
196    #[inline(always)]
197    pub const fn saru1(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
198        unsafe {
199            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
200                self._svd2pac_as_ptr().add(0xdusize),
201            )
202        }
203    }
204    #[inline(always)]
205    pub const fn saru2(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
206        unsafe {
207            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
208                self._svd2pac_as_ptr().add(0xfusize),
209            )
210        }
211    }
212
213    #[doc = "I2C Bus Bit Rate Low-Level Register"]
214    #[inline(always)]
215    pub const fn icbrl(&self) -> &'static crate::common::Reg<self::Icbrl_SPEC, crate::common::RW> {
216        unsafe {
217            crate::common::Reg::<self::Icbrl_SPEC, crate::common::RW>::from_ptr(
218                self._svd2pac_as_ptr().add(16usize),
219            )
220        }
221    }
222
223    #[doc = "I2C Bus Bit Rate High-Level Register"]
224    #[inline(always)]
225    pub const fn icbrh(&self) -> &'static crate::common::Reg<self::Icbrh_SPEC, crate::common::RW> {
226        unsafe {
227            crate::common::Reg::<self::Icbrh_SPEC, crate::common::RW>::from_ptr(
228                self._svd2pac_as_ptr().add(17usize),
229            )
230        }
231    }
232
233    #[doc = "I2C Bus Transmit Data Register"]
234    #[inline(always)]
235    pub const fn icdrt(&self) -> &'static crate::common::Reg<self::Icdrt_SPEC, crate::common::RW> {
236        unsafe {
237            crate::common::Reg::<self::Icdrt_SPEC, crate::common::RW>::from_ptr(
238                self._svd2pac_as_ptr().add(18usize),
239            )
240        }
241    }
242
243    #[doc = "I2C Bus Receive Data Register"]
244    #[inline(always)]
245    pub const fn icdrr(&self) -> &'static crate::common::Reg<self::Icdrr_SPEC, crate::common::R> {
246        unsafe {
247            crate::common::Reg::<self::Icdrr_SPEC, crate::common::R>::from_ptr(
248                self._svd2pac_as_ptr().add(19usize),
249            )
250        }
251    }
252}
253#[doc(hidden)]
254#[derive(Copy, Clone, Eq, PartialEq)]
255pub struct Iccr1_SPEC;
256impl crate::sealed::RegSpec for Iccr1_SPEC {
257    type DataType = u8;
258}
259
260#[doc = "I2C Bus Control Register 1"]
261pub type Iccr1 = crate::RegValueT<Iccr1_SPEC>;
262
263impl Iccr1 {
264    #[doc = "I2C Bus Interface Enable"]
265    #[inline(always)]
266    pub fn ice(
267        self,
268    ) -> crate::common::RegisterField<
269        7,
270        0x1,
271        1,
272        0,
273        iccr1::Ice,
274        iccr1::Ice,
275        Iccr1_SPEC,
276        crate::common::RW,
277    > {
278        crate::common::RegisterField::<
279            7,
280            0x1,
281            1,
282            0,
283            iccr1::Ice,
284            iccr1::Ice,
285            Iccr1_SPEC,
286            crate::common::RW,
287        >::from_register(self, 0)
288    }
289
290    #[doc = "I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information)."]
291    #[inline(always)]
292    pub fn iicrst(
293        self,
294    ) -> crate::common::RegisterField<
295        6,
296        0x1,
297        1,
298        0,
299        iccr1::Iicrst,
300        iccr1::Iicrst,
301        Iccr1_SPEC,
302        crate::common::RW,
303    > {
304        crate::common::RegisterField::<
305            6,
306            0x1,
307            1,
308            0,
309            iccr1::Iicrst,
310            iccr1::Iicrst,
311            Iccr1_SPEC,
312            crate::common::RW,
313        >::from_register(self, 0)
314    }
315
316    #[doc = "Extra SCL Clock Cycle Output"]
317    #[inline(always)]
318    pub fn clo(
319        self,
320    ) -> crate::common::RegisterField<
321        5,
322        0x1,
323        1,
324        0,
325        iccr1::Clo,
326        iccr1::Clo,
327        Iccr1_SPEC,
328        crate::common::RW,
329    > {
330        crate::common::RegisterField::<
331            5,
332            0x1,
333            1,
334            0,
335            iccr1::Clo,
336            iccr1::Clo,
337            Iccr1_SPEC,
338            crate::common::RW,
339        >::from_register(self, 0)
340    }
341
342    #[doc = "SCLO/SDAO Write Protect"]
343    #[inline(always)]
344    pub fn sowp(
345        self,
346    ) -> crate::common::RegisterField<
347        4,
348        0x1,
349        1,
350        0,
351        iccr1::Sowp,
352        iccr1::Sowp,
353        Iccr1_SPEC,
354        crate::common::W,
355    > {
356        crate::common::RegisterField::<
357            4,
358            0x1,
359            1,
360            0,
361            iccr1::Sowp,
362            iccr1::Sowp,
363            Iccr1_SPEC,
364            crate::common::W,
365        >::from_register(self, 0)
366    }
367
368    #[doc = "SCL Output Control/Monitor"]
369    #[inline(always)]
370    pub fn sclo(
371        self,
372    ) -> crate::common::RegisterField<
373        3,
374        0x1,
375        1,
376        0,
377        iccr1::Sclo,
378        iccr1::Sclo,
379        Iccr1_SPEC,
380        crate::common::RW,
381    > {
382        crate::common::RegisterField::<
383            3,
384            0x1,
385            1,
386            0,
387            iccr1::Sclo,
388            iccr1::Sclo,
389            Iccr1_SPEC,
390            crate::common::RW,
391        >::from_register(self, 0)
392    }
393
394    #[doc = "SDA Output Control/Monitor"]
395    #[inline(always)]
396    pub fn sdao(
397        self,
398    ) -> crate::common::RegisterField<
399        2,
400        0x1,
401        1,
402        0,
403        iccr1::Sdao,
404        iccr1::Sdao,
405        Iccr1_SPEC,
406        crate::common::RW,
407    > {
408        crate::common::RegisterField::<
409            2,
410            0x1,
411            1,
412            0,
413            iccr1::Sdao,
414            iccr1::Sdao,
415            Iccr1_SPEC,
416            crate::common::RW,
417        >::from_register(self, 0)
418    }
419
420    #[doc = "SCL Line Monitor"]
421    #[inline(always)]
422    pub fn scli(
423        self,
424    ) -> crate::common::RegisterField<
425        1,
426        0x1,
427        1,
428        0,
429        iccr1::Scli,
430        iccr1::Scli,
431        Iccr1_SPEC,
432        crate::common::R,
433    > {
434        crate::common::RegisterField::<
435            1,
436            0x1,
437            1,
438            0,
439            iccr1::Scli,
440            iccr1::Scli,
441            Iccr1_SPEC,
442            crate::common::R,
443        >::from_register(self, 0)
444    }
445
446    #[doc = "SDA Line Monitor"]
447    #[inline(always)]
448    pub fn sdai(
449        self,
450    ) -> crate::common::RegisterField<
451        0,
452        0x1,
453        1,
454        0,
455        iccr1::Sdai,
456        iccr1::Sdai,
457        Iccr1_SPEC,
458        crate::common::R,
459    > {
460        crate::common::RegisterField::<
461            0,
462            0x1,
463            1,
464            0,
465            iccr1::Sdai,
466            iccr1::Sdai,
467            Iccr1_SPEC,
468            crate::common::R,
469        >::from_register(self, 0)
470    }
471}
472impl ::core::default::Default for Iccr1 {
473    #[inline(always)]
474    fn default() -> Iccr1 {
475        <crate::RegValueT<Iccr1_SPEC> as RegisterValue<_>>::new(31)
476    }
477}
478pub mod iccr1 {
479
480    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
481    pub struct Ice_SPEC;
482    pub type Ice = crate::EnumBitfieldStruct<u8, Ice_SPEC>;
483    impl Ice {
484        #[doc = "Disable (SCLn and SDAn pins in inactive state)"]
485        pub const _0: Self = Self::new(0);
486
487        #[doc = "Enable (SCLn and SDAn pins in active state)"]
488        pub const _1: Self = Self::new(1);
489    }
490    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
491    pub struct Iicrst_SPEC;
492    pub type Iicrst = crate::EnumBitfieldStruct<u8, Iicrst_SPEC>;
493    impl Iicrst {
494        #[doc = "Releases the RIIC reset or internal reset."]
495        pub const _0: Self = Self::new(0);
496
497        #[doc = "Initiates the RIIC reset or internal reset."]
498        pub const _1: Self = Self::new(1);
499    }
500    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
501    pub struct Clo_SPEC;
502    pub type Clo = crate::EnumBitfieldStruct<u8, Clo_SPEC>;
503    impl Clo {
504        #[doc = "Does not output an extra SCL clock cycle."]
505        pub const _0: Self = Self::new(0);
506
507        #[doc = "Outputs an extra SCL clock cycle."]
508        pub const _1: Self = Self::new(1);
509    }
510    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
511    pub struct Sowp_SPEC;
512    pub type Sowp = crate::EnumBitfieldStruct<u8, Sowp_SPEC>;
513    impl Sowp {
514        #[doc = "Enables a value to be written in SCLO bit and SDAO bit."]
515        pub const _0: Self = Self::new(0);
516
517        #[doc = "Disables a value to be written in SCLO bit and SDAO bit."]
518        pub const _1: Self = Self::new(1);
519    }
520    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
521    pub struct Sclo_SPEC;
522    pub type Sclo = crate::EnumBitfieldStruct<u8, Sclo_SPEC>;
523    impl Sclo {
524        #[doc = "(Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low."]
525        pub const _0: Self = Self::new(0);
526
527        #[doc = "(Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin."]
528        pub const _1: Self = Self::new(1);
529    }
530    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
531    pub struct Sdao_SPEC;
532    pub type Sdao = crate::EnumBitfieldStruct<u8, Sdao_SPEC>;
533    impl Sdao {
534        #[doc = "(Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low."]
535        pub const _0: Self = Self::new(0);
536
537        #[doc = "(Read)The RIIC has released the SDAn pin./  (Write)The RIIC releases the SDAn pin."]
538        pub const _1: Self = Self::new(1);
539    }
540    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
541    pub struct Scli_SPEC;
542    pub type Scli = crate::EnumBitfieldStruct<u8, Scli_SPEC>;
543    impl Scli {
544        #[doc = "SCLn line is low."]
545        pub const _0: Self = Self::new(0);
546
547        #[doc = "SCLn line is high."]
548        pub const _1: Self = Self::new(1);
549    }
550    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
551    pub struct Sdai_SPEC;
552    pub type Sdai = crate::EnumBitfieldStruct<u8, Sdai_SPEC>;
553    impl Sdai {
554        #[doc = "SDAn line is low."]
555        pub const _0: Self = Self::new(0);
556
557        #[doc = "SDAn line is high."]
558        pub const _1: Self = Self::new(1);
559    }
560}
561#[doc(hidden)]
562#[derive(Copy, Clone, Eq, PartialEq)]
563pub struct Iccr2_SPEC;
564impl crate::sealed::RegSpec for Iccr2_SPEC {
565    type DataType = u8;
566}
567
568#[doc = "I2C Bus Control Register 2"]
569pub type Iccr2 = crate::RegValueT<Iccr2_SPEC>;
570
571impl Iccr2 {
572    #[doc = "Bus Busy Detection Flag"]
573    #[inline(always)]
574    pub fn bbsy(
575        self,
576    ) -> crate::common::RegisterField<
577        7,
578        0x1,
579        1,
580        0,
581        iccr2::Bbsy,
582        iccr2::Bbsy,
583        Iccr2_SPEC,
584        crate::common::R,
585    > {
586        crate::common::RegisterField::<
587            7,
588            0x1,
589            1,
590            0,
591            iccr2::Bbsy,
592            iccr2::Bbsy,
593            Iccr2_SPEC,
594            crate::common::R,
595        >::from_register(self, 0)
596    }
597
598    #[doc = "Master/Slave Mode"]
599    #[inline(always)]
600    pub fn mst(
601        self,
602    ) -> crate::common::RegisterField<
603        6,
604        0x1,
605        1,
606        0,
607        iccr2::Mst,
608        iccr2::Mst,
609        Iccr2_SPEC,
610        crate::common::RW,
611    > {
612        crate::common::RegisterField::<
613            6,
614            0x1,
615            1,
616            0,
617            iccr2::Mst,
618            iccr2::Mst,
619            Iccr2_SPEC,
620            crate::common::RW,
621        >::from_register(self, 0)
622    }
623
624    #[doc = "Transmit/Receive Mode"]
625    #[inline(always)]
626    pub fn trs(
627        self,
628    ) -> crate::common::RegisterField<
629        5,
630        0x1,
631        1,
632        0,
633        iccr2::Trs,
634        iccr2::Trs,
635        Iccr2_SPEC,
636        crate::common::RW,
637    > {
638        crate::common::RegisterField::<
639            5,
640            0x1,
641            1,
642            0,
643            iccr2::Trs,
644            iccr2::Trs,
645            Iccr2_SPEC,
646            crate::common::RW,
647        >::from_register(self, 0)
648    }
649
650    #[doc = "Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued."]
651    #[inline(always)]
652    pub fn sp(
653        self,
654    ) -> crate::common::RegisterField<
655        3,
656        0x1,
657        1,
658        0,
659        iccr2::Sp,
660        iccr2::Sp,
661        Iccr2_SPEC,
662        crate::common::RW,
663    > {
664        crate::common::RegisterField::<
665            3,
666            0x1,
667            1,
668            0,
669            iccr2::Sp,
670            iccr2::Sp,
671            Iccr2_SPEC,
672            crate::common::RW,
673        >::from_register(self, 0)
674    }
675
676    #[doc = "Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition."]
677    #[inline(always)]
678    pub fn rs(
679        self,
680    ) -> crate::common::RegisterField<
681        2,
682        0x1,
683        1,
684        0,
685        iccr2::Rs,
686        iccr2::Rs,
687        Iccr2_SPEC,
688        crate::common::RW,
689    > {
690        crate::common::RegisterField::<
691            2,
692            0x1,
693            1,
694            0,
695            iccr2::Rs,
696            iccr2::Rs,
697            Iccr2_SPEC,
698            crate::common::RW,
699        >::from_register(self, 0)
700    }
701
702    #[doc = "Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state)."]
703    #[inline(always)]
704    pub fn st(
705        self,
706    ) -> crate::common::RegisterField<
707        1,
708        0x1,
709        1,
710        0,
711        iccr2::St,
712        iccr2::St,
713        Iccr2_SPEC,
714        crate::common::RW,
715    > {
716        crate::common::RegisterField::<
717            1,
718            0x1,
719            1,
720            0,
721            iccr2::St,
722            iccr2::St,
723            Iccr2_SPEC,
724            crate::common::RW,
725        >::from_register(self, 0)
726    }
727}
728impl ::core::default::Default for Iccr2 {
729    #[inline(always)]
730    fn default() -> Iccr2 {
731        <crate::RegValueT<Iccr2_SPEC> as RegisterValue<_>>::new(0)
732    }
733}
734pub mod iccr2 {
735
736    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
737    pub struct Bbsy_SPEC;
738    pub type Bbsy = crate::EnumBitfieldStruct<u8, Bbsy_SPEC>;
739    impl Bbsy {
740        #[doc = "The I2C bus is released (bus free state)."]
741        pub const _0: Self = Self::new(0);
742
743        #[doc = "The I2C bus is occupied (bus busy state)."]
744        pub const _1: Self = Self::new(1);
745    }
746    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
747    pub struct Mst_SPEC;
748    pub type Mst = crate::EnumBitfieldStruct<u8, Mst_SPEC>;
749    impl Mst {
750        #[doc = "Slave mode"]
751        pub const _0: Self = Self::new(0);
752
753        #[doc = "Master mode"]
754        pub const _1: Self = Self::new(1);
755    }
756    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
757    pub struct Trs_SPEC;
758    pub type Trs = crate::EnumBitfieldStruct<u8, Trs_SPEC>;
759    impl Trs {
760        #[doc = "Receive mode"]
761        pub const _0: Self = Self::new(0);
762
763        #[doc = "Transmit mode"]
764        pub const _1: Self = Self::new(1);
765    }
766    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
767    pub struct Sp_SPEC;
768    pub type Sp = crate::EnumBitfieldStruct<u8, Sp_SPEC>;
769    impl Sp {
770        #[doc = "Does not request to issue a stop condition."]
771        pub const _0: Self = Self::new(0);
772
773        #[doc = "Requests to issue a stop condition."]
774        pub const _1: Self = Self::new(1);
775    }
776    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
777    pub struct Rs_SPEC;
778    pub type Rs = crate::EnumBitfieldStruct<u8, Rs_SPEC>;
779    impl Rs {
780        #[doc = "Does not request to issue a restart condition."]
781        pub const _0: Self = Self::new(0);
782
783        #[doc = "Requests to issue a restart condition."]
784        pub const _1: Self = Self::new(1);
785    }
786    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
787    pub struct St_SPEC;
788    pub type St = crate::EnumBitfieldStruct<u8, St_SPEC>;
789    impl St {
790        #[doc = "Does not request to issue a start condition."]
791        pub const _0: Self = Self::new(0);
792
793        #[doc = "Requests to issue a start condition."]
794        pub const _1: Self = Self::new(1);
795    }
796}
797#[doc(hidden)]
798#[derive(Copy, Clone, Eq, PartialEq)]
799pub struct Icmr1_SPEC;
800impl crate::sealed::RegSpec for Icmr1_SPEC {
801    type DataType = u8;
802}
803
804#[doc = "I2C Bus Mode Register 1"]
805pub type Icmr1 = crate::RegValueT<Icmr1_SPEC>;
806
807impl Icmr1 {
808    #[doc = "MST/TRS Write Protect"]
809    #[inline(always)]
810    pub fn mtwp(
811        self,
812    ) -> crate::common::RegisterField<
813        7,
814        0x1,
815        1,
816        0,
817        icmr1::Mtwp,
818        icmr1::Mtwp,
819        Icmr1_SPEC,
820        crate::common::RW,
821    > {
822        crate::common::RegisterField::<
823            7,
824            0x1,
825            1,
826            0,
827            icmr1::Mtwp,
828            icmr1::Mtwp,
829            Icmr1_SPEC,
830            crate::common::RW,
831        >::from_register(self, 0)
832    }
833
834    #[doc = "Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS )"]
835    #[inline(always)]
836    pub fn cks(
837        self,
838    ) -> crate::common::RegisterField<
839        4,
840        0x7,
841        1,
842        0,
843        icmr1::Cks,
844        icmr1::Cks,
845        Icmr1_SPEC,
846        crate::common::RW,
847    > {
848        crate::common::RegisterField::<
849            4,
850            0x7,
851            1,
852            0,
853            icmr1::Cks,
854            icmr1::Cks,
855            Icmr1_SPEC,
856            crate::common::RW,
857        >::from_register(self, 0)
858    }
859
860    #[doc = "BC Write Protect(This bit is read as 1.)"]
861    #[inline(always)]
862    pub fn bcwp(
863        self,
864    ) -> crate::common::RegisterField<
865        3,
866        0x1,
867        1,
868        0,
869        icmr1::Bcwp,
870        icmr1::Bcwp,
871        Icmr1_SPEC,
872        crate::common::W,
873    > {
874        crate::common::RegisterField::<
875            3,
876            0x1,
877            1,
878            0,
879            icmr1::Bcwp,
880            icmr1::Bcwp,
881            Icmr1_SPEC,
882            crate::common::W,
883        >::from_register(self, 0)
884    }
885
886    #[doc = "Bit Counter"]
887    #[inline(always)]
888    pub fn bc(
889        self,
890    ) -> crate::common::RegisterField<
891        0,
892        0x7,
893        1,
894        0,
895        icmr1::Bc,
896        icmr1::Bc,
897        Icmr1_SPEC,
898        crate::common::RW,
899    > {
900        crate::common::RegisterField::<
901            0,
902            0x7,
903            1,
904            0,
905            icmr1::Bc,
906            icmr1::Bc,
907            Icmr1_SPEC,
908            crate::common::RW,
909        >::from_register(self, 0)
910    }
911}
912impl ::core::default::Default for Icmr1 {
913    #[inline(always)]
914    fn default() -> Icmr1 {
915        <crate::RegValueT<Icmr1_SPEC> as RegisterValue<_>>::new(8)
916    }
917}
918pub mod icmr1 {
919
920    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
921    pub struct Mtwp_SPEC;
922    pub type Mtwp = crate::EnumBitfieldStruct<u8, Mtwp_SPEC>;
923    impl Mtwp {
924        #[doc = "Disables writing to the MST and TRS bits in ICCR2."]
925        pub const _0: Self = Self::new(0);
926
927        #[doc = "Enables writing to the MST and TRS bits in ICCR2."]
928        pub const _1: Self = Self::new(1);
929    }
930    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
931    pub struct Cks_SPEC;
932    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
933    impl Cks {
934        #[doc = "PCLKB/1 clock"]
935        pub const _000: Self = Self::new(0);
936
937        #[doc = "PCLKB/2 clock"]
938        pub const _001: Self = Self::new(1);
939
940        #[doc = "PCLKB/4 clock"]
941        pub const _010: Self = Self::new(2);
942
943        #[doc = "PCLKB/8 clock"]
944        pub const _011: Self = Self::new(3);
945
946        #[doc = "PCLKB/16 clock"]
947        pub const _100: Self = Self::new(4);
948
949        #[doc = "PCLKB/32 clock"]
950        pub const _101: Self = Self::new(5);
951
952        #[doc = "PCLKB/64 clock"]
953        pub const _110: Self = Self::new(6);
954
955        #[doc = "PCLKB/128 clock"]
956        pub const _111: Self = Self::new(7);
957    }
958    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
959    pub struct Bcwp_SPEC;
960    pub type Bcwp = crate::EnumBitfieldStruct<u8, Bcwp_SPEC>;
961    impl Bcwp {
962        #[doc = "Enables a value to be written in the BC\\[2:0\\] bits."]
963        pub const _0: Self = Self::new(0);
964
965        #[doc = "Disables a value to be written in the BC\\[2:0\\] bits."]
966        pub const _1: Self = Self::new(1);
967    }
968    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
969    pub struct Bc_SPEC;
970    pub type Bc = crate::EnumBitfieldStruct<u8, Bc_SPEC>;
971    impl Bc {
972        #[doc = "9 bits"]
973        pub const _000: Self = Self::new(0);
974
975        #[doc = "2 bits"]
976        pub const _001: Self = Self::new(1);
977
978        #[doc = "3 bits"]
979        pub const _010: Self = Self::new(2);
980
981        #[doc = "4 bits"]
982        pub const _011: Self = Self::new(3);
983
984        #[doc = "5 bits"]
985        pub const _100: Self = Self::new(4);
986
987        #[doc = "6 bits"]
988        pub const _101: Self = Self::new(5);
989
990        #[doc = "7 bits"]
991        pub const _110: Self = Self::new(6);
992
993        #[doc = "8 bits"]
994        pub const _111: Self = Self::new(7);
995    }
996}
997#[doc(hidden)]
998#[derive(Copy, Clone, Eq, PartialEq)]
999pub struct Icmr2_SPEC;
1000impl crate::sealed::RegSpec for Icmr2_SPEC {
1001    type DataType = u8;
1002}
1003
1004#[doc = "I2C Bus Mode Register 2"]
1005pub type Icmr2 = crate::RegValueT<Icmr2_SPEC>;
1006
1007impl Icmr2 {
1008    #[doc = "SDA Output Delay Clock Source Selection"]
1009    #[inline(always)]
1010    pub fn dlcs(
1011        self,
1012    ) -> crate::common::RegisterField<
1013        7,
1014        0x1,
1015        1,
1016        0,
1017        icmr2::Dlcs,
1018        icmr2::Dlcs,
1019        Icmr2_SPEC,
1020        crate::common::RW,
1021    > {
1022        crate::common::RegisterField::<
1023            7,
1024            0x1,
1025            1,
1026            0,
1027            icmr2::Dlcs,
1028            icmr2::Dlcs,
1029            Icmr2_SPEC,
1030            crate::common::RW,
1031        >::from_register(self, 0)
1032    }
1033
1034    #[doc = "SDA Output Delay Counter"]
1035    #[inline(always)]
1036    pub fn sddl(
1037        self,
1038    ) -> crate::common::RegisterField<
1039        4,
1040        0x7,
1041        1,
1042        0,
1043        icmr2::Sddl,
1044        icmr2::Sddl,
1045        Icmr2_SPEC,
1046        crate::common::RW,
1047    > {
1048        crate::common::RegisterField::<
1049            4,
1050            0x7,
1051            1,
1052            0,
1053            icmr2::Sddl,
1054            icmr2::Sddl,
1055            Icmr2_SPEC,
1056            crate::common::RW,
1057        >::from_register(self, 0)
1058    }
1059
1060    #[doc = "Timeout H Count Control"]
1061    #[inline(always)]
1062    pub fn tmoh(
1063        self,
1064    ) -> crate::common::RegisterField<
1065        2,
1066        0x1,
1067        1,
1068        0,
1069        icmr2::Tmoh,
1070        icmr2::Tmoh,
1071        Icmr2_SPEC,
1072        crate::common::RW,
1073    > {
1074        crate::common::RegisterField::<
1075            2,
1076            0x1,
1077            1,
1078            0,
1079            icmr2::Tmoh,
1080            icmr2::Tmoh,
1081            Icmr2_SPEC,
1082            crate::common::RW,
1083        >::from_register(self, 0)
1084    }
1085
1086    #[doc = "Timeout L Count Control"]
1087    #[inline(always)]
1088    pub fn tmol(
1089        self,
1090    ) -> crate::common::RegisterField<
1091        1,
1092        0x1,
1093        1,
1094        0,
1095        icmr2::Tmol,
1096        icmr2::Tmol,
1097        Icmr2_SPEC,
1098        crate::common::RW,
1099    > {
1100        crate::common::RegisterField::<
1101            1,
1102            0x1,
1103            1,
1104            0,
1105            icmr2::Tmol,
1106            icmr2::Tmol,
1107            Icmr2_SPEC,
1108            crate::common::RW,
1109        >::from_register(self, 0)
1110    }
1111
1112    #[doc = "Timeout Detection Time Selection"]
1113    #[inline(always)]
1114    pub fn tmos(
1115        self,
1116    ) -> crate::common::RegisterField<
1117        0,
1118        0x1,
1119        1,
1120        0,
1121        icmr2::Tmos,
1122        icmr2::Tmos,
1123        Icmr2_SPEC,
1124        crate::common::RW,
1125    > {
1126        crate::common::RegisterField::<
1127            0,
1128            0x1,
1129            1,
1130            0,
1131            icmr2::Tmos,
1132            icmr2::Tmos,
1133            Icmr2_SPEC,
1134            crate::common::RW,
1135        >::from_register(self, 0)
1136    }
1137}
1138impl ::core::default::Default for Icmr2 {
1139    #[inline(always)]
1140    fn default() -> Icmr2 {
1141        <crate::RegValueT<Icmr2_SPEC> as RegisterValue<_>>::new(6)
1142    }
1143}
1144pub mod icmr2 {
1145
1146    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1147    pub struct Dlcs_SPEC;
1148    pub type Dlcs = crate::EnumBitfieldStruct<u8, Dlcs_SPEC>;
1149    impl Dlcs {
1150        #[doc = "The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter."]
1151        pub const _0: Self = Self::new(0);
1152
1153        #[doc = "The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter."]
1154        pub const _1: Self = Self::new(1);
1155    }
1156    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1157    pub struct Sddl_SPEC;
1158    pub type Sddl = crate::EnumBitfieldStruct<u8, Sddl_SPEC>;
1159    impl Sddl {
1160        #[doc = "No output delay"]
1161        pub const _000: Self = Self::new(0);
1162
1163        #[doc = "1 fIIC cycle  (ICMR2.DLCS=0) / 1  or 2 fIIC cycles (ICMR2.DLCS=1)"]
1164        pub const _001: Self = Self::new(1);
1165
1166        #[doc = "2 fIIC cycles (ICMR2.DLCS=0) /  3 or 4 fIIC cycles (ICMR2.DLCS=1)"]
1167        pub const _010: Self = Self::new(2);
1168
1169        #[doc = "3 fIIC cycles (ICMR2.DLCS=0) /  5 or 6 fIIC cycles (ICMR2.DLCS=1)"]
1170        pub const _011: Self = Self::new(3);
1171
1172        #[doc = "4 fIIC cycles (ICMR2.DLCS=0) /  7 or 8 fIIC cycles (ICMR2.DLCS=1)"]
1173        pub const _100: Self = Self::new(4);
1174
1175        #[doc = "5 fIIC cycles (ICMR2.DLCS=0) /  9 or 10 fIIC cycles (ICMR2.DLCS=1)"]
1176        pub const _101: Self = Self::new(5);
1177
1178        #[doc = "6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1)"]
1179        pub const _110: Self = Self::new(6);
1180
1181        #[doc = "7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1)"]
1182        pub const _111: Self = Self::new(7);
1183    }
1184    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1185    pub struct Tmoh_SPEC;
1186    pub type Tmoh = crate::EnumBitfieldStruct<u8, Tmoh_SPEC>;
1187    impl Tmoh {
1188        #[doc = "Count is disabled while the SCLn line is at a high level."]
1189        pub const _0: Self = Self::new(0);
1190
1191        #[doc = "Count is enabled while the SCLn line is at a high level."]
1192        pub const _1: Self = Self::new(1);
1193    }
1194    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1195    pub struct Tmol_SPEC;
1196    pub type Tmol = crate::EnumBitfieldStruct<u8, Tmol_SPEC>;
1197    impl Tmol {
1198        #[doc = "Count is disabled while the SCLn line is at a low level."]
1199        pub const _0: Self = Self::new(0);
1200
1201        #[doc = "Count is enabled while the SCLn line is at a low level."]
1202        pub const _1: Self = Self::new(1);
1203    }
1204    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1205    pub struct Tmos_SPEC;
1206    pub type Tmos = crate::EnumBitfieldStruct<u8, Tmos_SPEC>;
1207    impl Tmos {
1208        #[doc = "Long mode is selected."]
1209        pub const _0: Self = Self::new(0);
1210
1211        #[doc = "Short mode is selected."]
1212        pub const _1: Self = Self::new(1);
1213    }
1214}
1215#[doc(hidden)]
1216#[derive(Copy, Clone, Eq, PartialEq)]
1217pub struct Icmr3_SPEC;
1218impl crate::sealed::RegSpec for Icmr3_SPEC {
1219    type DataType = u8;
1220}
1221
1222#[doc = "I2C Bus Mode Register 3"]
1223pub type Icmr3 = crate::RegValueT<Icmr3_SPEC>;
1224
1225impl Icmr3 {
1226    #[doc = "SMBus/I2C Bus Selection"]
1227    #[inline(always)]
1228    pub fn smbs(
1229        self,
1230    ) -> crate::common::RegisterField<
1231        7,
1232        0x1,
1233        1,
1234        0,
1235        icmr3::Smbs,
1236        icmr3::Smbs,
1237        Icmr3_SPEC,
1238        crate::common::RW,
1239    > {
1240        crate::common::RegisterField::<
1241            7,
1242            0x1,
1243            1,
1244            0,
1245            icmr3::Smbs,
1246            icmr3::Smbs,
1247            Icmr3_SPEC,
1248            crate::common::RW,
1249        >::from_register(self, 0)
1250    }
1251
1252    #[doc = "WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand."]
1253    #[inline(always)]
1254    pub fn wait(
1255        self,
1256    ) -> crate::common::RegisterField<
1257        6,
1258        0x1,
1259        1,
1260        0,
1261        icmr3::Wait,
1262        icmr3::Wait,
1263        Icmr3_SPEC,
1264        crate::common::RW,
1265    > {
1266        crate::common::RegisterField::<
1267            6,
1268            0x1,
1269            1,
1270            0,
1271            icmr3::Wait,
1272            icmr3::Wait,
1273            Icmr3_SPEC,
1274            crate::common::RW,
1275        >::from_register(self, 0)
1276    }
1277
1278    #[doc = "RDRF Flag Set Timing Selection"]
1279    #[inline(always)]
1280    pub fn rdrfs(
1281        self,
1282    ) -> crate::common::RegisterField<
1283        5,
1284        0x1,
1285        1,
1286        0,
1287        icmr3::Rdrfs,
1288        icmr3::Rdrfs,
1289        Icmr3_SPEC,
1290        crate::common::RW,
1291    > {
1292        crate::common::RegisterField::<
1293            5,
1294            0x1,
1295            1,
1296            0,
1297            icmr3::Rdrfs,
1298            icmr3::Rdrfs,
1299            Icmr3_SPEC,
1300            crate::common::RW,
1301        >::from_register(self, 0)
1302    }
1303
1304    #[doc = "ACKBT Write Protect"]
1305    #[inline(always)]
1306    pub fn ackwp(
1307        self,
1308    ) -> crate::common::RegisterField<
1309        4,
1310        0x1,
1311        1,
1312        0,
1313        icmr3::Ackwp,
1314        icmr3::Ackwp,
1315        Icmr3_SPEC,
1316        crate::common::RW,
1317    > {
1318        crate::common::RegisterField::<
1319            4,
1320            0x1,
1321            1,
1322            0,
1323            icmr3::Ackwp,
1324            icmr3::Ackwp,
1325            Icmr3_SPEC,
1326            crate::common::RW,
1327        >::from_register(self, 0)
1328    }
1329
1330    #[doc = "Transmit Acknowledge"]
1331    #[inline(always)]
1332    pub fn ackbt(
1333        self,
1334    ) -> crate::common::RegisterField<
1335        3,
1336        0x1,
1337        1,
1338        0,
1339        icmr3::Ackbt,
1340        icmr3::Ackbt,
1341        Icmr3_SPEC,
1342        crate::common::RW,
1343    > {
1344        crate::common::RegisterField::<
1345            3,
1346            0x1,
1347            1,
1348            0,
1349            icmr3::Ackbt,
1350            icmr3::Ackbt,
1351            Icmr3_SPEC,
1352            crate::common::RW,
1353        >::from_register(self, 0)
1354    }
1355
1356    #[doc = "Receive Acknowledge"]
1357    #[inline(always)]
1358    pub fn ackbr(
1359        self,
1360    ) -> crate::common::RegisterField<
1361        2,
1362        0x1,
1363        1,
1364        0,
1365        icmr3::Ackbr,
1366        icmr3::Ackbr,
1367        Icmr3_SPEC,
1368        crate::common::R,
1369    > {
1370        crate::common::RegisterField::<
1371            2,
1372            0x1,
1373            1,
1374            0,
1375            icmr3::Ackbr,
1376            icmr3::Ackbr,
1377            Icmr3_SPEC,
1378            crate::common::R,
1379        >::from_register(self, 0)
1380    }
1381
1382    #[doc = "Noise Filter Stage Selection"]
1383    #[inline(always)]
1384    pub fn nf(
1385        self,
1386    ) -> crate::common::RegisterField<
1387        0,
1388        0x3,
1389        1,
1390        0,
1391        icmr3::Nf,
1392        icmr3::Nf,
1393        Icmr3_SPEC,
1394        crate::common::RW,
1395    > {
1396        crate::common::RegisterField::<
1397            0,
1398            0x3,
1399            1,
1400            0,
1401            icmr3::Nf,
1402            icmr3::Nf,
1403            Icmr3_SPEC,
1404            crate::common::RW,
1405        >::from_register(self, 0)
1406    }
1407}
1408impl ::core::default::Default for Icmr3 {
1409    #[inline(always)]
1410    fn default() -> Icmr3 {
1411        <crate::RegValueT<Icmr3_SPEC> as RegisterValue<_>>::new(0)
1412    }
1413}
1414pub mod icmr3 {
1415
1416    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1417    pub struct Smbs_SPEC;
1418    pub type Smbs = crate::EnumBitfieldStruct<u8, Smbs_SPEC>;
1419    impl Smbs {
1420        #[doc = "The I2C bus is selected."]
1421        pub const _0: Self = Self::new(0);
1422
1423        #[doc = "The SMBus is selected."]
1424        pub const _1: Self = Self::new(1);
1425    }
1426    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1427    pub struct Wait_SPEC;
1428    pub type Wait = crate::EnumBitfieldStruct<u8, Wait_SPEC>;
1429    impl Wait {
1430        #[doc = "No WAIT (The period between ninth clock cycle and first clock cycle is not held low.)"]
1431        pub const _0: Self = Self::new(0);
1432
1433        #[doc = "WAIT (The period between ninth clock cycle and first clock cycle is held low.)"]
1434        pub const _1: Self = Self::new(1);
1435    }
1436    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1437    pub struct Rdrfs_SPEC;
1438    pub type Rdrfs = crate::EnumBitfieldStruct<u8, Rdrfs_SPEC>;
1439    impl Rdrfs {
1440        #[doc = "The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.)"]
1441        pub const _0: Self = Self::new(0);
1442
1443        #[doc = "The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.)"]
1444        pub const _1: Self = Self::new(1);
1445    }
1446    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1447    pub struct Ackwp_SPEC;
1448    pub type Ackwp = crate::EnumBitfieldStruct<u8, Ackwp_SPEC>;
1449    impl Ackwp {
1450        #[doc = "Modification of the ACKBT bit is disabled."]
1451        pub const _0: Self = Self::new(0);
1452
1453        #[doc = "Modification of the ACKBT bit is enabled."]
1454        pub const _1: Self = Self::new(1);
1455    }
1456    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1457    pub struct Ackbt_SPEC;
1458    pub type Ackbt = crate::EnumBitfieldStruct<u8, Ackbt_SPEC>;
1459    impl Ackbt {
1460        #[doc = "A 0 is sent as the acknowledge bit (ACK transmission)."]
1461        pub const _0: Self = Self::new(0);
1462
1463        #[doc = "A 1 is sent as the acknowledge bit (NACK transmission)."]
1464        pub const _1: Self = Self::new(1);
1465    }
1466    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1467    pub struct Ackbr_SPEC;
1468    pub type Ackbr = crate::EnumBitfieldStruct<u8, Ackbr_SPEC>;
1469    impl Ackbr {
1470        #[doc = "A 0 is received as the acknowledge bit (ACK reception)."]
1471        pub const _0: Self = Self::new(0);
1472
1473        #[doc = "A 1 is received as the acknowledge bit (NACK reception)."]
1474        pub const _1: Self = Self::new(1);
1475    }
1476    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1477    pub struct Nf_SPEC;
1478    pub type Nf = crate::EnumBitfieldStruct<u8, Nf_SPEC>;
1479    impl Nf {
1480        #[doc = "Noise of up to one fIIC cycle is filtered out (single-stage filter)."]
1481        pub const _00: Self = Self::new(0);
1482
1483        #[doc = "Noise of up to two fIIC cycles is filtered out (2-stage filter)."]
1484        pub const _01: Self = Self::new(1);
1485
1486        #[doc = "Noise of up to three fIIC cycles is filtered out (3-stage filter)."]
1487        pub const _10: Self = Self::new(2);
1488
1489        #[doc = "Noise of up to four fIIC cycles is filtered out (4-stage filter)"]
1490        pub const _11: Self = Self::new(3);
1491    }
1492}
1493#[doc(hidden)]
1494#[derive(Copy, Clone, Eq, PartialEq)]
1495pub struct Icfer_SPEC;
1496impl crate::sealed::RegSpec for Icfer_SPEC {
1497    type DataType = u8;
1498}
1499
1500#[doc = "I2C Bus Function Enable Register"]
1501pub type Icfer = crate::RegValueT<Icfer_SPEC>;
1502
1503impl Icfer {
1504    #[doc = "Fast-mode Plus Enable"]
1505    #[inline(always)]
1506    pub fn fmpe(
1507        self,
1508    ) -> crate::common::RegisterField<
1509        7,
1510        0x1,
1511        1,
1512        0,
1513        icfer::Fmpe,
1514        icfer::Fmpe,
1515        Icfer_SPEC,
1516        crate::common::RW,
1517    > {
1518        crate::common::RegisterField::<
1519            7,
1520            0x1,
1521            1,
1522            0,
1523            icfer::Fmpe,
1524            icfer::Fmpe,
1525            Icfer_SPEC,
1526            crate::common::RW,
1527        >::from_register(self, 0)
1528    }
1529
1530    #[doc = "SCL Synchronous Circuit Enable"]
1531    #[inline(always)]
1532    pub fn scle(
1533        self,
1534    ) -> crate::common::RegisterField<
1535        6,
1536        0x1,
1537        1,
1538        0,
1539        icfer::Scle,
1540        icfer::Scle,
1541        Icfer_SPEC,
1542        crate::common::RW,
1543    > {
1544        crate::common::RegisterField::<
1545            6,
1546            0x1,
1547            1,
1548            0,
1549            icfer::Scle,
1550            icfer::Scle,
1551            Icfer_SPEC,
1552            crate::common::RW,
1553        >::from_register(self, 0)
1554    }
1555
1556    #[doc = "Digital Noise Filter Circuit Enable"]
1557    #[inline(always)]
1558    pub fn nfe(
1559        self,
1560    ) -> crate::common::RegisterField<
1561        5,
1562        0x1,
1563        1,
1564        0,
1565        icfer::Nfe,
1566        icfer::Nfe,
1567        Icfer_SPEC,
1568        crate::common::RW,
1569    > {
1570        crate::common::RegisterField::<
1571            5,
1572            0x1,
1573            1,
1574            0,
1575            icfer::Nfe,
1576            icfer::Nfe,
1577            Icfer_SPEC,
1578            crate::common::RW,
1579        >::from_register(self, 0)
1580    }
1581
1582    #[doc = "NACK Reception Transfer Suspension Enable"]
1583    #[inline(always)]
1584    pub fn nacke(
1585        self,
1586    ) -> crate::common::RegisterField<
1587        4,
1588        0x1,
1589        1,
1590        0,
1591        icfer::Nacke,
1592        icfer::Nacke,
1593        Icfer_SPEC,
1594        crate::common::RW,
1595    > {
1596        crate::common::RegisterField::<
1597            4,
1598            0x1,
1599            1,
1600            0,
1601            icfer::Nacke,
1602            icfer::Nacke,
1603            Icfer_SPEC,
1604            crate::common::RW,
1605        >::from_register(self, 0)
1606    }
1607
1608    #[doc = "Slave Arbitration-Lost Detection Enable"]
1609    #[inline(always)]
1610    pub fn sale(
1611        self,
1612    ) -> crate::common::RegisterField<
1613        3,
1614        0x1,
1615        1,
1616        0,
1617        icfer::Sale,
1618        icfer::Sale,
1619        Icfer_SPEC,
1620        crate::common::RW,
1621    > {
1622        crate::common::RegisterField::<
1623            3,
1624            0x1,
1625            1,
1626            0,
1627            icfer::Sale,
1628            icfer::Sale,
1629            Icfer_SPEC,
1630            crate::common::RW,
1631        >::from_register(self, 0)
1632    }
1633
1634    #[doc = "NACK Transmission Arbitration-Lost Detection Enable"]
1635    #[inline(always)]
1636    pub fn nale(
1637        self,
1638    ) -> crate::common::RegisterField<
1639        2,
1640        0x1,
1641        1,
1642        0,
1643        icfer::Nale,
1644        icfer::Nale,
1645        Icfer_SPEC,
1646        crate::common::RW,
1647    > {
1648        crate::common::RegisterField::<
1649            2,
1650            0x1,
1651            1,
1652            0,
1653            icfer::Nale,
1654            icfer::Nale,
1655            Icfer_SPEC,
1656            crate::common::RW,
1657        >::from_register(self, 0)
1658    }
1659
1660    #[doc = "Master Arbitration-Lost Detection Enable"]
1661    #[inline(always)]
1662    pub fn male(
1663        self,
1664    ) -> crate::common::RegisterField<
1665        1,
1666        0x1,
1667        1,
1668        0,
1669        icfer::Male,
1670        icfer::Male,
1671        Icfer_SPEC,
1672        crate::common::RW,
1673    > {
1674        crate::common::RegisterField::<
1675            1,
1676            0x1,
1677            1,
1678            0,
1679            icfer::Male,
1680            icfer::Male,
1681            Icfer_SPEC,
1682            crate::common::RW,
1683        >::from_register(self, 0)
1684    }
1685
1686    #[doc = "Timeout Function Enable"]
1687    #[inline(always)]
1688    pub fn tmoe(
1689        self,
1690    ) -> crate::common::RegisterField<
1691        0,
1692        0x1,
1693        1,
1694        0,
1695        icfer::Tmoe,
1696        icfer::Tmoe,
1697        Icfer_SPEC,
1698        crate::common::RW,
1699    > {
1700        crate::common::RegisterField::<
1701            0,
1702            0x1,
1703            1,
1704            0,
1705            icfer::Tmoe,
1706            icfer::Tmoe,
1707            Icfer_SPEC,
1708            crate::common::RW,
1709        >::from_register(self, 0)
1710    }
1711}
1712impl ::core::default::Default for Icfer {
1713    #[inline(always)]
1714    fn default() -> Icfer {
1715        <crate::RegValueT<Icfer_SPEC> as RegisterValue<_>>::new(114)
1716    }
1717}
1718pub mod icfer {
1719
1720    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1721    pub struct Fmpe_SPEC;
1722    pub type Fmpe = crate::EnumBitfieldStruct<u8, Fmpe_SPEC>;
1723    impl Fmpe {
1724        #[doc = "No Fm+ slope control circuit is used for the SCLn pin and SDAn pin."]
1725        pub const _0: Self = Self::new(0);
1726
1727        #[doc = "An Fm+ slope control circuit is used for the SCLn pin and SDAn pin."]
1728        pub const _1: Self = Self::new(1);
1729    }
1730    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1731    pub struct Scle_SPEC;
1732    pub type Scle = crate::EnumBitfieldStruct<u8, Scle_SPEC>;
1733    impl Scle {
1734        #[doc = "No SCL synchronous circuit is used."]
1735        pub const _0: Self = Self::new(0);
1736
1737        #[doc = "An SCL synchronous circuit is used."]
1738        pub const _1: Self = Self::new(1);
1739    }
1740    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1741    pub struct Nfe_SPEC;
1742    pub type Nfe = crate::EnumBitfieldStruct<u8, Nfe_SPEC>;
1743    impl Nfe {
1744        #[doc = "No digital noise filter circuit is used."]
1745        pub const _0: Self = Self::new(0);
1746
1747        #[doc = "A digital noise filter circuit is used."]
1748        pub const _1: Self = Self::new(1);
1749    }
1750    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1751    pub struct Nacke_SPEC;
1752    pub type Nacke = crate::EnumBitfieldStruct<u8, Nacke_SPEC>;
1753    impl Nacke {
1754        #[doc = "Transfer operation is not suspended during NACK reception (transfer suspension disabled)."]
1755        pub const _0: Self = Self::new(0);
1756
1757        #[doc = "Transfer operation is suspended during NACK reception (transfer suspension enabled)."]
1758        pub const _1: Self = Self::new(1);
1759    }
1760    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1761    pub struct Sale_SPEC;
1762    pub type Sale = crate::EnumBitfieldStruct<u8, Sale_SPEC>;
1763    impl Sale {
1764        #[doc = "Slave arbitration-lost detection is disabled."]
1765        pub const _0: Self = Self::new(0);
1766
1767        #[doc = "Slave arbitration-lost detection is enabled."]
1768        pub const _1: Self = Self::new(1);
1769    }
1770    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1771    pub struct Nale_SPEC;
1772    pub type Nale = crate::EnumBitfieldStruct<u8, Nale_SPEC>;
1773    impl Nale {
1774        #[doc = "NACK transmission arbitration-lost detection is disabled."]
1775        pub const _0: Self = Self::new(0);
1776
1777        #[doc = "NACK transmission arbitration-lost detection is enabled."]
1778        pub const _1: Self = Self::new(1);
1779    }
1780    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1781    pub struct Male_SPEC;
1782    pub type Male = crate::EnumBitfieldStruct<u8, Male_SPEC>;
1783    impl Male {
1784        #[doc = "Master arbitration-lost detection is disabled."]
1785        pub const _0: Self = Self::new(0);
1786
1787        #[doc = "Master arbitration-lost detection is enabled."]
1788        pub const _1: Self = Self::new(1);
1789    }
1790    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1791    pub struct Tmoe_SPEC;
1792    pub type Tmoe = crate::EnumBitfieldStruct<u8, Tmoe_SPEC>;
1793    impl Tmoe {
1794        #[doc = "The timeout function is disabled."]
1795        pub const _0: Self = Self::new(0);
1796
1797        #[doc = "The timeout function is enabled."]
1798        pub const _1: Self = Self::new(1);
1799    }
1800}
1801#[doc(hidden)]
1802#[derive(Copy, Clone, Eq, PartialEq)]
1803pub struct Icser_SPEC;
1804impl crate::sealed::RegSpec for Icser_SPEC {
1805    type DataType = u8;
1806}
1807
1808#[doc = "I2C Bus Status Enable Register"]
1809pub type Icser = crate::RegValueT<Icser_SPEC>;
1810
1811impl Icser {
1812    #[doc = "Host Address Enable"]
1813    #[inline(always)]
1814    pub fn hoae(
1815        self,
1816    ) -> crate::common::RegisterField<
1817        7,
1818        0x1,
1819        1,
1820        0,
1821        icser::Hoae,
1822        icser::Hoae,
1823        Icser_SPEC,
1824        crate::common::RW,
1825    > {
1826        crate::common::RegisterField::<
1827            7,
1828            0x1,
1829            1,
1830            0,
1831            icser::Hoae,
1832            icser::Hoae,
1833            Icser_SPEC,
1834            crate::common::RW,
1835        >::from_register(self, 0)
1836    }
1837
1838    #[doc = "Device-ID Address Detection Enable"]
1839    #[inline(always)]
1840    pub fn dide(
1841        self,
1842    ) -> crate::common::RegisterField<
1843        5,
1844        0x1,
1845        1,
1846        0,
1847        icser::Dide,
1848        icser::Dide,
1849        Icser_SPEC,
1850        crate::common::RW,
1851    > {
1852        crate::common::RegisterField::<
1853            5,
1854            0x1,
1855            1,
1856            0,
1857            icser::Dide,
1858            icser::Dide,
1859            Icser_SPEC,
1860            crate::common::RW,
1861        >::from_register(self, 0)
1862    }
1863
1864    #[doc = "General Call Address Enable"]
1865    #[inline(always)]
1866    pub fn gcae(
1867        self,
1868    ) -> crate::common::RegisterField<
1869        3,
1870        0x1,
1871        1,
1872        0,
1873        icser::Gcae,
1874        icser::Gcae,
1875        Icser_SPEC,
1876        crate::common::RW,
1877    > {
1878        crate::common::RegisterField::<
1879            3,
1880            0x1,
1881            1,
1882            0,
1883            icser::Gcae,
1884            icser::Gcae,
1885            Icser_SPEC,
1886            crate::common::RW,
1887        >::from_register(self, 0)
1888    }
1889
1890    #[doc = "Slave Address Register 2 Enable"]
1891    #[inline(always)]
1892    pub fn sar2e(
1893        self,
1894    ) -> crate::common::RegisterField<
1895        2,
1896        0x1,
1897        1,
1898        0,
1899        icser::Sar2E,
1900        icser::Sar2E,
1901        Icser_SPEC,
1902        crate::common::RW,
1903    > {
1904        crate::common::RegisterField::<
1905            2,
1906            0x1,
1907            1,
1908            0,
1909            icser::Sar2E,
1910            icser::Sar2E,
1911            Icser_SPEC,
1912            crate::common::RW,
1913        >::from_register(self, 0)
1914    }
1915
1916    #[doc = "Slave Address Register 1 Enable"]
1917    #[inline(always)]
1918    pub fn sar1e(
1919        self,
1920    ) -> crate::common::RegisterField<
1921        1,
1922        0x1,
1923        1,
1924        0,
1925        icser::Sar1E,
1926        icser::Sar1E,
1927        Icser_SPEC,
1928        crate::common::RW,
1929    > {
1930        crate::common::RegisterField::<
1931            1,
1932            0x1,
1933            1,
1934            0,
1935            icser::Sar1E,
1936            icser::Sar1E,
1937            Icser_SPEC,
1938            crate::common::RW,
1939        >::from_register(self, 0)
1940    }
1941
1942    #[doc = "Slave Address Register 0 Enable"]
1943    #[inline(always)]
1944    pub fn sar0e(
1945        self,
1946    ) -> crate::common::RegisterField<
1947        0,
1948        0x1,
1949        1,
1950        0,
1951        icser::Sar0E,
1952        icser::Sar0E,
1953        Icser_SPEC,
1954        crate::common::RW,
1955    > {
1956        crate::common::RegisterField::<
1957            0,
1958            0x1,
1959            1,
1960            0,
1961            icser::Sar0E,
1962            icser::Sar0E,
1963            Icser_SPEC,
1964            crate::common::RW,
1965        >::from_register(self, 0)
1966    }
1967}
1968impl ::core::default::Default for Icser {
1969    #[inline(always)]
1970    fn default() -> Icser {
1971        <crate::RegValueT<Icser_SPEC> as RegisterValue<_>>::new(9)
1972    }
1973}
1974pub mod icser {
1975
1976    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1977    pub struct Hoae_SPEC;
1978    pub type Hoae = crate::EnumBitfieldStruct<u8, Hoae_SPEC>;
1979    impl Hoae {
1980        #[doc = "Host address detection is disabled."]
1981        pub const _0: Self = Self::new(0);
1982
1983        #[doc = "Host address detection is enabled."]
1984        pub const _1: Self = Self::new(1);
1985    }
1986    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1987    pub struct Dide_SPEC;
1988    pub type Dide = crate::EnumBitfieldStruct<u8, Dide_SPEC>;
1989    impl Dide {
1990        #[doc = "Device-ID address detection is disabled."]
1991        pub const _0: Self = Self::new(0);
1992
1993        #[doc = "Device-ID address detection is enabled."]
1994        pub const _1: Self = Self::new(1);
1995    }
1996    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1997    pub struct Gcae_SPEC;
1998    pub type Gcae = crate::EnumBitfieldStruct<u8, Gcae_SPEC>;
1999    impl Gcae {
2000        #[doc = "General call address detection is disabled."]
2001        pub const _0: Self = Self::new(0);
2002
2003        #[doc = "General call address detection is enabled."]
2004        pub const _1: Self = Self::new(1);
2005    }
2006    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2007    pub struct Sar2E_SPEC;
2008    pub type Sar2E = crate::EnumBitfieldStruct<u8, Sar2E_SPEC>;
2009    impl Sar2E {
2010        #[doc = "Slave address in SARL2 and SARU2 is disabled."]
2011        pub const _0: Self = Self::new(0);
2012
2013        #[doc = "Slave address in SARL2 and SARU2 is enabled"]
2014        pub const _1: Self = Self::new(1);
2015    }
2016    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2017    pub struct Sar1E_SPEC;
2018    pub type Sar1E = crate::EnumBitfieldStruct<u8, Sar1E_SPEC>;
2019    impl Sar1E {
2020        #[doc = "Slave address in SARL1 and SARU1 is disabled."]
2021        pub const _0: Self = Self::new(0);
2022
2023        #[doc = "Slave address in SARL1 and SARU1 is enabled."]
2024        pub const _1: Self = Self::new(1);
2025    }
2026    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2027    pub struct Sar0E_SPEC;
2028    pub type Sar0E = crate::EnumBitfieldStruct<u8, Sar0E_SPEC>;
2029    impl Sar0E {
2030        #[doc = "Slave address in SARL0 and SARU0 is disabled."]
2031        pub const _0: Self = Self::new(0);
2032
2033        #[doc = "Slave address in SARL0 and SARU0 is enabled."]
2034        pub const _1: Self = Self::new(1);
2035    }
2036}
2037#[doc(hidden)]
2038#[derive(Copy, Clone, Eq, PartialEq)]
2039pub struct Icier_SPEC;
2040impl crate::sealed::RegSpec for Icier_SPEC {
2041    type DataType = u8;
2042}
2043
2044#[doc = "I2C Bus Interrupt Enable Register"]
2045pub type Icier = crate::RegValueT<Icier_SPEC>;
2046
2047impl Icier {
2048    #[doc = "Transmit Data Empty Interrupt Request Enable"]
2049    #[inline(always)]
2050    pub fn tie(
2051        self,
2052    ) -> crate::common::RegisterField<
2053        7,
2054        0x1,
2055        1,
2056        0,
2057        icier::Tie,
2058        icier::Tie,
2059        Icier_SPEC,
2060        crate::common::RW,
2061    > {
2062        crate::common::RegisterField::<
2063            7,
2064            0x1,
2065            1,
2066            0,
2067            icier::Tie,
2068            icier::Tie,
2069            Icier_SPEC,
2070            crate::common::RW,
2071        >::from_register(self, 0)
2072    }
2073
2074    #[doc = "Transmit End Interrupt Request  Enable"]
2075    #[inline(always)]
2076    pub fn teie(
2077        self,
2078    ) -> crate::common::RegisterField<
2079        6,
2080        0x1,
2081        1,
2082        0,
2083        icier::Teie,
2084        icier::Teie,
2085        Icier_SPEC,
2086        crate::common::RW,
2087    > {
2088        crate::common::RegisterField::<
2089            6,
2090            0x1,
2091            1,
2092            0,
2093            icier::Teie,
2094            icier::Teie,
2095            Icier_SPEC,
2096            crate::common::RW,
2097        >::from_register(self, 0)
2098    }
2099
2100    #[doc = "Receive Data Full Interrupt Request Enable"]
2101    #[inline(always)]
2102    pub fn rie(
2103        self,
2104    ) -> crate::common::RegisterField<
2105        5,
2106        0x1,
2107        1,
2108        0,
2109        icier::Rie,
2110        icier::Rie,
2111        Icier_SPEC,
2112        crate::common::RW,
2113    > {
2114        crate::common::RegisterField::<
2115            5,
2116            0x1,
2117            1,
2118            0,
2119            icier::Rie,
2120            icier::Rie,
2121            Icier_SPEC,
2122            crate::common::RW,
2123        >::from_register(self, 0)
2124    }
2125
2126    #[doc = "NACK Reception Interrupt Request Enable"]
2127    #[inline(always)]
2128    pub fn nakie(
2129        self,
2130    ) -> crate::common::RegisterField<
2131        4,
2132        0x1,
2133        1,
2134        0,
2135        icier::Nakie,
2136        icier::Nakie,
2137        Icier_SPEC,
2138        crate::common::RW,
2139    > {
2140        crate::common::RegisterField::<
2141            4,
2142            0x1,
2143            1,
2144            0,
2145            icier::Nakie,
2146            icier::Nakie,
2147            Icier_SPEC,
2148            crate::common::RW,
2149        >::from_register(self, 0)
2150    }
2151
2152    #[doc = "Stop Condition Detection Interrupt Request Enable"]
2153    #[inline(always)]
2154    pub fn spie(
2155        self,
2156    ) -> crate::common::RegisterField<
2157        3,
2158        0x1,
2159        1,
2160        0,
2161        icier::Spie,
2162        icier::Spie,
2163        Icier_SPEC,
2164        crate::common::RW,
2165    > {
2166        crate::common::RegisterField::<
2167            3,
2168            0x1,
2169            1,
2170            0,
2171            icier::Spie,
2172            icier::Spie,
2173            Icier_SPEC,
2174            crate::common::RW,
2175        >::from_register(self, 0)
2176    }
2177
2178    #[doc = "Start Condition Detection Interrupt Request Enable"]
2179    #[inline(always)]
2180    pub fn stie(
2181        self,
2182    ) -> crate::common::RegisterField<
2183        2,
2184        0x1,
2185        1,
2186        0,
2187        icier::Stie,
2188        icier::Stie,
2189        Icier_SPEC,
2190        crate::common::RW,
2191    > {
2192        crate::common::RegisterField::<
2193            2,
2194            0x1,
2195            1,
2196            0,
2197            icier::Stie,
2198            icier::Stie,
2199            Icier_SPEC,
2200            crate::common::RW,
2201        >::from_register(self, 0)
2202    }
2203
2204    #[doc = "Arbitration-Lost Interrupt Request Enable"]
2205    #[inline(always)]
2206    pub fn alie(
2207        self,
2208    ) -> crate::common::RegisterField<
2209        1,
2210        0x1,
2211        1,
2212        0,
2213        icier::Alie,
2214        icier::Alie,
2215        Icier_SPEC,
2216        crate::common::RW,
2217    > {
2218        crate::common::RegisterField::<
2219            1,
2220            0x1,
2221            1,
2222            0,
2223            icier::Alie,
2224            icier::Alie,
2225            Icier_SPEC,
2226            crate::common::RW,
2227        >::from_register(self, 0)
2228    }
2229
2230    #[doc = "Timeout Interrupt Request Enable"]
2231    #[inline(always)]
2232    pub fn tmoie(
2233        self,
2234    ) -> crate::common::RegisterField<
2235        0,
2236        0x1,
2237        1,
2238        0,
2239        icier::Tmoie,
2240        icier::Tmoie,
2241        Icier_SPEC,
2242        crate::common::RW,
2243    > {
2244        crate::common::RegisterField::<
2245            0,
2246            0x1,
2247            1,
2248            0,
2249            icier::Tmoie,
2250            icier::Tmoie,
2251            Icier_SPEC,
2252            crate::common::RW,
2253        >::from_register(self, 0)
2254    }
2255}
2256impl ::core::default::Default for Icier {
2257    #[inline(always)]
2258    fn default() -> Icier {
2259        <crate::RegValueT<Icier_SPEC> as RegisterValue<_>>::new(0)
2260    }
2261}
2262pub mod icier {
2263
2264    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2265    pub struct Tie_SPEC;
2266    pub type Tie = crate::EnumBitfieldStruct<u8, Tie_SPEC>;
2267    impl Tie {
2268        #[doc = "Transmit data empty interrupt request (TXI) is disabled."]
2269        pub const _0: Self = Self::new(0);
2270
2271        #[doc = "Transmit data empty interrupt request (TXI) is enabled."]
2272        pub const _1: Self = Self::new(1);
2273    }
2274    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2275    pub struct Teie_SPEC;
2276    pub type Teie = crate::EnumBitfieldStruct<u8, Teie_SPEC>;
2277    impl Teie {
2278        #[doc = "Transmit end interrupt request (TEI) is disabled."]
2279        pub const _0: Self = Self::new(0);
2280
2281        #[doc = "Transmit end interrupt request (TEI) is enabled."]
2282        pub const _1: Self = Self::new(1);
2283    }
2284    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2285    pub struct Rie_SPEC;
2286    pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
2287    impl Rie {
2288        #[doc = "Receive data full interrupt request (RXI) is disabled."]
2289        pub const _0: Self = Self::new(0);
2290
2291        #[doc = "Receive data full interrupt request (RXI) is enabled."]
2292        pub const _1: Self = Self::new(1);
2293    }
2294    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2295    pub struct Nakie_SPEC;
2296    pub type Nakie = crate::EnumBitfieldStruct<u8, Nakie_SPEC>;
2297    impl Nakie {
2298        #[doc = "NACK reception interrupt request (NAKI) is disabled."]
2299        pub const _0: Self = Self::new(0);
2300
2301        #[doc = "NACK reception interrupt request (NAKI) is enabled."]
2302        pub const _1: Self = Self::new(1);
2303    }
2304    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2305    pub struct Spie_SPEC;
2306    pub type Spie = crate::EnumBitfieldStruct<u8, Spie_SPEC>;
2307    impl Spie {
2308        #[doc = "Stop condition detection interrupt request (SPI) is disabled."]
2309        pub const _0: Self = Self::new(0);
2310
2311        #[doc = "Stop condition detection interrupt request (SPI) is enabled."]
2312        pub const _1: Self = Self::new(1);
2313    }
2314    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2315    pub struct Stie_SPEC;
2316    pub type Stie = crate::EnumBitfieldStruct<u8, Stie_SPEC>;
2317    impl Stie {
2318        #[doc = "Start condition detection interrupt request (STI) is disabled."]
2319        pub const _0: Self = Self::new(0);
2320
2321        #[doc = "Start condition detection interrupt request (STI) is enabled."]
2322        pub const _1: Self = Self::new(1);
2323    }
2324    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2325    pub struct Alie_SPEC;
2326    pub type Alie = crate::EnumBitfieldStruct<u8, Alie_SPEC>;
2327    impl Alie {
2328        #[doc = "Arbitration-lost interrupt request (ALI) is disabled."]
2329        pub const _0: Self = Self::new(0);
2330
2331        #[doc = "Arbitration-lost interrupt request (ALI) is enabled."]
2332        pub const _1: Self = Self::new(1);
2333    }
2334    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2335    pub struct Tmoie_SPEC;
2336    pub type Tmoie = crate::EnumBitfieldStruct<u8, Tmoie_SPEC>;
2337    impl Tmoie {
2338        #[doc = "Timeout interrupt request (TMOI) is disabled."]
2339        pub const _0: Self = Self::new(0);
2340
2341        #[doc = "Timeout interrupt request (TMOI) is enabled."]
2342        pub const _1: Self = Self::new(1);
2343    }
2344}
2345#[doc(hidden)]
2346#[derive(Copy, Clone, Eq, PartialEq)]
2347pub struct Icsr1_SPEC;
2348impl crate::sealed::RegSpec for Icsr1_SPEC {
2349    type DataType = u8;
2350}
2351
2352#[doc = "I2C Bus Status Register 1"]
2353pub type Icsr1 = crate::RegValueT<Icsr1_SPEC>;
2354
2355impl Icsr1 {
2356    #[doc = "Host Address Detection Flag"]
2357    #[inline(always)]
2358    pub fn hoa(
2359        self,
2360    ) -> crate::common::RegisterField<
2361        7,
2362        0x1,
2363        1,
2364        0,
2365        icsr1::Hoa,
2366        icsr1::Hoa,
2367        Icsr1_SPEC,
2368        crate::common::RW,
2369    > {
2370        crate::common::RegisterField::<
2371            7,
2372            0x1,
2373            1,
2374            0,
2375            icsr1::Hoa,
2376            icsr1::Hoa,
2377            Icsr1_SPEC,
2378            crate::common::RW,
2379        >::from_register(self, 0)
2380    }
2381
2382    #[doc = "Device-ID Address Detection Flag"]
2383    #[inline(always)]
2384    pub fn did(
2385        self,
2386    ) -> crate::common::RegisterField<
2387        5,
2388        0x1,
2389        1,
2390        0,
2391        icsr1::Did,
2392        icsr1::Did,
2393        Icsr1_SPEC,
2394        crate::common::RW,
2395    > {
2396        crate::common::RegisterField::<
2397            5,
2398            0x1,
2399            1,
2400            0,
2401            icsr1::Did,
2402            icsr1::Did,
2403            Icsr1_SPEC,
2404            crate::common::RW,
2405        >::from_register(self, 0)
2406    }
2407
2408    #[doc = "General Call Address Detection Flag"]
2409    #[inline(always)]
2410    pub fn gca(
2411        self,
2412    ) -> crate::common::RegisterField<
2413        3,
2414        0x1,
2415        1,
2416        0,
2417        icsr1::Gca,
2418        icsr1::Gca,
2419        Icsr1_SPEC,
2420        crate::common::RW,
2421    > {
2422        crate::common::RegisterField::<
2423            3,
2424            0x1,
2425            1,
2426            0,
2427            icsr1::Gca,
2428            icsr1::Gca,
2429            Icsr1_SPEC,
2430            crate::common::RW,
2431        >::from_register(self, 0)
2432    }
2433
2434    #[doc = "Slave Address 2 Detection Flag"]
2435    #[inline(always)]
2436    pub fn aas2(
2437        self,
2438    ) -> crate::common::RegisterField<
2439        2,
2440        0x1,
2441        1,
2442        0,
2443        icsr1::Aas2,
2444        icsr1::Aas2,
2445        Icsr1_SPEC,
2446        crate::common::RW,
2447    > {
2448        crate::common::RegisterField::<
2449            2,
2450            0x1,
2451            1,
2452            0,
2453            icsr1::Aas2,
2454            icsr1::Aas2,
2455            Icsr1_SPEC,
2456            crate::common::RW,
2457        >::from_register(self, 0)
2458    }
2459
2460    #[doc = "Slave Address 1 Detection Flag"]
2461    #[inline(always)]
2462    pub fn aas1(
2463        self,
2464    ) -> crate::common::RegisterField<
2465        1,
2466        0x1,
2467        1,
2468        0,
2469        icsr1::Aas1,
2470        icsr1::Aas1,
2471        Icsr1_SPEC,
2472        crate::common::RW,
2473    > {
2474        crate::common::RegisterField::<
2475            1,
2476            0x1,
2477            1,
2478            0,
2479            icsr1::Aas1,
2480            icsr1::Aas1,
2481            Icsr1_SPEC,
2482            crate::common::RW,
2483        >::from_register(self, 0)
2484    }
2485
2486    #[doc = "Slave Address 0 Detection Flag"]
2487    #[inline(always)]
2488    pub fn aas0(
2489        self,
2490    ) -> crate::common::RegisterField<
2491        0,
2492        0x1,
2493        1,
2494        0,
2495        icsr1::Aas0,
2496        icsr1::Aas0,
2497        Icsr1_SPEC,
2498        crate::common::RW,
2499    > {
2500        crate::common::RegisterField::<
2501            0,
2502            0x1,
2503            1,
2504            0,
2505            icsr1::Aas0,
2506            icsr1::Aas0,
2507            Icsr1_SPEC,
2508            crate::common::RW,
2509        >::from_register(self, 0)
2510    }
2511}
2512impl ::core::default::Default for Icsr1 {
2513    #[inline(always)]
2514    fn default() -> Icsr1 {
2515        <crate::RegValueT<Icsr1_SPEC> as RegisterValue<_>>::new(0)
2516    }
2517}
2518pub mod icsr1 {
2519
2520    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2521    pub struct Hoa_SPEC;
2522    pub type Hoa = crate::EnumBitfieldStruct<u8, Hoa_SPEC>;
2523    impl Hoa {
2524        #[doc = "Host address is not detected."]
2525        pub const _0: Self = Self::new(0);
2526
2527        #[doc = "Host address is detected."]
2528        pub const _1: Self = Self::new(1);
2529    }
2530    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2531    pub struct Did_SPEC;
2532    pub type Did = crate::EnumBitfieldStruct<u8, Did_SPEC>;
2533    impl Did {
2534        #[doc = "Device-ID command is not detected."]
2535        pub const _0: Self = Self::new(0);
2536
2537        #[doc = "Device-ID command is detected."]
2538        pub const _1: Self = Self::new(1);
2539    }
2540    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2541    pub struct Gca_SPEC;
2542    pub type Gca = crate::EnumBitfieldStruct<u8, Gca_SPEC>;
2543    impl Gca {
2544        #[doc = "General call address is not detected."]
2545        pub const _0: Self = Self::new(0);
2546
2547        #[doc = "General call address is detected."]
2548        pub const _1: Self = Self::new(1);
2549    }
2550    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2551    pub struct Aas2_SPEC;
2552    pub type Aas2 = crate::EnumBitfieldStruct<u8, Aas2_SPEC>;
2553    impl Aas2 {
2554        #[doc = "Slave address 2 is not detected."]
2555        pub const _0: Self = Self::new(0);
2556
2557        #[doc = "Slave address 2 is detected"]
2558        pub const _1: Self = Self::new(1);
2559    }
2560    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2561    pub struct Aas1_SPEC;
2562    pub type Aas1 = crate::EnumBitfieldStruct<u8, Aas1_SPEC>;
2563    impl Aas1 {
2564        #[doc = "Slave address 1 is not detected."]
2565        pub const _0: Self = Self::new(0);
2566
2567        #[doc = "Slave address 1 is detected."]
2568        pub const _1: Self = Self::new(1);
2569    }
2570    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2571    pub struct Aas0_SPEC;
2572    pub type Aas0 = crate::EnumBitfieldStruct<u8, Aas0_SPEC>;
2573    impl Aas0 {
2574        #[doc = "Slave address 0 is not detected."]
2575        pub const _0: Self = Self::new(0);
2576
2577        #[doc = "Slave address 0 is detected."]
2578        pub const _1: Self = Self::new(1);
2579    }
2580}
2581#[doc(hidden)]
2582#[derive(Copy, Clone, Eq, PartialEq)]
2583pub struct Icsr2_SPEC;
2584impl crate::sealed::RegSpec for Icsr2_SPEC {
2585    type DataType = u8;
2586}
2587
2588#[doc = "I2C Bus Status Register 2"]
2589pub type Icsr2 = crate::RegValueT<Icsr2_SPEC>;
2590
2591impl Icsr2 {
2592    #[doc = "Transmit Data Empty Flag"]
2593    #[inline(always)]
2594    pub fn tdre(
2595        self,
2596    ) -> crate::common::RegisterField<
2597        7,
2598        0x1,
2599        1,
2600        0,
2601        icsr2::Tdre,
2602        icsr2::Tdre,
2603        Icsr2_SPEC,
2604        crate::common::R,
2605    > {
2606        crate::common::RegisterField::<
2607            7,
2608            0x1,
2609            1,
2610            0,
2611            icsr2::Tdre,
2612            icsr2::Tdre,
2613            Icsr2_SPEC,
2614            crate::common::R,
2615        >::from_register(self, 0)
2616    }
2617
2618    #[doc = "Transmit End Flag"]
2619    #[inline(always)]
2620    pub fn tend(
2621        self,
2622    ) -> crate::common::RegisterField<
2623        6,
2624        0x1,
2625        1,
2626        0,
2627        icsr2::Tend,
2628        icsr2::Tend,
2629        Icsr2_SPEC,
2630        crate::common::RW,
2631    > {
2632        crate::common::RegisterField::<
2633            6,
2634            0x1,
2635            1,
2636            0,
2637            icsr2::Tend,
2638            icsr2::Tend,
2639            Icsr2_SPEC,
2640            crate::common::RW,
2641        >::from_register(self, 0)
2642    }
2643
2644    #[doc = "Receive Data Full Flag"]
2645    #[inline(always)]
2646    pub fn rdrf(
2647        self,
2648    ) -> crate::common::RegisterField<
2649        5,
2650        0x1,
2651        1,
2652        0,
2653        icsr2::Rdrf,
2654        icsr2::Rdrf,
2655        Icsr2_SPEC,
2656        crate::common::RW,
2657    > {
2658        crate::common::RegisterField::<
2659            5,
2660            0x1,
2661            1,
2662            0,
2663            icsr2::Rdrf,
2664            icsr2::Rdrf,
2665            Icsr2_SPEC,
2666            crate::common::RW,
2667        >::from_register(self, 0)
2668    }
2669
2670    #[doc = "NACK Detection Flag"]
2671    #[inline(always)]
2672    pub fn nackf(
2673        self,
2674    ) -> crate::common::RegisterField<
2675        4,
2676        0x1,
2677        1,
2678        0,
2679        icsr2::Nackf,
2680        icsr2::Nackf,
2681        Icsr2_SPEC,
2682        crate::common::RW,
2683    > {
2684        crate::common::RegisterField::<
2685            4,
2686            0x1,
2687            1,
2688            0,
2689            icsr2::Nackf,
2690            icsr2::Nackf,
2691            Icsr2_SPEC,
2692            crate::common::RW,
2693        >::from_register(self, 0)
2694    }
2695
2696    #[doc = "Stop Condition Detection Flag"]
2697    #[inline(always)]
2698    pub fn stop(
2699        self,
2700    ) -> crate::common::RegisterField<
2701        3,
2702        0x1,
2703        1,
2704        0,
2705        icsr2::Stop,
2706        icsr2::Stop,
2707        Icsr2_SPEC,
2708        crate::common::RW,
2709    > {
2710        crate::common::RegisterField::<
2711            3,
2712            0x1,
2713            1,
2714            0,
2715            icsr2::Stop,
2716            icsr2::Stop,
2717            Icsr2_SPEC,
2718            crate::common::RW,
2719        >::from_register(self, 0)
2720    }
2721
2722    #[doc = "Start Condition Detection Flag"]
2723    #[inline(always)]
2724    pub fn start(
2725        self,
2726    ) -> crate::common::RegisterField<
2727        2,
2728        0x1,
2729        1,
2730        0,
2731        icsr2::Start,
2732        icsr2::Start,
2733        Icsr2_SPEC,
2734        crate::common::RW,
2735    > {
2736        crate::common::RegisterField::<
2737            2,
2738            0x1,
2739            1,
2740            0,
2741            icsr2::Start,
2742            icsr2::Start,
2743            Icsr2_SPEC,
2744            crate::common::RW,
2745        >::from_register(self, 0)
2746    }
2747
2748    #[doc = "Arbitration-Lost Flag"]
2749    #[inline(always)]
2750    pub fn al(
2751        self,
2752    ) -> crate::common::RegisterField<
2753        1,
2754        0x1,
2755        1,
2756        0,
2757        icsr2::Al,
2758        icsr2::Al,
2759        Icsr2_SPEC,
2760        crate::common::RW,
2761    > {
2762        crate::common::RegisterField::<
2763            1,
2764            0x1,
2765            1,
2766            0,
2767            icsr2::Al,
2768            icsr2::Al,
2769            Icsr2_SPEC,
2770            crate::common::RW,
2771        >::from_register(self, 0)
2772    }
2773
2774    #[doc = "Timeout Detection Flag"]
2775    #[inline(always)]
2776    pub fn tmof(
2777        self,
2778    ) -> crate::common::RegisterField<
2779        0,
2780        0x1,
2781        1,
2782        0,
2783        icsr2::Tmof,
2784        icsr2::Tmof,
2785        Icsr2_SPEC,
2786        crate::common::RW,
2787    > {
2788        crate::common::RegisterField::<
2789            0,
2790            0x1,
2791            1,
2792            0,
2793            icsr2::Tmof,
2794            icsr2::Tmof,
2795            Icsr2_SPEC,
2796            crate::common::RW,
2797        >::from_register(self, 0)
2798    }
2799}
2800impl ::core::default::Default for Icsr2 {
2801    #[inline(always)]
2802    fn default() -> Icsr2 {
2803        <crate::RegValueT<Icsr2_SPEC> as RegisterValue<_>>::new(0)
2804    }
2805}
2806pub mod icsr2 {
2807
2808    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2809    pub struct Tdre_SPEC;
2810    pub type Tdre = crate::EnumBitfieldStruct<u8, Tdre_SPEC>;
2811    impl Tdre {
2812        #[doc = "ICDRT contains transmit data."]
2813        pub const _0: Self = Self::new(0);
2814
2815        #[doc = "ICDRT contains no transmit data."]
2816        pub const _1: Self = Self::new(1);
2817    }
2818    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2819    pub struct Tend_SPEC;
2820    pub type Tend = crate::EnumBitfieldStruct<u8, Tend_SPEC>;
2821    impl Tend {
2822        #[doc = "Data is being transmitted."]
2823        pub const _0: Self = Self::new(0);
2824
2825        #[doc = "Data has been transmitted."]
2826        pub const _1: Self = Self::new(1);
2827    }
2828    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2829    pub struct Rdrf_SPEC;
2830    pub type Rdrf = crate::EnumBitfieldStruct<u8, Rdrf_SPEC>;
2831    impl Rdrf {
2832        #[doc = "ICDRR contains no receive data."]
2833        pub const _0: Self = Self::new(0);
2834
2835        #[doc = "ICDRR contains receive data."]
2836        pub const _1: Self = Self::new(1);
2837    }
2838    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2839    pub struct Nackf_SPEC;
2840    pub type Nackf = crate::EnumBitfieldStruct<u8, Nackf_SPEC>;
2841    impl Nackf {
2842        #[doc = "NACK is not detected."]
2843        pub const _0: Self = Self::new(0);
2844
2845        #[doc = "NACK is detected."]
2846        pub const _1: Self = Self::new(1);
2847    }
2848    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2849    pub struct Stop_SPEC;
2850    pub type Stop = crate::EnumBitfieldStruct<u8, Stop_SPEC>;
2851    impl Stop {
2852        #[doc = "Stop condition is not detected."]
2853        pub const _0: Self = Self::new(0);
2854
2855        #[doc = "Stop condition is detected."]
2856        pub const _1: Self = Self::new(1);
2857    }
2858    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2859    pub struct Start_SPEC;
2860    pub type Start = crate::EnumBitfieldStruct<u8, Start_SPEC>;
2861    impl Start {
2862        #[doc = "Start condition is not detected."]
2863        pub const _0: Self = Self::new(0);
2864
2865        #[doc = "Start condition is detected."]
2866        pub const _1: Self = Self::new(1);
2867    }
2868    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2869    pub struct Al_SPEC;
2870    pub type Al = crate::EnumBitfieldStruct<u8, Al_SPEC>;
2871    impl Al {
2872        #[doc = "Arbitration is not lost."]
2873        pub const _0: Self = Self::new(0);
2874
2875        #[doc = "Arbitration is lost."]
2876        pub const _1: Self = Self::new(1);
2877    }
2878    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2879    pub struct Tmof_SPEC;
2880    pub type Tmof = crate::EnumBitfieldStruct<u8, Tmof_SPEC>;
2881    impl Tmof {
2882        #[doc = "Timeout is not detected."]
2883        pub const _0: Self = Self::new(0);
2884
2885        #[doc = "Timeout is detected."]
2886        pub const _1: Self = Self::new(1);
2887    }
2888}
2889#[doc(hidden)]
2890#[derive(Copy, Clone, Eq, PartialEq)]
2891pub struct Sarl_SPEC;
2892impl crate::sealed::RegSpec for Sarl_SPEC {
2893    type DataType = u8;
2894}
2895
2896#[doc = "Slave Address Register L%s"]
2897pub type Sarl = crate::RegValueT<Sarl_SPEC>;
2898
2899impl Sarl {
2900    #[doc = "A slave address is set.7-Bit Address = SVA\\[7:1\\] 10-Bit Address = { SVA9,SVA8,SVA\\[7:0\\] }"]
2901    #[inline(always)]
2902    pub fn sva(
2903        self,
2904    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Sarl_SPEC, crate::common::RW> {
2905        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Sarl_SPEC,crate::common::RW>::from_register(self,0)
2906    }
2907}
2908impl ::core::default::Default for Sarl {
2909    #[inline(always)]
2910    fn default() -> Sarl {
2911        <crate::RegValueT<Sarl_SPEC> as RegisterValue<_>>::new(0)
2912    }
2913}
2914
2915#[doc(hidden)]
2916#[derive(Copy, Clone, Eq, PartialEq)]
2917pub struct Saru_SPEC;
2918impl crate::sealed::RegSpec for Saru_SPEC {
2919    type DataType = u8;
2920}
2921
2922#[doc = "Slave Address Register U%s"]
2923pub type Saru = crate::RegValueT<Saru_SPEC>;
2924
2925impl Saru {
2926    #[doc = "10-Bit Address(bit9)"]
2927    #[inline(always)]
2928    pub fn sva9(self) -> crate::common::RegisterFieldBool<2, 1, 0, Saru_SPEC, crate::common::RW> {
2929        crate::common::RegisterFieldBool::<2, 1, 0, Saru_SPEC, crate::common::RW>::from_register(
2930            self, 0,
2931        )
2932    }
2933
2934    #[doc = "10-Bit Address(bit8)"]
2935    #[inline(always)]
2936    pub fn sva8(self) -> crate::common::RegisterFieldBool<1, 1, 0, Saru_SPEC, crate::common::RW> {
2937        crate::common::RegisterFieldBool::<1, 1, 0, Saru_SPEC, crate::common::RW>::from_register(
2938            self, 0,
2939        )
2940    }
2941
2942    #[doc = "7-Bit/10-Bit Address Format Selection"]
2943    #[inline(always)]
2944    pub fn fs(
2945        self,
2946    ) -> crate::common::RegisterField<0, 0x1, 1, 0, saru::Fs, saru::Fs, Saru_SPEC, crate::common::RW>
2947    {
2948        crate::common::RegisterField::<0,0x1,1,0,saru::Fs,saru::Fs,Saru_SPEC,crate::common::RW>::from_register(self,0)
2949    }
2950}
2951impl ::core::default::Default for Saru {
2952    #[inline(always)]
2953    fn default() -> Saru {
2954        <crate::RegValueT<Saru_SPEC> as RegisterValue<_>>::new(0)
2955    }
2956}
2957pub mod saru {
2958
2959    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2960    pub struct Fs_SPEC;
2961    pub type Fs = crate::EnumBitfieldStruct<u8, Fs_SPEC>;
2962    impl Fs {
2963        #[doc = "The 7-bit address format is selected."]
2964        pub const _0: Self = Self::new(0);
2965
2966        #[doc = "The 10-bit address format is selected."]
2967        pub const _1: Self = Self::new(1);
2968    }
2969}
2970#[doc(hidden)]
2971#[derive(Copy, Clone, Eq, PartialEq)]
2972pub struct Icbrl_SPEC;
2973impl crate::sealed::RegSpec for Icbrl_SPEC {
2974    type DataType = u8;
2975}
2976
2977#[doc = "I2C Bus Bit Rate Low-Level Register"]
2978pub type Icbrl = crate::RegValueT<Icbrl_SPEC>;
2979
2980impl Icbrl {
2981    #[doc = "Bit Rate Low-Level Period(Low-level period of SCL clock)"]
2982    #[inline(always)]
2983    pub fn brl(
2984        self,
2985    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Icbrl_SPEC, crate::common::RW> {
2986        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Icbrl_SPEC,crate::common::RW>::from_register(self,0)
2987    }
2988}
2989impl ::core::default::Default for Icbrl {
2990    #[inline(always)]
2991    fn default() -> Icbrl {
2992        <crate::RegValueT<Icbrl_SPEC> as RegisterValue<_>>::new(255)
2993    }
2994}
2995
2996#[doc(hidden)]
2997#[derive(Copy, Clone, Eq, PartialEq)]
2998pub struct Icbrh_SPEC;
2999impl crate::sealed::RegSpec for Icbrh_SPEC {
3000    type DataType = u8;
3001}
3002
3003#[doc = "I2C Bus Bit Rate High-Level Register"]
3004pub type Icbrh = crate::RegValueT<Icbrh_SPEC>;
3005
3006impl Icbrh {
3007    #[doc = "Bit Rate High-Level Period(High-level period of SCL clock)"]
3008    #[inline(always)]
3009    pub fn brh(
3010        self,
3011    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Icbrh_SPEC, crate::common::RW> {
3012        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Icbrh_SPEC,crate::common::RW>::from_register(self,0)
3013    }
3014}
3015impl ::core::default::Default for Icbrh {
3016    #[inline(always)]
3017    fn default() -> Icbrh {
3018        <crate::RegValueT<Icbrh_SPEC> as RegisterValue<_>>::new(255)
3019    }
3020}
3021
3022#[doc(hidden)]
3023#[derive(Copy, Clone, Eq, PartialEq)]
3024pub struct Icdrt_SPEC;
3025impl crate::sealed::RegSpec for Icdrt_SPEC {
3026    type DataType = u8;
3027}
3028
3029#[doc = "I2C Bus Transmit Data Register"]
3030pub type Icdrt = crate::RegValueT<Icdrt_SPEC>;
3031
3032impl Icdrt {
3033    #[doc = "8-bit read-write register that stores transmit data."]
3034    #[inline(always)]
3035    pub fn icdrt(
3036        self,
3037    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Icdrt_SPEC, crate::common::RW> {
3038        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Icdrt_SPEC,crate::common::RW>::from_register(self,0)
3039    }
3040}
3041impl ::core::default::Default for Icdrt {
3042    #[inline(always)]
3043    fn default() -> Icdrt {
3044        <crate::RegValueT<Icdrt_SPEC> as RegisterValue<_>>::new(255)
3045    }
3046}
3047
3048#[doc(hidden)]
3049#[derive(Copy, Clone, Eq, PartialEq)]
3050pub struct Icdrr_SPEC;
3051impl crate::sealed::RegSpec for Icdrr_SPEC {
3052    type DataType = u8;
3053}
3054
3055#[doc = "I2C Bus Receive Data Register"]
3056pub type Icdrr = crate::RegValueT<Icdrr_SPEC>;
3057
3058impl Icdrr {
3059    #[doc = "8-bit register that stores the received data"]
3060    #[inline(always)]
3061    pub fn icdrr(
3062        self,
3063    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Icdrr_SPEC, crate::common::R> {
3064        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Icdrr_SPEC,crate::common::R>::from_register(self,0)
3065    }
3066}
3067impl ::core::default::Default for Icdrr {
3068    #[inline(always)]
3069    fn default() -> Icdrr {
3070        <crate::RegValueT<Icdrr_SPEC> as RegisterValue<_>>::new(0)
3071    }
3072}
ra6m2_pac/iic1.rs

ra6m2_pac/
iic1.rs
