1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Interrupt Controller"]
28unsafe impl ::core::marker::Send for super::Icu {}
29unsafe impl ::core::marker::Sync for super::Icu {}
30impl super::Icu {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "IRQ Control Register %s"]
38 #[inline(always)]
39 pub const fn irqcr(
40 &self,
41 ) -> &'static crate::common::ClusterRegisterArray<
42 crate::common::Reg<self::Irqcr_SPEC, crate::common::RW>,
43 16,
44 0x1,
45 > {
46 unsafe {
47 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
48 }
49 }
50 #[inline(always)]
51 pub const fn irqcr0(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
52 unsafe {
53 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
54 self._svd2pac_as_ptr().add(0x0usize),
55 )
56 }
57 }
58 #[inline(always)]
59 pub const fn irqcr1(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(0x1usize),
63 )
64 }
65 }
66 #[inline(always)]
67 pub const fn irqcr2(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
68 unsafe {
69 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
70 self._svd2pac_as_ptr().add(0x2usize),
71 )
72 }
73 }
74 #[inline(always)]
75 pub const fn irqcr3(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
76 unsafe {
77 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
78 self._svd2pac_as_ptr().add(0x3usize),
79 )
80 }
81 }
82 #[inline(always)]
83 pub const fn irqcr4(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
84 unsafe {
85 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
86 self._svd2pac_as_ptr().add(0x4usize),
87 )
88 }
89 }
90 #[inline(always)]
91 pub const fn irqcr5(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
92 unsafe {
93 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
94 self._svd2pac_as_ptr().add(0x5usize),
95 )
96 }
97 }
98 #[inline(always)]
99 pub const fn irqcr6(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(0x6usize),
103 )
104 }
105 }
106 #[inline(always)]
107 pub const fn irqcr7(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
108 unsafe {
109 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
110 self._svd2pac_as_ptr().add(0x7usize),
111 )
112 }
113 }
114 #[inline(always)]
115 pub const fn irqcr8(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
116 unsafe {
117 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
118 self._svd2pac_as_ptr().add(0x8usize),
119 )
120 }
121 }
122 #[inline(always)]
123 pub const fn irqcr9(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
124 unsafe {
125 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
126 self._svd2pac_as_ptr().add(0x9usize),
127 )
128 }
129 }
130 #[inline(always)]
131 pub const fn irqcr10(
132 &self,
133 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
134 unsafe {
135 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
136 self._svd2pac_as_ptr().add(0xausize),
137 )
138 }
139 }
140 #[inline(always)]
141 pub const fn irqcr11(
142 &self,
143 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
144 unsafe {
145 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
146 self._svd2pac_as_ptr().add(0xbusize),
147 )
148 }
149 }
150 #[inline(always)]
151 pub const fn irqcr12(
152 &self,
153 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
154 unsafe {
155 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
156 self._svd2pac_as_ptr().add(0xcusize),
157 )
158 }
159 }
160 #[inline(always)]
161 pub const fn irqcr13(
162 &self,
163 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
164 unsafe {
165 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
166 self._svd2pac_as_ptr().add(0xdusize),
167 )
168 }
169 }
170 #[inline(always)]
171 pub const fn irqcr14(
172 &self,
173 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
174 unsafe {
175 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
176 self._svd2pac_as_ptr().add(0xeusize),
177 )
178 }
179 }
180 #[inline(always)]
181 pub const fn irqcr15(
182 &self,
183 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
184 unsafe {
185 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
186 self._svd2pac_as_ptr().add(0xfusize),
187 )
188 }
189 }
190
191 #[doc = "Non-Maskable Interrupt Status Register"]
192 #[inline(always)]
193 pub const fn nmisr(&self) -> &'static crate::common::Reg<self::Nmisr_SPEC, crate::common::R> {
194 unsafe {
195 crate::common::Reg::<self::Nmisr_SPEC, crate::common::R>::from_ptr(
196 self._svd2pac_as_ptr().add(320usize),
197 )
198 }
199 }
200
201 #[doc = "Non-Maskable Interrupt Enable Register"]
202 #[inline(always)]
203 pub const fn nmier(&self) -> &'static crate::common::Reg<self::Nmier_SPEC, crate::common::RW> {
204 unsafe {
205 crate::common::Reg::<self::Nmier_SPEC, crate::common::RW>::from_ptr(
206 self._svd2pac_as_ptr().add(288usize),
207 )
208 }
209 }
210
211 #[doc = "Non-Maskable Interrupt Status Clear Register"]
212 #[inline(always)]
213 pub const fn nmiclr(&self) -> &'static crate::common::Reg<self::Nmiclr_SPEC, crate::common::W> {
214 unsafe {
215 crate::common::Reg::<self::Nmiclr_SPEC, crate::common::W>::from_ptr(
216 self._svd2pac_as_ptr().add(304usize),
217 )
218 }
219 }
220
221 #[doc = "NMI Pin Interrupt Control Register"]
222 #[inline(always)]
223 pub const fn nmicr(&self) -> &'static crate::common::Reg<self::Nmicr_SPEC, crate::common::RW> {
224 unsafe {
225 crate::common::Reg::<self::Nmicr_SPEC, crate::common::RW>::from_ptr(
226 self._svd2pac_as_ptr().add(256usize),
227 )
228 }
229 }
230
231 #[doc = "INT Event Link Setting Register %s"]
232 #[inline(always)]
233 pub const fn ielsr(
234 &self,
235 ) -> &'static crate::common::ClusterRegisterArray<
236 crate::common::Reg<self::Ielsr_SPEC, crate::common::RW>,
237 96,
238 0x4,
239 > {
240 unsafe {
241 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x300usize))
242 }
243 }
244 #[inline(always)]
245 pub const fn ielsr0(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
246 unsafe {
247 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
248 self._svd2pac_as_ptr().add(0x300usize),
249 )
250 }
251 }
252 #[inline(always)]
253 pub const fn ielsr1(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
254 unsafe {
255 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
256 self._svd2pac_as_ptr().add(0x304usize),
257 )
258 }
259 }
260 #[inline(always)]
261 pub const fn ielsr2(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
262 unsafe {
263 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
264 self._svd2pac_as_ptr().add(0x308usize),
265 )
266 }
267 }
268 #[inline(always)]
269 pub const fn ielsr3(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
270 unsafe {
271 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
272 self._svd2pac_as_ptr().add(0x30cusize),
273 )
274 }
275 }
276 #[inline(always)]
277 pub const fn ielsr4(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
278 unsafe {
279 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
280 self._svd2pac_as_ptr().add(0x310usize),
281 )
282 }
283 }
284 #[inline(always)]
285 pub const fn ielsr5(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
286 unsafe {
287 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
288 self._svd2pac_as_ptr().add(0x314usize),
289 )
290 }
291 }
292 #[inline(always)]
293 pub const fn ielsr6(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
294 unsafe {
295 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
296 self._svd2pac_as_ptr().add(0x318usize),
297 )
298 }
299 }
300 #[inline(always)]
301 pub const fn ielsr7(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
302 unsafe {
303 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
304 self._svd2pac_as_ptr().add(0x31cusize),
305 )
306 }
307 }
308 #[inline(always)]
309 pub const fn ielsr8(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
310 unsafe {
311 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
312 self._svd2pac_as_ptr().add(0x320usize),
313 )
314 }
315 }
316 #[inline(always)]
317 pub const fn ielsr9(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
318 unsafe {
319 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
320 self._svd2pac_as_ptr().add(0x324usize),
321 )
322 }
323 }
324 #[inline(always)]
325 pub const fn ielsr10(
326 &self,
327 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
328 unsafe {
329 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
330 self._svd2pac_as_ptr().add(0x328usize),
331 )
332 }
333 }
334 #[inline(always)]
335 pub const fn ielsr11(
336 &self,
337 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
338 unsafe {
339 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
340 self._svd2pac_as_ptr().add(0x32cusize),
341 )
342 }
343 }
344 #[inline(always)]
345 pub const fn ielsr12(
346 &self,
347 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
348 unsafe {
349 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
350 self._svd2pac_as_ptr().add(0x330usize),
351 )
352 }
353 }
354 #[inline(always)]
355 pub const fn ielsr13(
356 &self,
357 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
358 unsafe {
359 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
360 self._svd2pac_as_ptr().add(0x334usize),
361 )
362 }
363 }
364 #[inline(always)]
365 pub const fn ielsr14(
366 &self,
367 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
368 unsafe {
369 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
370 self._svd2pac_as_ptr().add(0x338usize),
371 )
372 }
373 }
374 #[inline(always)]
375 pub const fn ielsr15(
376 &self,
377 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
378 unsafe {
379 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
380 self._svd2pac_as_ptr().add(0x33cusize),
381 )
382 }
383 }
384 #[inline(always)]
385 pub const fn ielsr16(
386 &self,
387 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
388 unsafe {
389 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
390 self._svd2pac_as_ptr().add(0x340usize),
391 )
392 }
393 }
394 #[inline(always)]
395 pub const fn ielsr17(
396 &self,
397 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
398 unsafe {
399 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
400 self._svd2pac_as_ptr().add(0x344usize),
401 )
402 }
403 }
404 #[inline(always)]
405 pub const fn ielsr18(
406 &self,
407 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
408 unsafe {
409 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
410 self._svd2pac_as_ptr().add(0x348usize),
411 )
412 }
413 }
414 #[inline(always)]
415 pub const fn ielsr19(
416 &self,
417 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
418 unsafe {
419 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
420 self._svd2pac_as_ptr().add(0x34cusize),
421 )
422 }
423 }
424 #[inline(always)]
425 pub const fn ielsr20(
426 &self,
427 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
428 unsafe {
429 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
430 self._svd2pac_as_ptr().add(0x350usize),
431 )
432 }
433 }
434 #[inline(always)]
435 pub const fn ielsr21(
436 &self,
437 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
438 unsafe {
439 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
440 self._svd2pac_as_ptr().add(0x354usize),
441 )
442 }
443 }
444 #[inline(always)]
445 pub const fn ielsr22(
446 &self,
447 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
448 unsafe {
449 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
450 self._svd2pac_as_ptr().add(0x358usize),
451 )
452 }
453 }
454 #[inline(always)]
455 pub const fn ielsr23(
456 &self,
457 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
458 unsafe {
459 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
460 self._svd2pac_as_ptr().add(0x35cusize),
461 )
462 }
463 }
464 #[inline(always)]
465 pub const fn ielsr24(
466 &self,
467 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
468 unsafe {
469 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
470 self._svd2pac_as_ptr().add(0x360usize),
471 )
472 }
473 }
474 #[inline(always)]
475 pub const fn ielsr25(
476 &self,
477 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
478 unsafe {
479 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
480 self._svd2pac_as_ptr().add(0x364usize),
481 )
482 }
483 }
484 #[inline(always)]
485 pub const fn ielsr26(
486 &self,
487 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
488 unsafe {
489 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
490 self._svd2pac_as_ptr().add(0x368usize),
491 )
492 }
493 }
494 #[inline(always)]
495 pub const fn ielsr27(
496 &self,
497 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
498 unsafe {
499 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
500 self._svd2pac_as_ptr().add(0x36cusize),
501 )
502 }
503 }
504 #[inline(always)]
505 pub const fn ielsr28(
506 &self,
507 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
508 unsafe {
509 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
510 self._svd2pac_as_ptr().add(0x370usize),
511 )
512 }
513 }
514 #[inline(always)]
515 pub const fn ielsr29(
516 &self,
517 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
518 unsafe {
519 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
520 self._svd2pac_as_ptr().add(0x374usize),
521 )
522 }
523 }
524 #[inline(always)]
525 pub const fn ielsr30(
526 &self,
527 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
528 unsafe {
529 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
530 self._svd2pac_as_ptr().add(0x378usize),
531 )
532 }
533 }
534 #[inline(always)]
535 pub const fn ielsr31(
536 &self,
537 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
538 unsafe {
539 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
540 self._svd2pac_as_ptr().add(0x37cusize),
541 )
542 }
543 }
544 #[inline(always)]
545 pub const fn ielsr32(
546 &self,
547 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
548 unsafe {
549 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
550 self._svd2pac_as_ptr().add(0x380usize),
551 )
552 }
553 }
554 #[inline(always)]
555 pub const fn ielsr33(
556 &self,
557 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
558 unsafe {
559 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
560 self._svd2pac_as_ptr().add(0x384usize),
561 )
562 }
563 }
564 #[inline(always)]
565 pub const fn ielsr34(
566 &self,
567 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
568 unsafe {
569 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
570 self._svd2pac_as_ptr().add(0x388usize),
571 )
572 }
573 }
574 #[inline(always)]
575 pub const fn ielsr35(
576 &self,
577 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
578 unsafe {
579 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
580 self._svd2pac_as_ptr().add(0x38cusize),
581 )
582 }
583 }
584 #[inline(always)]
585 pub const fn ielsr36(
586 &self,
587 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
588 unsafe {
589 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
590 self._svd2pac_as_ptr().add(0x390usize),
591 )
592 }
593 }
594 #[inline(always)]
595 pub const fn ielsr37(
596 &self,
597 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
598 unsafe {
599 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
600 self._svd2pac_as_ptr().add(0x394usize),
601 )
602 }
603 }
604 #[inline(always)]
605 pub const fn ielsr38(
606 &self,
607 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
608 unsafe {
609 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
610 self._svd2pac_as_ptr().add(0x398usize),
611 )
612 }
613 }
614 #[inline(always)]
615 pub const fn ielsr39(
616 &self,
617 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
618 unsafe {
619 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
620 self._svd2pac_as_ptr().add(0x39cusize),
621 )
622 }
623 }
624 #[inline(always)]
625 pub const fn ielsr40(
626 &self,
627 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
628 unsafe {
629 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
630 self._svd2pac_as_ptr().add(0x3a0usize),
631 )
632 }
633 }
634 #[inline(always)]
635 pub const fn ielsr41(
636 &self,
637 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
638 unsafe {
639 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
640 self._svd2pac_as_ptr().add(0x3a4usize),
641 )
642 }
643 }
644 #[inline(always)]
645 pub const fn ielsr42(
646 &self,
647 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
648 unsafe {
649 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
650 self._svd2pac_as_ptr().add(0x3a8usize),
651 )
652 }
653 }
654 #[inline(always)]
655 pub const fn ielsr43(
656 &self,
657 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
658 unsafe {
659 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
660 self._svd2pac_as_ptr().add(0x3acusize),
661 )
662 }
663 }
664 #[inline(always)]
665 pub const fn ielsr44(
666 &self,
667 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
668 unsafe {
669 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
670 self._svd2pac_as_ptr().add(0x3b0usize),
671 )
672 }
673 }
674 #[inline(always)]
675 pub const fn ielsr45(
676 &self,
677 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
678 unsafe {
679 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
680 self._svd2pac_as_ptr().add(0x3b4usize),
681 )
682 }
683 }
684 #[inline(always)]
685 pub const fn ielsr46(
686 &self,
687 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
688 unsafe {
689 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
690 self._svd2pac_as_ptr().add(0x3b8usize),
691 )
692 }
693 }
694 #[inline(always)]
695 pub const fn ielsr47(
696 &self,
697 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
698 unsafe {
699 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
700 self._svd2pac_as_ptr().add(0x3bcusize),
701 )
702 }
703 }
704 #[inline(always)]
705 pub const fn ielsr48(
706 &self,
707 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
708 unsafe {
709 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
710 self._svd2pac_as_ptr().add(0x3c0usize),
711 )
712 }
713 }
714 #[inline(always)]
715 pub const fn ielsr49(
716 &self,
717 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
718 unsafe {
719 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
720 self._svd2pac_as_ptr().add(0x3c4usize),
721 )
722 }
723 }
724 #[inline(always)]
725 pub const fn ielsr50(
726 &self,
727 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
728 unsafe {
729 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
730 self._svd2pac_as_ptr().add(0x3c8usize),
731 )
732 }
733 }
734 #[inline(always)]
735 pub const fn ielsr51(
736 &self,
737 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
738 unsafe {
739 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
740 self._svd2pac_as_ptr().add(0x3ccusize),
741 )
742 }
743 }
744 #[inline(always)]
745 pub const fn ielsr52(
746 &self,
747 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
748 unsafe {
749 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
750 self._svd2pac_as_ptr().add(0x3d0usize),
751 )
752 }
753 }
754 #[inline(always)]
755 pub const fn ielsr53(
756 &self,
757 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
758 unsafe {
759 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
760 self._svd2pac_as_ptr().add(0x3d4usize),
761 )
762 }
763 }
764 #[inline(always)]
765 pub const fn ielsr54(
766 &self,
767 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
768 unsafe {
769 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
770 self._svd2pac_as_ptr().add(0x3d8usize),
771 )
772 }
773 }
774 #[inline(always)]
775 pub const fn ielsr55(
776 &self,
777 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
778 unsafe {
779 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
780 self._svd2pac_as_ptr().add(0x3dcusize),
781 )
782 }
783 }
784 #[inline(always)]
785 pub const fn ielsr56(
786 &self,
787 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
788 unsafe {
789 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
790 self._svd2pac_as_ptr().add(0x3e0usize),
791 )
792 }
793 }
794 #[inline(always)]
795 pub const fn ielsr57(
796 &self,
797 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
798 unsafe {
799 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
800 self._svd2pac_as_ptr().add(0x3e4usize),
801 )
802 }
803 }
804 #[inline(always)]
805 pub const fn ielsr58(
806 &self,
807 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
808 unsafe {
809 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
810 self._svd2pac_as_ptr().add(0x3e8usize),
811 )
812 }
813 }
814 #[inline(always)]
815 pub const fn ielsr59(
816 &self,
817 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
818 unsafe {
819 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
820 self._svd2pac_as_ptr().add(0x3ecusize),
821 )
822 }
823 }
824 #[inline(always)]
825 pub const fn ielsr60(
826 &self,
827 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
828 unsafe {
829 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
830 self._svd2pac_as_ptr().add(0x3f0usize),
831 )
832 }
833 }
834 #[inline(always)]
835 pub const fn ielsr61(
836 &self,
837 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
838 unsafe {
839 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
840 self._svd2pac_as_ptr().add(0x3f4usize),
841 )
842 }
843 }
844 #[inline(always)]
845 pub const fn ielsr62(
846 &self,
847 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
848 unsafe {
849 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
850 self._svd2pac_as_ptr().add(0x3f8usize),
851 )
852 }
853 }
854 #[inline(always)]
855 pub const fn ielsr63(
856 &self,
857 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
858 unsafe {
859 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
860 self._svd2pac_as_ptr().add(0x3fcusize),
861 )
862 }
863 }
864 #[inline(always)]
865 pub const fn ielsr64(
866 &self,
867 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
868 unsafe {
869 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
870 self._svd2pac_as_ptr().add(0x400usize),
871 )
872 }
873 }
874 #[inline(always)]
875 pub const fn ielsr65(
876 &self,
877 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
878 unsafe {
879 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
880 self._svd2pac_as_ptr().add(0x404usize),
881 )
882 }
883 }
884 #[inline(always)]
885 pub const fn ielsr66(
886 &self,
887 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
888 unsafe {
889 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
890 self._svd2pac_as_ptr().add(0x408usize),
891 )
892 }
893 }
894 #[inline(always)]
895 pub const fn ielsr67(
896 &self,
897 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
898 unsafe {
899 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
900 self._svd2pac_as_ptr().add(0x40cusize),
901 )
902 }
903 }
904 #[inline(always)]
905 pub const fn ielsr68(
906 &self,
907 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
908 unsafe {
909 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
910 self._svd2pac_as_ptr().add(0x410usize),
911 )
912 }
913 }
914 #[inline(always)]
915 pub const fn ielsr69(
916 &self,
917 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
918 unsafe {
919 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
920 self._svd2pac_as_ptr().add(0x414usize),
921 )
922 }
923 }
924 #[inline(always)]
925 pub const fn ielsr70(
926 &self,
927 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
928 unsafe {
929 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
930 self._svd2pac_as_ptr().add(0x418usize),
931 )
932 }
933 }
934 #[inline(always)]
935 pub const fn ielsr71(
936 &self,
937 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
938 unsafe {
939 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
940 self._svd2pac_as_ptr().add(0x41cusize),
941 )
942 }
943 }
944 #[inline(always)]
945 pub const fn ielsr72(
946 &self,
947 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
948 unsafe {
949 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
950 self._svd2pac_as_ptr().add(0x420usize),
951 )
952 }
953 }
954 #[inline(always)]
955 pub const fn ielsr73(
956 &self,
957 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
958 unsafe {
959 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
960 self._svd2pac_as_ptr().add(0x424usize),
961 )
962 }
963 }
964 #[inline(always)]
965 pub const fn ielsr74(
966 &self,
967 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
968 unsafe {
969 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
970 self._svd2pac_as_ptr().add(0x428usize),
971 )
972 }
973 }
974 #[inline(always)]
975 pub const fn ielsr75(
976 &self,
977 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
978 unsafe {
979 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
980 self._svd2pac_as_ptr().add(0x42cusize),
981 )
982 }
983 }
984 #[inline(always)]
985 pub const fn ielsr76(
986 &self,
987 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
988 unsafe {
989 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
990 self._svd2pac_as_ptr().add(0x430usize),
991 )
992 }
993 }
994 #[inline(always)]
995 pub const fn ielsr77(
996 &self,
997 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
998 unsafe {
999 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1000 self._svd2pac_as_ptr().add(0x434usize),
1001 )
1002 }
1003 }
1004 #[inline(always)]
1005 pub const fn ielsr78(
1006 &self,
1007 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1008 unsafe {
1009 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1010 self._svd2pac_as_ptr().add(0x438usize),
1011 )
1012 }
1013 }
1014 #[inline(always)]
1015 pub const fn ielsr79(
1016 &self,
1017 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1018 unsafe {
1019 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1020 self._svd2pac_as_ptr().add(0x43cusize),
1021 )
1022 }
1023 }
1024 #[inline(always)]
1025 pub const fn ielsr80(
1026 &self,
1027 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1028 unsafe {
1029 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1030 self._svd2pac_as_ptr().add(0x440usize),
1031 )
1032 }
1033 }
1034 #[inline(always)]
1035 pub const fn ielsr81(
1036 &self,
1037 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1038 unsafe {
1039 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1040 self._svd2pac_as_ptr().add(0x444usize),
1041 )
1042 }
1043 }
1044 #[inline(always)]
1045 pub const fn ielsr82(
1046 &self,
1047 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1048 unsafe {
1049 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1050 self._svd2pac_as_ptr().add(0x448usize),
1051 )
1052 }
1053 }
1054 #[inline(always)]
1055 pub const fn ielsr83(
1056 &self,
1057 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1058 unsafe {
1059 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1060 self._svd2pac_as_ptr().add(0x44cusize),
1061 )
1062 }
1063 }
1064 #[inline(always)]
1065 pub const fn ielsr84(
1066 &self,
1067 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1068 unsafe {
1069 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1070 self._svd2pac_as_ptr().add(0x450usize),
1071 )
1072 }
1073 }
1074 #[inline(always)]
1075 pub const fn ielsr85(
1076 &self,
1077 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1078 unsafe {
1079 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1080 self._svd2pac_as_ptr().add(0x454usize),
1081 )
1082 }
1083 }
1084 #[inline(always)]
1085 pub const fn ielsr86(
1086 &self,
1087 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1088 unsafe {
1089 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1090 self._svd2pac_as_ptr().add(0x458usize),
1091 )
1092 }
1093 }
1094 #[inline(always)]
1095 pub const fn ielsr87(
1096 &self,
1097 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1098 unsafe {
1099 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1100 self._svd2pac_as_ptr().add(0x45cusize),
1101 )
1102 }
1103 }
1104 #[inline(always)]
1105 pub const fn ielsr88(
1106 &self,
1107 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1108 unsafe {
1109 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1110 self._svd2pac_as_ptr().add(0x460usize),
1111 )
1112 }
1113 }
1114 #[inline(always)]
1115 pub const fn ielsr89(
1116 &self,
1117 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1118 unsafe {
1119 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1120 self._svd2pac_as_ptr().add(0x464usize),
1121 )
1122 }
1123 }
1124 #[inline(always)]
1125 pub const fn ielsr90(
1126 &self,
1127 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1128 unsafe {
1129 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1130 self._svd2pac_as_ptr().add(0x468usize),
1131 )
1132 }
1133 }
1134 #[inline(always)]
1135 pub const fn ielsr91(
1136 &self,
1137 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1138 unsafe {
1139 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1140 self._svd2pac_as_ptr().add(0x46cusize),
1141 )
1142 }
1143 }
1144 #[inline(always)]
1145 pub const fn ielsr92(
1146 &self,
1147 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1148 unsafe {
1149 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1150 self._svd2pac_as_ptr().add(0x470usize),
1151 )
1152 }
1153 }
1154 #[inline(always)]
1155 pub const fn ielsr93(
1156 &self,
1157 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1158 unsafe {
1159 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1160 self._svd2pac_as_ptr().add(0x474usize),
1161 )
1162 }
1163 }
1164 #[inline(always)]
1165 pub const fn ielsr94(
1166 &self,
1167 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1168 unsafe {
1169 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1170 self._svd2pac_as_ptr().add(0x478usize),
1171 )
1172 }
1173 }
1174 #[inline(always)]
1175 pub const fn ielsr95(
1176 &self,
1177 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1178 unsafe {
1179 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1180 self._svd2pac_as_ptr().add(0x47cusize),
1181 )
1182 }
1183 }
1184
1185 #[doc = "DMAC Event Link Setting Register %s"]
1186 #[inline(always)]
1187 pub const fn delsr(
1188 &self,
1189 ) -> &'static crate::common::ClusterRegisterArray<
1190 crate::common::Reg<self::Delsr_SPEC, crate::common::RW>,
1191 8,
1192 0x4,
1193 > {
1194 unsafe {
1195 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x280usize))
1196 }
1197 }
1198 #[inline(always)]
1199 pub const fn delsr0(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
1200 unsafe {
1201 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
1202 self._svd2pac_as_ptr().add(0x280usize),
1203 )
1204 }
1205 }
1206 #[inline(always)]
1207 pub const fn delsr1(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
1208 unsafe {
1209 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
1210 self._svd2pac_as_ptr().add(0x284usize),
1211 )
1212 }
1213 }
1214 #[inline(always)]
1215 pub const fn delsr2(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
1216 unsafe {
1217 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
1218 self._svd2pac_as_ptr().add(0x288usize),
1219 )
1220 }
1221 }
1222 #[inline(always)]
1223 pub const fn delsr3(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
1224 unsafe {
1225 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
1226 self._svd2pac_as_ptr().add(0x28cusize),
1227 )
1228 }
1229 }
1230 #[inline(always)]
1231 pub const fn delsr4(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
1232 unsafe {
1233 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
1234 self._svd2pac_as_ptr().add(0x290usize),
1235 )
1236 }
1237 }
1238 #[inline(always)]
1239 pub const fn delsr5(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
1240 unsafe {
1241 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
1242 self._svd2pac_as_ptr().add(0x294usize),
1243 )
1244 }
1245 }
1246 #[inline(always)]
1247 pub const fn delsr6(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
1248 unsafe {
1249 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
1250 self._svd2pac_as_ptr().add(0x298usize),
1251 )
1252 }
1253 }
1254 #[inline(always)]
1255 pub const fn delsr7(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
1256 unsafe {
1257 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
1258 self._svd2pac_as_ptr().add(0x29cusize),
1259 )
1260 }
1261 }
1262
1263 #[doc = "SYS Event Link Setting Register"]
1264 #[inline(always)]
1265 pub const fn selsr0(
1266 &self,
1267 ) -> &'static crate::common::Reg<self::Selsr0_SPEC, crate::common::RW> {
1268 unsafe {
1269 crate::common::Reg::<self::Selsr0_SPEC, crate::common::RW>::from_ptr(
1270 self._svd2pac_as_ptr().add(512usize),
1271 )
1272 }
1273 }
1274
1275 #[doc = "Wake Up interrupt enable register"]
1276 #[inline(always)]
1277 pub const fn wupen(&self) -> &'static crate::common::Reg<self::Wupen_SPEC, crate::common::RW> {
1278 unsafe {
1279 crate::common::Reg::<self::Wupen_SPEC, crate::common::RW>::from_ptr(
1280 self._svd2pac_as_ptr().add(416usize),
1281 )
1282 }
1283 }
1284}
1285#[doc(hidden)]
1286#[derive(Copy, Clone, Eq, PartialEq)]
1287pub struct Irqcr_SPEC;
1288impl crate::sealed::RegSpec for Irqcr_SPEC {
1289 type DataType = u8;
1290}
1291
1292#[doc = "IRQ Control Register %s"]
1293pub type Irqcr = crate::RegValueT<Irqcr_SPEC>;
1294
1295impl Irqcr {
1296 #[doc = "IRQ Digital Filter Enable"]
1297 #[inline(always)]
1298 pub fn flten(
1299 self,
1300 ) -> crate::common::RegisterField<
1301 7,
1302 0x1,
1303 1,
1304 0,
1305 irqcr::Flten,
1306 irqcr::Flten,
1307 Irqcr_SPEC,
1308 crate::common::RW,
1309 > {
1310 crate::common::RegisterField::<
1311 7,
1312 0x1,
1313 1,
1314 0,
1315 irqcr::Flten,
1316 irqcr::Flten,
1317 Irqcr_SPEC,
1318 crate::common::RW,
1319 >::from_register(self, 0)
1320 }
1321
1322 #[doc = "IRQ Digital Filter Sampling Clock"]
1323 #[inline(always)]
1324 pub fn fclksel(
1325 self,
1326 ) -> crate::common::RegisterField<
1327 4,
1328 0x3,
1329 1,
1330 0,
1331 irqcr::Fclksel,
1332 irqcr::Fclksel,
1333 Irqcr_SPEC,
1334 crate::common::RW,
1335 > {
1336 crate::common::RegisterField::<
1337 4,
1338 0x3,
1339 1,
1340 0,
1341 irqcr::Fclksel,
1342 irqcr::Fclksel,
1343 Irqcr_SPEC,
1344 crate::common::RW,
1345 >::from_register(self, 0)
1346 }
1347
1348 #[doc = "IRQ Detection Sense Select"]
1349 #[inline(always)]
1350 pub fn irqmd(
1351 self,
1352 ) -> crate::common::RegisterField<
1353 0,
1354 0x3,
1355 1,
1356 0,
1357 irqcr::Irqmd,
1358 irqcr::Irqmd,
1359 Irqcr_SPEC,
1360 crate::common::RW,
1361 > {
1362 crate::common::RegisterField::<
1363 0,
1364 0x3,
1365 1,
1366 0,
1367 irqcr::Irqmd,
1368 irqcr::Irqmd,
1369 Irqcr_SPEC,
1370 crate::common::RW,
1371 >::from_register(self, 0)
1372 }
1373}
1374impl ::core::default::Default for Irqcr {
1375 #[inline(always)]
1376 fn default() -> Irqcr {
1377 <crate::RegValueT<Irqcr_SPEC> as RegisterValue<_>>::new(0)
1378 }
1379}
1380pub mod irqcr {
1381
1382 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1383 pub struct Flten_SPEC;
1384 pub type Flten = crate::EnumBitfieldStruct<u8, Flten_SPEC>;
1385 impl Flten {
1386 #[doc = "Digital filter is disabled."]
1387 pub const _0: Self = Self::new(0);
1388
1389 #[doc = "Digital filter is enabled."]
1390 pub const _1: Self = Self::new(1);
1391 }
1392 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1393 pub struct Fclksel_SPEC;
1394 pub type Fclksel = crate::EnumBitfieldStruct<u8, Fclksel_SPEC>;
1395 impl Fclksel {
1396 #[doc = "PCLKB"]
1397 pub const _00: Self = Self::new(0);
1398
1399 #[doc = "PCLKB/8"]
1400 pub const _01: Self = Self::new(1);
1401
1402 #[doc = "PCLKB/32"]
1403 pub const _10: Self = Self::new(2);
1404
1405 #[doc = "PCLKB/64"]
1406 pub const _11: Self = Self::new(3);
1407 }
1408 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1409 pub struct Irqmd_SPEC;
1410 pub type Irqmd = crate::EnumBitfieldStruct<u8, Irqmd_SPEC>;
1411 impl Irqmd {
1412 #[doc = "Falling edge"]
1413 pub const _00: Self = Self::new(0);
1414
1415 #[doc = "Rising edge"]
1416 pub const _01: Self = Self::new(1);
1417
1418 #[doc = "Rising and falling edges"]
1419 pub const _10: Self = Self::new(2);
1420
1421 #[doc = "Low level"]
1422 pub const _11: Self = Self::new(3);
1423 }
1424}
1425#[doc(hidden)]
1426#[derive(Copy, Clone, Eq, PartialEq)]
1427pub struct Nmisr_SPEC;
1428impl crate::sealed::RegSpec for Nmisr_SPEC {
1429 type DataType = u16;
1430}
1431
1432#[doc = "Non-Maskable Interrupt Status Register"]
1433pub type Nmisr = crate::RegValueT<Nmisr_SPEC>;
1434
1435impl Nmisr {
1436 #[doc = "MPU Stack Error Interrupt Status Flag"]
1437 #[inline(always)]
1438 pub fn spest(
1439 self,
1440 ) -> crate::common::RegisterField<
1441 12,
1442 0x1,
1443 1,
1444 0,
1445 nmisr::Spest,
1446 nmisr::Spest,
1447 Nmisr_SPEC,
1448 crate::common::R,
1449 > {
1450 crate::common::RegisterField::<
1451 12,
1452 0x1,
1453 1,
1454 0,
1455 nmisr::Spest,
1456 nmisr::Spest,
1457 Nmisr_SPEC,
1458 crate::common::R,
1459 >::from_register(self, 0)
1460 }
1461
1462 #[doc = "MPU Bus Master Error Interrupt Status Flag"]
1463 #[inline(always)]
1464 pub fn busmst(
1465 self,
1466 ) -> crate::common::RegisterField<
1467 11,
1468 0x1,
1469 1,
1470 0,
1471 nmisr::Busmst,
1472 nmisr::Busmst,
1473 Nmisr_SPEC,
1474 crate::common::R,
1475 > {
1476 crate::common::RegisterField::<
1477 11,
1478 0x1,
1479 1,
1480 0,
1481 nmisr::Busmst,
1482 nmisr::Busmst,
1483 Nmisr_SPEC,
1484 crate::common::R,
1485 >::from_register(self, 0)
1486 }
1487
1488 #[doc = "MPU Bus Slave Error Interrupt Status Flag"]
1489 #[inline(always)]
1490 pub fn bussst(
1491 self,
1492 ) -> crate::common::RegisterField<
1493 10,
1494 0x1,
1495 1,
1496 0,
1497 nmisr::Bussst,
1498 nmisr::Bussst,
1499 Nmisr_SPEC,
1500 crate::common::R,
1501 > {
1502 crate::common::RegisterField::<
1503 10,
1504 0x1,
1505 1,
1506 0,
1507 nmisr::Bussst,
1508 nmisr::Bussst,
1509 Nmisr_SPEC,
1510 crate::common::R,
1511 >::from_register(self, 0)
1512 }
1513
1514 #[doc = "RAM ECC Error Interrupt Status Flag"]
1515 #[inline(always)]
1516 pub fn reccst(
1517 self,
1518 ) -> crate::common::RegisterField<
1519 9,
1520 0x1,
1521 1,
1522 0,
1523 nmisr::Reccst,
1524 nmisr::Reccst,
1525 Nmisr_SPEC,
1526 crate::common::R,
1527 > {
1528 crate::common::RegisterField::<
1529 9,
1530 0x1,
1531 1,
1532 0,
1533 nmisr::Reccst,
1534 nmisr::Reccst,
1535 Nmisr_SPEC,
1536 crate::common::R,
1537 >::from_register(self, 0)
1538 }
1539
1540 #[doc = "RAM Parity Error Interrupt Status Flag"]
1541 #[inline(always)]
1542 pub fn rpest(
1543 self,
1544 ) -> crate::common::RegisterField<
1545 8,
1546 0x1,
1547 1,
1548 0,
1549 nmisr::Rpest,
1550 nmisr::Rpest,
1551 Nmisr_SPEC,
1552 crate::common::R,
1553 > {
1554 crate::common::RegisterField::<
1555 8,
1556 0x1,
1557 1,
1558 0,
1559 nmisr::Rpest,
1560 nmisr::Rpest,
1561 Nmisr_SPEC,
1562 crate::common::R,
1563 >::from_register(self, 0)
1564 }
1565
1566 #[doc = "NMI Status Flag"]
1567 #[inline(always)]
1568 pub fn nmist(
1569 self,
1570 ) -> crate::common::RegisterField<
1571 7,
1572 0x1,
1573 1,
1574 0,
1575 nmisr::Nmist,
1576 nmisr::Nmist,
1577 Nmisr_SPEC,
1578 crate::common::R,
1579 > {
1580 crate::common::RegisterField::<
1581 7,
1582 0x1,
1583 1,
1584 0,
1585 nmisr::Nmist,
1586 nmisr::Nmist,
1587 Nmisr_SPEC,
1588 crate::common::R,
1589 >::from_register(self, 0)
1590 }
1591
1592 #[doc = "Oscillation Stop Detection Interrupt Status Flag"]
1593 #[inline(always)]
1594 pub fn ostst(
1595 self,
1596 ) -> crate::common::RegisterField<
1597 6,
1598 0x1,
1599 1,
1600 0,
1601 nmisr::Ostst,
1602 nmisr::Ostst,
1603 Nmisr_SPEC,
1604 crate::common::R,
1605 > {
1606 crate::common::RegisterField::<
1607 6,
1608 0x1,
1609 1,
1610 0,
1611 nmisr::Ostst,
1612 nmisr::Ostst,
1613 Nmisr_SPEC,
1614 crate::common::R,
1615 >::from_register(self, 0)
1616 }
1617
1618 #[doc = "Voltage-Monitoring 2 Interrupt Status Flag"]
1619 #[inline(always)]
1620 pub fn lvd2st(
1621 self,
1622 ) -> crate::common::RegisterField<
1623 3,
1624 0x1,
1625 1,
1626 0,
1627 nmisr::Lvd2St,
1628 nmisr::Lvd2St,
1629 Nmisr_SPEC,
1630 crate::common::R,
1631 > {
1632 crate::common::RegisterField::<
1633 3,
1634 0x1,
1635 1,
1636 0,
1637 nmisr::Lvd2St,
1638 nmisr::Lvd2St,
1639 Nmisr_SPEC,
1640 crate::common::R,
1641 >::from_register(self, 0)
1642 }
1643
1644 #[doc = "Voltage-Monitoring 1 Interrupt Status Flag"]
1645 #[inline(always)]
1646 pub fn lvd1st(
1647 self,
1648 ) -> crate::common::RegisterField<
1649 2,
1650 0x1,
1651 1,
1652 0,
1653 nmisr::Lvd1St,
1654 nmisr::Lvd1St,
1655 Nmisr_SPEC,
1656 crate::common::R,
1657 > {
1658 crate::common::RegisterField::<
1659 2,
1660 0x1,
1661 1,
1662 0,
1663 nmisr::Lvd1St,
1664 nmisr::Lvd1St,
1665 Nmisr_SPEC,
1666 crate::common::R,
1667 >::from_register(self, 0)
1668 }
1669
1670 #[doc = "WDT Underflow/Refresh Error Status Flag"]
1671 #[inline(always)]
1672 pub fn wdtst(
1673 self,
1674 ) -> crate::common::RegisterField<
1675 1,
1676 0x1,
1677 1,
1678 0,
1679 nmisr::Wdtst,
1680 nmisr::Wdtst,
1681 Nmisr_SPEC,
1682 crate::common::R,
1683 > {
1684 crate::common::RegisterField::<
1685 1,
1686 0x1,
1687 1,
1688 0,
1689 nmisr::Wdtst,
1690 nmisr::Wdtst,
1691 Nmisr_SPEC,
1692 crate::common::R,
1693 >::from_register(self, 0)
1694 }
1695
1696 #[doc = "IWDT Underflow/Refresh Error Status Flag"]
1697 #[inline(always)]
1698 pub fn iwdtst(
1699 self,
1700 ) -> crate::common::RegisterField<
1701 0,
1702 0x1,
1703 1,
1704 0,
1705 nmisr::Iwdtst,
1706 nmisr::Iwdtst,
1707 Nmisr_SPEC,
1708 crate::common::R,
1709 > {
1710 crate::common::RegisterField::<
1711 0,
1712 0x1,
1713 1,
1714 0,
1715 nmisr::Iwdtst,
1716 nmisr::Iwdtst,
1717 Nmisr_SPEC,
1718 crate::common::R,
1719 >::from_register(self, 0)
1720 }
1721}
1722impl ::core::default::Default for Nmisr {
1723 #[inline(always)]
1724 fn default() -> Nmisr {
1725 <crate::RegValueT<Nmisr_SPEC> as RegisterValue<_>>::new(0)
1726 }
1727}
1728pub mod nmisr {
1729
1730 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1731 pub struct Spest_SPEC;
1732 pub type Spest = crate::EnumBitfieldStruct<u8, Spest_SPEC>;
1733 impl Spest {
1734 #[doc = "MPU Stack Error interrupt is not requested."]
1735 pub const _0: Self = Self::new(0);
1736
1737 #[doc = "MPU Stack Error interrupt is requested."]
1738 pub const _1: Self = Self::new(1);
1739 }
1740 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1741 pub struct Busmst_SPEC;
1742 pub type Busmst = crate::EnumBitfieldStruct<u8, Busmst_SPEC>;
1743 impl Busmst {
1744 #[doc = "MPU Bus Master Error interrupt is not requested."]
1745 pub const _0: Self = Self::new(0);
1746
1747 #[doc = "MPU Bus Master Error interrupt is requested."]
1748 pub const _1: Self = Self::new(1);
1749 }
1750 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1751 pub struct Bussst_SPEC;
1752 pub type Bussst = crate::EnumBitfieldStruct<u8, Bussst_SPEC>;
1753 impl Bussst {
1754 #[doc = "MPU Bus Slave Error interrupt is not requested."]
1755 pub const _0: Self = Self::new(0);
1756
1757 #[doc = "MPU Bus Slave Error interrupt is requested."]
1758 pub const _1: Self = Self::new(1);
1759 }
1760 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1761 pub struct Reccst_SPEC;
1762 pub type Reccst = crate::EnumBitfieldStruct<u8, Reccst_SPEC>;
1763 impl Reccst {
1764 #[doc = "RAM ECC Error interrupt is not requested."]
1765 pub const _0: Self = Self::new(0);
1766
1767 #[doc = "RAM ECC Error interrupt is requested."]
1768 pub const _1: Self = Self::new(1);
1769 }
1770 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1771 pub struct Rpest_SPEC;
1772 pub type Rpest = crate::EnumBitfieldStruct<u8, Rpest_SPEC>;
1773 impl Rpest {
1774 #[doc = "RAM Parity Error interrupt is not requested."]
1775 pub const _0: Self = Self::new(0);
1776
1777 #[doc = "RAM Parity Error interrupt is requested."]
1778 pub const _1: Self = Self::new(1);
1779 }
1780 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1781 pub struct Nmist_SPEC;
1782 pub type Nmist = crate::EnumBitfieldStruct<u8, Nmist_SPEC>;
1783 impl Nmist {
1784 #[doc = "NMI pin interrupt is not requested."]
1785 pub const _0: Self = Self::new(0);
1786
1787 #[doc = "NMI pin interrupt is requested."]
1788 pub const _1: Self = Self::new(1);
1789 }
1790 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1791 pub struct Ostst_SPEC;
1792 pub type Ostst = crate::EnumBitfieldStruct<u8, Ostst_SPEC>;
1793 impl Ostst {
1794 #[doc = "Oscillation stop detection interrupt is not requested."]
1795 pub const _0: Self = Self::new(0);
1796
1797 #[doc = "Oscillation stop detection interrupt is requested."]
1798 pub const _1: Self = Self::new(1);
1799 }
1800 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1801 pub struct Lvd2St_SPEC;
1802 pub type Lvd2St = crate::EnumBitfieldStruct<u8, Lvd2St_SPEC>;
1803 impl Lvd2St {
1804 #[doc = "Voltage-monitoring 2 interrupt is not requested."]
1805 pub const _0: Self = Self::new(0);
1806
1807 #[doc = "Voltage-monitoring 2 interrupt is requested."]
1808 pub const _1: Self = Self::new(1);
1809 }
1810 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1811 pub struct Lvd1St_SPEC;
1812 pub type Lvd1St = crate::EnumBitfieldStruct<u8, Lvd1St_SPEC>;
1813 impl Lvd1St {
1814 #[doc = "Voltage-monitoring 1 interrupt is not requested."]
1815 pub const _0: Self = Self::new(0);
1816
1817 #[doc = "Voltage-monitoring 1 interrupt is requested."]
1818 pub const _1: Self = Self::new(1);
1819 }
1820 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1821 pub struct Wdtst_SPEC;
1822 pub type Wdtst = crate::EnumBitfieldStruct<u8, Wdtst_SPEC>;
1823 impl Wdtst {
1824 #[doc = "WDT underflow/refresh error interrupt is not requested."]
1825 pub const _0: Self = Self::new(0);
1826
1827 #[doc = "WDT underflow/refresh error interrupt is requested."]
1828 pub const _1: Self = Self::new(1);
1829 }
1830 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1831 pub struct Iwdtst_SPEC;
1832 pub type Iwdtst = crate::EnumBitfieldStruct<u8, Iwdtst_SPEC>;
1833 impl Iwdtst {
1834 #[doc = "IWDT underflow/refresh error interrupt is not requested."]
1835 pub const _0: Self = Self::new(0);
1836
1837 #[doc = "IWDT underflow/refresh error interrupt is requested."]
1838 pub const _1: Self = Self::new(1);
1839 }
1840}
1841#[doc(hidden)]
1842#[derive(Copy, Clone, Eq, PartialEq)]
1843pub struct Nmier_SPEC;
1844impl crate::sealed::RegSpec for Nmier_SPEC {
1845 type DataType = u16;
1846}
1847
1848#[doc = "Non-Maskable Interrupt Enable Register"]
1849pub type Nmier = crate::RegValueT<Nmier_SPEC>;
1850
1851impl Nmier {
1852 #[doc = "MPU Stack Error Interrupt Enable"]
1853 #[inline(always)]
1854 pub fn speen(
1855 self,
1856 ) -> crate::common::RegisterField<
1857 12,
1858 0x1,
1859 1,
1860 0,
1861 nmier::Speen,
1862 nmier::Speen,
1863 Nmier_SPEC,
1864 crate::common::RW,
1865 > {
1866 crate::common::RegisterField::<
1867 12,
1868 0x1,
1869 1,
1870 0,
1871 nmier::Speen,
1872 nmier::Speen,
1873 Nmier_SPEC,
1874 crate::common::RW,
1875 >::from_register(self, 0)
1876 }
1877
1878 #[doc = "MPU Bus Master Error Interrupt Enable"]
1879 #[inline(always)]
1880 pub fn busmen(
1881 self,
1882 ) -> crate::common::RegisterField<
1883 11,
1884 0x1,
1885 1,
1886 0,
1887 nmier::Busmen,
1888 nmier::Busmen,
1889 Nmier_SPEC,
1890 crate::common::RW,
1891 > {
1892 crate::common::RegisterField::<
1893 11,
1894 0x1,
1895 1,
1896 0,
1897 nmier::Busmen,
1898 nmier::Busmen,
1899 Nmier_SPEC,
1900 crate::common::RW,
1901 >::from_register(self, 0)
1902 }
1903
1904 #[doc = "MPU Bus Slave Error Interrupt Enable"]
1905 #[inline(always)]
1906 pub fn bussen(
1907 self,
1908 ) -> crate::common::RegisterField<
1909 10,
1910 0x1,
1911 1,
1912 0,
1913 nmier::Bussen,
1914 nmier::Bussen,
1915 Nmier_SPEC,
1916 crate::common::RW,
1917 > {
1918 crate::common::RegisterField::<
1919 10,
1920 0x1,
1921 1,
1922 0,
1923 nmier::Bussen,
1924 nmier::Bussen,
1925 Nmier_SPEC,
1926 crate::common::RW,
1927 >::from_register(self, 0)
1928 }
1929
1930 #[doc = "RAM ECC Error Interrupt Enable"]
1931 #[inline(always)]
1932 pub fn reccen(
1933 self,
1934 ) -> crate::common::RegisterField<
1935 9,
1936 0x1,
1937 1,
1938 0,
1939 nmier::Reccen,
1940 nmier::Reccen,
1941 Nmier_SPEC,
1942 crate::common::RW,
1943 > {
1944 crate::common::RegisterField::<
1945 9,
1946 0x1,
1947 1,
1948 0,
1949 nmier::Reccen,
1950 nmier::Reccen,
1951 Nmier_SPEC,
1952 crate::common::RW,
1953 >::from_register(self, 0)
1954 }
1955
1956 #[doc = "RAM Parity Error Interrupt Enable"]
1957 #[inline(always)]
1958 pub fn rpeen(
1959 self,
1960 ) -> crate::common::RegisterField<
1961 8,
1962 0x1,
1963 1,
1964 0,
1965 nmier::Rpeen,
1966 nmier::Rpeen,
1967 Nmier_SPEC,
1968 crate::common::RW,
1969 > {
1970 crate::common::RegisterField::<
1971 8,
1972 0x1,
1973 1,
1974 0,
1975 nmier::Rpeen,
1976 nmier::Rpeen,
1977 Nmier_SPEC,
1978 crate::common::RW,
1979 >::from_register(self, 0)
1980 }
1981
1982 #[doc = "NMI Pin Interrupt Enable"]
1983 #[inline(always)]
1984 pub fn nmien(
1985 self,
1986 ) -> crate::common::RegisterField<
1987 7,
1988 0x1,
1989 1,
1990 0,
1991 nmier::Nmien,
1992 nmier::Nmien,
1993 Nmier_SPEC,
1994 crate::common::RW,
1995 > {
1996 crate::common::RegisterField::<
1997 7,
1998 0x1,
1999 1,
2000 0,
2001 nmier::Nmien,
2002 nmier::Nmien,
2003 Nmier_SPEC,
2004 crate::common::RW,
2005 >::from_register(self, 0)
2006 }
2007
2008 #[doc = "Oscillation Stop Detection Interrupt Enable"]
2009 #[inline(always)]
2010 pub fn osten(
2011 self,
2012 ) -> crate::common::RegisterField<
2013 6,
2014 0x1,
2015 1,
2016 0,
2017 nmier::Osten,
2018 nmier::Osten,
2019 Nmier_SPEC,
2020 crate::common::RW,
2021 > {
2022 crate::common::RegisterField::<
2023 6,
2024 0x1,
2025 1,
2026 0,
2027 nmier::Osten,
2028 nmier::Osten,
2029 Nmier_SPEC,
2030 crate::common::RW,
2031 >::from_register(self, 0)
2032 }
2033
2034 #[doc = "Voltage-Monitoring 2 Interrupt Enable"]
2035 #[inline(always)]
2036 pub fn lvd2en(
2037 self,
2038 ) -> crate::common::RegisterField<
2039 3,
2040 0x1,
2041 1,
2042 0,
2043 nmier::Lvd2En,
2044 nmier::Lvd2En,
2045 Nmier_SPEC,
2046 crate::common::RW,
2047 > {
2048 crate::common::RegisterField::<
2049 3,
2050 0x1,
2051 1,
2052 0,
2053 nmier::Lvd2En,
2054 nmier::Lvd2En,
2055 Nmier_SPEC,
2056 crate::common::RW,
2057 >::from_register(self, 0)
2058 }
2059
2060 #[doc = "Voltage-Monitoring 1 Interrupt Enable"]
2061 #[inline(always)]
2062 pub fn lvd1en(
2063 self,
2064 ) -> crate::common::RegisterField<
2065 2,
2066 0x1,
2067 1,
2068 0,
2069 nmier::Lvd1En,
2070 nmier::Lvd1En,
2071 Nmier_SPEC,
2072 crate::common::RW,
2073 > {
2074 crate::common::RegisterField::<
2075 2,
2076 0x1,
2077 1,
2078 0,
2079 nmier::Lvd1En,
2080 nmier::Lvd1En,
2081 Nmier_SPEC,
2082 crate::common::RW,
2083 >::from_register(self, 0)
2084 }
2085
2086 #[doc = "WDT Underflow/Refresh Error Interrupt Enable"]
2087 #[inline(always)]
2088 pub fn wdten(
2089 self,
2090 ) -> crate::common::RegisterField<
2091 1,
2092 0x1,
2093 1,
2094 0,
2095 nmier::Wdten,
2096 nmier::Wdten,
2097 Nmier_SPEC,
2098 crate::common::RW,
2099 > {
2100 crate::common::RegisterField::<
2101 1,
2102 0x1,
2103 1,
2104 0,
2105 nmier::Wdten,
2106 nmier::Wdten,
2107 Nmier_SPEC,
2108 crate::common::RW,
2109 >::from_register(self, 0)
2110 }
2111
2112 #[doc = "IWDT Underflow/Refresh Error Interrupt Enable"]
2113 #[inline(always)]
2114 pub fn iwdten(
2115 self,
2116 ) -> crate::common::RegisterField<
2117 0,
2118 0x1,
2119 1,
2120 0,
2121 nmier::Iwdten,
2122 nmier::Iwdten,
2123 Nmier_SPEC,
2124 crate::common::RW,
2125 > {
2126 crate::common::RegisterField::<
2127 0,
2128 0x1,
2129 1,
2130 0,
2131 nmier::Iwdten,
2132 nmier::Iwdten,
2133 Nmier_SPEC,
2134 crate::common::RW,
2135 >::from_register(self, 0)
2136 }
2137}
2138impl ::core::default::Default for Nmier {
2139 #[inline(always)]
2140 fn default() -> Nmier {
2141 <crate::RegValueT<Nmier_SPEC> as RegisterValue<_>>::new(0)
2142 }
2143}
2144pub mod nmier {
2145
2146 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2147 pub struct Speen_SPEC;
2148 pub type Speen = crate::EnumBitfieldStruct<u8, Speen_SPEC>;
2149 impl Speen {
2150 #[doc = "MPU Stack Error interrupt is disabled."]
2151 pub const _0: Self = Self::new(0);
2152
2153 #[doc = "MPU Stack Error interrupt is enabled."]
2154 pub const _1: Self = Self::new(1);
2155 }
2156 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2157 pub struct Busmen_SPEC;
2158 pub type Busmen = crate::EnumBitfieldStruct<u8, Busmen_SPEC>;
2159 impl Busmen {
2160 #[doc = "MPU Bus Master Error interrupt is disabled."]
2161 pub const _0: Self = Self::new(0);
2162
2163 #[doc = "MPU Bus Master Error interrupt is enabled."]
2164 pub const _1: Self = Self::new(1);
2165 }
2166 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2167 pub struct Bussen_SPEC;
2168 pub type Bussen = crate::EnumBitfieldStruct<u8, Bussen_SPEC>;
2169 impl Bussen {
2170 #[doc = "MPU Bus Slave Error interrupt is disabled."]
2171 pub const _0: Self = Self::new(0);
2172
2173 #[doc = "MPU Bus Slave Error interrupt is enabled."]
2174 pub const _1: Self = Self::new(1);
2175 }
2176 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2177 pub struct Reccen_SPEC;
2178 pub type Reccen = crate::EnumBitfieldStruct<u8, Reccen_SPEC>;
2179 impl Reccen {
2180 #[doc = "RAM ECC Error interrupt is disabled."]
2181 pub const _0: Self = Self::new(0);
2182
2183 #[doc = "RAM ECC Error interrupt is enabled."]
2184 pub const _1: Self = Self::new(1);
2185 }
2186 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2187 pub struct Rpeen_SPEC;
2188 pub type Rpeen = crate::EnumBitfieldStruct<u8, Rpeen_SPEC>;
2189 impl Rpeen {
2190 #[doc = "RAM Parity Error interrupt is disabled."]
2191 pub const _0: Self = Self::new(0);
2192
2193 #[doc = "RAM Parity Error interrupt is enabled."]
2194 pub const _1: Self = Self::new(1);
2195 }
2196 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2197 pub struct Nmien_SPEC;
2198 pub type Nmien = crate::EnumBitfieldStruct<u8, Nmien_SPEC>;
2199 impl Nmien {
2200 #[doc = "NMI pin interrupt is disabled."]
2201 pub const _0: Self = Self::new(0);
2202
2203 #[doc = "NMI pin interrupt is enabled."]
2204 pub const _1: Self = Self::new(1);
2205 }
2206 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2207 pub struct Osten_SPEC;
2208 pub type Osten = crate::EnumBitfieldStruct<u8, Osten_SPEC>;
2209 impl Osten {
2210 #[doc = "Oscillation stop detection interrupt is disabled."]
2211 pub const _0: Self = Self::new(0);
2212
2213 #[doc = "Oscillation stop detection interrupt is enabled."]
2214 pub const _1: Self = Self::new(1);
2215 }
2216 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2217 pub struct Lvd2En_SPEC;
2218 pub type Lvd2En = crate::EnumBitfieldStruct<u8, Lvd2En_SPEC>;
2219 impl Lvd2En {
2220 #[doc = "Voltage-monitoring 2 interrupt is disabled."]
2221 pub const _0: Self = Self::new(0);
2222
2223 #[doc = "Voltage-monitoring 2 interrupt is enabled."]
2224 pub const _1: Self = Self::new(1);
2225 }
2226 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2227 pub struct Lvd1En_SPEC;
2228 pub type Lvd1En = crate::EnumBitfieldStruct<u8, Lvd1En_SPEC>;
2229 impl Lvd1En {
2230 #[doc = "Voltage-monitoring 1 interrupt is disabled."]
2231 pub const _0: Self = Self::new(0);
2232
2233 #[doc = "Voltage-monitoring 1 interrupt is enabled."]
2234 pub const _1: Self = Self::new(1);
2235 }
2236 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2237 pub struct Wdten_SPEC;
2238 pub type Wdten = crate::EnumBitfieldStruct<u8, Wdten_SPEC>;
2239 impl Wdten {
2240 #[doc = "WDT underflow/refresh error interrupt is disabled."]
2241 pub const _0: Self = Self::new(0);
2242
2243 #[doc = "WDT underflow/refresh error interrupt is enabled."]
2244 pub const _1: Self = Self::new(1);
2245 }
2246 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2247 pub struct Iwdten_SPEC;
2248 pub type Iwdten = crate::EnumBitfieldStruct<u8, Iwdten_SPEC>;
2249 impl Iwdten {
2250 #[doc = "IWDT underflow/refresh error interrupt is disabled."]
2251 pub const _0: Self = Self::new(0);
2252
2253 #[doc = "IWDT underflow/refresh error interrupt is enabled."]
2254 pub const _1: Self = Self::new(1);
2255 }
2256}
2257#[doc(hidden)]
2258#[derive(Copy, Clone, Eq, PartialEq)]
2259pub struct Nmiclr_SPEC;
2260impl crate::sealed::RegSpec for Nmiclr_SPEC {
2261 type DataType = u16;
2262}
2263
2264#[doc = "Non-Maskable Interrupt Status Clear Register"]
2265pub type Nmiclr = crate::RegValueT<Nmiclr_SPEC>;
2266
2267impl Nmiclr {
2268 #[doc = "SPEST Clear"]
2269 #[inline(always)]
2270 pub fn speclr(
2271 self,
2272 ) -> crate::common::RegisterField<
2273 12,
2274 0x1,
2275 1,
2276 0,
2277 nmiclr::Speclr,
2278 nmiclr::Speclr,
2279 Nmiclr_SPEC,
2280 crate::common::W,
2281 > {
2282 crate::common::RegisterField::<
2283 12,
2284 0x1,
2285 1,
2286 0,
2287 nmiclr::Speclr,
2288 nmiclr::Speclr,
2289 Nmiclr_SPEC,
2290 crate::common::W,
2291 >::from_register(self, 0)
2292 }
2293
2294 #[doc = "BUSMST Clear"]
2295 #[inline(always)]
2296 pub fn busmclr(
2297 self,
2298 ) -> crate::common::RegisterField<
2299 11,
2300 0x1,
2301 1,
2302 0,
2303 nmiclr::Busmclr,
2304 nmiclr::Busmclr,
2305 Nmiclr_SPEC,
2306 crate::common::W,
2307 > {
2308 crate::common::RegisterField::<
2309 11,
2310 0x1,
2311 1,
2312 0,
2313 nmiclr::Busmclr,
2314 nmiclr::Busmclr,
2315 Nmiclr_SPEC,
2316 crate::common::W,
2317 >::from_register(self, 0)
2318 }
2319
2320 #[doc = "BUSSST Clear"]
2321 #[inline(always)]
2322 pub fn bussclr(
2323 self,
2324 ) -> crate::common::RegisterField<
2325 10,
2326 0x1,
2327 1,
2328 0,
2329 nmiclr::Bussclr,
2330 nmiclr::Bussclr,
2331 Nmiclr_SPEC,
2332 crate::common::W,
2333 > {
2334 crate::common::RegisterField::<
2335 10,
2336 0x1,
2337 1,
2338 0,
2339 nmiclr::Bussclr,
2340 nmiclr::Bussclr,
2341 Nmiclr_SPEC,
2342 crate::common::W,
2343 >::from_register(self, 0)
2344 }
2345
2346 #[doc = "RECCST Clear"]
2347 #[inline(always)]
2348 pub fn reccclr(
2349 self,
2350 ) -> crate::common::RegisterField<
2351 9,
2352 0x1,
2353 1,
2354 0,
2355 nmiclr::Reccclr,
2356 nmiclr::Reccclr,
2357 Nmiclr_SPEC,
2358 crate::common::W,
2359 > {
2360 crate::common::RegisterField::<
2361 9,
2362 0x1,
2363 1,
2364 0,
2365 nmiclr::Reccclr,
2366 nmiclr::Reccclr,
2367 Nmiclr_SPEC,
2368 crate::common::W,
2369 >::from_register(self, 0)
2370 }
2371
2372 #[doc = "RPEST Clear"]
2373 #[inline(always)]
2374 pub fn rpeclr(
2375 self,
2376 ) -> crate::common::RegisterField<
2377 8,
2378 0x1,
2379 1,
2380 0,
2381 nmiclr::Rpeclr,
2382 nmiclr::Rpeclr,
2383 Nmiclr_SPEC,
2384 crate::common::W,
2385 > {
2386 crate::common::RegisterField::<
2387 8,
2388 0x1,
2389 1,
2390 0,
2391 nmiclr::Rpeclr,
2392 nmiclr::Rpeclr,
2393 Nmiclr_SPEC,
2394 crate::common::W,
2395 >::from_register(self, 0)
2396 }
2397
2398 #[doc = "NMIST Clear"]
2399 #[inline(always)]
2400 pub fn nmiclr(
2401 self,
2402 ) -> crate::common::RegisterField<
2403 7,
2404 0x1,
2405 1,
2406 0,
2407 nmiclr::Nmiclr,
2408 nmiclr::Nmiclr,
2409 Nmiclr_SPEC,
2410 crate::common::W,
2411 > {
2412 crate::common::RegisterField::<
2413 7,
2414 0x1,
2415 1,
2416 0,
2417 nmiclr::Nmiclr,
2418 nmiclr::Nmiclr,
2419 Nmiclr_SPEC,
2420 crate::common::W,
2421 >::from_register(self, 0)
2422 }
2423
2424 #[doc = "OSTST Clear"]
2425 #[inline(always)]
2426 pub fn ostclr(
2427 self,
2428 ) -> crate::common::RegisterField<
2429 6,
2430 0x1,
2431 1,
2432 0,
2433 nmiclr::Ostclr,
2434 nmiclr::Ostclr,
2435 Nmiclr_SPEC,
2436 crate::common::W,
2437 > {
2438 crate::common::RegisterField::<
2439 6,
2440 0x1,
2441 1,
2442 0,
2443 nmiclr::Ostclr,
2444 nmiclr::Ostclr,
2445 Nmiclr_SPEC,
2446 crate::common::W,
2447 >::from_register(self, 0)
2448 }
2449
2450 #[doc = "LVD2ST Clear"]
2451 #[inline(always)]
2452 pub fn lvd2clr(
2453 self,
2454 ) -> crate::common::RegisterField<
2455 3,
2456 0x1,
2457 1,
2458 0,
2459 nmiclr::Lvd2Clr,
2460 nmiclr::Lvd2Clr,
2461 Nmiclr_SPEC,
2462 crate::common::W,
2463 > {
2464 crate::common::RegisterField::<
2465 3,
2466 0x1,
2467 1,
2468 0,
2469 nmiclr::Lvd2Clr,
2470 nmiclr::Lvd2Clr,
2471 Nmiclr_SPEC,
2472 crate::common::W,
2473 >::from_register(self, 0)
2474 }
2475
2476 #[doc = "LVD1ST Clear"]
2477 #[inline(always)]
2478 pub fn lvd1clr(
2479 self,
2480 ) -> crate::common::RegisterField<
2481 2,
2482 0x1,
2483 1,
2484 0,
2485 nmiclr::Lvd1Clr,
2486 nmiclr::Lvd1Clr,
2487 Nmiclr_SPEC,
2488 crate::common::W,
2489 > {
2490 crate::common::RegisterField::<
2491 2,
2492 0x1,
2493 1,
2494 0,
2495 nmiclr::Lvd1Clr,
2496 nmiclr::Lvd1Clr,
2497 Nmiclr_SPEC,
2498 crate::common::W,
2499 >::from_register(self, 0)
2500 }
2501
2502 #[doc = "WDTST Clear"]
2503 #[inline(always)]
2504 pub fn wdtclr(
2505 self,
2506 ) -> crate::common::RegisterField<
2507 1,
2508 0x1,
2509 1,
2510 0,
2511 nmiclr::Wdtclr,
2512 nmiclr::Wdtclr,
2513 Nmiclr_SPEC,
2514 crate::common::W,
2515 > {
2516 crate::common::RegisterField::<
2517 1,
2518 0x1,
2519 1,
2520 0,
2521 nmiclr::Wdtclr,
2522 nmiclr::Wdtclr,
2523 Nmiclr_SPEC,
2524 crate::common::W,
2525 >::from_register(self, 0)
2526 }
2527
2528 #[doc = "IWDTST Clear"]
2529 #[inline(always)]
2530 pub fn iwdtclr(
2531 self,
2532 ) -> crate::common::RegisterField<
2533 0,
2534 0x1,
2535 1,
2536 0,
2537 nmiclr::Iwdtclr,
2538 nmiclr::Iwdtclr,
2539 Nmiclr_SPEC,
2540 crate::common::W,
2541 > {
2542 crate::common::RegisterField::<
2543 0,
2544 0x1,
2545 1,
2546 0,
2547 nmiclr::Iwdtclr,
2548 nmiclr::Iwdtclr,
2549 Nmiclr_SPEC,
2550 crate::common::W,
2551 >::from_register(self, 0)
2552 }
2553}
2554impl ::core::default::Default for Nmiclr {
2555 #[inline(always)]
2556 fn default() -> Nmiclr {
2557 <crate::RegValueT<Nmiclr_SPEC> as RegisterValue<_>>::new(0)
2558 }
2559}
2560pub mod nmiclr {
2561
2562 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2563 pub struct Speclr_SPEC;
2564 pub type Speclr = crate::EnumBitfieldStruct<u8, Speclr_SPEC>;
2565 impl Speclr {
2566 #[doc = "No effect."]
2567 pub const _0: Self = Self::new(0);
2568
2569 #[doc = "Clear the NMISR.SPEST flag."]
2570 pub const _1: Self = Self::new(1);
2571 }
2572 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2573 pub struct Busmclr_SPEC;
2574 pub type Busmclr = crate::EnumBitfieldStruct<u8, Busmclr_SPEC>;
2575 impl Busmclr {
2576 #[doc = "No effect."]
2577 pub const _0: Self = Self::new(0);
2578
2579 #[doc = "Clear the NMISR.BUSMST flag."]
2580 pub const _1: Self = Self::new(1);
2581 }
2582 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2583 pub struct Bussclr_SPEC;
2584 pub type Bussclr = crate::EnumBitfieldStruct<u8, Bussclr_SPEC>;
2585 impl Bussclr {
2586 #[doc = "No effect."]
2587 pub const _0: Self = Self::new(0);
2588
2589 #[doc = "Clear the NMISR.BUSSST flag."]
2590 pub const _1: Self = Self::new(1);
2591 }
2592 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2593 pub struct Reccclr_SPEC;
2594 pub type Reccclr = crate::EnumBitfieldStruct<u8, Reccclr_SPEC>;
2595 impl Reccclr {
2596 #[doc = "No effect."]
2597 pub const _0: Self = Self::new(0);
2598
2599 #[doc = "Clear the NMISR.RECCST flag."]
2600 pub const _1: Self = Self::new(1);
2601 }
2602 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2603 pub struct Rpeclr_SPEC;
2604 pub type Rpeclr = crate::EnumBitfieldStruct<u8, Rpeclr_SPEC>;
2605 impl Rpeclr {
2606 #[doc = "No effect."]
2607 pub const _0: Self = Self::new(0);
2608
2609 #[doc = "Clear the NMISR.RPEST flag."]
2610 pub const _1: Self = Self::new(1);
2611 }
2612 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2613 pub struct Nmiclr_SPEC;
2614 pub type Nmiclr = crate::EnumBitfieldStruct<u8, Nmiclr_SPEC>;
2615 impl Nmiclr {
2616 #[doc = "No effect."]
2617 pub const _0: Self = Self::new(0);
2618
2619 #[doc = "Clear the NMISR.NMIST flag."]
2620 pub const _1: Self = Self::new(1);
2621 }
2622 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2623 pub struct Ostclr_SPEC;
2624 pub type Ostclr = crate::EnumBitfieldStruct<u8, Ostclr_SPEC>;
2625 impl Ostclr {
2626 #[doc = "No effect."]
2627 pub const _0: Self = Self::new(0);
2628
2629 #[doc = "Clear the NMISR.OSTST flag."]
2630 pub const _1: Self = Self::new(1);
2631 }
2632 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2633 pub struct Lvd2Clr_SPEC;
2634 pub type Lvd2Clr = crate::EnumBitfieldStruct<u8, Lvd2Clr_SPEC>;
2635 impl Lvd2Clr {
2636 #[doc = "No effect."]
2637 pub const _0: Self = Self::new(0);
2638
2639 #[doc = "Clear the NMISR.LVD2ST flag."]
2640 pub const _1: Self = Self::new(1);
2641 }
2642 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2643 pub struct Lvd1Clr_SPEC;
2644 pub type Lvd1Clr = crate::EnumBitfieldStruct<u8, Lvd1Clr_SPEC>;
2645 impl Lvd1Clr {
2646 #[doc = "No effect."]
2647 pub const _0: Self = Self::new(0);
2648
2649 #[doc = "Clear the NMISR.LVD1ST flag."]
2650 pub const _1: Self = Self::new(1);
2651 }
2652 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2653 pub struct Wdtclr_SPEC;
2654 pub type Wdtclr = crate::EnumBitfieldStruct<u8, Wdtclr_SPEC>;
2655 impl Wdtclr {
2656 #[doc = "No effect."]
2657 pub const _0: Self = Self::new(0);
2658
2659 #[doc = "Clear the NMISR.WDTST flag."]
2660 pub const _1: Self = Self::new(1);
2661 }
2662 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2663 pub struct Iwdtclr_SPEC;
2664 pub type Iwdtclr = crate::EnumBitfieldStruct<u8, Iwdtclr_SPEC>;
2665 impl Iwdtclr {
2666 #[doc = "No effect."]
2667 pub const _0: Self = Self::new(0);
2668
2669 #[doc = "Clear the NMISR.IWDTST flag."]
2670 pub const _1: Self = Self::new(1);
2671 }
2672}
2673#[doc(hidden)]
2674#[derive(Copy, Clone, Eq, PartialEq)]
2675pub struct Nmicr_SPEC;
2676impl crate::sealed::RegSpec for Nmicr_SPEC {
2677 type DataType = u8;
2678}
2679
2680#[doc = "NMI Pin Interrupt Control Register"]
2681pub type Nmicr = crate::RegValueT<Nmicr_SPEC>;
2682
2683impl Nmicr {
2684 #[doc = "NMI Digital Filter Enable"]
2685 #[inline(always)]
2686 pub fn nflten(
2687 self,
2688 ) -> crate::common::RegisterField<
2689 7,
2690 0x1,
2691 1,
2692 0,
2693 nmicr::Nflten,
2694 nmicr::Nflten,
2695 Nmicr_SPEC,
2696 crate::common::RW,
2697 > {
2698 crate::common::RegisterField::<
2699 7,
2700 0x1,
2701 1,
2702 0,
2703 nmicr::Nflten,
2704 nmicr::Nflten,
2705 Nmicr_SPEC,
2706 crate::common::RW,
2707 >::from_register(self, 0)
2708 }
2709
2710 #[doc = "NMI Digital Filter Sampling Clock"]
2711 #[inline(always)]
2712 pub fn nfclksel(
2713 self,
2714 ) -> crate::common::RegisterField<
2715 4,
2716 0x3,
2717 1,
2718 0,
2719 nmicr::Nfclksel,
2720 nmicr::Nfclksel,
2721 Nmicr_SPEC,
2722 crate::common::RW,
2723 > {
2724 crate::common::RegisterField::<
2725 4,
2726 0x3,
2727 1,
2728 0,
2729 nmicr::Nfclksel,
2730 nmicr::Nfclksel,
2731 Nmicr_SPEC,
2732 crate::common::RW,
2733 >::from_register(self, 0)
2734 }
2735
2736 #[doc = "NMI Detection Set"]
2737 #[inline(always)]
2738 pub fn nmimd(
2739 self,
2740 ) -> crate::common::RegisterField<
2741 0,
2742 0x1,
2743 1,
2744 0,
2745 nmicr::Nmimd,
2746 nmicr::Nmimd,
2747 Nmicr_SPEC,
2748 crate::common::RW,
2749 > {
2750 crate::common::RegisterField::<
2751 0,
2752 0x1,
2753 1,
2754 0,
2755 nmicr::Nmimd,
2756 nmicr::Nmimd,
2757 Nmicr_SPEC,
2758 crate::common::RW,
2759 >::from_register(self, 0)
2760 }
2761}
2762impl ::core::default::Default for Nmicr {
2763 #[inline(always)]
2764 fn default() -> Nmicr {
2765 <crate::RegValueT<Nmicr_SPEC> as RegisterValue<_>>::new(0)
2766 }
2767}
2768pub mod nmicr {
2769
2770 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2771 pub struct Nflten_SPEC;
2772 pub type Nflten = crate::EnumBitfieldStruct<u8, Nflten_SPEC>;
2773 impl Nflten {
2774 #[doc = "Digital filter is disabled."]
2775 pub const _0: Self = Self::new(0);
2776
2777 #[doc = "Digital filter is enabled."]
2778 pub const _1: Self = Self::new(1);
2779 }
2780 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2781 pub struct Nfclksel_SPEC;
2782 pub type Nfclksel = crate::EnumBitfieldStruct<u8, Nfclksel_SPEC>;
2783 impl Nfclksel {
2784 #[doc = "PCLKB"]
2785 pub const _00: Self = Self::new(0);
2786
2787 #[doc = "PCLKB/8"]
2788 pub const _01: Self = Self::new(1);
2789
2790 #[doc = "PCLKB/32"]
2791 pub const _10: Self = Self::new(2);
2792
2793 #[doc = "PCLKB/64"]
2794 pub const _11: Self = Self::new(3);
2795 }
2796 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2797 pub struct Nmimd_SPEC;
2798 pub type Nmimd = crate::EnumBitfieldStruct<u8, Nmimd_SPEC>;
2799 impl Nmimd {
2800 #[doc = "Falling edge"]
2801 pub const _0: Self = Self::new(0);
2802
2803 #[doc = "Rising edge"]
2804 pub const _1: Self = Self::new(1);
2805 }
2806}
2807#[doc(hidden)]
2808#[derive(Copy, Clone, Eq, PartialEq)]
2809pub struct Ielsr_SPEC;
2810impl crate::sealed::RegSpec for Ielsr_SPEC {
2811 type DataType = u32;
2812}
2813
2814#[doc = "INT Event Link Setting Register %s"]
2815pub type Ielsr = crate::RegValueT<Ielsr_SPEC>;
2816
2817impl Ielsr {
2818 #[doc = "DTC Activation Enable"]
2819 #[inline(always)]
2820 pub fn dtce(
2821 self,
2822 ) -> crate::common::RegisterField<
2823 24,
2824 0x1,
2825 1,
2826 0,
2827 ielsr::Dtce,
2828 ielsr::Dtce,
2829 Ielsr_SPEC,
2830 crate::common::RW,
2831 > {
2832 crate::common::RegisterField::<
2833 24,
2834 0x1,
2835 1,
2836 0,
2837 ielsr::Dtce,
2838 ielsr::Dtce,
2839 Ielsr_SPEC,
2840 crate::common::RW,
2841 >::from_register(self, 0)
2842 }
2843
2844 #[doc = "Interrupt Status Flag"]
2845 #[inline(always)]
2846 pub fn ir(
2847 self,
2848 ) -> crate::common::RegisterField<
2849 16,
2850 0x1,
2851 1,
2852 0,
2853 ielsr::Ir,
2854 ielsr::Ir,
2855 Ielsr_SPEC,
2856 crate::common::RW,
2857 > {
2858 crate::common::RegisterField::<
2859 16,
2860 0x1,
2861 1,
2862 0,
2863 ielsr::Ir,
2864 ielsr::Ir,
2865 Ielsr_SPEC,
2866 crate::common::RW,
2867 >::from_register(self, 0)
2868 }
2869
2870 #[doc = "Event selection to NVIC"]
2871 #[inline(always)]
2872 pub fn iels(
2873 self,
2874 ) -> crate::common::RegisterField<
2875 0,
2876 0x1ff,
2877 1,
2878 0,
2879 ielsr::Iels,
2880 ielsr::Iels,
2881 Ielsr_SPEC,
2882 crate::common::RW,
2883 > {
2884 crate::common::RegisterField::<
2885 0,
2886 0x1ff,
2887 1,
2888 0,
2889 ielsr::Iels,
2890 ielsr::Iels,
2891 Ielsr_SPEC,
2892 crate::common::RW,
2893 >::from_register(self, 0)
2894 }
2895}
2896impl ::core::default::Default for Ielsr {
2897 #[inline(always)]
2898 fn default() -> Ielsr {
2899 <crate::RegValueT<Ielsr_SPEC> as RegisterValue<_>>::new(0)
2900 }
2901}
2902pub mod ielsr {
2903
2904 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2905 pub struct Dtce_SPEC;
2906 pub type Dtce = crate::EnumBitfieldStruct<u8, Dtce_SPEC>;
2907 impl Dtce {
2908 #[doc = "DTC activation is disabled"]
2909 pub const _0: Self = Self::new(0);
2910
2911 #[doc = "DTC activation is enabled"]
2912 pub const _1: Self = Self::new(1);
2913 }
2914 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2915 pub struct Ir_SPEC;
2916 pub type Ir = crate::EnumBitfieldStruct<u8, Ir_SPEC>;
2917 impl Ir {
2918 #[doc = "No interrupt request is generated"]
2919 pub const _0: Self = Self::new(0);
2920
2921 #[doc = "An interrupt request is generated ( \"1\" write to the IR bit is prohibited. )"]
2922 pub const _1: Self = Self::new(1);
2923 }
2924 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2925 pub struct Iels_SPEC;
2926 pub type Iels = crate::EnumBitfieldStruct<u8, Iels_SPEC>;
2927 impl Iels {
2928 #[doc = "Nothing is selected"]
2929 pub const _0_X_000: Self = Self::new(0);
2930 }
2931}
2932#[doc(hidden)]
2933#[derive(Copy, Clone, Eq, PartialEq)]
2934pub struct Delsr_SPEC;
2935impl crate::sealed::RegSpec for Delsr_SPEC {
2936 type DataType = u32;
2937}
2938
2939#[doc = "DMAC Event Link Setting Register %s"]
2940pub type Delsr = crate::RegValueT<Delsr_SPEC>;
2941
2942impl Delsr {
2943 #[doc = "Interrupt Status Flag for DMAC"]
2944 #[inline(always)]
2945 pub fn ir(
2946 self,
2947 ) -> crate::common::RegisterField<
2948 16,
2949 0x1,
2950 1,
2951 0,
2952 delsr::Ir,
2953 delsr::Ir,
2954 Delsr_SPEC,
2955 crate::common::RW,
2956 > {
2957 crate::common::RegisterField::<
2958 16,
2959 0x1,
2960 1,
2961 0,
2962 delsr::Ir,
2963 delsr::Ir,
2964 Delsr_SPEC,
2965 crate::common::RW,
2966 >::from_register(self, 0)
2967 }
2968
2969 #[doc = "DMAC Event Link Select"]
2970 #[inline(always)]
2971 pub fn dels(
2972 self,
2973 ) -> crate::common::RegisterField<
2974 0,
2975 0x1ff,
2976 1,
2977 0,
2978 delsr::Dels,
2979 delsr::Dels,
2980 Delsr_SPEC,
2981 crate::common::RW,
2982 > {
2983 crate::common::RegisterField::<
2984 0,
2985 0x1ff,
2986 1,
2987 0,
2988 delsr::Dels,
2989 delsr::Dels,
2990 Delsr_SPEC,
2991 crate::common::RW,
2992 >::from_register(self, 0)
2993 }
2994}
2995impl ::core::default::Default for Delsr {
2996 #[inline(always)]
2997 fn default() -> Delsr {
2998 <crate::RegValueT<Delsr_SPEC> as RegisterValue<_>>::new(0)
2999 }
3000}
3001pub mod delsr {
3002
3003 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3004 pub struct Ir_SPEC;
3005 pub type Ir = crate::EnumBitfieldStruct<u8, Ir_SPEC>;
3006 impl Ir {
3007 #[doc = "No interrupt request is generated"]
3008 pub const _0: Self = Self::new(0);
3009
3010 #[doc = "An interrupt request is generated ( \"1\" write to the IR bit is prohibited. )"]
3011 pub const _1: Self = Self::new(1);
3012 }
3013 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3014 pub struct Dels_SPEC;
3015 pub type Dels = crate::EnumBitfieldStruct<u8, Dels_SPEC>;
3016 impl Dels {
3017 #[doc = "Nothing is selected."]
3018 pub const _0_X_000: Self = Self::new(0);
3019 }
3020}
3021#[doc(hidden)]
3022#[derive(Copy, Clone, Eq, PartialEq)]
3023pub struct Selsr0_SPEC;
3024impl crate::sealed::RegSpec for Selsr0_SPEC {
3025 type DataType = u16;
3026}
3027
3028#[doc = "SYS Event Link Setting Register"]
3029pub type Selsr0 = crate::RegValueT<Selsr0_SPEC>;
3030
3031impl Selsr0 {
3032 #[doc = "SYS Event Link Select"]
3033 #[inline(always)]
3034 pub fn sels(
3035 self,
3036 ) -> crate::common::RegisterField<
3037 0,
3038 0x1ff,
3039 1,
3040 0,
3041 selsr0::Sels,
3042 selsr0::Sels,
3043 Selsr0_SPEC,
3044 crate::common::RW,
3045 > {
3046 crate::common::RegisterField::<
3047 0,
3048 0x1ff,
3049 1,
3050 0,
3051 selsr0::Sels,
3052 selsr0::Sels,
3053 Selsr0_SPEC,
3054 crate::common::RW,
3055 >::from_register(self, 0)
3056 }
3057}
3058impl ::core::default::Default for Selsr0 {
3059 #[inline(always)]
3060 fn default() -> Selsr0 {
3061 <crate::RegValueT<Selsr0_SPEC> as RegisterValue<_>>::new(0)
3062 }
3063}
3064pub mod selsr0 {
3065
3066 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3067 pub struct Sels_SPEC;
3068 pub type Sels = crate::EnumBitfieldStruct<u8, Sels_SPEC>;
3069 impl Sels {
3070 #[doc = "Disable event output to the associated low-power mode module"]
3071 pub const _000000000: Self = Self::new(0);
3072 }
3073}
3074#[doc(hidden)]
3075#[derive(Copy, Clone, Eq, PartialEq)]
3076pub struct Wupen_SPEC;
3077impl crate::sealed::RegSpec for Wupen_SPEC {
3078 type DataType = u32;
3079}
3080
3081#[doc = "Wake Up interrupt enable register"]
3082pub type Wupen = crate::RegValueT<Wupen_SPEC>;
3083
3084impl Wupen {
3085 #[doc = "IIC0 address match interrupt S/W standby returns enable bit"]
3086 #[inline(always)]
3087 pub fn iic0wupen(
3088 self,
3089 ) -> crate::common::RegisterField<
3090 31,
3091 0x1,
3092 1,
3093 0,
3094 wupen::Iic0Wupen,
3095 wupen::Iic0Wupen,
3096 Wupen_SPEC,
3097 crate::common::RW,
3098 > {
3099 crate::common::RegisterField::<
3100 31,
3101 0x1,
3102 1,
3103 0,
3104 wupen::Iic0Wupen,
3105 wupen::Iic0Wupen,
3106 Wupen_SPEC,
3107 crate::common::RW,
3108 >::from_register(self, 0)
3109 }
3110
3111 #[doc = "AGT1 compare match B interrupt S/W standby returns enable bit"]
3112 #[inline(always)]
3113 pub fn agt1cbwupen(
3114 self,
3115 ) -> crate::common::RegisterField<
3116 30,
3117 0x1,
3118 1,
3119 0,
3120 wupen::Agt1Cbwupen,
3121 wupen::Agt1Cbwupen,
3122 Wupen_SPEC,
3123 crate::common::RW,
3124 > {
3125 crate::common::RegisterField::<
3126 30,
3127 0x1,
3128 1,
3129 0,
3130 wupen::Agt1Cbwupen,
3131 wupen::Agt1Cbwupen,
3132 Wupen_SPEC,
3133 crate::common::RW,
3134 >::from_register(self, 0)
3135 }
3136
3137 #[doc = "AGT1 compare match A interrupt S/W standby returns enable bit"]
3138 #[inline(always)]
3139 pub fn agt1cawupen(
3140 self,
3141 ) -> crate::common::RegisterField<
3142 29,
3143 0x1,
3144 1,
3145 0,
3146 wupen::Agt1Cawupen,
3147 wupen::Agt1Cawupen,
3148 Wupen_SPEC,
3149 crate::common::RW,
3150 > {
3151 crate::common::RegisterField::<
3152 29,
3153 0x1,
3154 1,
3155 0,
3156 wupen::Agt1Cawupen,
3157 wupen::Agt1Cawupen,
3158 Wupen_SPEC,
3159 crate::common::RW,
3160 >::from_register(self, 0)
3161 }
3162
3163 #[doc = "AGT1 underflow interrupt S/W standby returns enable bit"]
3164 #[inline(always)]
3165 pub fn agt1udwupen(
3166 self,
3167 ) -> crate::common::RegisterField<
3168 28,
3169 0x1,
3170 1,
3171 0,
3172 wupen::Agt1Udwupen,
3173 wupen::Agt1Udwupen,
3174 Wupen_SPEC,
3175 crate::common::RW,
3176 > {
3177 crate::common::RegisterField::<
3178 28,
3179 0x1,
3180 1,
3181 0,
3182 wupen::Agt1Udwupen,
3183 wupen::Agt1Udwupen,
3184 Wupen_SPEC,
3185 crate::common::RW,
3186 >::from_register(self, 0)
3187 }
3188
3189 #[doc = "USBFS interrupt S/W standby returns enable bit"]
3190 #[inline(always)]
3191 pub fn usbfswupen(
3192 self,
3193 ) -> crate::common::RegisterField<
3194 27,
3195 0x1,
3196 1,
3197 0,
3198 wupen::Usbfswupen,
3199 wupen::Usbfswupen,
3200 Wupen_SPEC,
3201 crate::common::RW,
3202 > {
3203 crate::common::RegisterField::<
3204 27,
3205 0x1,
3206 1,
3207 0,
3208 wupen::Usbfswupen,
3209 wupen::Usbfswupen,
3210 Wupen_SPEC,
3211 crate::common::RW,
3212 >::from_register(self, 0)
3213 }
3214
3215 #[doc = "USBHS interrupt S/W standby returns enable bit"]
3216 #[inline(always)]
3217 pub fn usbhswupen(
3218 self,
3219 ) -> crate::common::RegisterField<
3220 26,
3221 0x1,
3222 1,
3223 0,
3224 wupen::Usbhswupen,
3225 wupen::Usbhswupen,
3226 Wupen_SPEC,
3227 crate::common::RW,
3228 > {
3229 crate::common::RegisterField::<
3230 26,
3231 0x1,
3232 1,
3233 0,
3234 wupen::Usbhswupen,
3235 wupen::Usbhswupen,
3236 Wupen_SPEC,
3237 crate::common::RW,
3238 >::from_register(self, 0)
3239 }
3240
3241 #[doc = "RCT period interrupt S/W standby returns enable bit"]
3242 #[inline(always)]
3243 pub fn rtcprdwupen(
3244 self,
3245 ) -> crate::common::RegisterField<
3246 25,
3247 0x1,
3248 1,
3249 0,
3250 wupen::Rtcprdwupen,
3251 wupen::Rtcprdwupen,
3252 Wupen_SPEC,
3253 crate::common::RW,
3254 > {
3255 crate::common::RegisterField::<
3256 25,
3257 0x1,
3258 1,
3259 0,
3260 wupen::Rtcprdwupen,
3261 wupen::Rtcprdwupen,
3262 Wupen_SPEC,
3263 crate::common::RW,
3264 >::from_register(self, 0)
3265 }
3266
3267 #[doc = "RTC alarm interrupt S/W standby returns enable bit"]
3268 #[inline(always)]
3269 pub fn rtcalmwupen(
3270 self,
3271 ) -> crate::common::RegisterField<
3272 24,
3273 0x1,
3274 1,
3275 0,
3276 wupen::Rtcalmwupen,
3277 wupen::Rtcalmwupen,
3278 Wupen_SPEC,
3279 crate::common::RW,
3280 > {
3281 crate::common::RegisterField::<
3282 24,
3283 0x1,
3284 1,
3285 0,
3286 wupen::Rtcalmwupen,
3287 wupen::Rtcalmwupen,
3288 Wupen_SPEC,
3289 crate::common::RW,
3290 >::from_register(self, 0)
3291 }
3292
3293 #[doc = "ACMPHS0 interrupt S/W standby returns enable bit"]
3294 #[inline(always)]
3295 pub fn acmphs0wupen(
3296 self,
3297 ) -> crate::common::RegisterField<
3298 22,
3299 0x1,
3300 1,
3301 0,
3302 wupen::Acmphs0Wupen,
3303 wupen::Acmphs0Wupen,
3304 Wupen_SPEC,
3305 crate::common::RW,
3306 > {
3307 crate::common::RegisterField::<
3308 22,
3309 0x1,
3310 1,
3311 0,
3312 wupen::Acmphs0Wupen,
3313 wupen::Acmphs0Wupen,
3314 Wupen_SPEC,
3315 crate::common::RW,
3316 >::from_register(self, 0)
3317 }
3318
3319 #[doc = "LVD2 interrupt S/W standby returns enable bit"]
3320 #[inline(always)]
3321 pub fn lvd2wupen(
3322 self,
3323 ) -> crate::common::RegisterField<
3324 19,
3325 0x1,
3326 1,
3327 0,
3328 wupen::Lvd2Wupen,
3329 wupen::Lvd2Wupen,
3330 Wupen_SPEC,
3331 crate::common::RW,
3332 > {
3333 crate::common::RegisterField::<
3334 19,
3335 0x1,
3336 1,
3337 0,
3338 wupen::Lvd2Wupen,
3339 wupen::Lvd2Wupen,
3340 Wupen_SPEC,
3341 crate::common::RW,
3342 >::from_register(self, 0)
3343 }
3344
3345 #[doc = "LVD1 interrupt S/W standby returns enable bit"]
3346 #[inline(always)]
3347 pub fn lvd1wupen(
3348 self,
3349 ) -> crate::common::RegisterField<
3350 18,
3351 0x1,
3352 1,
3353 0,
3354 wupen::Lvd1Wupen,
3355 wupen::Lvd1Wupen,
3356 Wupen_SPEC,
3357 crate::common::RW,
3358 > {
3359 crate::common::RegisterField::<
3360 18,
3361 0x1,
3362 1,
3363 0,
3364 wupen::Lvd1Wupen,
3365 wupen::Lvd1Wupen,
3366 Wupen_SPEC,
3367 crate::common::RW,
3368 >::from_register(self, 0)
3369 }
3370
3371 #[doc = "Key interrupt S/W standby returns enable bit"]
3372 #[inline(always)]
3373 pub fn keywupen(
3374 self,
3375 ) -> crate::common::RegisterField<
3376 17,
3377 0x1,
3378 1,
3379 0,
3380 wupen::Keywupen,
3381 wupen::Keywupen,
3382 Wupen_SPEC,
3383 crate::common::RW,
3384 > {
3385 crate::common::RegisterField::<
3386 17,
3387 0x1,
3388 1,
3389 0,
3390 wupen::Keywupen,
3391 wupen::Keywupen,
3392 Wupen_SPEC,
3393 crate::common::RW,
3394 >::from_register(self, 0)
3395 }
3396
3397 #[doc = "IWDT interrupt S/W standby returns enable bit"]
3398 #[inline(always)]
3399 pub fn iwdtwupen(
3400 self,
3401 ) -> crate::common::RegisterField<
3402 16,
3403 0x1,
3404 1,
3405 0,
3406 wupen::Iwdtwupen,
3407 wupen::Iwdtwupen,
3408 Wupen_SPEC,
3409 crate::common::RW,
3410 > {
3411 crate::common::RegisterField::<
3412 16,
3413 0x1,
3414 1,
3415 0,
3416 wupen::Iwdtwupen,
3417 wupen::Iwdtwupen,
3418 Wupen_SPEC,
3419 crate::common::RW,
3420 >::from_register(self, 0)
3421 }
3422
3423 #[doc = "IRQ15 interrupt S/W standby returns enable bit"]
3424 #[inline(always)]
3425 pub fn irqwupen15(
3426 self,
3427 ) -> crate::common::RegisterField<
3428 15,
3429 0x1,
3430 1,
3431 0,
3432 wupen::Irqwupen15,
3433 wupen::Irqwupen15,
3434 Wupen_SPEC,
3435 crate::common::RW,
3436 > {
3437 crate::common::RegisterField::<
3438 15,
3439 0x1,
3440 1,
3441 0,
3442 wupen::Irqwupen15,
3443 wupen::Irqwupen15,
3444 Wupen_SPEC,
3445 crate::common::RW,
3446 >::from_register(self, 0)
3447 }
3448
3449 #[doc = "IRQ14 interrupt S/W standby returns enable bit"]
3450 #[inline(always)]
3451 pub fn irqwupen14(
3452 self,
3453 ) -> crate::common::RegisterField<
3454 14,
3455 0x1,
3456 1,
3457 0,
3458 wupen::Irqwupen14,
3459 wupen::Irqwupen14,
3460 Wupen_SPEC,
3461 crate::common::RW,
3462 > {
3463 crate::common::RegisterField::<
3464 14,
3465 0x1,
3466 1,
3467 0,
3468 wupen::Irqwupen14,
3469 wupen::Irqwupen14,
3470 Wupen_SPEC,
3471 crate::common::RW,
3472 >::from_register(self, 0)
3473 }
3474
3475 #[doc = "IRQ13 interrupt S/W standby returns enable bit"]
3476 #[inline(always)]
3477 pub fn irqwupen13(
3478 self,
3479 ) -> crate::common::RegisterField<
3480 13,
3481 0x1,
3482 1,
3483 0,
3484 wupen::Irqwupen13,
3485 wupen::Irqwupen13,
3486 Wupen_SPEC,
3487 crate::common::RW,
3488 > {
3489 crate::common::RegisterField::<
3490 13,
3491 0x1,
3492 1,
3493 0,
3494 wupen::Irqwupen13,
3495 wupen::Irqwupen13,
3496 Wupen_SPEC,
3497 crate::common::RW,
3498 >::from_register(self, 0)
3499 }
3500
3501 #[doc = "IRQ12 interrupt S/W standby returns enable bit"]
3502 #[inline(always)]
3503 pub fn irqwupen12(
3504 self,
3505 ) -> crate::common::RegisterField<
3506 12,
3507 0x1,
3508 1,
3509 0,
3510 wupen::Irqwupen12,
3511 wupen::Irqwupen12,
3512 Wupen_SPEC,
3513 crate::common::RW,
3514 > {
3515 crate::common::RegisterField::<
3516 12,
3517 0x1,
3518 1,
3519 0,
3520 wupen::Irqwupen12,
3521 wupen::Irqwupen12,
3522 Wupen_SPEC,
3523 crate::common::RW,
3524 >::from_register(self, 0)
3525 }
3526
3527 #[doc = "IRQ11 interrupt S/W standby returns enable bit"]
3528 #[inline(always)]
3529 pub fn irqwupen11(
3530 self,
3531 ) -> crate::common::RegisterField<
3532 11,
3533 0x1,
3534 1,
3535 0,
3536 wupen::Irqwupen11,
3537 wupen::Irqwupen11,
3538 Wupen_SPEC,
3539 crate::common::RW,
3540 > {
3541 crate::common::RegisterField::<
3542 11,
3543 0x1,
3544 1,
3545 0,
3546 wupen::Irqwupen11,
3547 wupen::Irqwupen11,
3548 Wupen_SPEC,
3549 crate::common::RW,
3550 >::from_register(self, 0)
3551 }
3552
3553 #[doc = "IRQ10 interrupt S/W standby returns enable bit"]
3554 #[inline(always)]
3555 pub fn irqwupen10(
3556 self,
3557 ) -> crate::common::RegisterField<
3558 10,
3559 0x1,
3560 1,
3561 0,
3562 wupen::Irqwupen10,
3563 wupen::Irqwupen10,
3564 Wupen_SPEC,
3565 crate::common::RW,
3566 > {
3567 crate::common::RegisterField::<
3568 10,
3569 0x1,
3570 1,
3571 0,
3572 wupen::Irqwupen10,
3573 wupen::Irqwupen10,
3574 Wupen_SPEC,
3575 crate::common::RW,
3576 >::from_register(self, 0)
3577 }
3578
3579 #[doc = "IRQ9 interrupt S/W standby returns enable bit"]
3580 #[inline(always)]
3581 pub fn irqwupen9(
3582 self,
3583 ) -> crate::common::RegisterField<
3584 9,
3585 0x1,
3586 1,
3587 0,
3588 wupen::Irqwupen9,
3589 wupen::Irqwupen9,
3590 Wupen_SPEC,
3591 crate::common::RW,
3592 > {
3593 crate::common::RegisterField::<
3594 9,
3595 0x1,
3596 1,
3597 0,
3598 wupen::Irqwupen9,
3599 wupen::Irqwupen9,
3600 Wupen_SPEC,
3601 crate::common::RW,
3602 >::from_register(self, 0)
3603 }
3604
3605 #[doc = "IRQ8 interrupt S/W standby returns enable bit"]
3606 #[inline(always)]
3607 pub fn irqwupen8(
3608 self,
3609 ) -> crate::common::RegisterField<
3610 8,
3611 0x1,
3612 1,
3613 0,
3614 wupen::Irqwupen8,
3615 wupen::Irqwupen8,
3616 Wupen_SPEC,
3617 crate::common::RW,
3618 > {
3619 crate::common::RegisterField::<
3620 8,
3621 0x1,
3622 1,
3623 0,
3624 wupen::Irqwupen8,
3625 wupen::Irqwupen8,
3626 Wupen_SPEC,
3627 crate::common::RW,
3628 >::from_register(self, 0)
3629 }
3630
3631 #[doc = "IRQ7 interrupt S/W standby returns enable bit"]
3632 #[inline(always)]
3633 pub fn irqwupen7(
3634 self,
3635 ) -> crate::common::RegisterField<
3636 7,
3637 0x1,
3638 1,
3639 0,
3640 wupen::Irqwupen7,
3641 wupen::Irqwupen7,
3642 Wupen_SPEC,
3643 crate::common::RW,
3644 > {
3645 crate::common::RegisterField::<
3646 7,
3647 0x1,
3648 1,
3649 0,
3650 wupen::Irqwupen7,
3651 wupen::Irqwupen7,
3652 Wupen_SPEC,
3653 crate::common::RW,
3654 >::from_register(self, 0)
3655 }
3656
3657 #[doc = "IRQ6 interrupt S/W standby returns enable bit"]
3658 #[inline(always)]
3659 pub fn irqwupen6(
3660 self,
3661 ) -> crate::common::RegisterField<
3662 6,
3663 0x1,
3664 1,
3665 0,
3666 wupen::Irqwupen6,
3667 wupen::Irqwupen6,
3668 Wupen_SPEC,
3669 crate::common::RW,
3670 > {
3671 crate::common::RegisterField::<
3672 6,
3673 0x1,
3674 1,
3675 0,
3676 wupen::Irqwupen6,
3677 wupen::Irqwupen6,
3678 Wupen_SPEC,
3679 crate::common::RW,
3680 >::from_register(self, 0)
3681 }
3682
3683 #[doc = "IRQ5 interrupt S/W standby returns enable bit"]
3684 #[inline(always)]
3685 pub fn irqwupen5(
3686 self,
3687 ) -> crate::common::RegisterField<
3688 5,
3689 0x1,
3690 1,
3691 0,
3692 wupen::Irqwupen5,
3693 wupen::Irqwupen5,
3694 Wupen_SPEC,
3695 crate::common::RW,
3696 > {
3697 crate::common::RegisterField::<
3698 5,
3699 0x1,
3700 1,
3701 0,
3702 wupen::Irqwupen5,
3703 wupen::Irqwupen5,
3704 Wupen_SPEC,
3705 crate::common::RW,
3706 >::from_register(self, 0)
3707 }
3708
3709 #[doc = "IRQ4 interrupt S/W standby returns enable bit"]
3710 #[inline(always)]
3711 pub fn irqwupen4(
3712 self,
3713 ) -> crate::common::RegisterField<
3714 4,
3715 0x1,
3716 1,
3717 0,
3718 wupen::Irqwupen4,
3719 wupen::Irqwupen4,
3720 Wupen_SPEC,
3721 crate::common::RW,
3722 > {
3723 crate::common::RegisterField::<
3724 4,
3725 0x1,
3726 1,
3727 0,
3728 wupen::Irqwupen4,
3729 wupen::Irqwupen4,
3730 Wupen_SPEC,
3731 crate::common::RW,
3732 >::from_register(self, 0)
3733 }
3734
3735 #[doc = "IRQ3 interrupt S/W standby returns enable bit"]
3736 #[inline(always)]
3737 pub fn irqwupen3(
3738 self,
3739 ) -> crate::common::RegisterField<
3740 3,
3741 0x1,
3742 1,
3743 0,
3744 wupen::Irqwupen3,
3745 wupen::Irqwupen3,
3746 Wupen_SPEC,
3747 crate::common::RW,
3748 > {
3749 crate::common::RegisterField::<
3750 3,
3751 0x1,
3752 1,
3753 0,
3754 wupen::Irqwupen3,
3755 wupen::Irqwupen3,
3756 Wupen_SPEC,
3757 crate::common::RW,
3758 >::from_register(self, 0)
3759 }
3760
3761 #[doc = "IRQ2 interrupt S/W standby returns enable bit"]
3762 #[inline(always)]
3763 pub fn irqwupen2(
3764 self,
3765 ) -> crate::common::RegisterField<
3766 2,
3767 0x1,
3768 1,
3769 0,
3770 wupen::Irqwupen2,
3771 wupen::Irqwupen2,
3772 Wupen_SPEC,
3773 crate::common::RW,
3774 > {
3775 crate::common::RegisterField::<
3776 2,
3777 0x1,
3778 1,
3779 0,
3780 wupen::Irqwupen2,
3781 wupen::Irqwupen2,
3782 Wupen_SPEC,
3783 crate::common::RW,
3784 >::from_register(self, 0)
3785 }
3786
3787 #[doc = "IRQ1 interrupt S/W standby returns enable bit"]
3788 #[inline(always)]
3789 pub fn irqwupen1(
3790 self,
3791 ) -> crate::common::RegisterField<
3792 1,
3793 0x1,
3794 1,
3795 0,
3796 wupen::Irqwupen1,
3797 wupen::Irqwupen1,
3798 Wupen_SPEC,
3799 crate::common::RW,
3800 > {
3801 crate::common::RegisterField::<
3802 1,
3803 0x1,
3804 1,
3805 0,
3806 wupen::Irqwupen1,
3807 wupen::Irqwupen1,
3808 Wupen_SPEC,
3809 crate::common::RW,
3810 >::from_register(self, 0)
3811 }
3812
3813 #[doc = "IRQ0 interrupt S/W standby returns enable bit"]
3814 #[inline(always)]
3815 pub fn irqwupen0(
3816 self,
3817 ) -> crate::common::RegisterField<
3818 0,
3819 0x1,
3820 1,
3821 0,
3822 wupen::Irqwupen0,
3823 wupen::Irqwupen0,
3824 Wupen_SPEC,
3825 crate::common::RW,
3826 > {
3827 crate::common::RegisterField::<
3828 0,
3829 0x1,
3830 1,
3831 0,
3832 wupen::Irqwupen0,
3833 wupen::Irqwupen0,
3834 Wupen_SPEC,
3835 crate::common::RW,
3836 >::from_register(self, 0)
3837 }
3838}
3839impl ::core::default::Default for Wupen {
3840 #[inline(always)]
3841 fn default() -> Wupen {
3842 <crate::RegValueT<Wupen_SPEC> as RegisterValue<_>>::new(0)
3843 }
3844}
3845pub mod wupen {
3846
3847 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3848 pub struct Iic0Wupen_SPEC;
3849 pub type Iic0Wupen = crate::EnumBitfieldStruct<u8, Iic0Wupen_SPEC>;
3850 impl Iic0Wupen {
3851 #[doc = "S/W standby returns by IIC0 address match interrupt is disabled"]
3852 pub const _0: Self = Self::new(0);
3853
3854 #[doc = "S/W standby returns by IIC0 address match interrupt is enabled"]
3855 pub const _1: Self = Self::new(1);
3856 }
3857 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3858 pub struct Agt1Cbwupen_SPEC;
3859 pub type Agt1Cbwupen = crate::EnumBitfieldStruct<u8, Agt1Cbwupen_SPEC>;
3860 impl Agt1Cbwupen {
3861 #[doc = "S/W standby returns by AGT1 compare match B interrupt is disabled"]
3862 pub const _0: Self = Self::new(0);
3863
3864 #[doc = "S/W standby returns by AGT1 compare match B interrupt is enabled"]
3865 pub const _1: Self = Self::new(1);
3866 }
3867 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3868 pub struct Agt1Cawupen_SPEC;
3869 pub type Agt1Cawupen = crate::EnumBitfieldStruct<u8, Agt1Cawupen_SPEC>;
3870 impl Agt1Cawupen {
3871 #[doc = "S/W standby returns by AGT1 compare match A interrupt is disabled"]
3872 pub const _0: Self = Self::new(0);
3873
3874 #[doc = "S/W standby returns by AGT1 compare match A interrupt is enabled"]
3875 pub const _1: Self = Self::new(1);
3876 }
3877 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3878 pub struct Agt1Udwupen_SPEC;
3879 pub type Agt1Udwupen = crate::EnumBitfieldStruct<u8, Agt1Udwupen_SPEC>;
3880 impl Agt1Udwupen {
3881 #[doc = "S/W standby returns by AGT1 underflow interrupt is disabled"]
3882 pub const _0: Self = Self::new(0);
3883
3884 #[doc = "S/W standby returns by AGT1 underflow interrupt is enabled"]
3885 pub const _1: Self = Self::new(1);
3886 }
3887 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3888 pub struct Usbfswupen_SPEC;
3889 pub type Usbfswupen = crate::EnumBitfieldStruct<u8, Usbfswupen_SPEC>;
3890 impl Usbfswupen {
3891 #[doc = "S/W standby returns by USBFS interrupt is disabled"]
3892 pub const _0: Self = Self::new(0);
3893
3894 #[doc = "S/W standby returns by USBFS interrupt is enabled"]
3895 pub const _1: Self = Self::new(1);
3896 }
3897 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3898 pub struct Usbhswupen_SPEC;
3899 pub type Usbhswupen = crate::EnumBitfieldStruct<u8, Usbhswupen_SPEC>;
3900 impl Usbhswupen {
3901 #[doc = "S/W standby returns by USBHS interrupt is disabled"]
3902 pub const _0: Self = Self::new(0);
3903
3904 #[doc = "S/W standby returns by USBHS interrupt is enabled"]
3905 pub const _1: Self = Self::new(1);
3906 }
3907 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3908 pub struct Rtcprdwupen_SPEC;
3909 pub type Rtcprdwupen = crate::EnumBitfieldStruct<u8, Rtcprdwupen_SPEC>;
3910 impl Rtcprdwupen {
3911 #[doc = "S/W standby returns by RTC period interrupt is disabled"]
3912 pub const _0: Self = Self::new(0);
3913
3914 #[doc = "S/W standby returns by RTC period interrupt is enabled"]
3915 pub const _1: Self = Self::new(1);
3916 }
3917 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3918 pub struct Rtcalmwupen_SPEC;
3919 pub type Rtcalmwupen = crate::EnumBitfieldStruct<u8, Rtcalmwupen_SPEC>;
3920 impl Rtcalmwupen {
3921 #[doc = "S/W standby returns by RTC alarm interrupt is disabled"]
3922 pub const _0: Self = Self::new(0);
3923
3924 #[doc = "S/W standby returns by RTC alarm interrupt is enabled"]
3925 pub const _1: Self = Self::new(1);
3926 }
3927 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3928 pub struct Acmphs0Wupen_SPEC;
3929 pub type Acmphs0Wupen = crate::EnumBitfieldStruct<u8, Acmphs0Wupen_SPEC>;
3930 impl Acmphs0Wupen {
3931 #[doc = "S/W standby returns by ACMPHS0 interrupt is disabled"]
3932 pub const _0: Self = Self::new(0);
3933
3934 #[doc = "S/W standby returns by ACMPHS0 interrupt is enabled"]
3935 pub const _1: Self = Self::new(1);
3936 }
3937 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3938 pub struct Lvd2Wupen_SPEC;
3939 pub type Lvd2Wupen = crate::EnumBitfieldStruct<u8, Lvd2Wupen_SPEC>;
3940 impl Lvd2Wupen {
3941 #[doc = "S/W standby returns by LVD2 interrupt is disabled"]
3942 pub const _0: Self = Self::new(0);
3943
3944 #[doc = "S/W standby returns by LVD2 interrupt is enabled"]
3945 pub const _1: Self = Self::new(1);
3946 }
3947 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3948 pub struct Lvd1Wupen_SPEC;
3949 pub type Lvd1Wupen = crate::EnumBitfieldStruct<u8, Lvd1Wupen_SPEC>;
3950 impl Lvd1Wupen {
3951 #[doc = "S/W standby returns by LVD1 interrupt is disabled"]
3952 pub const _0: Self = Self::new(0);
3953
3954 #[doc = "S/W standby returns by LVD1 interrupt is enabled"]
3955 pub const _1: Self = Self::new(1);
3956 }
3957 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3958 pub struct Keywupen_SPEC;
3959 pub type Keywupen = crate::EnumBitfieldStruct<u8, Keywupen_SPEC>;
3960 impl Keywupen {
3961 #[doc = "S/W standby returns by KEY interrupt is disabled"]
3962 pub const _0: Self = Self::new(0);
3963
3964 #[doc = "S/W standby returns by KEY interrupt is enabled"]
3965 pub const _1: Self = Self::new(1);
3966 }
3967 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3968 pub struct Iwdtwupen_SPEC;
3969 pub type Iwdtwupen = crate::EnumBitfieldStruct<u8, Iwdtwupen_SPEC>;
3970 impl Iwdtwupen {
3971 #[doc = "S/W standby returns by IWDT interrupt is disabled"]
3972 pub const _0: Self = Self::new(0);
3973
3974 #[doc = "S/W standby returns by IWDT interrupt is enabled"]
3975 pub const _1: Self = Self::new(1);
3976 }
3977 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3978 pub struct Irqwupen15_SPEC;
3979 pub type Irqwupen15 = crate::EnumBitfieldStruct<u8, Irqwupen15_SPEC>;
3980 impl Irqwupen15 {
3981 #[doc = "S/W standby returns by IRQ15 interrupt is disabled"]
3982 pub const _0: Self = Self::new(0);
3983
3984 #[doc = "S/W standby returns by IRQ15 interrupt is enabled"]
3985 pub const _1: Self = Self::new(1);
3986 }
3987 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3988 pub struct Irqwupen14_SPEC;
3989 pub type Irqwupen14 = crate::EnumBitfieldStruct<u8, Irqwupen14_SPEC>;
3990 impl Irqwupen14 {
3991 #[doc = "S/W standby returns by IRQ14 interrupt is disabled"]
3992 pub const _0: Self = Self::new(0);
3993
3994 #[doc = "S/W standby returns by IRQ14 interrupt is enabled"]
3995 pub const _1: Self = Self::new(1);
3996 }
3997 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3998 pub struct Irqwupen13_SPEC;
3999 pub type Irqwupen13 = crate::EnumBitfieldStruct<u8, Irqwupen13_SPEC>;
4000 impl Irqwupen13 {
4001 #[doc = "S/W standby returns by IRQ13 interrupt is disabled"]
4002 pub const _0: Self = Self::new(0);
4003
4004 #[doc = "S/W standby returns by IRQ13 interrupt is enabled"]
4005 pub const _1: Self = Self::new(1);
4006 }
4007 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4008 pub struct Irqwupen12_SPEC;
4009 pub type Irqwupen12 = crate::EnumBitfieldStruct<u8, Irqwupen12_SPEC>;
4010 impl Irqwupen12 {
4011 #[doc = "S/W standby returns by IRQ12 interrupt is disabled"]
4012 pub const _0: Self = Self::new(0);
4013
4014 #[doc = "S/W standby returns by IRQ12 interrupt is enabled"]
4015 pub const _1: Self = Self::new(1);
4016 }
4017 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4018 pub struct Irqwupen11_SPEC;
4019 pub type Irqwupen11 = crate::EnumBitfieldStruct<u8, Irqwupen11_SPEC>;
4020 impl Irqwupen11 {
4021 #[doc = "S/W standby returns by IRQ11 interrupt is disabled"]
4022 pub const _0: Self = Self::new(0);
4023
4024 #[doc = "S/W standby returns by IRQ11 interrupt is enabled"]
4025 pub const _1: Self = Self::new(1);
4026 }
4027 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4028 pub struct Irqwupen10_SPEC;
4029 pub type Irqwupen10 = crate::EnumBitfieldStruct<u8, Irqwupen10_SPEC>;
4030 impl Irqwupen10 {
4031 #[doc = "S/W standby returns by IRQ10 interrupt is disabled"]
4032 pub const _0: Self = Self::new(0);
4033
4034 #[doc = "S/W standby returns by IRQ10 interrupt is enabled"]
4035 pub const _1: Self = Self::new(1);
4036 }
4037 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4038 pub struct Irqwupen9_SPEC;
4039 pub type Irqwupen9 = crate::EnumBitfieldStruct<u8, Irqwupen9_SPEC>;
4040 impl Irqwupen9 {
4041 #[doc = "S/W standby returns by IRQ9 interrupt is disabled"]
4042 pub const _0: Self = Self::new(0);
4043
4044 #[doc = "S/W standby returns by IRQ9 interrupt is enabled"]
4045 pub const _1: Self = Self::new(1);
4046 }
4047 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4048 pub struct Irqwupen8_SPEC;
4049 pub type Irqwupen8 = crate::EnumBitfieldStruct<u8, Irqwupen8_SPEC>;
4050 impl Irqwupen8 {
4051 #[doc = "S/W standby returns by IRQ8 interrupt is disabled"]
4052 pub const _0: Self = Self::new(0);
4053
4054 #[doc = "S/W standby returns by IRQ8 interrupt is enabled"]
4055 pub const _1: Self = Self::new(1);
4056 }
4057 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4058 pub struct Irqwupen7_SPEC;
4059 pub type Irqwupen7 = crate::EnumBitfieldStruct<u8, Irqwupen7_SPEC>;
4060 impl Irqwupen7 {
4061 #[doc = "S/W standby returns by IRQ7 interrupt is disabled"]
4062 pub const _0: Self = Self::new(0);
4063
4064 #[doc = "S/W standby returns by IRQ7 interrupt is enabled"]
4065 pub const _1: Self = Self::new(1);
4066 }
4067 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4068 pub struct Irqwupen6_SPEC;
4069 pub type Irqwupen6 = crate::EnumBitfieldStruct<u8, Irqwupen6_SPEC>;
4070 impl Irqwupen6 {
4071 #[doc = "S/W standby returns by IRQ6 interrupt is disabled"]
4072 pub const _0: Self = Self::new(0);
4073
4074 #[doc = "S/W standby returns by IRQ6 interrupt is enabled"]
4075 pub const _1: Self = Self::new(1);
4076 }
4077 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4078 pub struct Irqwupen5_SPEC;
4079 pub type Irqwupen5 = crate::EnumBitfieldStruct<u8, Irqwupen5_SPEC>;
4080 impl Irqwupen5 {
4081 #[doc = "S/W standby returns by IRQ5 interrupt is disabled"]
4082 pub const _0: Self = Self::new(0);
4083
4084 #[doc = "S/W standby returns by IRQ5 interrupt is enabled"]
4085 pub const _1: Self = Self::new(1);
4086 }
4087 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4088 pub struct Irqwupen4_SPEC;
4089 pub type Irqwupen4 = crate::EnumBitfieldStruct<u8, Irqwupen4_SPEC>;
4090 impl Irqwupen4 {
4091 #[doc = "S/W standby returns by IRQ4 interrupt is disabled"]
4092 pub const _0: Self = Self::new(0);
4093
4094 #[doc = "S/W standby returns by IRQ4 interrupt is enabled"]
4095 pub const _1: Self = Self::new(1);
4096 }
4097 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4098 pub struct Irqwupen3_SPEC;
4099 pub type Irqwupen3 = crate::EnumBitfieldStruct<u8, Irqwupen3_SPEC>;
4100 impl Irqwupen3 {
4101 #[doc = "S/W standby returns by IRQ3 interrupt is disabled"]
4102 pub const _0: Self = Self::new(0);
4103
4104 #[doc = "S/W standby returns by IRQ3 interrupt is enabled"]
4105 pub const _1: Self = Self::new(1);
4106 }
4107 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4108 pub struct Irqwupen2_SPEC;
4109 pub type Irqwupen2 = crate::EnumBitfieldStruct<u8, Irqwupen2_SPEC>;
4110 impl Irqwupen2 {
4111 #[doc = "S/W standby returns by IRQ2 interrupt is disabled"]
4112 pub const _0: Self = Self::new(0);
4113
4114 #[doc = "S/W standby returns by IRQ2 interrupt is enabled"]
4115 pub const _1: Self = Self::new(1);
4116 }
4117 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4118 pub struct Irqwupen1_SPEC;
4119 pub type Irqwupen1 = crate::EnumBitfieldStruct<u8, Irqwupen1_SPEC>;
4120 impl Irqwupen1 {
4121 #[doc = "S/W standby returns by IRQ1 interrupt is disabled"]
4122 pub const _0: Self = Self::new(0);
4123
4124 #[doc = "S/W standby returns by IRQ1 interrupt is enabled"]
4125 pub const _1: Self = Self::new(1);
4126 }
4127 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4128 pub struct Irqwupen0_SPEC;
4129 pub type Irqwupen0 = crate::EnumBitfieldStruct<u8, Irqwupen0_SPEC>;
4130 impl Irqwupen0 {
4131 #[doc = "S/W standby returns by IRQ0 interrupt is disabled"]
4132 pub const _0: Self = Self::new(0);
4133
4134 #[doc = "S/W standby returns by IRQ0 interrupt is enabled"]
4135 pub const _1: Self = Self::new(1);
4136 }
4137}