1#[doc = "Register `SMR` reader"]
2pub struct R(crate::R<SMR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SMR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SMR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SMR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `SMR` writer"]
17pub struct W(crate::W<SMR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SMR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SMR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SMR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CKS` reader - Clock Select"]
38pub type CKS_R = crate::FieldReader<u8, CKS_A>;
39#[doc = "Clock Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CKS_A {
43 #[doc = "0: PCLK clock"]
44 _00 = 0,
45 #[doc = "1: PCLK/4 clock"]
46 _01 = 1,
47 #[doc = "2: PCLK/16 clock"]
48 _10 = 2,
49 #[doc = "3: PCLK/64 clock"]
50 _11 = 3,
51}
52impl From<CKS_A> for u8 {
53 #[inline(always)]
54 fn from(variant: CKS_A) -> Self {
55 variant as _
56 }
57}
58impl CKS_R {
59 #[doc = "Get enumerated values variant"]
60 #[inline(always)]
61 pub fn variant(&self) -> CKS_A {
62 match self.bits {
63 0 => CKS_A::_00,
64 1 => CKS_A::_01,
65 2 => CKS_A::_10,
66 3 => CKS_A::_11,
67 _ => unreachable!(),
68 }
69 }
70 #[doc = "Checks if the value of the field is `_00`"]
71 #[inline(always)]
72 pub fn is_00(&self) -> bool {
73 *self == CKS_A::_00
74 }
75 #[doc = "Checks if the value of the field is `_01`"]
76 #[inline(always)]
77 pub fn is_01(&self) -> bool {
78 *self == CKS_A::_01
79 }
80 #[doc = "Checks if the value of the field is `_10`"]
81 #[inline(always)]
82 pub fn is_10(&self) -> bool {
83 *self == CKS_A::_10
84 }
85 #[doc = "Checks if the value of the field is `_11`"]
86 #[inline(always)]
87 pub fn is_11(&self) -> bool {
88 *self == CKS_A::_11
89 }
90}
91#[doc = "Field `CKS` writer - Clock Select"]
92pub type CKS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, SMR_SPEC, u8, CKS_A, 2, O>;
93impl<'a, const O: u8> CKS_W<'a, O> {
94 #[doc = "PCLK clock"]
95 #[inline(always)]
96 pub fn _00(self) -> &'a mut W {
97 self.variant(CKS_A::_00)
98 }
99 #[doc = "PCLK/4 clock"]
100 #[inline(always)]
101 pub fn _01(self) -> &'a mut W {
102 self.variant(CKS_A::_01)
103 }
104 #[doc = "PCLK/16 clock"]
105 #[inline(always)]
106 pub fn _10(self) -> &'a mut W {
107 self.variant(CKS_A::_10)
108 }
109 #[doc = "PCLK/64 clock"]
110 #[inline(always)]
111 pub fn _11(self) -> &'a mut W {
112 self.variant(CKS_A::_11)
113 }
114}
115#[doc = "Field `MP` reader - Multi-Processor Mode (Valid only in asynchronous mode)"]
116pub type MP_R = crate::BitReader<MP_A>;
117#[doc = "Multi-Processor Mode (Valid only in asynchronous mode)\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119pub enum MP_A {
120 #[doc = "0: Multi-processor communications function is disabled"]
121 _0 = 0,
122 #[doc = "1: Multi-processor communications function is enabled"]
123 _1 = 1,
124}
125impl From<MP_A> for bool {
126 #[inline(always)]
127 fn from(variant: MP_A) -> Self {
128 variant as u8 != 0
129 }
130}
131impl MP_R {
132 #[doc = "Get enumerated values variant"]
133 #[inline(always)]
134 pub fn variant(&self) -> MP_A {
135 match self.bits {
136 false => MP_A::_0,
137 true => MP_A::_1,
138 }
139 }
140 #[doc = "Checks if the value of the field is `_0`"]
141 #[inline(always)]
142 pub fn is_0(&self) -> bool {
143 *self == MP_A::_0
144 }
145 #[doc = "Checks if the value of the field is `_1`"]
146 #[inline(always)]
147 pub fn is_1(&self) -> bool {
148 *self == MP_A::_1
149 }
150}
151#[doc = "Field `MP` writer - Multi-Processor Mode (Valid only in asynchronous mode)"]
152pub type MP_W<'a, const O: u8> = crate::BitWriter<'a, u8, SMR_SPEC, MP_A, O>;
153impl<'a, const O: u8> MP_W<'a, O> {
154 #[doc = "Multi-processor communications function is disabled"]
155 #[inline(always)]
156 pub fn _0(self) -> &'a mut W {
157 self.variant(MP_A::_0)
158 }
159 #[doc = "Multi-processor communications function is enabled"]
160 #[inline(always)]
161 pub fn _1(self) -> &'a mut W {
162 self.variant(MP_A::_1)
163 }
164}
165#[doc = "Field `STOP` reader - Stop Bit Length (Valid only in asynchronous mode)"]
166pub type STOP_R = crate::BitReader<STOP_A>;
167#[doc = "Stop Bit Length (Valid only in asynchronous mode)\n\nValue on reset: 0"]
168#[derive(Clone, Copy, Debug, PartialEq, Eq)]
169pub enum STOP_A {
170 #[doc = "0: 1 stop bit"]
171 _0 = 0,
172 #[doc = "1: 2 stop bits"]
173 _1 = 1,
174}
175impl From<STOP_A> for bool {
176 #[inline(always)]
177 fn from(variant: STOP_A) -> Self {
178 variant as u8 != 0
179 }
180}
181impl STOP_R {
182 #[doc = "Get enumerated values variant"]
183 #[inline(always)]
184 pub fn variant(&self) -> STOP_A {
185 match self.bits {
186 false => STOP_A::_0,
187 true => STOP_A::_1,
188 }
189 }
190 #[doc = "Checks if the value of the field is `_0`"]
191 #[inline(always)]
192 pub fn is_0(&self) -> bool {
193 *self == STOP_A::_0
194 }
195 #[doc = "Checks if the value of the field is `_1`"]
196 #[inline(always)]
197 pub fn is_1(&self) -> bool {
198 *self == STOP_A::_1
199 }
200}
201#[doc = "Field `STOP` writer - Stop Bit Length (Valid only in asynchronous mode)"]
202pub type STOP_W<'a, const O: u8> = crate::BitWriter<'a, u8, SMR_SPEC, STOP_A, O>;
203impl<'a, const O: u8> STOP_W<'a, O> {
204 #[doc = "1 stop bit"]
205 #[inline(always)]
206 pub fn _0(self) -> &'a mut W {
207 self.variant(STOP_A::_0)
208 }
209 #[doc = "2 stop bits"]
210 #[inline(always)]
211 pub fn _1(self) -> &'a mut W {
212 self.variant(STOP_A::_1)
213 }
214}
215#[doc = "Field `PM` reader - Parity Mode (Valid only when the PE bit is 1)"]
216pub type PM_R = crate::BitReader<PM_A>;
217#[doc = "Parity Mode (Valid only when the PE bit is 1)\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219pub enum PM_A {
220 #[doc = "0: Selects even parity"]
221 _0 = 0,
222 #[doc = "1: Selects odd parity"]
223 _1 = 1,
224}
225impl From<PM_A> for bool {
226 #[inline(always)]
227 fn from(variant: PM_A) -> Self {
228 variant as u8 != 0
229 }
230}
231impl PM_R {
232 #[doc = "Get enumerated values variant"]
233 #[inline(always)]
234 pub fn variant(&self) -> PM_A {
235 match self.bits {
236 false => PM_A::_0,
237 true => PM_A::_1,
238 }
239 }
240 #[doc = "Checks if the value of the field is `_0`"]
241 #[inline(always)]
242 pub fn is_0(&self) -> bool {
243 *self == PM_A::_0
244 }
245 #[doc = "Checks if the value of the field is `_1`"]
246 #[inline(always)]
247 pub fn is_1(&self) -> bool {
248 *self == PM_A::_1
249 }
250}
251#[doc = "Field `PM` writer - Parity Mode (Valid only when the PE bit is 1)"]
252pub type PM_W<'a, const O: u8> = crate::BitWriter<'a, u8, SMR_SPEC, PM_A, O>;
253impl<'a, const O: u8> PM_W<'a, O> {
254 #[doc = "Selects even parity"]
255 #[inline(always)]
256 pub fn _0(self) -> &'a mut W {
257 self.variant(PM_A::_0)
258 }
259 #[doc = "Selects odd parity"]
260 #[inline(always)]
261 pub fn _1(self) -> &'a mut W {
262 self.variant(PM_A::_1)
263 }
264}
265#[doc = "Field `PE` reader - Parity Enable (Valid only in asynchronous mode)"]
266pub type PE_R = crate::BitReader<PE_A>;
267#[doc = "Parity Enable (Valid only in asynchronous mode)\n\nValue on reset: 0"]
268#[derive(Clone, Copy, Debug, PartialEq, Eq)]
269pub enum PE_A {
270 #[doc = "0: Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving )"]
271 _0 = 0,
272 #[doc = "1: The parity bit is added (transmitting) / The parity bit is checked (receiving)"]
273 _1 = 1,
274}
275impl From<PE_A> for bool {
276 #[inline(always)]
277 fn from(variant: PE_A) -> Self {
278 variant as u8 != 0
279 }
280}
281impl PE_R {
282 #[doc = "Get enumerated values variant"]
283 #[inline(always)]
284 pub fn variant(&self) -> PE_A {
285 match self.bits {
286 false => PE_A::_0,
287 true => PE_A::_1,
288 }
289 }
290 #[doc = "Checks if the value of the field is `_0`"]
291 #[inline(always)]
292 pub fn is_0(&self) -> bool {
293 *self == PE_A::_0
294 }
295 #[doc = "Checks if the value of the field is `_1`"]
296 #[inline(always)]
297 pub fn is_1(&self) -> bool {
298 *self == PE_A::_1
299 }
300}
301#[doc = "Field `PE` writer - Parity Enable (Valid only in asynchronous mode)"]
302pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SMR_SPEC, PE_A, O>;
303impl<'a, const O: u8> PE_W<'a, O> {
304 #[doc = "Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving )"]
305 #[inline(always)]
306 pub fn _0(self) -> &'a mut W {
307 self.variant(PE_A::_0)
308 }
309 #[doc = "The parity bit is added (transmitting) / The parity bit is checked (receiving)"]
310 #[inline(always)]
311 pub fn _1(self) -> &'a mut W {
312 self.variant(PE_A::_1)
313 }
314}
315#[doc = "Field `CHR` reader - Character Length (Valid only in asynchronous mode)"]
316pub type CHR_R = crate::BitReader<CHR_A>;
317#[doc = "Character Length (Valid only in asynchronous mode)\n\nValue on reset: 0"]
318#[derive(Clone, Copy, Debug, PartialEq, Eq)]
319pub enum CHR_A {
320 #[doc = "0: Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1)"]
321 _0 = 0,
322 #[doc = "1: Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1)"]
323 _1 = 1,
324}
325impl From<CHR_A> for bool {
326 #[inline(always)]
327 fn from(variant: CHR_A) -> Self {
328 variant as u8 != 0
329 }
330}
331impl CHR_R {
332 #[doc = "Get enumerated values variant"]
333 #[inline(always)]
334 pub fn variant(&self) -> CHR_A {
335 match self.bits {
336 false => CHR_A::_0,
337 true => CHR_A::_1,
338 }
339 }
340 #[doc = "Checks if the value of the field is `_0`"]
341 #[inline(always)]
342 pub fn is_0(&self) -> bool {
343 *self == CHR_A::_0
344 }
345 #[doc = "Checks if the value of the field is `_1`"]
346 #[inline(always)]
347 pub fn is_1(&self) -> bool {
348 *self == CHR_A::_1
349 }
350}
351#[doc = "Field `CHR` writer - Character Length (Valid only in asynchronous mode)"]
352pub type CHR_W<'a, const O: u8> = crate::BitWriter<'a, u8, SMR_SPEC, CHR_A, O>;
353impl<'a, const O: u8> CHR_W<'a, O> {
354 #[doc = "Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1)"]
355 #[inline(always)]
356 pub fn _0(self) -> &'a mut W {
357 self.variant(CHR_A::_0)
358 }
359 #[doc = "Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1)"]
360 #[inline(always)]
361 pub fn _1(self) -> &'a mut W {
362 self.variant(CHR_A::_1)
363 }
364}
365#[doc = "Field `CM` reader - Communications Mode"]
366pub type CM_R = crate::BitReader<CM_A>;
367#[doc = "Communications Mode\n\nValue on reset: 0"]
368#[derive(Clone, Copy, Debug, PartialEq, Eq)]
369pub enum CM_A {
370 #[doc = "0: Asynchronous mode or simple I2C mode"]
371 _0 = 0,
372 #[doc = "1: Clock synchronous mode"]
373 _1 = 1,
374}
375impl From<CM_A> for bool {
376 #[inline(always)]
377 fn from(variant: CM_A) -> Self {
378 variant as u8 != 0
379 }
380}
381impl CM_R {
382 #[doc = "Get enumerated values variant"]
383 #[inline(always)]
384 pub fn variant(&self) -> CM_A {
385 match self.bits {
386 false => CM_A::_0,
387 true => CM_A::_1,
388 }
389 }
390 #[doc = "Checks if the value of the field is `_0`"]
391 #[inline(always)]
392 pub fn is_0(&self) -> bool {
393 *self == CM_A::_0
394 }
395 #[doc = "Checks if the value of the field is `_1`"]
396 #[inline(always)]
397 pub fn is_1(&self) -> bool {
398 *self == CM_A::_1
399 }
400}
401#[doc = "Field `CM` writer - Communications Mode"]
402pub type CM_W<'a, const O: u8> = crate::BitWriter<'a, u8, SMR_SPEC, CM_A, O>;
403impl<'a, const O: u8> CM_W<'a, O> {
404 #[doc = "Asynchronous mode or simple I2C mode"]
405 #[inline(always)]
406 pub fn _0(self) -> &'a mut W {
407 self.variant(CM_A::_0)
408 }
409 #[doc = "Clock synchronous mode"]
410 #[inline(always)]
411 pub fn _1(self) -> &'a mut W {
412 self.variant(CM_A::_1)
413 }
414}
415impl R {
416 #[doc = "Bits 0:1 - Clock Select"]
417 #[inline(always)]
418 pub fn cks(&self) -> CKS_R {
419 CKS_R::new(self.bits & 3)
420 }
421 #[doc = "Bit 2 - Multi-Processor Mode (Valid only in asynchronous mode)"]
422 #[inline(always)]
423 pub fn mp(&self) -> MP_R {
424 MP_R::new(((self.bits >> 2) & 1) != 0)
425 }
426 #[doc = "Bit 3 - Stop Bit Length (Valid only in asynchronous mode)"]
427 #[inline(always)]
428 pub fn stop(&self) -> STOP_R {
429 STOP_R::new(((self.bits >> 3) & 1) != 0)
430 }
431 #[doc = "Bit 4 - Parity Mode (Valid only when the PE bit is 1)"]
432 #[inline(always)]
433 pub fn pm(&self) -> PM_R {
434 PM_R::new(((self.bits >> 4) & 1) != 0)
435 }
436 #[doc = "Bit 5 - Parity Enable (Valid only in asynchronous mode)"]
437 #[inline(always)]
438 pub fn pe(&self) -> PE_R {
439 PE_R::new(((self.bits >> 5) & 1) != 0)
440 }
441 #[doc = "Bit 6 - Character Length (Valid only in asynchronous mode)"]
442 #[inline(always)]
443 pub fn chr(&self) -> CHR_R {
444 CHR_R::new(((self.bits >> 6) & 1) != 0)
445 }
446 #[doc = "Bit 7 - Communications Mode"]
447 #[inline(always)]
448 pub fn cm(&self) -> CM_R {
449 CM_R::new(((self.bits >> 7) & 1) != 0)
450 }
451}
452impl W {
453 #[doc = "Bits 0:1 - Clock Select"]
454 #[inline(always)]
455 #[must_use]
456 pub fn cks(&mut self) -> CKS_W<0> {
457 CKS_W::new(self)
458 }
459 #[doc = "Bit 2 - Multi-Processor Mode (Valid only in asynchronous mode)"]
460 #[inline(always)]
461 #[must_use]
462 pub fn mp(&mut self) -> MP_W<2> {
463 MP_W::new(self)
464 }
465 #[doc = "Bit 3 - Stop Bit Length (Valid only in asynchronous mode)"]
466 #[inline(always)]
467 #[must_use]
468 pub fn stop(&mut self) -> STOP_W<3> {
469 STOP_W::new(self)
470 }
471 #[doc = "Bit 4 - Parity Mode (Valid only when the PE bit is 1)"]
472 #[inline(always)]
473 #[must_use]
474 pub fn pm(&mut self) -> PM_W<4> {
475 PM_W::new(self)
476 }
477 #[doc = "Bit 5 - Parity Enable (Valid only in asynchronous mode)"]
478 #[inline(always)]
479 #[must_use]
480 pub fn pe(&mut self) -> PE_W<5> {
481 PE_W::new(self)
482 }
483 #[doc = "Bit 6 - Character Length (Valid only in asynchronous mode)"]
484 #[inline(always)]
485 #[must_use]
486 pub fn chr(&mut self) -> CHR_W<6> {
487 CHR_W::new(self)
488 }
489 #[doc = "Bit 7 - Communications Mode"]
490 #[inline(always)]
491 #[must_use]
492 pub fn cm(&mut self) -> CM_W<7> {
493 CM_W::new(self)
494 }
495 #[doc = "Writes raw bits to the register."]
496 #[inline(always)]
497 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
498 self.0.bits(bits);
499 self
500 }
501}
502#[doc = "Serial Mode Register (SCMR.SMIF = 0)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smr](index.html) module"]
503pub struct SMR_SPEC;
504impl crate::RegisterSpec for SMR_SPEC {
505 type Ux = u8;
506}
507#[doc = "`read()` method returns [smr::R](R) reader structure"]
508impl crate::Readable for SMR_SPEC {
509 type Reader = R;
510}
511#[doc = "`write(|w| ..)` method takes [smr::W](W) writer structure"]
512impl crate::Writable for SMR_SPEC {
513 type Writer = W;
514 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
515 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
516}
517#[doc = "`reset()` method sets SMR to value 0"]
518impl crate::Resettable for SMR_SPEC {
519 const RESET_VALUE: Self::Ux = 0;
520}