ra6e1/sci3/
rdrhl_man.rs

1#[doc = "Register `RDRHL_MAN` reader"]
2pub struct R(crate::R<RDRHL_MAN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RDRHL_MAN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RDRHL_MAN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RDRHL_MAN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `RDAT` reader - Serial receive data"]
17pub type RDAT_R = crate::FieldReader<u16, u16>;
18#[doc = "Field `MPB` reader - Multi-processor bit"]
19pub type MPB_R = crate::BitReader<MPB_A>;
20#[doc = "Multi-processor bit\n\nValue on reset: 0"]
21#[derive(Clone, Copy, Debug, PartialEq, Eq)]
22pub enum MPB_A {
23    #[doc = "0: Data transmission cycles"]
24    _0 = 0,
25    #[doc = "1: ID transmission cycles"]
26    _1 = 1,
27}
28impl From<MPB_A> for bool {
29    #[inline(always)]
30    fn from(variant: MPB_A) -> Self {
31        variant as u8 != 0
32    }
33}
34impl MPB_R {
35    #[doc = "Get enumerated values variant"]
36    #[inline(always)]
37    pub fn variant(&self) -> MPB_A {
38        match self.bits {
39            false => MPB_A::_0,
40            true => MPB_A::_1,
41        }
42    }
43    #[doc = "Checks if the value of the field is `_0`"]
44    #[inline(always)]
45    pub fn is_0(&self) -> bool {
46        *self == MPB_A::_0
47    }
48    #[doc = "Checks if the value of the field is `_1`"]
49    #[inline(always)]
50    pub fn is_1(&self) -> bool {
51        *self == MPB_A::_1
52    }
53}
54#[doc = "Field `RSYNC` reader - Receive SYNC data bit"]
55pub type RSYNC_R = crate::BitReader<RSYNC_A>;
56#[doc = "Receive SYNC data bit\n\nValue on reset: 0"]
57#[derive(Clone, Copy, Debug, PartialEq, Eq)]
58pub enum RSYNC_A {
59    #[doc = "0: The received the Start Bit is DATA SYNC"]
60    _0 = 0,
61    #[doc = "1: The received the Start Bit is COMMAND SYNC"]
62    _1 = 1,
63}
64impl From<RSYNC_A> for bool {
65    #[inline(always)]
66    fn from(variant: RSYNC_A) -> Self {
67        variant as u8 != 0
68    }
69}
70impl RSYNC_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> RSYNC_A {
74        match self.bits {
75            false => RSYNC_A::_0,
76            true => RSYNC_A::_1,
77        }
78    }
79    #[doc = "Checks if the value of the field is `_0`"]
80    #[inline(always)]
81    pub fn is_0(&self) -> bool {
82        *self == RSYNC_A::_0
83    }
84    #[doc = "Checks if the value of the field is `_1`"]
85    #[inline(always)]
86    pub fn is_1(&self) -> bool {
87        *self == RSYNC_A::_1
88    }
89}
90impl R {
91    #[doc = "Bits 0:8 - Serial receive data"]
92    #[inline(always)]
93    pub fn rdat(&self) -> RDAT_R {
94        RDAT_R::new(self.bits & 0x01ff)
95    }
96    #[doc = "Bit 9 - Multi-processor bit"]
97    #[inline(always)]
98    pub fn mpb(&self) -> MPB_R {
99        MPB_R::new(((self.bits >> 9) & 1) != 0)
100    }
101    #[doc = "Bit 12 - Receive SYNC data bit"]
102    #[inline(always)]
103    pub fn rsync(&self) -> RSYNC_R {
104        RSYNC_R::new(((self.bits >> 12) & 1) != 0)
105    }
106}
107#[doc = "Receive Data Register for Manchester mode (MMR.MANEN = 1)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdrhl_man](index.html) module"]
108pub struct RDRHL_MAN_SPEC;
109impl crate::RegisterSpec for RDRHL_MAN_SPEC {
110    type Ux = u16;
111}
112#[doc = "`read()` method returns [rdrhl_man::R](R) reader structure"]
113impl crate::Readable for RDRHL_MAN_SPEC {
114    type Reader = R;
115}
116#[doc = "`reset()` method sets RDRHL_MAN to value 0"]
117impl crate::Resettable for RDRHL_MAN_SPEC {
118    const RESET_VALUE: Self::Ux = 0;
119}
ra6e1/sci3/rdrhl_man.rs

ra6e1/sci3/
rdrhl_man.rs
