1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved_0_smr: [u8; 0x01],
5 #[doc = "0x01 - Bit Rate Register"]
6 pub brr: BRR,
7 _reserved_2_scr: [u8; 0x01],
8 #[doc = "0x03 - Transmit Data Register"]
9 pub tdr: TDR,
10 _reserved_4_ssr: [u8; 0x01],
11 #[doc = "0x05 - Receive Data Register"]
12 pub rdr: RDR,
13 #[doc = "0x06 - Smart Card Mode Register"]
14 pub scmr: SCMR,
15 #[doc = "0x07 - Serial Extended Mode Register"]
16 pub semr: SEMR,
17 #[doc = "0x08 - Noise Filter Setting Register"]
18 pub snfr: SNFR,
19 #[doc = "0x09 - IIC Mode Register 1"]
20 pub simr1: SIMR1,
21 #[doc = "0x0a - IIC Mode Register 2"]
22 pub simr2: SIMR2,
23 #[doc = "0x0b - IIC Mode Register 3"]
24 pub simr3: SIMR3,
25 #[doc = "0x0c - IIC Status Register"]
26 pub sisr: SISR,
27 #[doc = "0x0d - SPI Mode Register"]
28 pub spmr: SPMR,
29 _reserved_14_ftdrh: [u8; 0x02],
30 _reserved_15_frdrh: [u8; 0x02],
31 #[doc = "0x12 - Modulation Duty Register"]
32 pub mddr: MDDR,
33 #[doc = "0x13 - Data Compare Match Control Register"]
34 pub dccr: DCCR,
35 #[doc = "0x14 - FIFO Control Register"]
36 pub fcr: FCR,
37 #[doc = "0x16 - FIFO Data Count Register"]
38 pub fdr: FDR,
39 #[doc = "0x18 - Line Status Register"]
40 pub lsr: LSR,
41 #[doc = "0x1a - Compare Match Data Register"]
42 pub cdr: CDR,
43 #[doc = "0x1c - Serial Port Register"]
44 pub sptr: SPTR,
45 #[doc = "0x1d - Adjustment Communication Timing Register"]
46 pub actr: ACTR,
47 _reserved24: [u8; 0x02],
48 _reserved_24_mmr: [u8; 0x01],
49 #[doc = "0x21 - Control Register 0"]
50 pub cr0: CR0,
51 _reserved_26_cr1: [u8; 0x01],
52 _reserved_27_cr2: [u8; 0x01],
53 _reserved_28_cr3: [u8; 0x01],
54 _reserved_29_pcr: [u8; 0x01],
55 #[doc = "0x26 - Interrupt Control Register"]
56 pub icr: ICR,
57 #[doc = "0x27 - Status Register"]
58 pub str: STR,
59 #[doc = "0x28 - Status Clear Register"]
60 pub stcr: STCR,
61 #[doc = "0x29 - Control Field 0 Data Register"]
62 pub cf0dr: CF0DR,
63 #[doc = "0x2a - Control Field 0 Compare Enable Register"]
64 pub cf0cr: CF0CR,
65 #[doc = "0x2b - Control Field 0 Receive Data Register"]
66 pub cf0rr: CF0RR,
67 #[doc = "0x2c - Primary Control Field 1 Data Register"]
68 pub pcf1dr: PCF1DR,
69 #[doc = "0x2d - Secondary Control Field 1 Data Register"]
70 pub scf1dr: SCF1DR,
71 #[doc = "0x2e - Control Field 1 Compare Enable Register"]
72 pub cf1cr: CF1CR,
73 #[doc = "0x2f - Control Field 1 Receive Data Register"]
74 pub cf1rr: CF1RR,
75 #[doc = "0x30 - Timer Control Register"]
76 pub tcr: TCR,
77 #[doc = "0x31 - Timer Mode Register"]
78 pub tmr: TMR,
79 #[doc = "0x32 - Timer Prescaler Register"]
80 pub tpre: TPRE,
81 #[doc = "0x33 - Timer Count Register"]
82 pub tcnt: TCNT,
83}
84impl RegisterBlock {
85 #[doc = "0x00 - Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)"]
86 #[inline(always)]
87 pub const fn smr_smci(&self) -> &SMR_SMCI {
88 unsafe { &*(self as *const Self).cast::<u8>().add(0usize).cast() }
89 }
90 #[doc = "0x00 - Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"]
91 #[inline(always)]
92 pub const fn smr(&self) -> &SMR {
93 unsafe { &*(self as *const Self).cast::<u8>().add(0usize).cast() }
94 }
95 #[doc = "0x02 - Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)"]
96 #[inline(always)]
97 pub const fn scr_smci(&self) -> &SCR_SMCI {
98 unsafe { &*(self as *const Self).cast::<u8>().add(2usize).cast() }
99 }
100 #[doc = "0x02 - Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"]
101 #[inline(always)]
102 pub const fn scr(&self) -> &SCR {
103 unsafe { &*(self as *const Self).cast::<u8>().add(2usize).cast() }
104 }
105 #[doc = "0x04 - Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1, and MMR.MANEN = 0)"]
106 #[inline(always)]
107 pub const fn ssr_smci(&self) -> &SSR_SMCI {
108 unsafe { &*(self as *const Self).cast::<u8>().add(4usize).cast() }
109 }
110 #[doc = "0x04 - Serial Status Register for Manchester Mode (SCMR.SMIF = 0, and MMR.MANEN = 1)"]
111 #[inline(always)]
112 pub const fn ssr_manc(&self) -> &SSR_MANC {
113 unsafe { &*(self as *const Self).cast::<u8>().add(4usize).cast() }
114 }
115 #[doc = "0x04 - Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1, and MMR.MANEN = 0)"]
116 #[inline(always)]
117 pub const fn ssr_fifo(&self) -> &SSR_FIFO {
118 unsafe { &*(self as *const Self).cast::<u8>().add(4usize).cast() }
119 }
120 #[doc = "0x04 - Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0, and MMR.MANEN = 0)"]
121 #[inline(always)]
122 pub const fn ssr(&self) -> &SSR {
123 unsafe { &*(self as *const Self).cast::<u8>().add(4usize).cast() }
124 }
125 #[doc = "0x0e - Transmit FIFO Data Register"]
126 #[inline(always)]
127 pub const fn ftdrh(&self) -> &FTDRH {
128 unsafe { &*(self as *const Self).cast::<u8>().add(14usize).cast() }
129 }
130 #[doc = "0x0e - Transmit Data Register for Non-Manchester mode (MMR.MANEN = 0)"]
131 #[inline(always)]
132 pub const fn tdrhl(&self) -> &TDRHL {
133 unsafe { &*(self as *const Self).cast::<u8>().add(14usize).cast() }
134 }
135 #[doc = "0x0e - Transmit FIFO Data Register"]
136 #[inline(always)]
137 pub const fn ftdrhl(&self) -> &FTDRHL {
138 unsafe { &*(self as *const Self).cast::<u8>().add(14usize).cast() }
139 }
140 #[doc = "0x0f - Transmit FIFO Data Register"]
141 #[inline(always)]
142 pub const fn ftdrl(&self) -> &FTDRL {
143 unsafe { &*(self as *const Self).cast::<u8>().add(15usize).cast() }
144 }
145 #[doc = "0x10 - Receive FIFO Data Register"]
146 #[inline(always)]
147 pub const fn frdrh(&self) -> &FRDRH {
148 unsafe { &*(self as *const Self).cast::<u8>().add(16usize).cast() }
149 }
150 #[doc = "0x10 - Receive Data Register for Non-Manchester mode (MMR.MANEN = 0)"]
151 #[inline(always)]
152 pub const fn rdrhl(&self) -> &RDRHL {
153 unsafe { &*(self as *const Self).cast::<u8>().add(16usize).cast() }
154 }
155 #[doc = "0x10 - Receive FIFO Data Register"]
156 #[inline(always)]
157 pub const fn frdrhl(&self) -> &FRDRHL {
158 unsafe { &*(self as *const Self).cast::<u8>().add(16usize).cast() }
159 }
160 #[doc = "0x11 - Receive FIFO Data Register"]
161 #[inline(always)]
162 pub const fn frdrl(&self) -> &FRDRL {
163 unsafe { &*(self as *const Self).cast::<u8>().add(17usize).cast() }
164 }
165 #[doc = "0x20 - Manchester Mode Register"]
166 #[inline(always)]
167 pub const fn mmr(&self) -> &MMR {
168 unsafe { &*(self as *const Self).cast::<u8>().add(32usize).cast() }
169 }
170 #[doc = "0x20 - Extended Serial Module Enable Register"]
171 #[inline(always)]
172 pub const fn esmer(&self) -> &ESMER {
173 unsafe { &*(self as *const Self).cast::<u8>().add(32usize).cast() }
174 }
175 #[doc = "0x22 - Transmit Manchester Preface Setting Register"]
176 #[inline(always)]
177 pub const fn tmpr(&self) -> &TMPR {
178 unsafe { &*(self as *const Self).cast::<u8>().add(34usize).cast() }
179 }
180 #[doc = "0x22 - Control Register 1"]
181 #[inline(always)]
182 pub const fn cr1(&self) -> &CR1 {
183 unsafe { &*(self as *const Self).cast::<u8>().add(34usize).cast() }
184 }
185 #[doc = "0x23 - Receive Manchester Preface Setting Register"]
186 #[inline(always)]
187 pub const fn rmpr(&self) -> &RMPR {
188 unsafe { &*(self as *const Self).cast::<u8>().add(35usize).cast() }
189 }
190 #[doc = "0x23 - Control Register 2"]
191 #[inline(always)]
192 pub const fn cr2(&self) -> &CR2 {
193 unsafe { &*(self as *const Self).cast::<u8>().add(35usize).cast() }
194 }
195 #[doc = "0x24 - Manchester Extended Error Status Register"]
196 #[inline(always)]
197 pub const fn mesr(&self) -> &MESR {
198 unsafe { &*(self as *const Self).cast::<u8>().add(36usize).cast() }
199 }
200 #[doc = "0x24 - Control Register 3"]
201 #[inline(always)]
202 pub const fn cr3(&self) -> &CR3 {
203 unsafe { &*(self as *const Self).cast::<u8>().add(36usize).cast() }
204 }
205 #[doc = "0x25 - Port Control Register"]
206 #[inline(always)]
207 pub const fn pcr(&self) -> &PCR {
208 unsafe { &*(self as *const Self).cast::<u8>().add(37usize).cast() }
209 }
210 #[doc = "0x25 - Manchester Extended Error Control Register"]
211 #[inline(always)]
212 pub const fn mecr(&self) -> &MECR {
213 unsafe { &*(self as *const Self).cast::<u8>().add(37usize).cast() }
214 }
215}
216#[doc = "SMR (rw) register accessor: an alias for `Reg<SMR_SPEC>`"]
217pub type SMR = crate::Reg<smr::SMR_SPEC>;
218#[doc = "Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"]
219pub mod smr;
220#[doc = "SMR_SMCI (rw) register accessor: an alias for `Reg<SMR_SMCI_SPEC>`"]
221pub type SMR_SMCI = crate::Reg<smr_smci::SMR_SMCI_SPEC>;
222#[doc = "Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)"]
223pub mod smr_smci;
224#[doc = "BRR (rw) register accessor: an alias for `Reg<BRR_SPEC>`"]
225pub type BRR = crate::Reg<brr::BRR_SPEC>;
226#[doc = "Bit Rate Register"]
227pub mod brr;
228#[doc = "SCR (rw) register accessor: an alias for `Reg<SCR_SPEC>`"]
229pub type SCR = crate::Reg<scr::SCR_SPEC>;
230#[doc = "Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"]
231pub mod scr;
232#[doc = "SCR_SMCI (rw) register accessor: an alias for `Reg<SCR_SMCI_SPEC>`"]
233pub type SCR_SMCI = crate::Reg<scr_smci::SCR_SMCI_SPEC>;
234#[doc = "Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)"]
235pub mod scr_smci;
236#[doc = "TDR (rw) register accessor: an alias for `Reg<TDR_SPEC>`"]
237pub type TDR = crate::Reg<tdr::TDR_SPEC>;
238#[doc = "Transmit Data Register"]
239pub mod tdr;
240#[doc = "SSR (rw) register accessor: an alias for `Reg<SSR_SPEC>`"]
241pub type SSR = crate::Reg<ssr::SSR_SPEC>;
242#[doc = "Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0, and MMR.MANEN = 0)"]
243pub mod ssr;
244#[doc = "SSR_FIFO (rw) register accessor: an alias for `Reg<SSR_FIFO_SPEC>`"]
245pub type SSR_FIFO = crate::Reg<ssr_fifo::SSR_FIFO_SPEC>;
246#[doc = "Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1, and MMR.MANEN = 0)"]
247pub mod ssr_fifo;
248#[doc = "SSR_MANC (rw) register accessor: an alias for `Reg<SSR_MANC_SPEC>`"]
249pub type SSR_MANC = crate::Reg<ssr_manc::SSR_MANC_SPEC>;
250#[doc = "Serial Status Register for Manchester Mode (SCMR.SMIF = 0, and MMR.MANEN = 1)"]
251pub mod ssr_manc;
252#[doc = "SSR_SMCI (rw) register accessor: an alias for `Reg<SSR_SMCI_SPEC>`"]
253pub type SSR_SMCI = crate::Reg<ssr_smci::SSR_SMCI_SPEC>;
254#[doc = "Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1, and MMR.MANEN = 0)"]
255pub mod ssr_smci;
256#[doc = "RDR (r) register accessor: an alias for `Reg<RDR_SPEC>`"]
257pub type RDR = crate::Reg<rdr::RDR_SPEC>;
258#[doc = "Receive Data Register"]
259pub mod rdr;
260#[doc = "SCMR (rw) register accessor: an alias for `Reg<SCMR_SPEC>`"]
261pub type SCMR = crate::Reg<scmr::SCMR_SPEC>;
262#[doc = "Smart Card Mode Register"]
263pub mod scmr;
264#[doc = "SEMR (rw) register accessor: an alias for `Reg<SEMR_SPEC>`"]
265pub type SEMR = crate::Reg<semr::SEMR_SPEC>;
266#[doc = "Serial Extended Mode Register"]
267pub mod semr;
268#[doc = "SNFR (rw) register accessor: an alias for `Reg<SNFR_SPEC>`"]
269pub type SNFR = crate::Reg<snfr::SNFR_SPEC>;
270#[doc = "Noise Filter Setting Register"]
271pub mod snfr;
272#[doc = "SIMR1 (rw) register accessor: an alias for `Reg<SIMR1_SPEC>`"]
273pub type SIMR1 = crate::Reg<simr1::SIMR1_SPEC>;
274#[doc = "IIC Mode Register 1"]
275pub mod simr1;
276#[doc = "SIMR2 (rw) register accessor: an alias for `Reg<SIMR2_SPEC>`"]
277pub type SIMR2 = crate::Reg<simr2::SIMR2_SPEC>;
278#[doc = "IIC Mode Register 2"]
279pub mod simr2;
280#[doc = "SIMR3 (rw) register accessor: an alias for `Reg<SIMR3_SPEC>`"]
281pub type SIMR3 = crate::Reg<simr3::SIMR3_SPEC>;
282#[doc = "IIC Mode Register 3"]
283pub mod simr3;
284#[doc = "SISR (r) register accessor: an alias for `Reg<SISR_SPEC>`"]
285pub type SISR = crate::Reg<sisr::SISR_SPEC>;
286#[doc = "IIC Status Register"]
287pub mod sisr;
288#[doc = "SPMR (rw) register accessor: an alias for `Reg<SPMR_SPEC>`"]
289pub type SPMR = crate::Reg<spmr::SPMR_SPEC>;
290#[doc = "SPI Mode Register"]
291pub mod spmr;
292#[doc = "FTDRHL (w) register accessor: an alias for `Reg<FTDRHL_SPEC>`"]
293pub type FTDRHL = crate::Reg<ftdrhl::FTDRHL_SPEC>;
294#[doc = "Transmit FIFO Data Register"]
295pub mod ftdrhl;
296#[doc = "TDRHL (rw) register accessor: an alias for `Reg<TDRHL_SPEC>`"]
297pub type TDRHL = crate::Reg<tdrhl::TDRHL_SPEC>;
298#[doc = "Transmit Data Register for Non-Manchester mode (MMR.MANEN = 0)"]
299pub mod tdrhl;
300#[doc = "FTDRH (w) register accessor: an alias for `Reg<FTDRH_SPEC>`"]
301pub type FTDRH = crate::Reg<ftdrh::FTDRH_SPEC>;
302#[doc = "Transmit FIFO Data Register"]
303pub mod ftdrh;
304#[doc = "FTDRL (w) register accessor: an alias for `Reg<FTDRL_SPEC>`"]
305pub type FTDRL = crate::Reg<ftdrl::FTDRL_SPEC>;
306#[doc = "Transmit FIFO Data Register"]
307pub mod ftdrl;
308#[doc = "FRDRHL (r) register accessor: an alias for `Reg<FRDRHL_SPEC>`"]
309pub type FRDRHL = crate::Reg<frdrhl::FRDRHL_SPEC>;
310#[doc = "Receive FIFO Data Register"]
311pub mod frdrhl;
312#[doc = "RDRHL (r) register accessor: an alias for `Reg<RDRHL_SPEC>`"]
313pub type RDRHL = crate::Reg<rdrhl::RDRHL_SPEC>;
314#[doc = "Receive Data Register for Non-Manchester mode (MMR.MANEN = 0)"]
315pub mod rdrhl;
316#[doc = "FRDRH (r) register accessor: an alias for `Reg<FRDRH_SPEC>`"]
317pub type FRDRH = crate::Reg<frdrh::FRDRH_SPEC>;
318#[doc = "Receive FIFO Data Register"]
319pub mod frdrh;
320#[doc = "FRDRL (r) register accessor: an alias for `Reg<FRDRL_SPEC>`"]
321pub type FRDRL = crate::Reg<frdrl::FRDRL_SPEC>;
322#[doc = "Receive FIFO Data Register"]
323pub mod frdrl;
324#[doc = "MDDR (rw) register accessor: an alias for `Reg<MDDR_SPEC>`"]
325pub type MDDR = crate::Reg<mddr::MDDR_SPEC>;
326#[doc = "Modulation Duty Register"]
327pub mod mddr;
328#[doc = "DCCR (rw) register accessor: an alias for `Reg<DCCR_SPEC>`"]
329pub type DCCR = crate::Reg<dccr::DCCR_SPEC>;
330#[doc = "Data Compare Match Control Register"]
331pub mod dccr;
332#[doc = "FCR (rw) register accessor: an alias for `Reg<FCR_SPEC>`"]
333pub type FCR = crate::Reg<fcr::FCR_SPEC>;
334#[doc = "FIFO Control Register"]
335pub mod fcr;
336#[doc = "FDR (r) register accessor: an alias for `Reg<FDR_SPEC>`"]
337pub type FDR = crate::Reg<fdr::FDR_SPEC>;
338#[doc = "FIFO Data Count Register"]
339pub mod fdr;
340#[doc = "LSR (r) register accessor: an alias for `Reg<LSR_SPEC>`"]
341pub type LSR = crate::Reg<lsr::LSR_SPEC>;
342#[doc = "Line Status Register"]
343pub mod lsr;
344#[doc = "CDR (rw) register accessor: an alias for `Reg<CDR_SPEC>`"]
345pub type CDR = crate::Reg<cdr::CDR_SPEC>;
346#[doc = "Compare Match Data Register"]
347pub mod cdr;
348#[doc = "SPTR (rw) register accessor: an alias for `Reg<SPTR_SPEC>`"]
349pub type SPTR = crate::Reg<sptr::SPTR_SPEC>;
350#[doc = "Serial Port Register"]
351pub mod sptr;
352#[doc = "ACTR (rw) register accessor: an alias for `Reg<ACTR_SPEC>`"]
353pub type ACTR = crate::Reg<actr::ACTR_SPEC>;
354#[doc = "Adjustment Communication Timing Register"]
355pub mod actr;
356#[doc = "ESMER (rw) register accessor: an alias for `Reg<ESMER_SPEC>`"]
357pub type ESMER = crate::Reg<esmer::ESMER_SPEC>;
358#[doc = "Extended Serial Module Enable Register"]
359pub mod esmer;
360#[doc = "MMR (rw) register accessor: an alias for `Reg<MMR_SPEC>`"]
361pub type MMR = crate::Reg<mmr::MMR_SPEC>;
362#[doc = "Manchester Mode Register"]
363pub mod mmr;
364#[doc = "CR0 (rw) register accessor: an alias for `Reg<CR0_SPEC>`"]
365pub type CR0 = crate::Reg<cr0::CR0_SPEC>;
366#[doc = "Control Register 0"]
367pub mod cr0;
368#[doc = "CR1 (rw) register accessor: an alias for `Reg<CR1_SPEC>`"]
369pub type CR1 = crate::Reg<cr1::CR1_SPEC>;
370#[doc = "Control Register 1"]
371pub mod cr1;
372#[doc = "TMPR (rw) register accessor: an alias for `Reg<TMPR_SPEC>`"]
373pub type TMPR = crate::Reg<tmpr::TMPR_SPEC>;
374#[doc = "Transmit Manchester Preface Setting Register"]
375pub mod tmpr;
376#[doc = "CR2 (rw) register accessor: an alias for `Reg<CR2_SPEC>`"]
377pub type CR2 = crate::Reg<cr2::CR2_SPEC>;
378#[doc = "Control Register 2"]
379pub mod cr2;
380#[doc = "RMPR (rw) register accessor: an alias for `Reg<RMPR_SPEC>`"]
381pub type RMPR = crate::Reg<rmpr::RMPR_SPEC>;
382#[doc = "Receive Manchester Preface Setting Register"]
383pub mod rmpr;
384#[doc = "CR3 (rw) register accessor: an alias for `Reg<CR3_SPEC>`"]
385pub type CR3 = crate::Reg<cr3::CR3_SPEC>;
386#[doc = "Control Register 3"]
387pub mod cr3;
388#[doc = "MESR (rw) register accessor: an alias for `Reg<MESR_SPEC>`"]
389pub type MESR = crate::Reg<mesr::MESR_SPEC>;
390#[doc = "Manchester Extended Error Status Register"]
391pub mod mesr;
392#[doc = "MECR (rw) register accessor: an alias for `Reg<MECR_SPEC>`"]
393pub type MECR = crate::Reg<mecr::MECR_SPEC>;
394#[doc = "Manchester Extended Error Control Register"]
395pub mod mecr;
396#[doc = "PCR (rw) register accessor: an alias for `Reg<PCR_SPEC>`"]
397pub type PCR = crate::Reg<pcr::PCR_SPEC>;
398#[doc = "Port Control Register"]
399pub mod pcr;
400#[doc = "ICR (rw) register accessor: an alias for `Reg<ICR_SPEC>`"]
401pub type ICR = crate::Reg<icr::ICR_SPEC>;
402#[doc = "Interrupt Control Register"]
403pub mod icr;
404#[doc = "STR (r) register accessor: an alias for `Reg<STR_SPEC>`"]
405pub type STR = crate::Reg<str::STR_SPEC>;
406#[doc = "Status Register"]
407pub mod str;
408#[doc = "STCR (rw) register accessor: an alias for `Reg<STCR_SPEC>`"]
409pub type STCR = crate::Reg<stcr::STCR_SPEC>;
410#[doc = "Status Clear Register"]
411pub mod stcr;
412#[doc = "CF0DR (rw) register accessor: an alias for `Reg<CF0DR_SPEC>`"]
413pub type CF0DR = crate::Reg<cf0dr::CF0DR_SPEC>;
414#[doc = "Control Field 0 Data Register"]
415pub mod cf0dr;
416#[doc = "CF0CR (rw) register accessor: an alias for `Reg<CF0CR_SPEC>`"]
417pub type CF0CR = crate::Reg<cf0cr::CF0CR_SPEC>;
418#[doc = "Control Field 0 Compare Enable Register"]
419pub mod cf0cr;
420#[doc = "CF0RR (rw) register accessor: an alias for `Reg<CF0RR_SPEC>`"]
421pub type CF0RR = crate::Reg<cf0rr::CF0RR_SPEC>;
422#[doc = "Control Field 0 Receive Data Register"]
423pub mod cf0rr;
424#[doc = "PCF1DR (rw) register accessor: an alias for `Reg<PCF1DR_SPEC>`"]
425pub type PCF1DR = crate::Reg<pcf1dr::PCF1DR_SPEC>;
426#[doc = "Primary Control Field 1 Data Register"]
427pub mod pcf1dr;
428#[doc = "SCF1DR (rw) register accessor: an alias for `Reg<SCF1DR_SPEC>`"]
429pub type SCF1DR = crate::Reg<scf1dr::SCF1DR_SPEC>;
430#[doc = "Secondary Control Field 1 Data Register"]
431pub mod scf1dr;
432#[doc = "CF1CR (rw) register accessor: an alias for `Reg<CF1CR_SPEC>`"]
433pub type CF1CR = crate::Reg<cf1cr::CF1CR_SPEC>;
434#[doc = "Control Field 1 Compare Enable Register"]
435pub mod cf1cr;
436#[doc = "CF1RR (rw) register accessor: an alias for `Reg<CF1RR_SPEC>`"]
437pub type CF1RR = crate::Reg<cf1rr::CF1RR_SPEC>;
438#[doc = "Control Field 1 Receive Data Register"]
439pub mod cf1rr;
440#[doc = "TCR (rw) register accessor: an alias for `Reg<TCR_SPEC>`"]
441pub type TCR = crate::Reg<tcr::TCR_SPEC>;
442#[doc = "Timer Control Register"]
443pub mod tcr;
444#[doc = "TMR (rw) register accessor: an alias for `Reg<TMR_SPEC>`"]
445pub type TMR = crate::Reg<tmr::TMR_SPEC>;
446#[doc = "Timer Mode Register"]
447pub mod tmr;
448#[doc = "TPRE (rw) register accessor: an alias for `Reg<TPRE_SPEC>`"]
449pub type TPRE = crate::Reg<tpre::TPRE_SPEC>;
450#[doc = "Timer Prescaler Register"]
451pub mod tpre;
452#[doc = "TCNT (rw) register accessor: an alias for `Reg<TCNT_SPEC>`"]
453pub type TCNT = crate::Reg<tcnt::TCNT_SPEC>;
454#[doc = "Timer Count Register"]
455pub mod tcnt;