1#[doc = "Register `CFIFOCTR` reader"]
2pub struct R(crate::R<CFIFOCTR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CFIFOCTR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CFIFOCTR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CFIFOCTR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CFIFOCTR` writer"]
17pub struct W(crate::W<CFIFOCTR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CFIFOCTR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CFIFOCTR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CFIFOCTR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `DTLN` reader - Receive Data Length"]
38pub type DTLN_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `FRDY` reader - FIFO Port Ready"]
40pub type FRDY_R = crate::BitReader<FRDY_A>;
41#[doc = "FIFO Port Ready\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum FRDY_A {
44 #[doc = "0: FIFO port access disabled"]
45 _0 = 0,
46 #[doc = "1: FIFO port access enabled"]
47 _1 = 1,
48}
49impl From<FRDY_A> for bool {
50 #[inline(always)]
51 fn from(variant: FRDY_A) -> Self {
52 variant as u8 != 0
53 }
54}
55impl FRDY_R {
56 #[doc = "Get enumerated values variant"]
57 #[inline(always)]
58 pub fn variant(&self) -> FRDY_A {
59 match self.bits {
60 false => FRDY_A::_0,
61 true => FRDY_A::_1,
62 }
63 }
64 #[doc = "Checks if the value of the field is `_0`"]
65 #[inline(always)]
66 pub fn is_0(&self) -> bool {
67 *self == FRDY_A::_0
68 }
69 #[doc = "Checks if the value of the field is `_1`"]
70 #[inline(always)]
71 pub fn is_1(&self) -> bool {
72 *self == FRDY_A::_1
73 }
74}
75#[doc = "CPU Buffer Clear\n\nValue on reset: 0"]
76#[derive(Clone, Copy, Debug, PartialEq, Eq)]
77pub enum BCLR_AW {
78 #[doc = "0: No operation"]
79 _0 = 0,
80 #[doc = "1: Clear FIFO buffer on the CPU side"]
81 _1 = 1,
82}
83impl From<BCLR_AW> for bool {
84 #[inline(always)]
85 fn from(variant: BCLR_AW) -> Self {
86 variant as u8 != 0
87 }
88}
89#[doc = "Field `BCLR` writer - CPU Buffer Clear"]
90pub type BCLR_W<'a, const O: u8> = crate::BitWriter<'a, u16, CFIFOCTR_SPEC, BCLR_AW, O>;
91impl<'a, const O: u8> BCLR_W<'a, O> {
92 #[doc = "No operation"]
93 #[inline(always)]
94 pub fn _0(self) -> &'a mut W {
95 self.variant(BCLR_AW::_0)
96 }
97 #[doc = "Clear FIFO buffer on the CPU side"]
98 #[inline(always)]
99 pub fn _1(self) -> &'a mut W {
100 self.variant(BCLR_AW::_1)
101 }
102}
103#[doc = "Field `BVAL` reader - Buffer Memory Valid Flag"]
104pub type BVAL_R = crate::BitReader<BVAL_A>;
105#[doc = "Buffer Memory Valid Flag\n\nValue on reset: 0"]
106#[derive(Clone, Copy, Debug, PartialEq, Eq)]
107pub enum BVAL_A {
108 #[doc = "0: Invalid (writing 0 has no effect)"]
109 _0 = 0,
110 #[doc = "1: Writing ended"]
111 _1 = 1,
112}
113impl From<BVAL_A> for bool {
114 #[inline(always)]
115 fn from(variant: BVAL_A) -> Self {
116 variant as u8 != 0
117 }
118}
119impl BVAL_R {
120 #[doc = "Get enumerated values variant"]
121 #[inline(always)]
122 pub fn variant(&self) -> BVAL_A {
123 match self.bits {
124 false => BVAL_A::_0,
125 true => BVAL_A::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline(always)]
130 pub fn is_0(&self) -> bool {
131 *self == BVAL_A::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline(always)]
135 pub fn is_1(&self) -> bool {
136 *self == BVAL_A::_1
137 }
138}
139#[doc = "Field `BVAL` writer - Buffer Memory Valid Flag"]
140pub type BVAL_W<'a, const O: u8> = crate::BitWriter<'a, u16, CFIFOCTR_SPEC, BVAL_A, O>;
141impl<'a, const O: u8> BVAL_W<'a, O> {
142 #[doc = "Invalid (writing 0 has no effect)"]
143 #[inline(always)]
144 pub fn _0(self) -> &'a mut W {
145 self.variant(BVAL_A::_0)
146 }
147 #[doc = "Writing ended"]
148 #[inline(always)]
149 pub fn _1(self) -> &'a mut W {
150 self.variant(BVAL_A::_1)
151 }
152}
153impl R {
154 #[doc = "Bits 0:8 - Receive Data Length"]
155 #[inline(always)]
156 pub fn dtln(&self) -> DTLN_R {
157 DTLN_R::new(self.bits & 0x01ff)
158 }
159 #[doc = "Bit 13 - FIFO Port Ready"]
160 #[inline(always)]
161 pub fn frdy(&self) -> FRDY_R {
162 FRDY_R::new(((self.bits >> 13) & 1) != 0)
163 }
164 #[doc = "Bit 15 - Buffer Memory Valid Flag"]
165 #[inline(always)]
166 pub fn bval(&self) -> BVAL_R {
167 BVAL_R::new(((self.bits >> 15) & 1) != 0)
168 }
169}
170impl W {
171 #[doc = "Bit 14 - CPU Buffer Clear"]
172 #[inline(always)]
173 #[must_use]
174 pub fn bclr(&mut self) -> BCLR_W<14> {
175 BCLR_W::new(self)
176 }
177 #[doc = "Bit 15 - Buffer Memory Valid Flag"]
178 #[inline(always)]
179 #[must_use]
180 pub fn bval(&mut self) -> BVAL_W<15> {
181 BVAL_W::new(self)
182 }
183 #[doc = "Writes raw bits to the register."]
184 #[inline(always)]
185 pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
186 self.0.bits(bits);
187 self
188 }
189}
190#[doc = "CFIFO Port Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfifoctr](index.html) module"]
191pub struct CFIFOCTR_SPEC;
192impl crate::RegisterSpec for CFIFOCTR_SPEC {
193 type Ux = u16;
194}
195#[doc = "`read()` method returns [cfifoctr::R](R) reader structure"]
196impl crate::Readable for CFIFOCTR_SPEC {
197 type Reader = R;
198}
199#[doc = "`write(|w| ..)` method takes [cfifoctr::W](W) writer structure"]
200impl crate::Writable for CFIFOCTR_SPEC {
201 type Writer = W;
202 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
203 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
204}
205#[doc = "`reset()` method sets CFIFOCTR to value 0"]
206impl crate::Resettable for CFIFOCTR_SPEC {
207 const RESET_VALUE: Self::Ux = 0;
208}