1#[doc = "Register `ELSEGR%s` reader"]
2pub struct R(crate::R<ELSEGR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<ELSEGR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<ELSEGR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<ELSEGR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `ELSEGR%s` writer"]
17pub struct W(crate::W<ELSEGR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<ELSEGR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<ELSEGR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<ELSEGR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Software Event Generation\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq, Eq)]
39pub enum SEG_AW {
40 #[doc = "0: Normal operation"]
41 _0 = 0,
42 #[doc = "1: Software event is generated."]
43 _1 = 1,
44}
45impl From<SEG_AW> for bool {
46 #[inline(always)]
47 fn from(variant: SEG_AW) -> Self {
48 variant as u8 != 0
49 }
50}
51#[doc = "Field `SEG` writer - Software Event Generation"]
52pub type SEG_W<'a, const O: u8> = crate::BitWriter<'a, u8, ELSEGR_SPEC, SEG_AW, O>;
53impl<'a, const O: u8> SEG_W<'a, O> {
54 #[doc = "Normal operation"]
55 #[inline(always)]
56 pub fn _0(self) -> &'a mut W {
57 self.variant(SEG_AW::_0)
58 }
59 #[doc = "Software event is generated."]
60 #[inline(always)]
61 pub fn _1(self) -> &'a mut W {
62 self.variant(SEG_AW::_1)
63 }
64}
65#[doc = "Field `WE` reader - SEG Bit Write Enable"]
66pub type WE_R = crate::BitReader<WE_A>;
67#[doc = "SEG Bit Write Enable\n\nValue on reset: 0"]
68#[derive(Clone, Copy, Debug, PartialEq, Eq)]
69pub enum WE_A {
70 #[doc = "0: Write to SEG bit disabled."]
71 _0 = 0,
72 #[doc = "1: Write to SEG bit enabled."]
73 _1 = 1,
74}
75impl From<WE_A> for bool {
76 #[inline(always)]
77 fn from(variant: WE_A) -> Self {
78 variant as u8 != 0
79 }
80}
81impl WE_R {
82 #[doc = "Get enumerated values variant"]
83 #[inline(always)]
84 pub fn variant(&self) -> WE_A {
85 match self.bits {
86 false => WE_A::_0,
87 true => WE_A::_1,
88 }
89 }
90 #[doc = "Checks if the value of the field is `_0`"]
91 #[inline(always)]
92 pub fn is_0(&self) -> bool {
93 *self == WE_A::_0
94 }
95 #[doc = "Checks if the value of the field is `_1`"]
96 #[inline(always)]
97 pub fn is_1(&self) -> bool {
98 *self == WE_A::_1
99 }
100}
101#[doc = "Field `WE` writer - SEG Bit Write Enable"]
102pub type WE_W<'a, const O: u8> = crate::BitWriter<'a, u8, ELSEGR_SPEC, WE_A, O>;
103impl<'a, const O: u8> WE_W<'a, O> {
104 #[doc = "Write to SEG bit disabled."]
105 #[inline(always)]
106 pub fn _0(self) -> &'a mut W {
107 self.variant(WE_A::_0)
108 }
109 #[doc = "Write to SEG bit enabled."]
110 #[inline(always)]
111 pub fn _1(self) -> &'a mut W {
112 self.variant(WE_A::_1)
113 }
114}
115#[doc = "ELSEGR Register Write Disable\n\nValue on reset: 1"]
116#[derive(Clone, Copy, Debug, PartialEq, Eq)]
117pub enum WI_AW {
118 #[doc = "0: Write to ELSEGR register enabled."]
119 _0 = 0,
120 #[doc = "1: Write to ELSEGR register disabled."]
121 _1 = 1,
122}
123impl From<WI_AW> for bool {
124 #[inline(always)]
125 fn from(variant: WI_AW) -> Self {
126 variant as u8 != 0
127 }
128}
129#[doc = "Field `WI` writer - ELSEGR Register Write Disable"]
130pub type WI_W<'a, const O: u8> = crate::BitWriter<'a, u8, ELSEGR_SPEC, WI_AW, O>;
131impl<'a, const O: u8> WI_W<'a, O> {
132 #[doc = "Write to ELSEGR register enabled."]
133 #[inline(always)]
134 pub fn _0(self) -> &'a mut W {
135 self.variant(WI_AW::_0)
136 }
137 #[doc = "Write to ELSEGR register disabled."]
138 #[inline(always)]
139 pub fn _1(self) -> &'a mut W {
140 self.variant(WI_AW::_1)
141 }
142}
143impl R {
144 #[doc = "Bit 6 - SEG Bit Write Enable"]
145 #[inline(always)]
146 pub fn we(&self) -> WE_R {
147 WE_R::new(((self.bits >> 6) & 1) != 0)
148 }
149}
150impl W {
151 #[doc = "Bit 0 - Software Event Generation"]
152 #[inline(always)]
153 #[must_use]
154 pub fn seg(&mut self) -> SEG_W<0> {
155 SEG_W::new(self)
156 }
157 #[doc = "Bit 6 - SEG Bit Write Enable"]
158 #[inline(always)]
159 #[must_use]
160 pub fn we(&mut self) -> WE_W<6> {
161 WE_W::new(self)
162 }
163 #[doc = "Bit 7 - ELSEGR Register Write Disable"]
164 #[inline(always)]
165 #[must_use]
166 pub fn wi(&mut self) -> WI_W<7> {
167 WI_W::new(self)
168 }
169 #[doc = "Writes raw bits to the register."]
170 #[inline(always)]
171 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
172 self.0.bits(bits);
173 self
174 }
175}
176#[doc = "Event Link Software Event Generation Register %s\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [elsegr](index.html) module"]
177pub struct ELSEGR_SPEC;
178impl crate::RegisterSpec for ELSEGR_SPEC {
179 type Ux = u8;
180}
181#[doc = "`read()` method returns [elsegr::R](R) reader structure"]
182impl crate::Readable for ELSEGR_SPEC {
183 type Reader = R;
184}
185#[doc = "`write(|w| ..)` method takes [elsegr::W](W) writer structure"]
186impl crate::Writable for ELSEGR_SPEC {
187 type Writer = W;
188 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
189 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
190}
191#[doc = "`reset()` method sets ELSEGR%s to value 0x80"]
192impl crate::Resettable for ELSEGR_SPEC {
193 const RESET_VALUE: Self::Ux = 0x80;
194}