ra4w1/can0/
mb_d4.rs

1#[doc = "Register `MB%s_D4` reader"]
2pub struct R(crate::R<MB_D4_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MB_D4_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MB_D4_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MB_D4_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MB%s_D4` writer"]
17pub struct W(crate::W<MB_D4_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MB_D4_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MB_D4_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MB_D4_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DATA4` reader - Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7."]
38pub type DATA4_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `DATA4` writer - Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7."]
40pub type DATA4_W<'a, const O: u8> = crate::FieldWriter<'a, u8, MB_D4_SPEC, u8, u8, 8, O>;
41impl R {
42    #[doc = "Bits 0:7 - Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7."]
43    #[inline(always)]
44    pub fn data4(&self) -> DATA4_R {
45        DATA4_R::new(self.bits)
46    }
47}
48impl W {
49    #[doc = "Bits 0:7 - Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7."]
50    #[inline(always)]
51    #[must_use]
52    pub fn data4(&mut self) -> DATA4_W<0> {
53        DATA4_W::new(self)
54    }
55    #[doc = "Writes raw bits to the register."]
56    #[inline(always)]
57    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
58        self.0.bits(bits);
59        self
60    }
61}
62#[doc = "Mailbox Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mb_d4](index.html) module"]
63pub struct MB_D4_SPEC;
64impl crate::RegisterSpec for MB_D4_SPEC {
65    type Ux = u8;
66}
67#[doc = "`read()` method returns [mb_d4::R](R) reader structure"]
68impl crate::Readable for MB_D4_SPEC {
69    type Reader = R;
70}
71#[doc = "`write(|w| ..)` method takes [mb_d4::W](W) writer structure"]
72impl crate::Writable for MB_D4_SPEC {
73    type Writer = W;
74    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
75    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
76}
77#[doc = "`reset()` method sets MB%s_D4 to value 0"]
78impl crate::Resettable for MB_D4_SPEC {
79    const RESET_VALUE: Self::Ux = 0;
80}
ra4w1/can0/mb_d4.rs

ra4w1/can0/
mb_d4.rs
