ra4m3/adc120/
adexicr.rs

1#[doc = "Register `ADEXICR` reader"]
2pub struct R(crate::R<ADEXICR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ADEXICR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ADEXICR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ADEXICR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ADEXICR` writer"]
17pub struct W(crate::W<ADEXICR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ADEXICR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ADEXICR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ADEXICR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TSSAD` reader - Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select"]
38pub type TSSAD_R = crate::BitReader<TSSAD_A>;
39#[doc = "Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum TSSAD_A {
42    #[doc = "0: Do not select addition/average mode for temperature sensor output."]
43    _0 = 0,
44    #[doc = "1: Select addition/average mode for temperature sensor output."]
45    _1 = 1,
46}
47impl From<TSSAD_A> for bool {
48    #[inline(always)]
49    fn from(variant: TSSAD_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl TSSAD_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> TSSAD_A {
57        match self.bits {
58            false => TSSAD_A::_0,
59            true => TSSAD_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == TSSAD_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == TSSAD_A::_1
71    }
72}
73#[doc = "Field `TSSAD` writer - Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select"]
74pub type TSSAD_W<'a, const O: u8> = crate::BitWriter<'a, u16, ADEXICR_SPEC, TSSAD_A, O>;
75impl<'a, const O: u8> TSSAD_W<'a, O> {
76    #[doc = "Do not select addition/average mode for temperature sensor output."]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(TSSAD_A::_0)
80    }
81    #[doc = "Select addition/average mode for temperature sensor output."]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(TSSAD_A::_1)
85    }
86}
87#[doc = "Field `OCSAD` reader - Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select"]
88pub type OCSAD_R = crate::BitReader<OCSAD_A>;
89#[doc = "Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum OCSAD_A {
92    #[doc = "0: Do not select addition/average mode for internal reference voltage."]
93    _0 = 0,
94    #[doc = "1: Select addition/average mode for internal reference voltage."]
95    _1 = 1,
96}
97impl From<OCSAD_A> for bool {
98    #[inline(always)]
99    fn from(variant: OCSAD_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl OCSAD_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> OCSAD_A {
107        match self.bits {
108            false => OCSAD_A::_0,
109            true => OCSAD_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == OCSAD_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == OCSAD_A::_1
121    }
122}
123#[doc = "Field `OCSAD` writer - Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select"]
124pub type OCSAD_W<'a, const O: u8> = crate::BitWriter<'a, u16, ADEXICR_SPEC, OCSAD_A, O>;
125impl<'a, const O: u8> OCSAD_W<'a, O> {
126    #[doc = "Do not select addition/average mode for internal reference voltage."]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(OCSAD_A::_0)
130    }
131    #[doc = "Select addition/average mode for internal reference voltage."]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(OCSAD_A::_1)
135    }
136}
137#[doc = "Field `TSSA` reader - Temperature Sensor Output A/D Conversion Select"]
138pub type TSSA_R = crate::BitReader<TSSA_A>;
139#[doc = "Temperature Sensor Output A/D Conversion Select\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum TSSA_A {
142    #[doc = "0: Disable A/D conversion of temperature sensor output"]
143    _0 = 0,
144    #[doc = "1: Enable A/D conversion of temperature sensor output"]
145    _1 = 1,
146}
147impl From<TSSA_A> for bool {
148    #[inline(always)]
149    fn from(variant: TSSA_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl TSSA_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> TSSA_A {
157        match self.bits {
158            false => TSSA_A::_0,
159            true => TSSA_A::_1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `_0`"]
163    #[inline(always)]
164    pub fn is_0(&self) -> bool {
165        *self == TSSA_A::_0
166    }
167    #[doc = "Checks if the value of the field is `_1`"]
168    #[inline(always)]
169    pub fn is_1(&self) -> bool {
170        *self == TSSA_A::_1
171    }
172}
173#[doc = "Field `TSSA` writer - Temperature Sensor Output A/D Conversion Select"]
174pub type TSSA_W<'a, const O: u8> = crate::BitWriter<'a, u16, ADEXICR_SPEC, TSSA_A, O>;
175impl<'a, const O: u8> TSSA_W<'a, O> {
176    #[doc = "Disable A/D conversion of temperature sensor output"]
177    #[inline(always)]
178    pub fn _0(self) -> &'a mut W {
179        self.variant(TSSA_A::_0)
180    }
181    #[doc = "Enable A/D conversion of temperature sensor output"]
182    #[inline(always)]
183    pub fn _1(self) -> &'a mut W {
184        self.variant(TSSA_A::_1)
185    }
186}
187#[doc = "Field `OCSA` reader - Internal Reference Voltage A/D Conversion Select"]
188pub type OCSA_R = crate::BitReader<OCSA_A>;
189#[doc = "Internal Reference Voltage A/D Conversion Select\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum OCSA_A {
192    #[doc = "0: Disable A/D conversion of internal reference voltage"]
193    _0 = 0,
194    #[doc = "1: Enable A/D conversion of internal reference voltage"]
195    _1 = 1,
196}
197impl From<OCSA_A> for bool {
198    #[inline(always)]
199    fn from(variant: OCSA_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl OCSA_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> OCSA_A {
207        match self.bits {
208            false => OCSA_A::_0,
209            true => OCSA_A::_1,
210        }
211    }
212    #[doc = "Checks if the value of the field is `_0`"]
213    #[inline(always)]
214    pub fn is_0(&self) -> bool {
215        *self == OCSA_A::_0
216    }
217    #[doc = "Checks if the value of the field is `_1`"]
218    #[inline(always)]
219    pub fn is_1(&self) -> bool {
220        *self == OCSA_A::_1
221    }
222}
223#[doc = "Field `OCSA` writer - Internal Reference Voltage A/D Conversion Select"]
224pub type OCSA_W<'a, const O: u8> = crate::BitWriter<'a, u16, ADEXICR_SPEC, OCSA_A, O>;
225impl<'a, const O: u8> OCSA_W<'a, O> {
226    #[doc = "Disable A/D conversion of internal reference voltage"]
227    #[inline(always)]
228    pub fn _0(self) -> &'a mut W {
229        self.variant(OCSA_A::_0)
230    }
231    #[doc = "Enable A/D conversion of internal reference voltage"]
232    #[inline(always)]
233    pub fn _1(self) -> &'a mut W {
234        self.variant(OCSA_A::_1)
235    }
236}
237#[doc = "Field `TSSB` reader - Temperature Sensor Output A/D Conversion Select for Group B"]
238pub type TSSB_R = crate::BitReader<TSSB_A>;
239#[doc = "Temperature Sensor Output A/D Conversion Select for Group B\n\nValue on reset: 0"]
240#[derive(Clone, Copy, Debug, PartialEq, Eq)]
241pub enum TSSB_A {
242    #[doc = "0: Disable A/D conversion of temperature sensor output"]
243    _0 = 0,
244    #[doc = "1: Enable A/D conversion of temperature sensor output"]
245    _1 = 1,
246}
247impl From<TSSB_A> for bool {
248    #[inline(always)]
249    fn from(variant: TSSB_A) -> Self {
250        variant as u8 != 0
251    }
252}
253impl TSSB_R {
254    #[doc = "Get enumerated values variant"]
255    #[inline(always)]
256    pub fn variant(&self) -> TSSB_A {
257        match self.bits {
258            false => TSSB_A::_0,
259            true => TSSB_A::_1,
260        }
261    }
262    #[doc = "Checks if the value of the field is `_0`"]
263    #[inline(always)]
264    pub fn is_0(&self) -> bool {
265        *self == TSSB_A::_0
266    }
267    #[doc = "Checks if the value of the field is `_1`"]
268    #[inline(always)]
269    pub fn is_1(&self) -> bool {
270        *self == TSSB_A::_1
271    }
272}
273#[doc = "Field `TSSB` writer - Temperature Sensor Output A/D Conversion Select for Group B"]
274pub type TSSB_W<'a, const O: u8> = crate::BitWriter<'a, u16, ADEXICR_SPEC, TSSB_A, O>;
275impl<'a, const O: u8> TSSB_W<'a, O> {
276    #[doc = "Disable A/D conversion of temperature sensor output"]
277    #[inline(always)]
278    pub fn _0(self) -> &'a mut W {
279        self.variant(TSSB_A::_0)
280    }
281    #[doc = "Enable A/D conversion of temperature sensor output"]
282    #[inline(always)]
283    pub fn _1(self) -> &'a mut W {
284        self.variant(TSSB_A::_1)
285    }
286}
287#[doc = "Field `OCSB` reader - Internal Reference Voltage A/D Conversion Select for Group B"]
288pub type OCSB_R = crate::BitReader<OCSB_A>;
289#[doc = "Internal Reference Voltage A/D Conversion Select for Group B\n\nValue on reset: 0"]
290#[derive(Clone, Copy, Debug, PartialEq, Eq)]
291pub enum OCSB_A {
292    #[doc = "0: Disable A/D conversion of internal reference voltage"]
293    _0 = 0,
294    #[doc = "1: Enable A/D conversion of internal reference voltage"]
295    _1 = 1,
296}
297impl From<OCSB_A> for bool {
298    #[inline(always)]
299    fn from(variant: OCSB_A) -> Self {
300        variant as u8 != 0
301    }
302}
303impl OCSB_R {
304    #[doc = "Get enumerated values variant"]
305    #[inline(always)]
306    pub fn variant(&self) -> OCSB_A {
307        match self.bits {
308            false => OCSB_A::_0,
309            true => OCSB_A::_1,
310        }
311    }
312    #[doc = "Checks if the value of the field is `_0`"]
313    #[inline(always)]
314    pub fn is_0(&self) -> bool {
315        *self == OCSB_A::_0
316    }
317    #[doc = "Checks if the value of the field is `_1`"]
318    #[inline(always)]
319    pub fn is_1(&self) -> bool {
320        *self == OCSB_A::_1
321    }
322}
323#[doc = "Field `OCSB` writer - Internal Reference Voltage A/D Conversion Select for Group B"]
324pub type OCSB_W<'a, const O: u8> = crate::BitWriter<'a, u16, ADEXICR_SPEC, OCSB_A, O>;
325impl<'a, const O: u8> OCSB_W<'a, O> {
326    #[doc = "Disable A/D conversion of internal reference voltage"]
327    #[inline(always)]
328    pub fn _0(self) -> &'a mut W {
329        self.variant(OCSB_A::_0)
330    }
331    #[doc = "Enable A/D conversion of internal reference voltage"]
332    #[inline(always)]
333    pub fn _1(self) -> &'a mut W {
334        self.variant(OCSB_A::_1)
335    }
336}
337impl R {
338    #[doc = "Bit 0 - Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select"]
339    #[inline(always)]
340    pub fn tssad(&self) -> TSSAD_R {
341        TSSAD_R::new((self.bits & 1) != 0)
342    }
343    #[doc = "Bit 1 - Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select"]
344    #[inline(always)]
345    pub fn ocsad(&self) -> OCSAD_R {
346        OCSAD_R::new(((self.bits >> 1) & 1) != 0)
347    }
348    #[doc = "Bit 8 - Temperature Sensor Output A/D Conversion Select"]
349    #[inline(always)]
350    pub fn tssa(&self) -> TSSA_R {
351        TSSA_R::new(((self.bits >> 8) & 1) != 0)
352    }
353    #[doc = "Bit 9 - Internal Reference Voltage A/D Conversion Select"]
354    #[inline(always)]
355    pub fn ocsa(&self) -> OCSA_R {
356        OCSA_R::new(((self.bits >> 9) & 1) != 0)
357    }
358    #[doc = "Bit 10 - Temperature Sensor Output A/D Conversion Select for Group B"]
359    #[inline(always)]
360    pub fn tssb(&self) -> TSSB_R {
361        TSSB_R::new(((self.bits >> 10) & 1) != 0)
362    }
363    #[doc = "Bit 11 - Internal Reference Voltage A/D Conversion Select for Group B"]
364    #[inline(always)]
365    pub fn ocsb(&self) -> OCSB_R {
366        OCSB_R::new(((self.bits >> 11) & 1) != 0)
367    }
368}
369impl W {
370    #[doc = "Bit 0 - Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select"]
371    #[inline(always)]
372    #[must_use]
373    pub fn tssad(&mut self) -> TSSAD_W<0> {
374        TSSAD_W::new(self)
375    }
376    #[doc = "Bit 1 - Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select"]
377    #[inline(always)]
378    #[must_use]
379    pub fn ocsad(&mut self) -> OCSAD_W<1> {
380        OCSAD_W::new(self)
381    }
382    #[doc = "Bit 8 - Temperature Sensor Output A/D Conversion Select"]
383    #[inline(always)]
384    #[must_use]
385    pub fn tssa(&mut self) -> TSSA_W<8> {
386        TSSA_W::new(self)
387    }
388    #[doc = "Bit 9 - Internal Reference Voltage A/D Conversion Select"]
389    #[inline(always)]
390    #[must_use]
391    pub fn ocsa(&mut self) -> OCSA_W<9> {
392        OCSA_W::new(self)
393    }
394    #[doc = "Bit 10 - Temperature Sensor Output A/D Conversion Select for Group B"]
395    #[inline(always)]
396    #[must_use]
397    pub fn tssb(&mut self) -> TSSB_W<10> {
398        TSSB_W::new(self)
399    }
400    #[doc = "Bit 11 - Internal Reference Voltage A/D Conversion Select for Group B"]
401    #[inline(always)]
402    #[must_use]
403    pub fn ocsb(&mut self) -> OCSB_W<11> {
404        OCSB_W::new(self)
405    }
406    #[doc = "Writes raw bits to the register."]
407    #[inline(always)]
408    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
409        self.0.bits(bits);
410        self
411    }
412}
413#[doc = "A/D Conversion Extended Input Control Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adexicr](index.html) module"]
414pub struct ADEXICR_SPEC;
415impl crate::RegisterSpec for ADEXICR_SPEC {
416    type Ux = u16;
417}
418#[doc = "`read()` method returns [adexicr::R](R) reader structure"]
419impl crate::Readable for ADEXICR_SPEC {
420    type Reader = R;
421}
422#[doc = "`write(|w| ..)` method takes [adexicr::W](W) writer structure"]
423impl crate::Writable for ADEXICR_SPEC {
424    type Writer = W;
425    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
426    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
427}
428#[doc = "`reset()` method sets ADEXICR to value 0"]
429impl crate::Resettable for ADEXICR_SPEC {
430    const RESET_VALUE: Self::Ux = 0;
431}
ra4m3/adc120/adexicr.rs

ra4m3/adc120/
adexicr.rs
