ra4m3/sci3/
semr.rs

1#[doc = "Register `SEMR` reader"]
2pub struct R(crate::R<SEMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SEMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SEMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SEMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SEMR` writer"]
17pub struct W(crate::W<SEMR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SEMR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SEMR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SEMR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ACS0` reader - Asynchronous Mode Clock Source Select"]
38pub type ACS0_R = crate::BitReader<ACS0_A>;
39#[doc = "Asynchronous Mode Clock Source Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum ACS0_A {
42    #[doc = "0: External clock input"]
43    _0 = 0,
44    #[doc = "1: Logical AND of compare matches output from the internal GPT. These bit for the other SCI channels than SCIn (n = 1, 2) are reserved."]
45    _1 = 1,
46}
47impl From<ACS0_A> for bool {
48    #[inline(always)]
49    fn from(variant: ACS0_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl ACS0_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> ACS0_A {
57        match self.bits {
58            false => ACS0_A::_0,
59            true => ACS0_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == ACS0_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == ACS0_A::_1
71    }
72}
73#[doc = "Field `ACS0` writer - Asynchronous Mode Clock Source Select"]
74pub type ACS0_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, ACS0_A, O>;
75impl<'a, const O: u8> ACS0_W<'a, O> {
76    #[doc = "External clock input"]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(ACS0_A::_0)
80    }
81    #[doc = "Logical AND of compare matches output from the internal GPT. These bit for the other SCI channels than SCIn (n = 1, 2) are reserved."]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(ACS0_A::_1)
85    }
86}
87#[doc = "Field `PADIS` reader - Preamble function Disable"]
88pub type PADIS_R = crate::BitReader<PADIS_A>;
89#[doc = "Preamble function Disable\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum PADIS_A {
92    #[doc = "0: Preamble output function is enabled"]
93    _0 = 0,
94    #[doc = "1: Preamble output function is disabled These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved."]
95    _1 = 1,
96}
97impl From<PADIS_A> for bool {
98    #[inline(always)]
99    fn from(variant: PADIS_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl PADIS_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> PADIS_A {
107        match self.bits {
108            false => PADIS_A::_0,
109            true => PADIS_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == PADIS_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == PADIS_A::_1
121    }
122}
123#[doc = "Field `PADIS` writer - Preamble function Disable"]
124pub type PADIS_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, PADIS_A, O>;
125impl<'a, const O: u8> PADIS_W<'a, O> {
126    #[doc = "Preamble output function is enabled"]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(PADIS_A::_0)
130    }
131    #[doc = "Preamble output function is disabled These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved."]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(PADIS_A::_1)
135    }
136}
137#[doc = "Field `BRME` reader - Bit Rate Modulation Enable"]
138pub type BRME_R = crate::BitReader<BRME_A>;
139#[doc = "Bit Rate Modulation Enable\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum BRME_A {
142    #[doc = "0: Disable bit rate modulation function"]
143    _0 = 0,
144    #[doc = "1: Enable bit rate modulation function"]
145    _1 = 1,
146}
147impl From<BRME_A> for bool {
148    #[inline(always)]
149    fn from(variant: BRME_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl BRME_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> BRME_A {
157        match self.bits {
158            false => BRME_A::_0,
159            true => BRME_A::_1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `_0`"]
163    #[inline(always)]
164    pub fn is_0(&self) -> bool {
165        *self == BRME_A::_0
166    }
167    #[doc = "Checks if the value of the field is `_1`"]
168    #[inline(always)]
169    pub fn is_1(&self) -> bool {
170        *self == BRME_A::_1
171    }
172}
173#[doc = "Field `BRME` writer - Bit Rate Modulation Enable"]
174pub type BRME_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, BRME_A, O>;
175impl<'a, const O: u8> BRME_W<'a, O> {
176    #[doc = "Disable bit rate modulation function"]
177    #[inline(always)]
178    pub fn _0(self) -> &'a mut W {
179        self.variant(BRME_A::_0)
180    }
181    #[doc = "Enable bit rate modulation function"]
182    #[inline(always)]
183    pub fn _1(self) -> &'a mut W {
184        self.variant(BRME_A::_1)
185    }
186}
187#[doc = "Field `ABCSE` reader - Asynchronous Mode Extended Base Clock Select 1"]
188pub type ABCSE_R = crate::BitReader<ABCSE_A>;
189#[doc = "Asynchronous Mode Extended Base Clock Select 1\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum ABCSE_A {
192    #[doc = "0: Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register"]
193    _0 = 0,
194    #[doc = "1: Baud rate is 6 base clock cycles for 1-bit period These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved."]
195    _1 = 1,
196}
197impl From<ABCSE_A> for bool {
198    #[inline(always)]
199    fn from(variant: ABCSE_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl ABCSE_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> ABCSE_A {
207        match self.bits {
208            false => ABCSE_A::_0,
209            true => ABCSE_A::_1,
210        }
211    }
212    #[doc = "Checks if the value of the field is `_0`"]
213    #[inline(always)]
214    pub fn is_0(&self) -> bool {
215        *self == ABCSE_A::_0
216    }
217    #[doc = "Checks if the value of the field is `_1`"]
218    #[inline(always)]
219    pub fn is_1(&self) -> bool {
220        *self == ABCSE_A::_1
221    }
222}
223#[doc = "Field `ABCSE` writer - Asynchronous Mode Extended Base Clock Select 1"]
224pub type ABCSE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, ABCSE_A, O>;
225impl<'a, const O: u8> ABCSE_W<'a, O> {
226    #[doc = "Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register"]
227    #[inline(always)]
228    pub fn _0(self) -> &'a mut W {
229        self.variant(ABCSE_A::_0)
230    }
231    #[doc = "Baud rate is 6 base clock cycles for 1-bit period These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved."]
232    #[inline(always)]
233    pub fn _1(self) -> &'a mut W {
234        self.variant(ABCSE_A::_1)
235    }
236}
237#[doc = "Field `ABCS` reader - Asynchronous Mode Base Clock Select"]
238pub type ABCS_R = crate::BitReader<ABCS_A>;
239#[doc = "Asynchronous Mode Base Clock Select\n\nValue on reset: 0"]
240#[derive(Clone, Copy, Debug, PartialEq, Eq)]
241pub enum ABCS_A {
242    #[doc = "0: Select 16 base clock cycles for 1-bit period"]
243    _0 = 0,
244    #[doc = "1: Select 8 base clock cycles for 1-bit period"]
245    _1 = 1,
246}
247impl From<ABCS_A> for bool {
248    #[inline(always)]
249    fn from(variant: ABCS_A) -> Self {
250        variant as u8 != 0
251    }
252}
253impl ABCS_R {
254    #[doc = "Get enumerated values variant"]
255    #[inline(always)]
256    pub fn variant(&self) -> ABCS_A {
257        match self.bits {
258            false => ABCS_A::_0,
259            true => ABCS_A::_1,
260        }
261    }
262    #[doc = "Checks if the value of the field is `_0`"]
263    #[inline(always)]
264    pub fn is_0(&self) -> bool {
265        *self == ABCS_A::_0
266    }
267    #[doc = "Checks if the value of the field is `_1`"]
268    #[inline(always)]
269    pub fn is_1(&self) -> bool {
270        *self == ABCS_A::_1
271    }
272}
273#[doc = "Field `ABCS` writer - Asynchronous Mode Base Clock Select"]
274pub type ABCS_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, ABCS_A, O>;
275impl<'a, const O: u8> ABCS_W<'a, O> {
276    #[doc = "Select 16 base clock cycles for 1-bit period"]
277    #[inline(always)]
278    pub fn _0(self) -> &'a mut W {
279        self.variant(ABCS_A::_0)
280    }
281    #[doc = "Select 8 base clock cycles for 1-bit period"]
282    #[inline(always)]
283    pub fn _1(self) -> &'a mut W {
284        self.variant(ABCS_A::_1)
285    }
286}
287#[doc = "Field `NFEN` reader - Digital Noise Filter Function Enable"]
288pub type NFEN_R = crate::BitReader<NFEN_A>;
289#[doc = "Digital Noise Filter Function Enable\n\nValue on reset: 0"]
290#[derive(Clone, Copy, Debug, PartialEq, Eq)]
291pub enum NFEN_A {
292    #[doc = "0: In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple I2C mode: Disable noise cancellation function for SCLn and SDAn input signals"]
293    _0 = 0,
294    #[doc = "1: In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple I2C mode: Enable noise cancellation function for SCLn and SDAn input signals"]
295    _1 = 1,
296}
297impl From<NFEN_A> for bool {
298    #[inline(always)]
299    fn from(variant: NFEN_A) -> Self {
300        variant as u8 != 0
301    }
302}
303impl NFEN_R {
304    #[doc = "Get enumerated values variant"]
305    #[inline(always)]
306    pub fn variant(&self) -> NFEN_A {
307        match self.bits {
308            false => NFEN_A::_0,
309            true => NFEN_A::_1,
310        }
311    }
312    #[doc = "Checks if the value of the field is `_0`"]
313    #[inline(always)]
314    pub fn is_0(&self) -> bool {
315        *self == NFEN_A::_0
316    }
317    #[doc = "Checks if the value of the field is `_1`"]
318    #[inline(always)]
319    pub fn is_1(&self) -> bool {
320        *self == NFEN_A::_1
321    }
322}
323#[doc = "Field `NFEN` writer - Digital Noise Filter Function Enable"]
324pub type NFEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, NFEN_A, O>;
325impl<'a, const O: u8> NFEN_W<'a, O> {
326    #[doc = "In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple I2C mode: Disable noise cancellation function for SCLn and SDAn input signals"]
327    #[inline(always)]
328    pub fn _0(self) -> &'a mut W {
329        self.variant(NFEN_A::_0)
330    }
331    #[doc = "In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple I2C mode: Enable noise cancellation function for SCLn and SDAn input signals"]
332    #[inline(always)]
333    pub fn _1(self) -> &'a mut W {
334        self.variant(NFEN_A::_1)
335    }
336}
337#[doc = "Field `BGDM` reader - Baud Rate Generator Double-Speed Mode Select"]
338pub type BGDM_R = crate::BitReader<BGDM_A>;
339#[doc = "Baud Rate Generator Double-Speed Mode Select\n\nValue on reset: 0"]
340#[derive(Clone, Copy, Debug, PartialEq, Eq)]
341pub enum BGDM_A {
342    #[doc = "0: Output clock from baud rate generator with normal frequency"]
343    _0 = 0,
344    #[doc = "1: Output clock from baud rate generator with doubled frequency"]
345    _1 = 1,
346}
347impl From<BGDM_A> for bool {
348    #[inline(always)]
349    fn from(variant: BGDM_A) -> Self {
350        variant as u8 != 0
351    }
352}
353impl BGDM_R {
354    #[doc = "Get enumerated values variant"]
355    #[inline(always)]
356    pub fn variant(&self) -> BGDM_A {
357        match self.bits {
358            false => BGDM_A::_0,
359            true => BGDM_A::_1,
360        }
361    }
362    #[doc = "Checks if the value of the field is `_0`"]
363    #[inline(always)]
364    pub fn is_0(&self) -> bool {
365        *self == BGDM_A::_0
366    }
367    #[doc = "Checks if the value of the field is `_1`"]
368    #[inline(always)]
369    pub fn is_1(&self) -> bool {
370        *self == BGDM_A::_1
371    }
372}
373#[doc = "Field `BGDM` writer - Baud Rate Generator Double-Speed Mode Select"]
374pub type BGDM_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, BGDM_A, O>;
375impl<'a, const O: u8> BGDM_W<'a, O> {
376    #[doc = "Output clock from baud rate generator with normal frequency"]
377    #[inline(always)]
378    pub fn _0(self) -> &'a mut W {
379        self.variant(BGDM_A::_0)
380    }
381    #[doc = "Output clock from baud rate generator with doubled frequency"]
382    #[inline(always)]
383    pub fn _1(self) -> &'a mut W {
384        self.variant(BGDM_A::_1)
385    }
386}
387#[doc = "Field `RXDESEL` reader - Asynchronous Start Bit Edge Detection Select"]
388pub type RXDESEL_R = crate::BitReader<RXDESEL_A>;
389#[doc = "Asynchronous Start Bit Edge Detection Select\n\nValue on reset: 0"]
390#[derive(Clone, Copy, Debug, PartialEq, Eq)]
391pub enum RXDESEL_A {
392    #[doc = "0: Detect low level on RXDn pin as start bit"]
393    _0 = 0,
394    #[doc = "1: Detect falling edge of RXDn pin as start bit"]
395    _1 = 1,
396}
397impl From<RXDESEL_A> for bool {
398    #[inline(always)]
399    fn from(variant: RXDESEL_A) -> Self {
400        variant as u8 != 0
401    }
402}
403impl RXDESEL_R {
404    #[doc = "Get enumerated values variant"]
405    #[inline(always)]
406    pub fn variant(&self) -> RXDESEL_A {
407        match self.bits {
408            false => RXDESEL_A::_0,
409            true => RXDESEL_A::_1,
410        }
411    }
412    #[doc = "Checks if the value of the field is `_0`"]
413    #[inline(always)]
414    pub fn is_0(&self) -> bool {
415        *self == RXDESEL_A::_0
416    }
417    #[doc = "Checks if the value of the field is `_1`"]
418    #[inline(always)]
419    pub fn is_1(&self) -> bool {
420        *self == RXDESEL_A::_1
421    }
422}
423#[doc = "Field `RXDESEL` writer - Asynchronous Start Bit Edge Detection Select"]
424pub type RXDESEL_W<'a, const O: u8> = crate::BitWriter<'a, u8, SEMR_SPEC, RXDESEL_A, O>;
425impl<'a, const O: u8> RXDESEL_W<'a, O> {
426    #[doc = "Detect low level on RXDn pin as start bit"]
427    #[inline(always)]
428    pub fn _0(self) -> &'a mut W {
429        self.variant(RXDESEL_A::_0)
430    }
431    #[doc = "Detect falling edge of RXDn pin as start bit"]
432    #[inline(always)]
433    pub fn _1(self) -> &'a mut W {
434        self.variant(RXDESEL_A::_1)
435    }
436}
437impl R {
438    #[doc = "Bit 0 - Asynchronous Mode Clock Source Select"]
439    #[inline(always)]
440    pub fn acs0(&self) -> ACS0_R {
441        ACS0_R::new((self.bits & 1) != 0)
442    }
443    #[doc = "Bit 1 - Preamble function Disable"]
444    #[inline(always)]
445    pub fn padis(&self) -> PADIS_R {
446        PADIS_R::new(((self.bits >> 1) & 1) != 0)
447    }
448    #[doc = "Bit 2 - Bit Rate Modulation Enable"]
449    #[inline(always)]
450    pub fn brme(&self) -> BRME_R {
451        BRME_R::new(((self.bits >> 2) & 1) != 0)
452    }
453    #[doc = "Bit 3 - Asynchronous Mode Extended Base Clock Select 1"]
454    #[inline(always)]
455    pub fn abcse(&self) -> ABCSE_R {
456        ABCSE_R::new(((self.bits >> 3) & 1) != 0)
457    }
458    #[doc = "Bit 4 - Asynchronous Mode Base Clock Select"]
459    #[inline(always)]
460    pub fn abcs(&self) -> ABCS_R {
461        ABCS_R::new(((self.bits >> 4) & 1) != 0)
462    }
463    #[doc = "Bit 5 - Digital Noise Filter Function Enable"]
464    #[inline(always)]
465    pub fn nfen(&self) -> NFEN_R {
466        NFEN_R::new(((self.bits >> 5) & 1) != 0)
467    }
468    #[doc = "Bit 6 - Baud Rate Generator Double-Speed Mode Select"]
469    #[inline(always)]
470    pub fn bgdm(&self) -> BGDM_R {
471        BGDM_R::new(((self.bits >> 6) & 1) != 0)
472    }
473    #[doc = "Bit 7 - Asynchronous Start Bit Edge Detection Select"]
474    #[inline(always)]
475    pub fn rxdesel(&self) -> RXDESEL_R {
476        RXDESEL_R::new(((self.bits >> 7) & 1) != 0)
477    }
478}
479impl W {
480    #[doc = "Bit 0 - Asynchronous Mode Clock Source Select"]
481    #[inline(always)]
482    #[must_use]
483    pub fn acs0(&mut self) -> ACS0_W<0> {
484        ACS0_W::new(self)
485    }
486    #[doc = "Bit 1 - Preamble function Disable"]
487    #[inline(always)]
488    #[must_use]
489    pub fn padis(&mut self) -> PADIS_W<1> {
490        PADIS_W::new(self)
491    }
492    #[doc = "Bit 2 - Bit Rate Modulation Enable"]
493    #[inline(always)]
494    #[must_use]
495    pub fn brme(&mut self) -> BRME_W<2> {
496        BRME_W::new(self)
497    }
498    #[doc = "Bit 3 - Asynchronous Mode Extended Base Clock Select 1"]
499    #[inline(always)]
500    #[must_use]
501    pub fn abcse(&mut self) -> ABCSE_W<3> {
502        ABCSE_W::new(self)
503    }
504    #[doc = "Bit 4 - Asynchronous Mode Base Clock Select"]
505    #[inline(always)]
506    #[must_use]
507    pub fn abcs(&mut self) -> ABCS_W<4> {
508        ABCS_W::new(self)
509    }
510    #[doc = "Bit 5 - Digital Noise Filter Function Enable"]
511    #[inline(always)]
512    #[must_use]
513    pub fn nfen(&mut self) -> NFEN_W<5> {
514        NFEN_W::new(self)
515    }
516    #[doc = "Bit 6 - Baud Rate Generator Double-Speed Mode Select"]
517    #[inline(always)]
518    #[must_use]
519    pub fn bgdm(&mut self) -> BGDM_W<6> {
520        BGDM_W::new(self)
521    }
522    #[doc = "Bit 7 - Asynchronous Start Bit Edge Detection Select"]
523    #[inline(always)]
524    #[must_use]
525    pub fn rxdesel(&mut self) -> RXDESEL_W<7> {
526        RXDESEL_W::new(self)
527    }
528    #[doc = "Writes raw bits to the register."]
529    #[inline(always)]
530    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
531        self.0.bits(bits);
532        self
533    }
534}
535#[doc = "Serial Extended Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [semr](index.html) module"]
536pub struct SEMR_SPEC;
537impl crate::RegisterSpec for SEMR_SPEC {
538    type Ux = u8;
539}
540#[doc = "`read()` method returns [semr::R](R) reader structure"]
541impl crate::Readable for SEMR_SPEC {
542    type Reader = R;
543}
544#[doc = "`write(|w| ..)` method takes [semr::W](W) writer structure"]
545impl crate::Writable for SEMR_SPEC {
546    type Writer = W;
547    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
548    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
549}
550#[doc = "`reset()` method sets SEMR to value 0"]
551impl crate::Resettable for SEMR_SPEC {
552    const RESET_VALUE: Self::Ux = 0;
553}
ra4m3/sci3/semr.rs

ra4m3/sci3/
semr.rs
