ra4m1/iic0/
iccr1.rs

1#[doc = "Register `ICCR1` reader"]
2pub struct R(crate::R<ICCR1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ICCR1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ICCR1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ICCR1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ICCR1` writer"]
17pub struct W(crate::W<ICCR1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ICCR1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ICCR1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ICCR1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SDAI` reader - SDA Line Monitor"]
38pub type SDAI_R = crate::BitReader<SDAI_A>;
39#[doc = "SDA Line Monitor\n\nValue on reset: 1"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum SDAI_A {
42    #[doc = "0: SDAn line is low."]
43    _0 = 0,
44    #[doc = "1: SDAn line is high."]
45    _1 = 1,
46}
47impl From<SDAI_A> for bool {
48    #[inline(always)]
49    fn from(variant: SDAI_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl SDAI_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> SDAI_A {
57        match self.bits {
58            false => SDAI_A::_0,
59            true => SDAI_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == SDAI_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == SDAI_A::_1
71    }
72}
73#[doc = "Field `SCLI` reader - SCL Line Monitor"]
74pub type SCLI_R = crate::BitReader<SCLI_A>;
75#[doc = "SCL Line Monitor\n\nValue on reset: 1"]
76#[derive(Clone, Copy, Debug, PartialEq, Eq)]
77pub enum SCLI_A {
78    #[doc = "0: SCLn line is low."]
79    _0 = 0,
80    #[doc = "1: SCLn line is high."]
81    _1 = 1,
82}
83impl From<SCLI_A> for bool {
84    #[inline(always)]
85    fn from(variant: SCLI_A) -> Self {
86        variant as u8 != 0
87    }
88}
89impl SCLI_R {
90    #[doc = "Get enumerated values variant"]
91    #[inline(always)]
92    pub fn variant(&self) -> SCLI_A {
93        match self.bits {
94            false => SCLI_A::_0,
95            true => SCLI_A::_1,
96        }
97    }
98    #[doc = "Checks if the value of the field is `_0`"]
99    #[inline(always)]
100    pub fn is_0(&self) -> bool {
101        *self == SCLI_A::_0
102    }
103    #[doc = "Checks if the value of the field is `_1`"]
104    #[inline(always)]
105    pub fn is_1(&self) -> bool {
106        *self == SCLI_A::_1
107    }
108}
109#[doc = "Field `SDAO` reader - SDA Output Control/Monitor"]
110pub type SDAO_R = crate::BitReader<SDAO_A>;
111#[doc = "SDA Output Control/Monitor\n\nValue on reset: 1"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum SDAO_A {
114    #[doc = "0: (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low."]
115    _0 = 0,
116    #[doc = "1: (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin."]
117    _1 = 1,
118}
119impl From<SDAO_A> for bool {
120    #[inline(always)]
121    fn from(variant: SDAO_A) -> Self {
122        variant as u8 != 0
123    }
124}
125impl SDAO_R {
126    #[doc = "Get enumerated values variant"]
127    #[inline(always)]
128    pub fn variant(&self) -> SDAO_A {
129        match self.bits {
130            false => SDAO_A::_0,
131            true => SDAO_A::_1,
132        }
133    }
134    #[doc = "Checks if the value of the field is `_0`"]
135    #[inline(always)]
136    pub fn is_0(&self) -> bool {
137        *self == SDAO_A::_0
138    }
139    #[doc = "Checks if the value of the field is `_1`"]
140    #[inline(always)]
141    pub fn is_1(&self) -> bool {
142        *self == SDAO_A::_1
143    }
144}
145#[doc = "Field `SDAO` writer - SDA Output Control/Monitor"]
146pub type SDAO_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, SDAO_A, O>;
147impl<'a, const O: u8> SDAO_W<'a, O> {
148    #[doc = "(Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low."]
149    #[inline(always)]
150    pub fn _0(self) -> &'a mut W {
151        self.variant(SDAO_A::_0)
152    }
153    #[doc = "(Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin."]
154    #[inline(always)]
155    pub fn _1(self) -> &'a mut W {
156        self.variant(SDAO_A::_1)
157    }
158}
159#[doc = "Field `SCLO` reader - SCL Output Control/Monitor"]
160pub type SCLO_R = crate::BitReader<SCLO_A>;
161#[doc = "SCL Output Control/Monitor\n\nValue on reset: 1"]
162#[derive(Clone, Copy, Debug, PartialEq, Eq)]
163pub enum SCLO_A {
164    #[doc = "0: (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low."]
165    _0 = 0,
166    #[doc = "1: (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin."]
167    _1 = 1,
168}
169impl From<SCLO_A> for bool {
170    #[inline(always)]
171    fn from(variant: SCLO_A) -> Self {
172        variant as u8 != 0
173    }
174}
175impl SCLO_R {
176    #[doc = "Get enumerated values variant"]
177    #[inline(always)]
178    pub fn variant(&self) -> SCLO_A {
179        match self.bits {
180            false => SCLO_A::_0,
181            true => SCLO_A::_1,
182        }
183    }
184    #[doc = "Checks if the value of the field is `_0`"]
185    #[inline(always)]
186    pub fn is_0(&self) -> bool {
187        *self == SCLO_A::_0
188    }
189    #[doc = "Checks if the value of the field is `_1`"]
190    #[inline(always)]
191    pub fn is_1(&self) -> bool {
192        *self == SCLO_A::_1
193    }
194}
195#[doc = "Field `SCLO` writer - SCL Output Control/Monitor"]
196pub type SCLO_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, SCLO_A, O>;
197impl<'a, const O: u8> SCLO_W<'a, O> {
198    #[doc = "(Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low."]
199    #[inline(always)]
200    pub fn _0(self) -> &'a mut W {
201        self.variant(SCLO_A::_0)
202    }
203    #[doc = "(Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin."]
204    #[inline(always)]
205    pub fn _1(self) -> &'a mut W {
206        self.variant(SCLO_A::_1)
207    }
208}
209#[doc = "Field `SOWP` reader - SCLO/SDAO Write Protect"]
210pub type SOWP_R = crate::BitReader<SOWP_A>;
211#[doc = "SCLO/SDAO Write Protect\n\nValue on reset: 1"]
212#[derive(Clone, Copy, Debug, PartialEq, Eq)]
213pub enum SOWP_A {
214    #[doc = "0: Bits SCLO and SDAO can be written"]
215    _0 = 0,
216    #[doc = "1: Bits SCLO and SDAO are protected."]
217    _1 = 1,
218}
219impl From<SOWP_A> for bool {
220    #[inline(always)]
221    fn from(variant: SOWP_A) -> Self {
222        variant as u8 != 0
223    }
224}
225impl SOWP_R {
226    #[doc = "Get enumerated values variant"]
227    #[inline(always)]
228    pub fn variant(&self) -> SOWP_A {
229        match self.bits {
230            false => SOWP_A::_0,
231            true => SOWP_A::_1,
232        }
233    }
234    #[doc = "Checks if the value of the field is `_0`"]
235    #[inline(always)]
236    pub fn is_0(&self) -> bool {
237        *self == SOWP_A::_0
238    }
239    #[doc = "Checks if the value of the field is `_1`"]
240    #[inline(always)]
241    pub fn is_1(&self) -> bool {
242        *self == SOWP_A::_1
243    }
244}
245#[doc = "Field `SOWP` writer - SCLO/SDAO Write Protect"]
246pub type SOWP_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, SOWP_A, O>;
247impl<'a, const O: u8> SOWP_W<'a, O> {
248    #[doc = "Bits SCLO and SDAO can be written"]
249    #[inline(always)]
250    pub fn _0(self) -> &'a mut W {
251        self.variant(SOWP_A::_0)
252    }
253    #[doc = "Bits SCLO and SDAO are protected."]
254    #[inline(always)]
255    pub fn _1(self) -> &'a mut W {
256        self.variant(SOWP_A::_1)
257    }
258}
259#[doc = "Field `CLO` reader - Extra SCL Clock Cycle Output"]
260pub type CLO_R = crate::BitReader<CLO_A>;
261#[doc = "Extra SCL Clock Cycle Output\n\nValue on reset: 0"]
262#[derive(Clone, Copy, Debug, PartialEq, Eq)]
263pub enum CLO_A {
264    #[doc = "0: Does not output an extra SCL clock cycle."]
265    _0 = 0,
266    #[doc = "1: Outputs an extra SCL clock cycle."]
267    _1 = 1,
268}
269impl From<CLO_A> for bool {
270    #[inline(always)]
271    fn from(variant: CLO_A) -> Self {
272        variant as u8 != 0
273    }
274}
275impl CLO_R {
276    #[doc = "Get enumerated values variant"]
277    #[inline(always)]
278    pub fn variant(&self) -> CLO_A {
279        match self.bits {
280            false => CLO_A::_0,
281            true => CLO_A::_1,
282        }
283    }
284    #[doc = "Checks if the value of the field is `_0`"]
285    #[inline(always)]
286    pub fn is_0(&self) -> bool {
287        *self == CLO_A::_0
288    }
289    #[doc = "Checks if the value of the field is `_1`"]
290    #[inline(always)]
291    pub fn is_1(&self) -> bool {
292        *self == CLO_A::_1
293    }
294}
295#[doc = "Field `CLO` writer - Extra SCL Clock Cycle Output"]
296pub type CLO_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, CLO_A, O>;
297impl<'a, const O: u8> CLO_W<'a, O> {
298    #[doc = "Does not output an extra SCL clock cycle."]
299    #[inline(always)]
300    pub fn _0(self) -> &'a mut W {
301        self.variant(CLO_A::_0)
302    }
303    #[doc = "Outputs an extra SCL clock cycle."]
304    #[inline(always)]
305    pub fn _1(self) -> &'a mut W {
306        self.variant(CLO_A::_1)
307    }
308}
309#[doc = "Field `IICRST` reader - I2C Bus Interface Internal Reset Note:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information)."]
310pub type IICRST_R = crate::BitReader<IICRST_A>;
311#[doc = "I2C Bus Interface Internal Reset Note:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information).\n\nValue on reset: 0"]
312#[derive(Clone, Copy, Debug, PartialEq, Eq)]
313pub enum IICRST_A {
314    #[doc = "0: Releases the RIIC reset or internal reset."]
315    _0 = 0,
316    #[doc = "1: Initiates the RIIC reset or internal reset."]
317    _1 = 1,
318}
319impl From<IICRST_A> for bool {
320    #[inline(always)]
321    fn from(variant: IICRST_A) -> Self {
322        variant as u8 != 0
323    }
324}
325impl IICRST_R {
326    #[doc = "Get enumerated values variant"]
327    #[inline(always)]
328    pub fn variant(&self) -> IICRST_A {
329        match self.bits {
330            false => IICRST_A::_0,
331            true => IICRST_A::_1,
332        }
333    }
334    #[doc = "Checks if the value of the field is `_0`"]
335    #[inline(always)]
336    pub fn is_0(&self) -> bool {
337        *self == IICRST_A::_0
338    }
339    #[doc = "Checks if the value of the field is `_1`"]
340    #[inline(always)]
341    pub fn is_1(&self) -> bool {
342        *self == IICRST_A::_1
343    }
344}
345#[doc = "Field `IICRST` writer - I2C Bus Interface Internal Reset Note:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information)."]
346pub type IICRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, IICRST_A, O>;
347impl<'a, const O: u8> IICRST_W<'a, O> {
348    #[doc = "Releases the RIIC reset or internal reset."]
349    #[inline(always)]
350    pub fn _0(self) -> &'a mut W {
351        self.variant(IICRST_A::_0)
352    }
353    #[doc = "Initiates the RIIC reset or internal reset."]
354    #[inline(always)]
355    pub fn _1(self) -> &'a mut W {
356        self.variant(IICRST_A::_1)
357    }
358}
359#[doc = "Field `ICE` reader - I2C Bus Interface Enable"]
360pub type ICE_R = crate::BitReader<ICE_A>;
361#[doc = "I2C Bus Interface Enable\n\nValue on reset: 0"]
362#[derive(Clone, Copy, Debug, PartialEq, Eq)]
363pub enum ICE_A {
364    #[doc = "0: Disable (SCLn and SDAn pins in inactive state)"]
365    _0 = 0,
366    #[doc = "1: Enable (SCLn and SDAn pins in active state)"]
367    _1 = 1,
368}
369impl From<ICE_A> for bool {
370    #[inline(always)]
371    fn from(variant: ICE_A) -> Self {
372        variant as u8 != 0
373    }
374}
375impl ICE_R {
376    #[doc = "Get enumerated values variant"]
377    #[inline(always)]
378    pub fn variant(&self) -> ICE_A {
379        match self.bits {
380            false => ICE_A::_0,
381            true => ICE_A::_1,
382        }
383    }
384    #[doc = "Checks if the value of the field is `_0`"]
385    #[inline(always)]
386    pub fn is_0(&self) -> bool {
387        *self == ICE_A::_0
388    }
389    #[doc = "Checks if the value of the field is `_1`"]
390    #[inline(always)]
391    pub fn is_1(&self) -> bool {
392        *self == ICE_A::_1
393    }
394}
395#[doc = "Field `ICE` writer - I2C Bus Interface Enable"]
396pub type ICE_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, ICE_A, O>;
397impl<'a, const O: u8> ICE_W<'a, O> {
398    #[doc = "Disable (SCLn and SDAn pins in inactive state)"]
399    #[inline(always)]
400    pub fn _0(self) -> &'a mut W {
401        self.variant(ICE_A::_0)
402    }
403    #[doc = "Enable (SCLn and SDAn pins in active state)"]
404    #[inline(always)]
405    pub fn _1(self) -> &'a mut W {
406        self.variant(ICE_A::_1)
407    }
408}
409impl R {
410    #[doc = "Bit 0 - SDA Line Monitor"]
411    #[inline(always)]
412    pub fn sdai(&self) -> SDAI_R {
413        SDAI_R::new((self.bits & 1) != 0)
414    }
415    #[doc = "Bit 1 - SCL Line Monitor"]
416    #[inline(always)]
417    pub fn scli(&self) -> SCLI_R {
418        SCLI_R::new(((self.bits >> 1) & 1) != 0)
419    }
420    #[doc = "Bit 2 - SDA Output Control/Monitor"]
421    #[inline(always)]
422    pub fn sdao(&self) -> SDAO_R {
423        SDAO_R::new(((self.bits >> 2) & 1) != 0)
424    }
425    #[doc = "Bit 3 - SCL Output Control/Monitor"]
426    #[inline(always)]
427    pub fn sclo(&self) -> SCLO_R {
428        SCLO_R::new(((self.bits >> 3) & 1) != 0)
429    }
430    #[doc = "Bit 4 - SCLO/SDAO Write Protect"]
431    #[inline(always)]
432    pub fn sowp(&self) -> SOWP_R {
433        SOWP_R::new(((self.bits >> 4) & 1) != 0)
434    }
435    #[doc = "Bit 5 - Extra SCL Clock Cycle Output"]
436    #[inline(always)]
437    pub fn clo(&self) -> CLO_R {
438        CLO_R::new(((self.bits >> 5) & 1) != 0)
439    }
440    #[doc = "Bit 6 - I2C Bus Interface Internal Reset Note:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information)."]
441    #[inline(always)]
442    pub fn iicrst(&self) -> IICRST_R {
443        IICRST_R::new(((self.bits >> 6) & 1) != 0)
444    }
445    #[doc = "Bit 7 - I2C Bus Interface Enable"]
446    #[inline(always)]
447    pub fn ice(&self) -> ICE_R {
448        ICE_R::new(((self.bits >> 7) & 1) != 0)
449    }
450}
451impl W {
452    #[doc = "Bit 2 - SDA Output Control/Monitor"]
453    #[inline(always)]
454    #[must_use]
455    pub fn sdao(&mut self) -> SDAO_W<2> {
456        SDAO_W::new(self)
457    }
458    #[doc = "Bit 3 - SCL Output Control/Monitor"]
459    #[inline(always)]
460    #[must_use]
461    pub fn sclo(&mut self) -> SCLO_W<3> {
462        SCLO_W::new(self)
463    }
464    #[doc = "Bit 4 - SCLO/SDAO Write Protect"]
465    #[inline(always)]
466    #[must_use]
467    pub fn sowp(&mut self) -> SOWP_W<4> {
468        SOWP_W::new(self)
469    }
470    #[doc = "Bit 5 - Extra SCL Clock Cycle Output"]
471    #[inline(always)]
472    #[must_use]
473    pub fn clo(&mut self) -> CLO_W<5> {
474        CLO_W::new(self)
475    }
476    #[doc = "Bit 6 - I2C Bus Interface Internal Reset Note:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information)."]
477    #[inline(always)]
478    #[must_use]
479    pub fn iicrst(&mut self) -> IICRST_W<6> {
480        IICRST_W::new(self)
481    }
482    #[doc = "Bit 7 - I2C Bus Interface Enable"]
483    #[inline(always)]
484    #[must_use]
485    pub fn ice(&mut self) -> ICE_W<7> {
486        ICE_W::new(self)
487    }
488    #[doc = "Writes raw bits to the register."]
489    #[inline(always)]
490    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
491        self.0.bits(bits);
492        self
493    }
494}
495#[doc = "I2C Bus Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iccr1](index.html) module"]
496pub struct ICCR1_SPEC;
497impl crate::RegisterSpec for ICCR1_SPEC {
498    type Ux = u8;
499}
500#[doc = "`read()` method returns [iccr1::R](R) reader structure"]
501impl crate::Readable for ICCR1_SPEC {
502    type Reader = R;
503}
504#[doc = "`write(|w| ..)` method takes [iccr1::W](W) writer structure"]
505impl crate::Writable for ICCR1_SPEC {
506    type Writer = W;
507    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
508    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
509}
510#[doc = "`reset()` method sets ICCR1 to value 0x1f"]
511impl crate::Resettable for ICCR1_SPEC {
512    const RESET_VALUE: Self::Ux = 0x1f;
513}
ra4m1/iic0/iccr1.rs

ra4m1/iic0/
iccr1.rs
