ra4m1 0.2.0

Peripheral access API for ra4m1 microcontrollers (generated using svd2rust)
Documentation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
#[doc = "Register `DCPCTR` reader"]
pub struct R(crate::R<DCPCTR_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<DCPCTR_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<DCPCTR_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<DCPCTR_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `DCPCTR` writer"]
pub struct W(crate::W<DCPCTR_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<DCPCTR_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<DCPCTR_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<DCPCTR_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `PID` reader - Response PID"]
pub type PID_R = crate::FieldReader<u8, PID_A>;
#[doc = "Response PID\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PID_A {
    #[doc = "0: NAK response"]
    _00 = 0,
    #[doc = "1: BUF response (depending on the buffer state)"]
    _01 = 1,
    #[doc = "2: STALL response"]
    _10 = 2,
    #[doc = "3: STALL response"]
    _11 = 3,
}
impl From<PID_A> for u8 {
    #[inline(always)]
    fn from(variant: PID_A) -> Self {
        variant as _
    }
}
impl PID_R {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> PID_A {
        match self.bits {
            0 => PID_A::_00,
            1 => PID_A::_01,
            2 => PID_A::_10,
            3 => PID_A::_11,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `_00`"]
    #[inline(always)]
    pub fn is_00(&self) -> bool {
        *self == PID_A::_00
    }
    #[doc = "Checks if the value of the field is `_01`"]
    #[inline(always)]
    pub fn is_01(&self) -> bool {
        *self == PID_A::_01
    }
    #[doc = "Checks if the value of the field is `_10`"]
    #[inline(always)]
    pub fn is_10(&self) -> bool {
        *self == PID_A::_10
    }
    #[doc = "Checks if the value of the field is `_11`"]
    #[inline(always)]
    pub fn is_11(&self) -> bool {
        *self == PID_A::_11
    }
}
#[doc = "Field `PID` writer - Response PID"]
pub type PID_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u16, DCPCTR_SPEC, u8, PID_A, 2, O>;
impl<'a, const O: u8> PID_W<'a, O> {
    #[doc = "NAK response"]
    #[inline(always)]
    pub fn _00(self) -> &'a mut W {
        self.variant(PID_A::_00)
    }
    #[doc = "BUF response (depending on the buffer state)"]
    #[inline(always)]
    pub fn _01(self) -> &'a mut W {
        self.variant(PID_A::_01)
    }
    #[doc = "STALL response"]
    #[inline(always)]
    pub fn _10(self) -> &'a mut W {
        self.variant(PID_A::_10)
    }
    #[doc = "STALL response"]
    #[inline(always)]
    pub fn _11(self) -> &'a mut W {
        self.variant(PID_A::_11)
    }
}
#[doc = "Field `CCPL` reader - Control Transfer End Enable"]
pub type CCPL_R = crate::BitReader<CCPL_A>;
#[doc = "Control Transfer End Enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCPL_A {
    #[doc = "0: Invalid"]
    _0 = 0,
    #[doc = "1: Completion of control transfer is enabled."]
    _1 = 1,
}
impl From<CCPL_A> for bool {
    #[inline(always)]
    fn from(variant: CCPL_A) -> Self {
        variant as u8 != 0
    }
}
impl CCPL_R {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> CCPL_A {
        match self.bits {
            false => CCPL_A::_0,
            true => CCPL_A::_1,
        }
    }
    #[doc = "Checks if the value of the field is `_0`"]
    #[inline(always)]
    pub fn is_0(&self) -> bool {
        *self == CCPL_A::_0
    }
    #[doc = "Checks if the value of the field is `_1`"]
    #[inline(always)]
    pub fn is_1(&self) -> bool {
        *self == CCPL_A::_1
    }
}
#[doc = "Field `CCPL` writer - Control Transfer End Enable"]
pub type CCPL_W<'a, const O: u8> = crate::BitWriter<'a, u16, DCPCTR_SPEC, CCPL_A, O>;
impl<'a, const O: u8> CCPL_W<'a, O> {
    #[doc = "Invalid"]
    #[inline(always)]
    pub fn _0(self) -> &'a mut W {
        self.variant(CCPL_A::_0)
    }
    #[doc = "Completion of control transfer is enabled."]
    #[inline(always)]
    pub fn _1(self) -> &'a mut W {
        self.variant(CCPL_A::_1)
    }
}
#[doc = "Field `PBUSY` reader - Pipe Busy"]
pub type PBUSY_R = crate::BitReader<PBUSY_A>;
#[doc = "Pipe Busy\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PBUSY_A {
    #[doc = "0: DCP is not used for the transaction."]
    _0 = 0,
    #[doc = "1: DCP is used for the transaction."]
    _1 = 1,
}
impl From<PBUSY_A> for bool {
    #[inline(always)]
    fn from(variant: PBUSY_A) -> Self {
        variant as u8 != 0
    }
}
impl PBUSY_R {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> PBUSY_A {
        match self.bits {
            false => PBUSY_A::_0,
            true => PBUSY_A::_1,
        }
    }
    #[doc = "Checks if the value of the field is `_0`"]
    #[inline(always)]
    pub fn is_0(&self) -> bool {
        *self == PBUSY_A::_0
    }
    #[doc = "Checks if the value of the field is `_1`"]
    #[inline(always)]
    pub fn is_1(&self) -> bool {
        *self == PBUSY_A::_1
    }
}
#[doc = "Field `SQMON` reader - Sequence Toggle Bit Monitor"]
pub type SQMON_R = crate::BitReader<SQMON_A>;
#[doc = "Sequence Toggle Bit Monitor\n\nValue on reset: 1"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SQMON_A {
    #[doc = "0: DATA0"]
    _0 = 0,
    #[doc = "1: DATA1"]
    _1 = 1,
}
impl From<SQMON_A> for bool {
    #[inline(always)]
    fn from(variant: SQMON_A) -> Self {
        variant as u8 != 0
    }
}
impl SQMON_R {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SQMON_A {
        match self.bits {
            false => SQMON_A::_0,
            true => SQMON_A::_1,
        }
    }
    #[doc = "Checks if the value of the field is `_0`"]
    #[inline(always)]
    pub fn is_0(&self) -> bool {
        *self == SQMON_A::_0
    }
    #[doc = "Checks if the value of the field is `_1`"]
    #[inline(always)]
    pub fn is_1(&self) -> bool {
        *self == SQMON_A::_1
    }
}
#[doc = "Sequence Toggle Bit Set\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SQSET_AW {
    #[doc = "0: Invalid"]
    _0 = 0,
    #[doc = "1: Specifies DATA1."]
    _1 = 1,
}
impl From<SQSET_AW> for bool {
    #[inline(always)]
    fn from(variant: SQSET_AW) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `SQSET` writer - Sequence Toggle Bit Set"]
pub type SQSET_W<'a, const O: u8> = crate::BitWriter<'a, u16, DCPCTR_SPEC, SQSET_AW, O>;
impl<'a, const O: u8> SQSET_W<'a, O> {
    #[doc = "Invalid"]
    #[inline(always)]
    pub fn _0(self) -> &'a mut W {
        self.variant(SQSET_AW::_0)
    }
    #[doc = "Specifies DATA1."]
    #[inline(always)]
    pub fn _1(self) -> &'a mut W {
        self.variant(SQSET_AW::_1)
    }
}
#[doc = "Sequence Toggle Bit Clear\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SQCLR_AW {
    #[doc = "0: Invalid"]
    _0 = 0,
    #[doc = "1: Specifies DATA0."]
    _1 = 1,
}
impl From<SQCLR_AW> for bool {
    #[inline(always)]
    fn from(variant: SQCLR_AW) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `SQCLR` writer - Sequence Toggle Bit Clear"]
pub type SQCLR_W<'a, const O: u8> = crate::BitWriter<'a, u16, DCPCTR_SPEC, SQCLR_AW, O>;
impl<'a, const O: u8> SQCLR_W<'a, O> {
    #[doc = "Invalid"]
    #[inline(always)]
    pub fn _0(self) -> &'a mut W {
        self.variant(SQCLR_AW::_0)
    }
    #[doc = "Specifies DATA0."]
    #[inline(always)]
    pub fn _1(self) -> &'a mut W {
        self.variant(SQCLR_AW::_1)
    }
}
#[doc = "Field `SUREQCLR` reader - SUREQ Bit Clear"]
pub type SUREQCLR_R = crate::BitReader<SUREQCLR_A>;
#[doc = "SUREQ Bit Clear\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SUREQCLR_A {
    #[doc = "0: Invalid"]
    _0 = 0,
    #[doc = "1: Clears the SUREQ bit to 0."]
    _1 = 1,
}
impl From<SUREQCLR_A> for bool {
    #[inline(always)]
    fn from(variant: SUREQCLR_A) -> Self {
        variant as u8 != 0
    }
}
impl SUREQCLR_R {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SUREQCLR_A {
        match self.bits {
            false => SUREQCLR_A::_0,
            true => SUREQCLR_A::_1,
        }
    }
    #[doc = "Checks if the value of the field is `_0`"]
    #[inline(always)]
    pub fn is_0(&self) -> bool {
        *self == SUREQCLR_A::_0
    }
    #[doc = "Checks if the value of the field is `_1`"]
    #[inline(always)]
    pub fn is_1(&self) -> bool {
        *self == SUREQCLR_A::_1
    }
}
#[doc = "Field `SUREQCLR` writer - SUREQ Bit Clear"]
pub type SUREQCLR_W<'a, const O: u8> = crate::BitWriter<'a, u16, DCPCTR_SPEC, SUREQCLR_A, O>;
impl<'a, const O: u8> SUREQCLR_W<'a, O> {
    #[doc = "Invalid"]
    #[inline(always)]
    pub fn _0(self) -> &'a mut W {
        self.variant(SUREQCLR_A::_0)
    }
    #[doc = "Clears the SUREQ bit to 0."]
    #[inline(always)]
    pub fn _1(self) -> &'a mut W {
        self.variant(SUREQCLR_A::_1)
    }
}
#[doc = "Field `SUREQ` reader - Setup Token Transmission"]
pub type SUREQ_R = crate::BitReader<SUREQ_A>;
#[doc = "Setup Token Transmission\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SUREQ_A {
    #[doc = "0: Invalid"]
    _0 = 0,
    #[doc = "1: Transmits the setup packet."]
    _1 = 1,
}
impl From<SUREQ_A> for bool {
    #[inline(always)]
    fn from(variant: SUREQ_A) -> Self {
        variant as u8 != 0
    }
}
impl SUREQ_R {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SUREQ_A {
        match self.bits {
            false => SUREQ_A::_0,
            true => SUREQ_A::_1,
        }
    }
    #[doc = "Checks if the value of the field is `_0`"]
    #[inline(always)]
    pub fn is_0(&self) -> bool {
        *self == SUREQ_A::_0
    }
    #[doc = "Checks if the value of the field is `_1`"]
    #[inline(always)]
    pub fn is_1(&self) -> bool {
        *self == SUREQ_A::_1
    }
}
#[doc = "Field `SUREQ` writer - Setup Token Transmission"]
pub type SUREQ_W<'a, const O: u8> = crate::BitWriter<'a, u16, DCPCTR_SPEC, SUREQ_A, O>;
impl<'a, const O: u8> SUREQ_W<'a, O> {
    #[doc = "Invalid"]
    #[inline(always)]
    pub fn _0(self) -> &'a mut W {
        self.variant(SUREQ_A::_0)
    }
    #[doc = "Transmits the setup packet."]
    #[inline(always)]
    pub fn _1(self) -> &'a mut W {
        self.variant(SUREQ_A::_1)
    }
}
#[doc = "Field `BSTS` reader - Buffer Status"]
pub type BSTS_R = crate::BitReader<BSTS_A>;
#[doc = "Buffer Status\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum BSTS_A {
    #[doc = "0: Buffer access is disabled."]
    _0 = 0,
    #[doc = "1: Buffer access is enabled."]
    _1 = 1,
}
impl From<BSTS_A> for bool {
    #[inline(always)]
    fn from(variant: BSTS_A) -> Self {
        variant as u8 != 0
    }
}
impl BSTS_R {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> BSTS_A {
        match self.bits {
            false => BSTS_A::_0,
            true => BSTS_A::_1,
        }
    }
    #[doc = "Checks if the value of the field is `_0`"]
    #[inline(always)]
    pub fn is_0(&self) -> bool {
        *self == BSTS_A::_0
    }
    #[doc = "Checks if the value of the field is `_1`"]
    #[inline(always)]
    pub fn is_1(&self) -> bool {
        *self == BSTS_A::_1
    }
}
impl R {
    #[doc = "Bits 0:1 - Response PID"]
    #[inline(always)]
    pub fn pid(&self) -> PID_R {
        PID_R::new((self.bits & 3) as u8)
    }
    #[doc = "Bit 2 - Control Transfer End Enable"]
    #[inline(always)]
    pub fn ccpl(&self) -> CCPL_R {
        CCPL_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 5 - Pipe Busy"]
    #[inline(always)]
    pub fn pbusy(&self) -> PBUSY_R {
        PBUSY_R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6 - Sequence Toggle Bit Monitor"]
    #[inline(always)]
    pub fn sqmon(&self) -> SQMON_R {
        SQMON_R::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 11 - SUREQ Bit Clear"]
    #[inline(always)]
    pub fn sureqclr(&self) -> SUREQCLR_R {
        SUREQCLR_R::new(((self.bits >> 11) & 1) != 0)
    }
    #[doc = "Bit 14 - Setup Token Transmission"]
    #[inline(always)]
    pub fn sureq(&self) -> SUREQ_R {
        SUREQ_R::new(((self.bits >> 14) & 1) != 0)
    }
    #[doc = "Bit 15 - Buffer Status"]
    #[inline(always)]
    pub fn bsts(&self) -> BSTS_R {
        BSTS_R::new(((self.bits >> 15) & 1) != 0)
    }
}
impl W {
    #[doc = "Bits 0:1 - Response PID"]
    #[inline(always)]
    #[must_use]
    pub fn pid(&mut self) -> PID_W<0> {
        PID_W::new(self)
    }
    #[doc = "Bit 2 - Control Transfer End Enable"]
    #[inline(always)]
    #[must_use]
    pub fn ccpl(&mut self) -> CCPL_W<2> {
        CCPL_W::new(self)
    }
    #[doc = "Bit 7 - Sequence Toggle Bit Set"]
    #[inline(always)]
    #[must_use]
    pub fn sqset(&mut self) -> SQSET_W<7> {
        SQSET_W::new(self)
    }
    #[doc = "Bit 8 - Sequence Toggle Bit Clear"]
    #[inline(always)]
    #[must_use]
    pub fn sqclr(&mut self) -> SQCLR_W<8> {
        SQCLR_W::new(self)
    }
    #[doc = "Bit 11 - SUREQ Bit Clear"]
    #[inline(always)]
    #[must_use]
    pub fn sureqclr(&mut self) -> SUREQCLR_W<11> {
        SUREQCLR_W::new(self)
    }
    #[doc = "Bit 14 - Setup Token Transmission"]
    #[inline(always)]
    #[must_use]
    pub fn sureq(&mut self) -> SUREQ_W<14> {
        SUREQ_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "DCP Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcpctr](index.html) module"]
pub struct DCPCTR_SPEC;
impl crate::RegisterSpec for DCPCTR_SPEC {
    type Ux = u16;
}
#[doc = "`read()` method returns [dcpctr::R](R) reader structure"]
impl crate::Readable for DCPCTR_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dcpctr::W](W) writer structure"]
impl crate::Writable for DCPCTR_SPEC {
    type Writer = W;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DCPCTR to value 0x40"]
impl crate::Resettable for DCPCTR_SPEC {
    const RESET_VALUE: Self::Ux = 0x40;
}