1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"USB 2.0 Full-Speed Module"]
28unsafe impl ::core::marker::Send for super::Usbfs {}
29unsafe impl ::core::marker::Sync for super::Usbfs {}
30impl super::Usbfs {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36 #[doc = "System Configuration Control Register"]
37 #[inline(always)]
38 pub const fn syscfg(
39 &self,
40 ) -> &'static crate::common::Reg<self::Syscfg_SPEC, crate::common::RW> {
41 unsafe {
42 crate::common::Reg::<self::Syscfg_SPEC, crate::common::RW>::from_ptr(
43 self._svd2pac_as_ptr().add(0usize),
44 )
45 }
46 }
47
48 #[doc = "System Configuration Status Register 0"]
49 #[inline(always)]
50 pub const fn syssts0(
51 &self,
52 ) -> &'static crate::common::Reg<self::Syssts0_SPEC, crate::common::R> {
53 unsafe {
54 crate::common::Reg::<self::Syssts0_SPEC, crate::common::R>::from_ptr(
55 self._svd2pac_as_ptr().add(4usize),
56 )
57 }
58 }
59
60 #[doc = "Device State Control Register 0"]
61 #[inline(always)]
62 pub const fn dvstctr0(
63 &self,
64 ) -> &'static crate::common::Reg<self::Dvstctr0_SPEC, crate::common::RW> {
65 unsafe {
66 crate::common::Reg::<self::Dvstctr0_SPEC, crate::common::RW>::from_ptr(
67 self._svd2pac_as_ptr().add(8usize),
68 )
69 }
70 }
71
72 #[doc = "CFIFO Port Register"]
73 #[inline(always)]
74 pub const fn cfifo(&self) -> &'static crate::common::Reg<self::Cfifo_SPEC, crate::common::RW> {
75 unsafe {
76 crate::common::Reg::<self::Cfifo_SPEC, crate::common::RW>::from_ptr(
77 self._svd2pac_as_ptr().add(20usize),
78 )
79 }
80 }
81
82 #[doc = "CFIFO Port Register"]
83 #[inline(always)]
84 pub const fn cfifol(
85 &self,
86 ) -> &'static crate::common::Reg<self::Cfifol_SPEC, crate::common::RW> {
87 unsafe {
88 crate::common::Reg::<self::Cfifol_SPEC, crate::common::RW>::from_ptr(
89 self._svd2pac_as_ptr().add(20usize),
90 )
91 }
92 }
93
94 #[doc = "CFIFO Port Select Register"]
95 #[inline(always)]
96 pub const fn cfifosel(
97 &self,
98 ) -> &'static crate::common::Reg<self::Cfifosel_SPEC, crate::common::RW> {
99 unsafe {
100 crate::common::Reg::<self::Cfifosel_SPEC, crate::common::RW>::from_ptr(
101 self._svd2pac_as_ptr().add(32usize),
102 )
103 }
104 }
105
106 #[doc = "CFIFO Port Control Register"]
107 #[inline(always)]
108 pub const fn cfifoctr(
109 &self,
110 ) -> &'static crate::common::Reg<self::Cfifoctr_SPEC, crate::common::RW> {
111 unsafe {
112 crate::common::Reg::<self::Cfifoctr_SPEC, crate::common::RW>::from_ptr(
113 self._svd2pac_as_ptr().add(34usize),
114 )
115 }
116 }
117
118 #[doc = "Interrupt Enable Register 0"]
119 #[inline(always)]
120 pub const fn intenb0(
121 &self,
122 ) -> &'static crate::common::Reg<self::Intenb0_SPEC, crate::common::RW> {
123 unsafe {
124 crate::common::Reg::<self::Intenb0_SPEC, crate::common::RW>::from_ptr(
125 self._svd2pac_as_ptr().add(48usize),
126 )
127 }
128 }
129
130 #[doc = "BRDY Interrupt Enable Register"]
131 #[inline(always)]
132 pub const fn brdyenb(
133 &self,
134 ) -> &'static crate::common::Reg<self::Brdyenb_SPEC, crate::common::RW> {
135 unsafe {
136 crate::common::Reg::<self::Brdyenb_SPEC, crate::common::RW>::from_ptr(
137 self._svd2pac_as_ptr().add(54usize),
138 )
139 }
140 }
141
142 #[doc = "NRDY Interrupt Enable Register"]
143 #[inline(always)]
144 pub const fn nrdyenb(
145 &self,
146 ) -> &'static crate::common::Reg<self::Nrdyenb_SPEC, crate::common::RW> {
147 unsafe {
148 crate::common::Reg::<self::Nrdyenb_SPEC, crate::common::RW>::from_ptr(
149 self._svd2pac_as_ptr().add(56usize),
150 )
151 }
152 }
153
154 #[doc = "BEMP Interrupt Enable Register"]
155 #[inline(always)]
156 pub const fn bempenb(
157 &self,
158 ) -> &'static crate::common::Reg<self::Bempenb_SPEC, crate::common::RW> {
159 unsafe {
160 crate::common::Reg::<self::Bempenb_SPEC, crate::common::RW>::from_ptr(
161 self._svd2pac_as_ptr().add(58usize),
162 )
163 }
164 }
165
166 #[doc = "SOF Output Configuration Register"]
167 #[inline(always)]
168 pub const fn sofcfg(
169 &self,
170 ) -> &'static crate::common::Reg<self::Sofcfg_SPEC, crate::common::RW> {
171 unsafe {
172 crate::common::Reg::<self::Sofcfg_SPEC, crate::common::RW>::from_ptr(
173 self._svd2pac_as_ptr().add(60usize),
174 )
175 }
176 }
177
178 #[doc = "Interrupt Status Register 0"]
179 #[inline(always)]
180 pub const fn intsts0(
181 &self,
182 ) -> &'static crate::common::Reg<self::Intsts0_SPEC, crate::common::RW> {
183 unsafe {
184 crate::common::Reg::<self::Intsts0_SPEC, crate::common::RW>::from_ptr(
185 self._svd2pac_as_ptr().add(64usize),
186 )
187 }
188 }
189
190 #[doc = "BRDY Interrupt Status Register"]
191 #[inline(always)]
192 pub const fn brdysts(
193 &self,
194 ) -> &'static crate::common::Reg<self::Brdysts_SPEC, crate::common::RW> {
195 unsafe {
196 crate::common::Reg::<self::Brdysts_SPEC, crate::common::RW>::from_ptr(
197 self._svd2pac_as_ptr().add(70usize),
198 )
199 }
200 }
201
202 #[doc = "NRDY Interrupt Status Register"]
203 #[inline(always)]
204 pub const fn nrdysts(
205 &self,
206 ) -> &'static crate::common::Reg<self::Nrdysts_SPEC, crate::common::RW> {
207 unsafe {
208 crate::common::Reg::<self::Nrdysts_SPEC, crate::common::RW>::from_ptr(
209 self._svd2pac_as_ptr().add(72usize),
210 )
211 }
212 }
213
214 #[doc = "BEMP Interrupt Status Register"]
215 #[inline(always)]
216 pub const fn bempsts(
217 &self,
218 ) -> &'static crate::common::Reg<self::Bempsts_SPEC, crate::common::RW> {
219 unsafe {
220 crate::common::Reg::<self::Bempsts_SPEC, crate::common::RW>::from_ptr(
221 self._svd2pac_as_ptr().add(74usize),
222 )
223 }
224 }
225
226 #[doc = "Frame Number Register"]
227 #[inline(always)]
228 pub const fn frmnum(&self) -> &'static crate::common::Reg<self::Frmnum_SPEC, crate::common::R> {
229 unsafe {
230 crate::common::Reg::<self::Frmnum_SPEC, crate::common::R>::from_ptr(
231 self._svd2pac_as_ptr().add(76usize),
232 )
233 }
234 }
235
236 #[doc = "Device State Change Register"]
237 #[inline(always)]
238 pub const fn dvchgr(
239 &self,
240 ) -> &'static crate::common::Reg<self::Dvchgr_SPEC, crate::common::RW> {
241 unsafe {
242 crate::common::Reg::<self::Dvchgr_SPEC, crate::common::RW>::from_ptr(
243 self._svd2pac_as_ptr().add(78usize),
244 )
245 }
246 }
247
248 #[doc = "USB Address Register"]
249 #[inline(always)]
250 pub const fn usbaddr(
251 &self,
252 ) -> &'static crate::common::Reg<self::Usbaddr_SPEC, crate::common::RW> {
253 unsafe {
254 crate::common::Reg::<self::Usbaddr_SPEC, crate::common::RW>::from_ptr(
255 self._svd2pac_as_ptr().add(80usize),
256 )
257 }
258 }
259
260 #[doc = "USB Request Type Register"]
261 #[inline(always)]
262 pub const fn usbreq(&self) -> &'static crate::common::Reg<self::Usbreq_SPEC, crate::common::R> {
263 unsafe {
264 crate::common::Reg::<self::Usbreq_SPEC, crate::common::R>::from_ptr(
265 self._svd2pac_as_ptr().add(84usize),
266 )
267 }
268 }
269
270 #[doc = "USB Request Value Register"]
271 #[inline(always)]
272 pub const fn usbval(&self) -> &'static crate::common::Reg<self::Usbval_SPEC, crate::common::R> {
273 unsafe {
274 crate::common::Reg::<self::Usbval_SPEC, crate::common::R>::from_ptr(
275 self._svd2pac_as_ptr().add(86usize),
276 )
277 }
278 }
279
280 #[doc = "USB Request Index Register"]
281 #[inline(always)]
282 pub const fn usbindx(
283 &self,
284 ) -> &'static crate::common::Reg<self::Usbindx_SPEC, crate::common::R> {
285 unsafe {
286 crate::common::Reg::<self::Usbindx_SPEC, crate::common::R>::from_ptr(
287 self._svd2pac_as_ptr().add(88usize),
288 )
289 }
290 }
291
292 #[doc = "USB Request Length Register"]
293 #[inline(always)]
294 pub const fn usbleng(
295 &self,
296 ) -> &'static crate::common::Reg<self::Usbleng_SPEC, crate::common::R> {
297 unsafe {
298 crate::common::Reg::<self::Usbleng_SPEC, crate::common::R>::from_ptr(
299 self._svd2pac_as_ptr().add(90usize),
300 )
301 }
302 }
303
304 #[doc = "DCP Configuration Register"]
305 #[inline(always)]
306 pub const fn dcpcfg(
307 &self,
308 ) -> &'static crate::common::Reg<self::Dcpcfg_SPEC, crate::common::RW> {
309 unsafe {
310 crate::common::Reg::<self::Dcpcfg_SPEC, crate::common::RW>::from_ptr(
311 self._svd2pac_as_ptr().add(92usize),
312 )
313 }
314 }
315
316 #[doc = "DCP Maximum Packet Size Register"]
317 #[inline(always)]
318 pub const fn dcpmaxp(
319 &self,
320 ) -> &'static crate::common::Reg<self::Dcpmaxp_SPEC, crate::common::RW> {
321 unsafe {
322 crate::common::Reg::<self::Dcpmaxp_SPEC, crate::common::RW>::from_ptr(
323 self._svd2pac_as_ptr().add(94usize),
324 )
325 }
326 }
327
328 #[doc = "DCP Control Register"]
329 #[inline(always)]
330 pub const fn dcpctr(
331 &self,
332 ) -> &'static crate::common::Reg<self::Dcpctr_SPEC, crate::common::RW> {
333 unsafe {
334 crate::common::Reg::<self::Dcpctr_SPEC, crate::common::RW>::from_ptr(
335 self._svd2pac_as_ptr().add(96usize),
336 )
337 }
338 }
339
340 #[doc = "Pipe Window Select Register"]
341 #[inline(always)]
342 pub const fn pipesel(
343 &self,
344 ) -> &'static crate::common::Reg<self::Pipesel_SPEC, crate::common::RW> {
345 unsafe {
346 crate::common::Reg::<self::Pipesel_SPEC, crate::common::RW>::from_ptr(
347 self._svd2pac_as_ptr().add(100usize),
348 )
349 }
350 }
351
352 #[doc = "Pipe Configuration Register"]
353 #[inline(always)]
354 pub const fn pipecfg(
355 &self,
356 ) -> &'static crate::common::Reg<self::Pipecfg_SPEC, crate::common::RW> {
357 unsafe {
358 crate::common::Reg::<self::Pipecfg_SPEC, crate::common::RW>::from_ptr(
359 self._svd2pac_as_ptr().add(104usize),
360 )
361 }
362 }
363
364 #[doc = "Pipe Maximum Packet Size Register"]
365 #[inline(always)]
366 pub const fn pipemaxp(
367 &self,
368 ) -> &'static crate::common::Reg<self::Pipemaxp_SPEC, crate::common::RW> {
369 unsafe {
370 crate::common::Reg::<self::Pipemaxp_SPEC, crate::common::RW>::from_ptr(
371 self._svd2pac_as_ptr().add(108usize),
372 )
373 }
374 }
375
376 #[doc = "PIPE%s Control Registers"]
377 #[inline(always)]
378 pub const fn pipectr(
379 &self,
380 ) -> &'static crate::common::ClusterRegisterArray<
381 crate::common::Reg<self::Pipectr_SPEC, crate::common::RW>,
382 2,
383 0x2,
384 > {
385 unsafe {
386 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x7ausize))
387 }
388 }
389
390 #[doc = "PIPE%s Transaction Counter Enable Register"]
391 #[inline(always)]
392 pub const fn pipetre(
393 &self,
394 ) -> &'static crate::common::ClusterRegisterArray<
395 crate::common::Reg<self::Pipetre_SPEC, crate::common::RW>,
396 2,
397 0x4,
398 > {
399 unsafe {
400 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x9cusize))
401 }
402 }
403
404 #[doc = "PIPE%s Transaction Counter Register"]
405 #[inline(always)]
406 pub const fn pipetrn(
407 &self,
408 ) -> &'static crate::common::ClusterRegisterArray<
409 crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW>,
410 2,
411 0x4,
412 > {
413 unsafe {
414 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x9eusize))
415 }
416 }
417
418 #[doc = "PHY Single-ended Receiver Control Register"]
419 #[inline(always)]
420 pub const fn physectrl(
421 &self,
422 ) -> &'static crate::common::Reg<self::Physectrl_SPEC, crate::common::RW> {
423 unsafe {
424 crate::common::Reg::<self::Physectrl_SPEC, crate::common::RW>::from_ptr(
425 self._svd2pac_as_ptr().add(244usize),
426 )
427 }
428 }
429
430 #[doc = "Deep Software Standby USB Transceiver Control/Pin Monitor Register"]
431 #[inline(always)]
432 pub const fn dpusr0r(
433 &self,
434 ) -> &'static crate::common::Reg<self::Dpusr0R_SPEC, crate::common::RW> {
435 unsafe {
436 crate::common::Reg::<self::Dpusr0R_SPEC, crate::common::RW>::from_ptr(
437 self._svd2pac_as_ptr().add(1024usize),
438 )
439 }
440 }
441
442 #[doc = "Deep Software Standby USB Suspend/Resume Interrupt Register"]
443 #[inline(always)]
444 pub const fn dpusr1r(
445 &self,
446 ) -> &'static crate::common::Reg<self::Dpusr1R_SPEC, crate::common::RW> {
447 unsafe {
448 crate::common::Reg::<self::Dpusr1R_SPEC, crate::common::RW>::from_ptr(
449 self._svd2pac_as_ptr().add(1028usize),
450 )
451 }
452 }
453}
454#[doc(hidden)]
455#[derive(Copy, Clone, Eq, PartialEq)]
456pub struct Syscfg_SPEC;
457impl crate::sealed::RegSpec for Syscfg_SPEC {
458 type DataType = u16;
459}
460#[doc = "System Configuration Control Register"]
461pub type Syscfg = crate::RegValueT<Syscfg_SPEC>;
462
463impl Syscfg {
464 #[doc = "USBFS Operation Enable"]
465 #[inline(always)]
466 pub fn usbe(
467 self,
468 ) -> crate::common::RegisterField<0, 0x1, 1, 0, syscfg::Usbe, Syscfg_SPEC, crate::common::RW>
469 {
470 crate::common::RegisterField::<0,0x1,1,0,syscfg::Usbe, Syscfg_SPEC,crate::common::RW>::from_register(self,0)
471 }
472 #[doc = "D+ Line Resistor Control"]
473 #[inline(always)]
474 pub fn dprpu(
475 self,
476 ) -> crate::common::RegisterField<4, 0x1, 1, 0, syscfg::Dprpu, Syscfg_SPEC, crate::common::RW>
477 {
478 crate::common::RegisterField::<4,0x1,1,0,syscfg::Dprpu, Syscfg_SPEC,crate::common::RW>::from_register(self,0)
479 }
480 #[doc = "USB Clock Enable"]
481 #[inline(always)]
482 pub fn scke(
483 self,
484 ) -> crate::common::RegisterField<10, 0x1, 1, 0, syscfg::Scke, Syscfg_SPEC, crate::common::RW>
485 {
486 crate::common::RegisterField::<10,0x1,1,0,syscfg::Scke, Syscfg_SPEC,crate::common::RW>::from_register(self,0)
487 }
488}
489impl ::core::default::Default for Syscfg {
490 #[inline(always)]
491 fn default() -> Syscfg {
492 <crate::RegValueT<Syscfg_SPEC> as RegisterValue<_>>::new(0)
493 }
494}
495pub mod syscfg {
496
497 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
498 pub struct Usbe_SPEC;
499 pub type Usbe = crate::EnumBitfieldStruct<u8, Usbe_SPEC>;
500 impl Usbe {
501 #[doc = "Disable"]
502 pub const _0: Self = Self::new(0);
503 #[doc = "Enable"]
504 pub const _1: Self = Self::new(1);
505 }
506 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
507 pub struct Dprpu_SPEC;
508 pub type Dprpu = crate::EnumBitfieldStruct<u8, Dprpu_SPEC>;
509 impl Dprpu {
510 #[doc = "Disable line pull-up"]
511 pub const _0: Self = Self::new(0);
512 #[doc = "Enable line pull-up"]
513 pub const _1: Self = Self::new(1);
514 }
515 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
516 pub struct Scke_SPEC;
517 pub type Scke = crate::EnumBitfieldStruct<u8, Scke_SPEC>;
518 impl Scke {
519 #[doc = "Stop clock supply to the USBFS"]
520 pub const _0: Self = Self::new(0);
521 #[doc = "Enable clock supply to the USBFS"]
522 pub const _1: Self = Self::new(1);
523 }
524}
525#[doc(hidden)]
526#[derive(Copy, Clone, Eq, PartialEq)]
527pub struct Syssts0_SPEC;
528impl crate::sealed::RegSpec for Syssts0_SPEC {
529 type DataType = u16;
530}
531#[doc = "System Configuration Status Register 0"]
532pub type Syssts0 = crate::RegValueT<Syssts0_SPEC>;
533
534impl Syssts0 {
535 #[doc = "USB Data Line Status Monitor"]
536 #[inline(always)]
537 pub fn lnst(
538 self,
539 ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, Syssts0_SPEC, crate::common::R> {
540 crate::common::RegisterField::<0,0x3,1,0,u8, Syssts0_SPEC,crate::common::R>::from_register(self,0)
541 }
542}
543impl ::core::default::Default for Syssts0 {
544 #[inline(always)]
545 fn default() -> Syssts0 {
546 <crate::RegValueT<Syssts0_SPEC> as RegisterValue<_>>::new(0)
547 }
548}
549
550#[doc(hidden)]
551#[derive(Copy, Clone, Eq, PartialEq)]
552pub struct Dvstctr0_SPEC;
553impl crate::sealed::RegSpec for Dvstctr0_SPEC {
554 type DataType = u16;
555}
556#[doc = "Device State Control Register 0"]
557pub type Dvstctr0 = crate::RegValueT<Dvstctr0_SPEC>;
558
559impl Dvstctr0 {
560 #[doc = "USB Bus Reset Status"]
561 #[inline(always)]
562 pub fn rhst(
563 self,
564 ) -> crate::common::RegisterField<0, 0x7, 1, 0, dvstctr0::Rhst, Dvstctr0_SPEC, crate::common::R>
565 {
566 crate::common::RegisterField::<0,0x7,1,0,dvstctr0::Rhst, Dvstctr0_SPEC,crate::common::R>::from_register(self,0)
567 }
568 #[doc = "Wakeup Output"]
569 #[inline(always)]
570 pub fn wkup(
571 self,
572 ) -> crate::common::RegisterField<8, 0x1, 1, 0, dvstctr0::Wkup, Dvstctr0_SPEC, crate::common::RW>
573 {
574 crate::common::RegisterField::<8,0x1,1,0,dvstctr0::Wkup, Dvstctr0_SPEC,crate::common::RW>::from_register(self,0)
575 }
576}
577impl ::core::default::Default for Dvstctr0 {
578 #[inline(always)]
579 fn default() -> Dvstctr0 {
580 <crate::RegValueT<Dvstctr0_SPEC> as RegisterValue<_>>::new(0)
581 }
582}
583pub mod dvstctr0 {
584
585 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
586 pub struct Rhst_SPEC;
587 pub type Rhst = crate::EnumBitfieldStruct<u8, Rhst_SPEC>;
588 impl Rhst {
589 #[doc = "Communication speed indeterminate"]
590 pub const _000: Self = Self::new(0);
591 #[doc = "USB bus reset in progress"]
592 pub const _001: Self = Self::new(1);
593 #[doc = "USB bus reset in progress or full-speed connection"]
594 pub const _010: Self = Self::new(2);
595 #[doc = "Setting prohibited"]
596 pub const OTHERS: Self = Self::new(0);
597 }
598 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
599 pub struct Wkup_SPEC;
600 pub type Wkup = crate::EnumBitfieldStruct<u8, Wkup_SPEC>;
601 impl Wkup {
602 #[doc = "Do not output remote wakeup signal"]
603 pub const _0: Self = Self::new(0);
604 #[doc = "Output remote wakeup signal"]
605 pub const _1: Self = Self::new(1);
606 }
607}
608#[doc(hidden)]
609#[derive(Copy, Clone, Eq, PartialEq)]
610pub struct Cfifo_SPEC;
611impl crate::sealed::RegSpec for Cfifo_SPEC {
612 type DataType = u16;
613}
614#[doc = "CFIFO Port Register"]
615pub type Cfifo = crate::RegValueT<Cfifo_SPEC>;
616
617impl Cfifo {
618 #[doc = "FIFO Port"]
619 #[inline(always)]
620 pub fn fifoport(
621 self,
622 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, Cfifo_SPEC, crate::common::RW> {
623 crate::common::RegisterField::<0,0xffff,1,0,u16, Cfifo_SPEC,crate::common::RW>::from_register(self,0)
624 }
625}
626impl ::core::default::Default for Cfifo {
627 #[inline(always)]
628 fn default() -> Cfifo {
629 <crate::RegValueT<Cfifo_SPEC> as RegisterValue<_>>::new(0)
630 }
631}
632
633#[doc(hidden)]
634#[derive(Copy, Clone, Eq, PartialEq)]
635pub struct Cfifol_SPEC;
636impl crate::sealed::RegSpec for Cfifol_SPEC {
637 type DataType = u8;
638}
639#[doc = "CFIFO Port Register"]
640pub type Cfifol = crate::RegValueT<Cfifol_SPEC>;
641
642impl Cfifol {
643 #[doc = "FIFO Port"]
644 #[inline(always)]
645 pub fn fifoport(
646 self,
647 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, Cfifol_SPEC, crate::common::RW> {
648 crate::common::RegisterField::<0,0xff,1,0,u8, Cfifol_SPEC,crate::common::RW>::from_register(self,0)
649 }
650}
651impl ::core::default::Default for Cfifol {
652 #[inline(always)]
653 fn default() -> Cfifol {
654 <crate::RegValueT<Cfifol_SPEC> as RegisterValue<_>>::new(0)
655 }
656}
657
658#[doc(hidden)]
659#[derive(Copy, Clone, Eq, PartialEq)]
660pub struct Cfifosel_SPEC;
661impl crate::sealed::RegSpec for Cfifosel_SPEC {
662 type DataType = u16;
663}
664#[doc = "CFIFO Port Select Register"]
665pub type Cfifosel = crate::RegValueT<Cfifosel_SPEC>;
666
667impl Cfifosel {
668 #[doc = "CFIFO Port Access Pipe Specification"]
669 #[inline(always)]
670 pub fn curpipe(
671 self,
672 ) -> crate::common::RegisterField<
673 0,
674 0xf,
675 1,
676 0,
677 cfifosel::Curpipe,
678 Cfifosel_SPEC,
679 crate::common::RW,
680 > {
681 crate::common::RegisterField::<
682 0,
683 0xf,
684 1,
685 0,
686 cfifosel::Curpipe,
687 Cfifosel_SPEC,
688 crate::common::RW,
689 >::from_register(self, 0)
690 }
691 #[doc = "CFIFO Port Access Direction When DCP Is Selected"]
692 #[inline(always)]
693 pub fn isel(
694 self,
695 ) -> crate::common::RegisterField<5, 0x1, 1, 0, cfifosel::Isel, Cfifosel_SPEC, crate::common::RW>
696 {
697 crate::common::RegisterField::<5,0x1,1,0,cfifosel::Isel, Cfifosel_SPEC,crate::common::RW>::from_register(self,0)
698 }
699 #[doc = "CFIFO Port Endian Control"]
700 #[inline(always)]
701 pub fn bigend(
702 self,
703 ) -> crate::common::RegisterField<
704 8,
705 0x1,
706 1,
707 0,
708 cfifosel::Bigend,
709 Cfifosel_SPEC,
710 crate::common::RW,
711 > {
712 crate::common::RegisterField::<
713 8,
714 0x1,
715 1,
716 0,
717 cfifosel::Bigend,
718 Cfifosel_SPEC,
719 crate::common::RW,
720 >::from_register(self, 0)
721 }
722 #[doc = "CFIFO Port Access Bit Width"]
723 #[inline(always)]
724 pub fn mbw(
725 self,
726 ) -> crate::common::RegisterField<10, 0x1, 1, 0, cfifosel::Mbw, Cfifosel_SPEC, crate::common::RW>
727 {
728 crate::common::RegisterField::<10,0x1,1,0,cfifosel::Mbw, Cfifosel_SPEC,crate::common::RW>::from_register(self,0)
729 }
730 #[doc = "Buffer Pointer Rewind"]
731 #[inline(always)]
732 pub fn rew(
733 self,
734 ) -> crate::common::RegisterField<14, 0x1, 1, 0, cfifosel::Rew, Cfifosel_SPEC, crate::common::W>
735 {
736 crate::common::RegisterField::<14,0x1,1,0,cfifosel::Rew, Cfifosel_SPEC,crate::common::W>::from_register(self,0)
737 }
738 #[doc = "Read Count Mode"]
739 #[inline(always)]
740 pub fn rcnt(
741 self,
742 ) -> crate::common::RegisterField<15, 0x1, 1, 0, cfifosel::Rcnt, Cfifosel_SPEC, crate::common::RW>
743 {
744 crate::common::RegisterField::<
745 15,
746 0x1,
747 1,
748 0,
749 cfifosel::Rcnt,
750 Cfifosel_SPEC,
751 crate::common::RW,
752 >::from_register(self, 0)
753 }
754}
755impl ::core::default::Default for Cfifosel {
756 #[inline(always)]
757 fn default() -> Cfifosel {
758 <crate::RegValueT<Cfifosel_SPEC> as RegisterValue<_>>::new(0)
759 }
760}
761pub mod cfifosel {
762
763 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
764 pub struct Curpipe_SPEC;
765 pub type Curpipe = crate::EnumBitfieldStruct<u8, Curpipe_SPEC>;
766 impl Curpipe {
767 #[doc = "Default Control Pipe"]
768 pub const _0_X_0: Self = Self::new(0);
769 #[doc = "Pipe 4"]
770 pub const _0_X_4: Self = Self::new(4);
771 #[doc = "Pipe 5"]
772 pub const _0_X_5: Self = Self::new(5);
773 #[doc = "Pipe 6"]
774 pub const _0_X_6: Self = Self::new(6);
775 #[doc = "Pipe 7"]
776 pub const _0_X_7: Self = Self::new(7);
777 #[doc = "Setting prohibited"]
778 pub const OTHERS: Self = Self::new(0);
779 }
780 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
781 pub struct Isel_SPEC;
782 pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
783 impl Isel {
784 #[doc = "Select reading from the FIFO buffer"]
785 pub const _0: Self = Self::new(0);
786 #[doc = "Select writing to the FIFO buffer"]
787 pub const _1: Self = Self::new(1);
788 }
789 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
790 pub struct Bigend_SPEC;
791 pub type Bigend = crate::EnumBitfieldStruct<u8, Bigend_SPEC>;
792 impl Bigend {
793 #[doc = "Little endian"]
794 pub const _0: Self = Self::new(0);
795 #[doc = "Big endian"]
796 pub const _1: Self = Self::new(1);
797 }
798 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
799 pub struct Mbw_SPEC;
800 pub type Mbw = crate::EnumBitfieldStruct<u8, Mbw_SPEC>;
801 impl Mbw {
802 #[doc = "8-bit width"]
803 pub const _0: Self = Self::new(0);
804 #[doc = "16-bit width"]
805 pub const _1: Self = Self::new(1);
806 }
807 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
808 pub struct Rew_SPEC;
809 pub type Rew = crate::EnumBitfieldStruct<u8, Rew_SPEC>;
810 impl Rew {
811 #[doc = "Do not rewind buffer pointer"]
812 pub const _0: Self = Self::new(0);
813 #[doc = "Rewind buffer pointer"]
814 pub const _1: Self = Self::new(1);
815 }
816 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
817 pub struct Rcnt_SPEC;
818 pub type Rcnt = crate::EnumBitfieldStruct<u8, Rcnt_SPEC>;
819 impl Rcnt {
820 #[doc = "The DTLN\\[8:0\\] bits (CFIFOCTR.DTLN\\[8:0\\]) are cleared when all receive data is read from the CFIFO. In double buffer mode, the DTLN\\[8:0\\] value is cleared when all data is read from only a single plane."]
821 pub const _0: Self = Self::new(0);
822 #[doc = "The DTLN\\[8:0\\] bits are decremented each time the receive data is read from the CFIFO."]
823 pub const _1: Self = Self::new(1);
824 }
825}
826#[doc(hidden)]
827#[derive(Copy, Clone, Eq, PartialEq)]
828pub struct Cfifoctr_SPEC;
829impl crate::sealed::RegSpec for Cfifoctr_SPEC {
830 type DataType = u16;
831}
832#[doc = "CFIFO Port Control Register"]
833pub type Cfifoctr = crate::RegValueT<Cfifoctr_SPEC>;
834
835impl Cfifoctr {
836 #[doc = "Receive Data Length"]
837 #[inline(always)]
838 pub fn dtln(
839 self,
840 ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, Cfifoctr_SPEC, crate::common::R> {
841 crate::common::RegisterField::<0,0x1ff,1,0,u16, Cfifoctr_SPEC,crate::common::R>::from_register(self,0)
842 }
843 #[doc = "FIFO Port Ready"]
844 #[inline(always)]
845 pub fn frdy(
846 self,
847 ) -> crate::common::RegisterField<13, 0x1, 1, 0, cfifoctr::Frdy, Cfifoctr_SPEC, crate::common::R>
848 {
849 crate::common::RegisterField::<13,0x1,1,0,cfifoctr::Frdy, Cfifoctr_SPEC,crate::common::R>::from_register(self,0)
850 }
851 #[doc = "CPU Buffer Clear"]
852 #[inline(always)]
853 pub fn bclr(
854 self,
855 ) -> crate::common::RegisterField<14, 0x1, 1, 0, cfifoctr::Bclr, Cfifoctr_SPEC, crate::common::W>
856 {
857 crate::common::RegisterField::<14,0x1,1,0,cfifoctr::Bclr, Cfifoctr_SPEC,crate::common::W>::from_register(self,0)
858 }
859 #[doc = "Buffer Memory Valid Flag"]
860 #[inline(always)]
861 pub fn bval(
862 self,
863 ) -> crate::common::RegisterField<15, 0x1, 1, 0, cfifoctr::Bval, Cfifoctr_SPEC, crate::common::RW>
864 {
865 crate::common::RegisterField::<
866 15,
867 0x1,
868 1,
869 0,
870 cfifoctr::Bval,
871 Cfifoctr_SPEC,
872 crate::common::RW,
873 >::from_register(self, 0)
874 }
875}
876impl ::core::default::Default for Cfifoctr {
877 #[inline(always)]
878 fn default() -> Cfifoctr {
879 <crate::RegValueT<Cfifoctr_SPEC> as RegisterValue<_>>::new(0)
880 }
881}
882pub mod cfifoctr {
883
884 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
885 pub struct Frdy_SPEC;
886 pub type Frdy = crate::EnumBitfieldStruct<u8, Frdy_SPEC>;
887 impl Frdy {
888 #[doc = "FIFO port access disabled"]
889 pub const _0: Self = Self::new(0);
890 #[doc = "FIFO port access enabled"]
891 pub const _1: Self = Self::new(1);
892 }
893 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
894 pub struct Bclr_SPEC;
895 pub type Bclr = crate::EnumBitfieldStruct<u8, Bclr_SPEC>;
896 impl Bclr {
897 #[doc = "No operation"]
898 pub const _0: Self = Self::new(0);
899 #[doc = "Clear FIFO buffer on the CPU side"]
900 pub const _1: Self = Self::new(1);
901 }
902 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
903 pub struct Bval_SPEC;
904 pub type Bval = crate::EnumBitfieldStruct<u8, Bval_SPEC>;
905 impl Bval {
906 #[doc = "Invalid (writing 0 has no effect)"]
907 pub const _0: Self = Self::new(0);
908 #[doc = "Writing ended"]
909 pub const _1: Self = Self::new(1);
910 }
911}
912#[doc(hidden)]
913#[derive(Copy, Clone, Eq, PartialEq)]
914pub struct Intenb0_SPEC;
915impl crate::sealed::RegSpec for Intenb0_SPEC {
916 type DataType = u16;
917}
918#[doc = "Interrupt Enable Register 0"]
919pub type Intenb0 = crate::RegValueT<Intenb0_SPEC>;
920
921impl Intenb0 {
922 #[doc = "Buffer Ready Interrupt Enable"]
923 #[inline(always)]
924 pub fn brdye(
925 self,
926 ) -> crate::common::RegisterField<8, 0x1, 1, 0, intenb0::Brdye, Intenb0_SPEC, crate::common::RW>
927 {
928 crate::common::RegisterField::<8,0x1,1,0,intenb0::Brdye, Intenb0_SPEC,crate::common::RW>::from_register(self,0)
929 }
930 #[doc = "Buffer Not Ready Response Interrupt Enable"]
931 #[inline(always)]
932 pub fn nrdye(
933 self,
934 ) -> crate::common::RegisterField<9, 0x1, 1, 0, intenb0::Nrdye, Intenb0_SPEC, crate::common::RW>
935 {
936 crate::common::RegisterField::<9,0x1,1,0,intenb0::Nrdye, Intenb0_SPEC,crate::common::RW>::from_register(self,0)
937 }
938 #[doc = "Buffer Empty Interrupt Enable"]
939 #[inline(always)]
940 pub fn bempe(
941 self,
942 ) -> crate::common::RegisterField<10, 0x1, 1, 0, intenb0::Bempe, Intenb0_SPEC, crate::common::RW>
943 {
944 crate::common::RegisterField::<10,0x1,1,0,intenb0::Bempe, Intenb0_SPEC,crate::common::RW>::from_register(self,0)
945 }
946 #[doc = "Control Transfer Stage Transition Interrupt Enable"]
947 #[inline(always)]
948 pub fn ctre(
949 self,
950 ) -> crate::common::RegisterField<11, 0x1, 1, 0, intenb0::Ctre, Intenb0_SPEC, crate::common::RW>
951 {
952 crate::common::RegisterField::<11,0x1,1,0,intenb0::Ctre, Intenb0_SPEC,crate::common::RW>::from_register(self,0)
953 }
954 #[doc = "Device State Transition Interrupt Enable"]
955 #[inline(always)]
956 pub fn dvse(
957 self,
958 ) -> crate::common::RegisterField<12, 0x1, 1, 0, intenb0::Dvse, Intenb0_SPEC, crate::common::RW>
959 {
960 crate::common::RegisterField::<12,0x1,1,0,intenb0::Dvse, Intenb0_SPEC,crate::common::RW>::from_register(self,0)
961 }
962 #[doc = "Frame Number Update Interrupt Enable"]
963 #[inline(always)]
964 pub fn sofe(
965 self,
966 ) -> crate::common::RegisterField<13, 0x1, 1, 0, intenb0::Sofe, Intenb0_SPEC, crate::common::RW>
967 {
968 crate::common::RegisterField::<13,0x1,1,0,intenb0::Sofe, Intenb0_SPEC,crate::common::RW>::from_register(self,0)
969 }
970 #[doc = "Resume Interrupt Enable"]
971 #[inline(always)]
972 pub fn rsme(
973 self,
974 ) -> crate::common::RegisterField<14, 0x1, 1, 0, intenb0::Rsme, Intenb0_SPEC, crate::common::RW>
975 {
976 crate::common::RegisterField::<14,0x1,1,0,intenb0::Rsme, Intenb0_SPEC,crate::common::RW>::from_register(self,0)
977 }
978 #[doc = "VBUS Interrupt Enable"]
979 #[inline(always)]
980 pub fn vbse(
981 self,
982 ) -> crate::common::RegisterField<15, 0x1, 1, 0, intenb0::Vbse, Intenb0_SPEC, crate::common::RW>
983 {
984 crate::common::RegisterField::<15,0x1,1,0,intenb0::Vbse, Intenb0_SPEC,crate::common::RW>::from_register(self,0)
985 }
986}
987impl ::core::default::Default for Intenb0 {
988 #[inline(always)]
989 fn default() -> Intenb0 {
990 <crate::RegValueT<Intenb0_SPEC> as RegisterValue<_>>::new(0)
991 }
992}
993pub mod intenb0 {
994
995 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
996 pub struct Brdye_SPEC;
997 pub type Brdye = crate::EnumBitfieldStruct<u8, Brdye_SPEC>;
998 impl Brdye {
999 #[doc = "Disable interrupt request"]
1000 pub const _0: Self = Self::new(0);
1001 #[doc = "Enable interrupt request"]
1002 pub const _1: Self = Self::new(1);
1003 }
1004 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1005 pub struct Nrdye_SPEC;
1006 pub type Nrdye = crate::EnumBitfieldStruct<u8, Nrdye_SPEC>;
1007 impl Nrdye {
1008 #[doc = "Disable interrupt request"]
1009 pub const _0: Self = Self::new(0);
1010 #[doc = "Enable interrupt request"]
1011 pub const _1: Self = Self::new(1);
1012 }
1013 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1014 pub struct Bempe_SPEC;
1015 pub type Bempe = crate::EnumBitfieldStruct<u8, Bempe_SPEC>;
1016 impl Bempe {
1017 #[doc = "Disable interrupt request"]
1018 pub const _0: Self = Self::new(0);
1019 #[doc = "Enable interrupt request"]
1020 pub const _1: Self = Self::new(1);
1021 }
1022 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1023 pub struct Ctre_SPEC;
1024 pub type Ctre = crate::EnumBitfieldStruct<u8, Ctre_SPEC>;
1025 impl Ctre {
1026 #[doc = "Disable interrupt request"]
1027 pub const _0: Self = Self::new(0);
1028 #[doc = "Enable interrupt request"]
1029 pub const _1: Self = Self::new(1);
1030 }
1031 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1032 pub struct Dvse_SPEC;
1033 pub type Dvse = crate::EnumBitfieldStruct<u8, Dvse_SPEC>;
1034 impl Dvse {
1035 #[doc = "Disable interrupt request"]
1036 pub const _0: Self = Self::new(0);
1037 #[doc = "Enable interrupt request"]
1038 pub const _1: Self = Self::new(1);
1039 }
1040 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1041 pub struct Sofe_SPEC;
1042 pub type Sofe = crate::EnumBitfieldStruct<u8, Sofe_SPEC>;
1043 impl Sofe {
1044 #[doc = "Disable interrupt request"]
1045 pub const _0: Self = Self::new(0);
1046 #[doc = "Enable interrupt request"]
1047 pub const _1: Self = Self::new(1);
1048 }
1049 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1050 pub struct Rsme_SPEC;
1051 pub type Rsme = crate::EnumBitfieldStruct<u8, Rsme_SPEC>;
1052 impl Rsme {
1053 #[doc = "Disable interrupt request"]
1054 pub const _0: Self = Self::new(0);
1055 #[doc = "Enable interrupt request"]
1056 pub const _1: Self = Self::new(1);
1057 }
1058 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1059 pub struct Vbse_SPEC;
1060 pub type Vbse = crate::EnumBitfieldStruct<u8, Vbse_SPEC>;
1061 impl Vbse {
1062 #[doc = "Disable interrupt request"]
1063 pub const _0: Self = Self::new(0);
1064 #[doc = "Enable interrupt request"]
1065 pub const _1: Self = Self::new(1);
1066 }
1067}
1068#[doc(hidden)]
1069#[derive(Copy, Clone, Eq, PartialEq)]
1070pub struct Brdyenb_SPEC;
1071impl crate::sealed::RegSpec for Brdyenb_SPEC {
1072 type DataType = u16;
1073}
1074#[doc = "BRDY Interrupt Enable Register"]
1075pub type Brdyenb = crate::RegValueT<Brdyenb_SPEC>;
1076
1077impl Brdyenb {
1078 #[doc = "BRDY Interrupt Enable for Pipe 0"]
1079 #[inline(always)]
1080 pub fn pipe0brdye(
1081 self,
1082 ) -> crate::common::RegisterField<
1083 0,
1084 0x1,
1085 1,
1086 0,
1087 brdyenb::Pipe0Brdye,
1088 Brdyenb_SPEC,
1089 crate::common::RW,
1090 > {
1091 crate::common::RegisterField::<
1092 0,
1093 0x1,
1094 1,
1095 0,
1096 brdyenb::Pipe0Brdye,
1097 Brdyenb_SPEC,
1098 crate::common::RW,
1099 >::from_register(self, 0)
1100 }
1101 #[doc = "BRDY Interrupt Enable for Pipe 4"]
1102 #[inline(always)]
1103 pub fn pipe4brdye(
1104 self,
1105 ) -> crate::common::RegisterField<
1106 4,
1107 0x1,
1108 1,
1109 0,
1110 brdyenb::Pipe4Brdye,
1111 Brdyenb_SPEC,
1112 crate::common::RW,
1113 > {
1114 crate::common::RegisterField::<
1115 4,
1116 0x1,
1117 1,
1118 0,
1119 brdyenb::Pipe4Brdye,
1120 Brdyenb_SPEC,
1121 crate::common::RW,
1122 >::from_register(self, 0)
1123 }
1124 #[doc = "BRDY Interrupt Enable for Pipe 5"]
1125 #[inline(always)]
1126 pub fn pipe5brdye(
1127 self,
1128 ) -> crate::common::RegisterField<
1129 5,
1130 0x1,
1131 1,
1132 0,
1133 brdyenb::Pipe5Brdye,
1134 Brdyenb_SPEC,
1135 crate::common::RW,
1136 > {
1137 crate::common::RegisterField::<
1138 5,
1139 0x1,
1140 1,
1141 0,
1142 brdyenb::Pipe5Brdye,
1143 Brdyenb_SPEC,
1144 crate::common::RW,
1145 >::from_register(self, 0)
1146 }
1147 #[doc = "BRDY Interrupt Enable for Pipe 6"]
1148 #[inline(always)]
1149 pub fn pipe6brdye(
1150 self,
1151 ) -> crate::common::RegisterField<
1152 6,
1153 0x1,
1154 1,
1155 0,
1156 brdyenb::Pipe6Brdye,
1157 Brdyenb_SPEC,
1158 crate::common::RW,
1159 > {
1160 crate::common::RegisterField::<
1161 6,
1162 0x1,
1163 1,
1164 0,
1165 brdyenb::Pipe6Brdye,
1166 Brdyenb_SPEC,
1167 crate::common::RW,
1168 >::from_register(self, 0)
1169 }
1170 #[doc = "BRDY Interrupt Enable for Pipe 7"]
1171 #[inline(always)]
1172 pub fn pipe7brdye(
1173 self,
1174 ) -> crate::common::RegisterField<
1175 7,
1176 0x1,
1177 1,
1178 0,
1179 brdyenb::Pipe7Brdye,
1180 Brdyenb_SPEC,
1181 crate::common::RW,
1182 > {
1183 crate::common::RegisterField::<
1184 7,
1185 0x1,
1186 1,
1187 0,
1188 brdyenb::Pipe7Brdye,
1189 Brdyenb_SPEC,
1190 crate::common::RW,
1191 >::from_register(self, 0)
1192 }
1193}
1194impl ::core::default::Default for Brdyenb {
1195 #[inline(always)]
1196 fn default() -> Brdyenb {
1197 <crate::RegValueT<Brdyenb_SPEC> as RegisterValue<_>>::new(0)
1198 }
1199}
1200pub mod brdyenb {
1201
1202 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1203 pub struct Pipe0Brdye_SPEC;
1204 pub type Pipe0Brdye = crate::EnumBitfieldStruct<u8, Pipe0Brdye_SPEC>;
1205 impl Pipe0Brdye {
1206 #[doc = "Disable interrupt request"]
1207 pub const _0: Self = Self::new(0);
1208 #[doc = "Enable interrupt request"]
1209 pub const _1: Self = Self::new(1);
1210 }
1211 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1212 pub struct Pipe4Brdye_SPEC;
1213 pub type Pipe4Brdye = crate::EnumBitfieldStruct<u8, Pipe4Brdye_SPEC>;
1214 impl Pipe4Brdye {
1215 #[doc = "Disable interrupt request"]
1216 pub const _0: Self = Self::new(0);
1217 #[doc = "Enable interrupt request"]
1218 pub const _1: Self = Self::new(1);
1219 }
1220 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1221 pub struct Pipe5Brdye_SPEC;
1222 pub type Pipe5Brdye = crate::EnumBitfieldStruct<u8, Pipe5Brdye_SPEC>;
1223 impl Pipe5Brdye {
1224 #[doc = "Disable interrupt request"]
1225 pub const _0: Self = Self::new(0);
1226 #[doc = "Enable interrupt request"]
1227 pub const _1: Self = Self::new(1);
1228 }
1229 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1230 pub struct Pipe6Brdye_SPEC;
1231 pub type Pipe6Brdye = crate::EnumBitfieldStruct<u8, Pipe6Brdye_SPEC>;
1232 impl Pipe6Brdye {
1233 #[doc = "Disable interrupt request"]
1234 pub const _0: Self = Self::new(0);
1235 #[doc = "Enable interrupt request"]
1236 pub const _1: Self = Self::new(1);
1237 }
1238 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1239 pub struct Pipe7Brdye_SPEC;
1240 pub type Pipe7Brdye = crate::EnumBitfieldStruct<u8, Pipe7Brdye_SPEC>;
1241 impl Pipe7Brdye {
1242 #[doc = "Disable interrupt request"]
1243 pub const _0: Self = Self::new(0);
1244 #[doc = "Enable interrupt request"]
1245 pub const _1: Self = Self::new(1);
1246 }
1247}
1248#[doc(hidden)]
1249#[derive(Copy, Clone, Eq, PartialEq)]
1250pub struct Nrdyenb_SPEC;
1251impl crate::sealed::RegSpec for Nrdyenb_SPEC {
1252 type DataType = u16;
1253}
1254#[doc = "NRDY Interrupt Enable Register"]
1255pub type Nrdyenb = crate::RegValueT<Nrdyenb_SPEC>;
1256
1257impl Nrdyenb {
1258 #[doc = "NRDY Interrupt Enable for Pipe 0"]
1259 #[inline(always)]
1260 pub fn pipe0nrdye(
1261 self,
1262 ) -> crate::common::RegisterField<
1263 0,
1264 0x1,
1265 1,
1266 0,
1267 nrdyenb::Pipe0Nrdye,
1268 Nrdyenb_SPEC,
1269 crate::common::RW,
1270 > {
1271 crate::common::RegisterField::<
1272 0,
1273 0x1,
1274 1,
1275 0,
1276 nrdyenb::Pipe0Nrdye,
1277 Nrdyenb_SPEC,
1278 crate::common::RW,
1279 >::from_register(self, 0)
1280 }
1281 #[doc = "NRDY Interrupt Enable for Pipe 4"]
1282 #[inline(always)]
1283 pub fn pipe4nrdye(
1284 self,
1285 ) -> crate::common::RegisterField<
1286 4,
1287 0x1,
1288 1,
1289 0,
1290 nrdyenb::Pipe4Nrdye,
1291 Nrdyenb_SPEC,
1292 crate::common::RW,
1293 > {
1294 crate::common::RegisterField::<
1295 4,
1296 0x1,
1297 1,
1298 0,
1299 nrdyenb::Pipe4Nrdye,
1300 Nrdyenb_SPEC,
1301 crate::common::RW,
1302 >::from_register(self, 0)
1303 }
1304 #[doc = "NRDY Interrupt Enable for Pipe 5"]
1305 #[inline(always)]
1306 pub fn pipe5nrdye(
1307 self,
1308 ) -> crate::common::RegisterField<
1309 5,
1310 0x1,
1311 1,
1312 0,
1313 nrdyenb::Pipe5Nrdye,
1314 Nrdyenb_SPEC,
1315 crate::common::RW,
1316 > {
1317 crate::common::RegisterField::<
1318 5,
1319 0x1,
1320 1,
1321 0,
1322 nrdyenb::Pipe5Nrdye,
1323 Nrdyenb_SPEC,
1324 crate::common::RW,
1325 >::from_register(self, 0)
1326 }
1327 #[doc = "NRDY Interrupt Enable for Pipe 6"]
1328 #[inline(always)]
1329 pub fn pipe6nrdye(
1330 self,
1331 ) -> crate::common::RegisterField<
1332 6,
1333 0x1,
1334 1,
1335 0,
1336 nrdyenb::Pipe6Nrdye,
1337 Nrdyenb_SPEC,
1338 crate::common::RW,
1339 > {
1340 crate::common::RegisterField::<
1341 6,
1342 0x1,
1343 1,
1344 0,
1345 nrdyenb::Pipe6Nrdye,
1346 Nrdyenb_SPEC,
1347 crate::common::RW,
1348 >::from_register(self, 0)
1349 }
1350 #[doc = "NRDY Interrupt Enable for Pipe 7"]
1351 #[inline(always)]
1352 pub fn pipe7nrdye(
1353 self,
1354 ) -> crate::common::RegisterField<
1355 7,
1356 0x1,
1357 1,
1358 0,
1359 nrdyenb::Pipe7Nrdye,
1360 Nrdyenb_SPEC,
1361 crate::common::RW,
1362 > {
1363 crate::common::RegisterField::<
1364 7,
1365 0x1,
1366 1,
1367 0,
1368 nrdyenb::Pipe7Nrdye,
1369 Nrdyenb_SPEC,
1370 crate::common::RW,
1371 >::from_register(self, 0)
1372 }
1373}
1374impl ::core::default::Default for Nrdyenb {
1375 #[inline(always)]
1376 fn default() -> Nrdyenb {
1377 <crate::RegValueT<Nrdyenb_SPEC> as RegisterValue<_>>::new(0)
1378 }
1379}
1380pub mod nrdyenb {
1381
1382 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1383 pub struct Pipe0Nrdye_SPEC;
1384 pub type Pipe0Nrdye = crate::EnumBitfieldStruct<u8, Pipe0Nrdye_SPEC>;
1385 impl Pipe0Nrdye {
1386 #[doc = "Disable interrupt request"]
1387 pub const _0: Self = Self::new(0);
1388 #[doc = "Enable interrupt request"]
1389 pub const _1: Self = Self::new(1);
1390 }
1391 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1392 pub struct Pipe4Nrdye_SPEC;
1393 pub type Pipe4Nrdye = crate::EnumBitfieldStruct<u8, Pipe4Nrdye_SPEC>;
1394 impl Pipe4Nrdye {
1395 #[doc = "Disable interrupt request"]
1396 pub const _0: Self = Self::new(0);
1397 #[doc = "Enable interrupt request"]
1398 pub const _1: Self = Self::new(1);
1399 }
1400 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1401 pub struct Pipe5Nrdye_SPEC;
1402 pub type Pipe5Nrdye = crate::EnumBitfieldStruct<u8, Pipe5Nrdye_SPEC>;
1403 impl Pipe5Nrdye {
1404 #[doc = "Disable interrupt request"]
1405 pub const _0: Self = Self::new(0);
1406 #[doc = "Enable interrupt request"]
1407 pub const _1: Self = Self::new(1);
1408 }
1409 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1410 pub struct Pipe6Nrdye_SPEC;
1411 pub type Pipe6Nrdye = crate::EnumBitfieldStruct<u8, Pipe6Nrdye_SPEC>;
1412 impl Pipe6Nrdye {
1413 #[doc = "Disable interrupt request"]
1414 pub const _0: Self = Self::new(0);
1415 #[doc = "Enable interrupt request"]
1416 pub const _1: Self = Self::new(1);
1417 }
1418 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1419 pub struct Pipe7Nrdye_SPEC;
1420 pub type Pipe7Nrdye = crate::EnumBitfieldStruct<u8, Pipe7Nrdye_SPEC>;
1421 impl Pipe7Nrdye {
1422 #[doc = "Disable interrupt request"]
1423 pub const _0: Self = Self::new(0);
1424 #[doc = "Enable interrupt request"]
1425 pub const _1: Self = Self::new(1);
1426 }
1427}
1428#[doc(hidden)]
1429#[derive(Copy, Clone, Eq, PartialEq)]
1430pub struct Bempenb_SPEC;
1431impl crate::sealed::RegSpec for Bempenb_SPEC {
1432 type DataType = u16;
1433}
1434#[doc = "BEMP Interrupt Enable Register"]
1435pub type Bempenb = crate::RegValueT<Bempenb_SPEC>;
1436
1437impl Bempenb {
1438 #[doc = "BEMP Interrupt Enable for Pipe 0"]
1439 #[inline(always)]
1440 pub fn pipe0bempe(
1441 self,
1442 ) -> crate::common::RegisterField<
1443 0,
1444 0x1,
1445 1,
1446 0,
1447 bempenb::Pipe0Bempe,
1448 Bempenb_SPEC,
1449 crate::common::RW,
1450 > {
1451 crate::common::RegisterField::<
1452 0,
1453 0x1,
1454 1,
1455 0,
1456 bempenb::Pipe0Bempe,
1457 Bempenb_SPEC,
1458 crate::common::RW,
1459 >::from_register(self, 0)
1460 }
1461 #[doc = "BEMP Interrupt Enable for Pipe 4"]
1462 #[inline(always)]
1463 pub fn pipe4bempe(
1464 self,
1465 ) -> crate::common::RegisterField<
1466 4,
1467 0x1,
1468 1,
1469 0,
1470 bempenb::Pipe4Bempe,
1471 Bempenb_SPEC,
1472 crate::common::RW,
1473 > {
1474 crate::common::RegisterField::<
1475 4,
1476 0x1,
1477 1,
1478 0,
1479 bempenb::Pipe4Bempe,
1480 Bempenb_SPEC,
1481 crate::common::RW,
1482 >::from_register(self, 0)
1483 }
1484 #[doc = "BEMP Interrupt Enable for Pipe 5"]
1485 #[inline(always)]
1486 pub fn pipe5bempe(
1487 self,
1488 ) -> crate::common::RegisterField<
1489 5,
1490 0x1,
1491 1,
1492 0,
1493 bempenb::Pipe5Bempe,
1494 Bempenb_SPEC,
1495 crate::common::RW,
1496 > {
1497 crate::common::RegisterField::<
1498 5,
1499 0x1,
1500 1,
1501 0,
1502 bempenb::Pipe5Bempe,
1503 Bempenb_SPEC,
1504 crate::common::RW,
1505 >::from_register(self, 0)
1506 }
1507 #[doc = "BEMP Interrupt Enable for Pipe 6"]
1508 #[inline(always)]
1509 pub fn pipe6bempe(
1510 self,
1511 ) -> crate::common::RegisterField<
1512 6,
1513 0x1,
1514 1,
1515 0,
1516 bempenb::Pipe6Bempe,
1517 Bempenb_SPEC,
1518 crate::common::RW,
1519 > {
1520 crate::common::RegisterField::<
1521 6,
1522 0x1,
1523 1,
1524 0,
1525 bempenb::Pipe6Bempe,
1526 Bempenb_SPEC,
1527 crate::common::RW,
1528 >::from_register(self, 0)
1529 }
1530 #[doc = "BEMP Interrupt Enable for Pipe 7"]
1531 #[inline(always)]
1532 pub fn pipe7bempe(
1533 self,
1534 ) -> crate::common::RegisterField<
1535 7,
1536 0x1,
1537 1,
1538 0,
1539 bempenb::Pipe7Bempe,
1540 Bempenb_SPEC,
1541 crate::common::RW,
1542 > {
1543 crate::common::RegisterField::<
1544 7,
1545 0x1,
1546 1,
1547 0,
1548 bempenb::Pipe7Bempe,
1549 Bempenb_SPEC,
1550 crate::common::RW,
1551 >::from_register(self, 0)
1552 }
1553}
1554impl ::core::default::Default for Bempenb {
1555 #[inline(always)]
1556 fn default() -> Bempenb {
1557 <crate::RegValueT<Bempenb_SPEC> as RegisterValue<_>>::new(0)
1558 }
1559}
1560pub mod bempenb {
1561
1562 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1563 pub struct Pipe0Bempe_SPEC;
1564 pub type Pipe0Bempe = crate::EnumBitfieldStruct<u8, Pipe0Bempe_SPEC>;
1565 impl Pipe0Bempe {
1566 #[doc = "Disable interrupt request"]
1567 pub const _0: Self = Self::new(0);
1568 #[doc = "Enable interrupt request"]
1569 pub const _1: Self = Self::new(1);
1570 }
1571 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1572 pub struct Pipe4Bempe_SPEC;
1573 pub type Pipe4Bempe = crate::EnumBitfieldStruct<u8, Pipe4Bempe_SPEC>;
1574 impl Pipe4Bempe {
1575 #[doc = "Disable interrupt request"]
1576 pub const _0: Self = Self::new(0);
1577 #[doc = "Enable interrupt request"]
1578 pub const _1: Self = Self::new(1);
1579 }
1580 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1581 pub struct Pipe5Bempe_SPEC;
1582 pub type Pipe5Bempe = crate::EnumBitfieldStruct<u8, Pipe5Bempe_SPEC>;
1583 impl Pipe5Bempe {
1584 #[doc = "Disable interrupt request"]
1585 pub const _0: Self = Self::new(0);
1586 #[doc = "Enable interrupt request"]
1587 pub const _1: Self = Self::new(1);
1588 }
1589 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1590 pub struct Pipe6Bempe_SPEC;
1591 pub type Pipe6Bempe = crate::EnumBitfieldStruct<u8, Pipe6Bempe_SPEC>;
1592 impl Pipe6Bempe {
1593 #[doc = "Disable interrupt request"]
1594 pub const _0: Self = Self::new(0);
1595 #[doc = "Enable interrupt request"]
1596 pub const _1: Self = Self::new(1);
1597 }
1598 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1599 pub struct Pipe7Bempe_SPEC;
1600 pub type Pipe7Bempe = crate::EnumBitfieldStruct<u8, Pipe7Bempe_SPEC>;
1601 impl Pipe7Bempe {
1602 #[doc = "Disable interrupt request"]
1603 pub const _0: Self = Self::new(0);
1604 #[doc = "Enable interrupt request"]
1605 pub const _1: Self = Self::new(1);
1606 }
1607}
1608#[doc(hidden)]
1609#[derive(Copy, Clone, Eq, PartialEq)]
1610pub struct Sofcfg_SPEC;
1611impl crate::sealed::RegSpec for Sofcfg_SPEC {
1612 type DataType = u16;
1613}
1614#[doc = "SOF Output Configuration Register"]
1615pub type Sofcfg = crate::RegValueT<Sofcfg_SPEC>;
1616
1617impl Sofcfg {
1618 #[doc = "Edge Interrupt Output Status Monitor"]
1619 #[inline(always)]
1620 pub fn edgests(
1621 self,
1622 ) -> crate::common::RegisterFieldBool<4, 1, 0, Sofcfg_SPEC, crate::common::R> {
1623 crate::common::RegisterFieldBool::<4, 1, 0, Sofcfg_SPEC, crate::common::R>::from_register(
1624 self, 0,
1625 )
1626 }
1627 #[doc = "BRDY Interrupt Status Clear Timing"]
1628 #[inline(always)]
1629 pub fn brdym(
1630 self,
1631 ) -> crate::common::RegisterField<6, 0x1, 1, 0, sofcfg::Brdym, Sofcfg_SPEC, crate::common::RW>
1632 {
1633 crate::common::RegisterField::<6,0x1,1,0,sofcfg::Brdym, Sofcfg_SPEC,crate::common::RW>::from_register(self,0)
1634 }
1635}
1636impl ::core::default::Default for Sofcfg {
1637 #[inline(always)]
1638 fn default() -> Sofcfg {
1639 <crate::RegValueT<Sofcfg_SPEC> as RegisterValue<_>>::new(0)
1640 }
1641}
1642pub mod sofcfg {
1643
1644 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1645 pub struct Brdym_SPEC;
1646 pub type Brdym = crate::EnumBitfieldStruct<u8, Brdym_SPEC>;
1647 impl Brdym {
1648 #[doc = "Clear BRDY flag by software"]
1649 pub const _0: Self = Self::new(0);
1650 #[doc = "Clear BRDY flag by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer"]
1651 pub const _1: Self = Self::new(1);
1652 }
1653}
1654#[doc(hidden)]
1655#[derive(Copy, Clone, Eq, PartialEq)]
1656pub struct Intsts0_SPEC;
1657impl crate::sealed::RegSpec for Intsts0_SPEC {
1658 type DataType = u16;
1659}
1660#[doc = "Interrupt Status Register 0"]
1661pub type Intsts0 = crate::RegValueT<Intsts0_SPEC>;
1662
1663impl Intsts0 {
1664 #[doc = "Control Transfer Stage"]
1665 #[inline(always)]
1666 pub fn ctsq(
1667 self,
1668 ) -> crate::common::RegisterField<0, 0x7, 1, 0, intsts0::Ctsq, Intsts0_SPEC, crate::common::R>
1669 {
1670 crate::common::RegisterField::<0,0x7,1,0,intsts0::Ctsq, Intsts0_SPEC,crate::common::R>::from_register(self,0)
1671 }
1672 #[doc = "USB Request Reception"]
1673 #[inline(always)]
1674 pub fn valid(
1675 self,
1676 ) -> crate::common::RegisterField<3, 0x1, 1, 0, intsts0::Valid, Intsts0_SPEC, crate::common::RW>
1677 {
1678 crate::common::RegisterField::<3,0x1,1,0,intsts0::Valid, Intsts0_SPEC,crate::common::RW>::from_register(self,0)
1679 }
1680 #[doc = "Device State"]
1681 #[inline(always)]
1682 pub fn dvsq(
1683 self,
1684 ) -> crate::common::RegisterField<4, 0x7, 1, 0, intsts0::Dvsq, Intsts0_SPEC, crate::common::R>
1685 {
1686 crate::common::RegisterField::<4,0x7,1,0,intsts0::Dvsq, Intsts0_SPEC,crate::common::R>::from_register(self,0)
1687 }
1688 #[doc = "VBUS Input Status"]
1689 #[inline(always)]
1690 pub fn vbsts(
1691 self,
1692 ) -> crate::common::RegisterField<7, 0x1, 1, 0, intsts0::Vbsts, Intsts0_SPEC, crate::common::R>
1693 {
1694 crate::common::RegisterField::<7,0x1,1,0,intsts0::Vbsts, Intsts0_SPEC,crate::common::R>::from_register(self,0)
1695 }
1696 #[doc = "Buffer Ready Interrupt Status"]
1697 #[inline(always)]
1698 pub fn brdy(
1699 self,
1700 ) -> crate::common::RegisterField<8, 0x1, 1, 0, intsts0::Brdy, Intsts0_SPEC, crate::common::R>
1701 {
1702 crate::common::RegisterField::<8,0x1,1,0,intsts0::Brdy, Intsts0_SPEC,crate::common::R>::from_register(self,0)
1703 }
1704 #[doc = "Buffer Not Ready Interrupt Status"]
1705 #[inline(always)]
1706 pub fn nrdy(
1707 self,
1708 ) -> crate::common::RegisterField<9, 0x1, 1, 0, intsts0::Nrdy, Intsts0_SPEC, crate::common::R>
1709 {
1710 crate::common::RegisterField::<9,0x1,1,0,intsts0::Nrdy, Intsts0_SPEC,crate::common::R>::from_register(self,0)
1711 }
1712 #[doc = "Buffer Empty Interrupt Status"]
1713 #[inline(always)]
1714 pub fn bemp(
1715 self,
1716 ) -> crate::common::RegisterField<10, 0x1, 1, 0, intsts0::Bemp, Intsts0_SPEC, crate::common::R>
1717 {
1718 crate::common::RegisterField::<10,0x1,1,0,intsts0::Bemp, Intsts0_SPEC,crate::common::R>::from_register(self,0)
1719 }
1720 #[doc = "Control Transfer Stage Transition Interrupt Status"]
1721 #[inline(always)]
1722 pub fn ctrt(
1723 self,
1724 ) -> crate::common::RegisterField<11, 0x1, 1, 0, intsts0::Ctrt, Intsts0_SPEC, crate::common::RW>
1725 {
1726 crate::common::RegisterField::<11,0x1,1,0,intsts0::Ctrt, Intsts0_SPEC,crate::common::RW>::from_register(self,0)
1727 }
1728 #[doc = "Device State Transition Interrupt Status"]
1729 #[inline(always)]
1730 pub fn dvst(
1731 self,
1732 ) -> crate::common::RegisterField<12, 0x1, 1, 0, intsts0::Dvst, Intsts0_SPEC, crate::common::RW>
1733 {
1734 crate::common::RegisterField::<12,0x1,1,0,intsts0::Dvst, Intsts0_SPEC,crate::common::RW>::from_register(self,0)
1735 }
1736 #[doc = "Frame Number Refresh Interrupt Status"]
1737 #[inline(always)]
1738 pub fn sofr(
1739 self,
1740 ) -> crate::common::RegisterField<13, 0x1, 1, 0, intsts0::Sofr, Intsts0_SPEC, crate::common::RW>
1741 {
1742 crate::common::RegisterField::<13,0x1,1,0,intsts0::Sofr, Intsts0_SPEC,crate::common::RW>::from_register(self,0)
1743 }
1744 #[doc = "Resume Interrupt Status"]
1745 #[inline(always)]
1746 pub fn resm(
1747 self,
1748 ) -> crate::common::RegisterField<14, 0x1, 1, 0, intsts0::Resm, Intsts0_SPEC, crate::common::RW>
1749 {
1750 crate::common::RegisterField::<14,0x1,1,0,intsts0::Resm, Intsts0_SPEC,crate::common::RW>::from_register(self,0)
1751 }
1752 #[doc = "VBUS Interrupt Status"]
1753 #[inline(always)]
1754 pub fn vbint(
1755 self,
1756 ) -> crate::common::RegisterField<15, 0x1, 1, 0, intsts0::Vbint, Intsts0_SPEC, crate::common::RW>
1757 {
1758 crate::common::RegisterField::<15,0x1,1,0,intsts0::Vbint, Intsts0_SPEC,crate::common::RW>::from_register(self,0)
1759 }
1760}
1761impl ::core::default::Default for Intsts0 {
1762 #[inline(always)]
1763 fn default() -> Intsts0 {
1764 <crate::RegValueT<Intsts0_SPEC> as RegisterValue<_>>::new(0)
1765 }
1766}
1767pub mod intsts0 {
1768
1769 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1770 pub struct Ctsq_SPEC;
1771 pub type Ctsq = crate::EnumBitfieldStruct<u8, Ctsq_SPEC>;
1772 impl Ctsq {
1773 #[doc = "Idle or setup stage"]
1774 pub const _000: Self = Self::new(0);
1775 #[doc = "Control read data stage"]
1776 pub const _001: Self = Self::new(1);
1777 #[doc = "Control read status stage"]
1778 pub const _010: Self = Self::new(2);
1779 #[doc = "Control write data stage"]
1780 pub const _011: Self = Self::new(3);
1781 #[doc = "Control write status stage"]
1782 pub const _100: Self = Self::new(4);
1783 #[doc = "Control write (no data) status stage"]
1784 pub const _101: Self = Self::new(5);
1785 #[doc = "Control transfer sequence error"]
1786 pub const _110: Self = Self::new(6);
1787 }
1788 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1789 pub struct Valid_SPEC;
1790 pub type Valid = crate::EnumBitfieldStruct<u8, Valid_SPEC>;
1791 impl Valid {
1792 #[doc = "Setup packet not received"]
1793 pub const _0: Self = Self::new(0);
1794 #[doc = "Setup packet received"]
1795 pub const _1: Self = Self::new(1);
1796 }
1797 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1798 pub struct Dvsq_SPEC;
1799 pub type Dvsq = crate::EnumBitfieldStruct<u8, Dvsq_SPEC>;
1800 impl Dvsq {
1801 #[doc = "Powered state"]
1802 pub const _000: Self = Self::new(0);
1803 #[doc = "Default state"]
1804 pub const _001: Self = Self::new(1);
1805 #[doc = "Address state"]
1806 pub const _010: Self = Self::new(2);
1807 #[doc = "Configured state"]
1808 pub const _011: Self = Self::new(3);
1809 #[doc = "Suspend state"]
1810 pub const OTHERS: Self = Self::new(0);
1811 }
1812 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1813 pub struct Vbsts_SPEC;
1814 pub type Vbsts = crate::EnumBitfieldStruct<u8, Vbsts_SPEC>;
1815 impl Vbsts {
1816 #[doc = "USB_VBUS pin is low"]
1817 pub const _0: Self = Self::new(0);
1818 #[doc = "USB_VBUS pin is high"]
1819 pub const _1: Self = Self::new(1);
1820 }
1821 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1822 pub struct Brdy_SPEC;
1823 pub type Brdy = crate::EnumBitfieldStruct<u8, Brdy_SPEC>;
1824 impl Brdy {
1825 #[doc = "No BRDY interrupt occurred"]
1826 pub const _0: Self = Self::new(0);
1827 #[doc = "BRDY interrupt occurred"]
1828 pub const _1: Self = Self::new(1);
1829 }
1830 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1831 pub struct Nrdy_SPEC;
1832 pub type Nrdy = crate::EnumBitfieldStruct<u8, Nrdy_SPEC>;
1833 impl Nrdy {
1834 #[doc = "No NRDY interrupt occurred"]
1835 pub const _0: Self = Self::new(0);
1836 #[doc = "NRDY interrupt occurred"]
1837 pub const _1: Self = Self::new(1);
1838 }
1839 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1840 pub struct Bemp_SPEC;
1841 pub type Bemp = crate::EnumBitfieldStruct<u8, Bemp_SPEC>;
1842 impl Bemp {
1843 #[doc = "No BEMP interrupt occurred"]
1844 pub const _0: Self = Self::new(0);
1845 #[doc = "BEMP interrupt occurred"]
1846 pub const _1: Self = Self::new(1);
1847 }
1848 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1849 pub struct Ctrt_SPEC;
1850 pub type Ctrt = crate::EnumBitfieldStruct<u8, Ctrt_SPEC>;
1851 impl Ctrt {
1852 #[doc = "No control transfer stage transition interrupt occurred"]
1853 pub const _0: Self = Self::new(0);
1854 #[doc = "Control transfer stage transition interrupt occurred"]
1855 pub const _1: Self = Self::new(1);
1856 }
1857 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1858 pub struct Dvst_SPEC;
1859 pub type Dvst = crate::EnumBitfieldStruct<u8, Dvst_SPEC>;
1860 impl Dvst {
1861 #[doc = "No device state transition interrupt occurred"]
1862 pub const _0: Self = Self::new(0);
1863 #[doc = "Device state transition interrupt occurred"]
1864 pub const _1: Self = Self::new(1);
1865 }
1866 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1867 pub struct Sofr_SPEC;
1868 pub type Sofr = crate::EnumBitfieldStruct<u8, Sofr_SPEC>;
1869 impl Sofr {
1870 #[doc = "No SOF interrupt occurred"]
1871 pub const _0: Self = Self::new(0);
1872 #[doc = "SOF interrupt occurred"]
1873 pub const _1: Self = Self::new(1);
1874 }
1875 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1876 pub struct Resm_SPEC;
1877 pub type Resm = crate::EnumBitfieldStruct<u8, Resm_SPEC>;
1878 impl Resm {
1879 #[doc = "No resume interrupt occurred"]
1880 pub const _0: Self = Self::new(0);
1881 #[doc = "Resume interrupt occurred"]
1882 pub const _1: Self = Self::new(1);
1883 }
1884 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1885 pub struct Vbint_SPEC;
1886 pub type Vbint = crate::EnumBitfieldStruct<u8, Vbint_SPEC>;
1887 impl Vbint {
1888 #[doc = "No VBUS interrupt occurred"]
1889 pub const _0: Self = Self::new(0);
1890 #[doc = "VBUS interrupt occurred"]
1891 pub const _1: Self = Self::new(1);
1892 }
1893}
1894#[doc(hidden)]
1895#[derive(Copy, Clone, Eq, PartialEq)]
1896pub struct Brdysts_SPEC;
1897impl crate::sealed::RegSpec for Brdysts_SPEC {
1898 type DataType = u16;
1899}
1900#[doc = "BRDY Interrupt Status Register"]
1901pub type Brdysts = crate::RegValueT<Brdysts_SPEC>;
1902
1903impl Brdysts {
1904 #[doc = "BRDY Interrupt Status for Pipe 0"]
1905 #[inline(always)]
1906 pub fn pipe0brdy(
1907 self,
1908 ) -> crate::common::RegisterField<
1909 0,
1910 0x1,
1911 1,
1912 0,
1913 brdysts::Pipe0Brdy,
1914 Brdysts_SPEC,
1915 crate::common::RW,
1916 > {
1917 crate::common::RegisterField::<
1918 0,
1919 0x1,
1920 1,
1921 0,
1922 brdysts::Pipe0Brdy,
1923 Brdysts_SPEC,
1924 crate::common::RW,
1925 >::from_register(self, 0)
1926 }
1927 #[doc = "BRDY Interrupt Status for Pipe 4"]
1928 #[inline(always)]
1929 pub fn pipe4brdy(
1930 self,
1931 ) -> crate::common::RegisterField<
1932 4,
1933 0x1,
1934 1,
1935 0,
1936 brdysts::Pipe4Brdy,
1937 Brdysts_SPEC,
1938 crate::common::RW,
1939 > {
1940 crate::common::RegisterField::<
1941 4,
1942 0x1,
1943 1,
1944 0,
1945 brdysts::Pipe4Brdy,
1946 Brdysts_SPEC,
1947 crate::common::RW,
1948 >::from_register(self, 0)
1949 }
1950 #[doc = "BRDY Interrupt Status for Pipe 5"]
1951 #[inline(always)]
1952 pub fn pipe5brdy(
1953 self,
1954 ) -> crate::common::RegisterField<
1955 5,
1956 0x1,
1957 1,
1958 0,
1959 brdysts::Pipe5Brdy,
1960 Brdysts_SPEC,
1961 crate::common::RW,
1962 > {
1963 crate::common::RegisterField::<
1964 5,
1965 0x1,
1966 1,
1967 0,
1968 brdysts::Pipe5Brdy,
1969 Brdysts_SPEC,
1970 crate::common::RW,
1971 >::from_register(self, 0)
1972 }
1973 #[doc = "BRDY Interrupt Status for Pipe 6"]
1974 #[inline(always)]
1975 pub fn pipe6brdy(
1976 self,
1977 ) -> crate::common::RegisterField<
1978 6,
1979 0x1,
1980 1,
1981 0,
1982 brdysts::Pipe6Brdy,
1983 Brdysts_SPEC,
1984 crate::common::RW,
1985 > {
1986 crate::common::RegisterField::<
1987 6,
1988 0x1,
1989 1,
1990 0,
1991 brdysts::Pipe6Brdy,
1992 Brdysts_SPEC,
1993 crate::common::RW,
1994 >::from_register(self, 0)
1995 }
1996 #[doc = "BRDY Interrupt Status for Pipe 7"]
1997 #[inline(always)]
1998 pub fn pipe7brdy(
1999 self,
2000 ) -> crate::common::RegisterField<
2001 7,
2002 0x1,
2003 1,
2004 0,
2005 brdysts::Pipe7Brdy,
2006 Brdysts_SPEC,
2007 crate::common::RW,
2008 > {
2009 crate::common::RegisterField::<
2010 7,
2011 0x1,
2012 1,
2013 0,
2014 brdysts::Pipe7Brdy,
2015 Brdysts_SPEC,
2016 crate::common::RW,
2017 >::from_register(self, 0)
2018 }
2019}
2020impl ::core::default::Default for Brdysts {
2021 #[inline(always)]
2022 fn default() -> Brdysts {
2023 <crate::RegValueT<Brdysts_SPEC> as RegisterValue<_>>::new(0)
2024 }
2025}
2026pub mod brdysts {
2027
2028 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2029 pub struct Pipe0Brdy_SPEC;
2030 pub type Pipe0Brdy = crate::EnumBitfieldStruct<u8, Pipe0Brdy_SPEC>;
2031 impl Pipe0Brdy {
2032 #[doc = "No BRDY interrupt occurred"]
2033 pub const _0: Self = Self::new(0);
2034 #[doc = "BRDY interrupt occurred"]
2035 pub const _1: Self = Self::new(1);
2036 }
2037 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2038 pub struct Pipe4Brdy_SPEC;
2039 pub type Pipe4Brdy = crate::EnumBitfieldStruct<u8, Pipe4Brdy_SPEC>;
2040 impl Pipe4Brdy {
2041 #[doc = "No BRDY interrupt occurred"]
2042 pub const _0: Self = Self::new(0);
2043 #[doc = "BRDY interrupt occurred"]
2044 pub const _1: Self = Self::new(1);
2045 }
2046 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2047 pub struct Pipe5Brdy_SPEC;
2048 pub type Pipe5Brdy = crate::EnumBitfieldStruct<u8, Pipe5Brdy_SPEC>;
2049 impl Pipe5Brdy {
2050 #[doc = "No BRDY interrupt occurred"]
2051 pub const _0: Self = Self::new(0);
2052 #[doc = "BRDY interrupt occurred"]
2053 pub const _1: Self = Self::new(1);
2054 }
2055 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2056 pub struct Pipe6Brdy_SPEC;
2057 pub type Pipe6Brdy = crate::EnumBitfieldStruct<u8, Pipe6Brdy_SPEC>;
2058 impl Pipe6Brdy {
2059 #[doc = "No BRDY interrupt occurred"]
2060 pub const _0: Self = Self::new(0);
2061 #[doc = "BRDY interrupt occurred"]
2062 pub const _1: Self = Self::new(1);
2063 }
2064 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2065 pub struct Pipe7Brdy_SPEC;
2066 pub type Pipe7Brdy = crate::EnumBitfieldStruct<u8, Pipe7Brdy_SPEC>;
2067 impl Pipe7Brdy {
2068 #[doc = "No BRDY interrupt occurred"]
2069 pub const _0: Self = Self::new(0);
2070 #[doc = "BRDY interrupt occurred"]
2071 pub const _1: Self = Self::new(1);
2072 }
2073}
2074#[doc(hidden)]
2075#[derive(Copy, Clone, Eq, PartialEq)]
2076pub struct Nrdysts_SPEC;
2077impl crate::sealed::RegSpec for Nrdysts_SPEC {
2078 type DataType = u16;
2079}
2080#[doc = "NRDY Interrupt Status Register"]
2081pub type Nrdysts = crate::RegValueT<Nrdysts_SPEC>;
2082
2083impl Nrdysts {
2084 #[doc = "NRDY Interrupt Status for Pipe 0"]
2085 #[inline(always)]
2086 pub fn pipe0nrdy(
2087 self,
2088 ) -> crate::common::RegisterField<
2089 0,
2090 0x1,
2091 1,
2092 0,
2093 nrdysts::Pipe0Nrdy,
2094 Nrdysts_SPEC,
2095 crate::common::RW,
2096 > {
2097 crate::common::RegisterField::<
2098 0,
2099 0x1,
2100 1,
2101 0,
2102 nrdysts::Pipe0Nrdy,
2103 Nrdysts_SPEC,
2104 crate::common::RW,
2105 >::from_register(self, 0)
2106 }
2107 #[doc = "NRDY Interrupt Status for Pipe 4"]
2108 #[inline(always)]
2109 pub fn pipe4nrdy(
2110 self,
2111 ) -> crate::common::RegisterField<
2112 4,
2113 0x1,
2114 1,
2115 0,
2116 nrdysts::Pipe4Nrdy,
2117 Nrdysts_SPEC,
2118 crate::common::RW,
2119 > {
2120 crate::common::RegisterField::<
2121 4,
2122 0x1,
2123 1,
2124 0,
2125 nrdysts::Pipe4Nrdy,
2126 Nrdysts_SPEC,
2127 crate::common::RW,
2128 >::from_register(self, 0)
2129 }
2130 #[doc = "NRDY Interrupt Status for Pipe 5"]
2131 #[inline(always)]
2132 pub fn pipe5nrdy(
2133 self,
2134 ) -> crate::common::RegisterField<
2135 5,
2136 0x1,
2137 1,
2138 0,
2139 nrdysts::Pipe5Nrdy,
2140 Nrdysts_SPEC,
2141 crate::common::RW,
2142 > {
2143 crate::common::RegisterField::<
2144 5,
2145 0x1,
2146 1,
2147 0,
2148 nrdysts::Pipe5Nrdy,
2149 Nrdysts_SPEC,
2150 crate::common::RW,
2151 >::from_register(self, 0)
2152 }
2153 #[doc = "NRDY Interrupt Status for Pipe 6"]
2154 #[inline(always)]
2155 pub fn pipe6nrdy(
2156 self,
2157 ) -> crate::common::RegisterField<
2158 6,
2159 0x1,
2160 1,
2161 0,
2162 nrdysts::Pipe6Nrdy,
2163 Nrdysts_SPEC,
2164 crate::common::RW,
2165 > {
2166 crate::common::RegisterField::<
2167 6,
2168 0x1,
2169 1,
2170 0,
2171 nrdysts::Pipe6Nrdy,
2172 Nrdysts_SPEC,
2173 crate::common::RW,
2174 >::from_register(self, 0)
2175 }
2176 #[doc = "NRDY Interrupt Status for Pipe 7"]
2177 #[inline(always)]
2178 pub fn pipe7nrdy(
2179 self,
2180 ) -> crate::common::RegisterField<
2181 7,
2182 0x1,
2183 1,
2184 0,
2185 nrdysts::Pipe7Nrdy,
2186 Nrdysts_SPEC,
2187 crate::common::RW,
2188 > {
2189 crate::common::RegisterField::<
2190 7,
2191 0x1,
2192 1,
2193 0,
2194 nrdysts::Pipe7Nrdy,
2195 Nrdysts_SPEC,
2196 crate::common::RW,
2197 >::from_register(self, 0)
2198 }
2199}
2200impl ::core::default::Default for Nrdysts {
2201 #[inline(always)]
2202 fn default() -> Nrdysts {
2203 <crate::RegValueT<Nrdysts_SPEC> as RegisterValue<_>>::new(0)
2204 }
2205}
2206pub mod nrdysts {
2207
2208 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2209 pub struct Pipe0Nrdy_SPEC;
2210 pub type Pipe0Nrdy = crate::EnumBitfieldStruct<u8, Pipe0Nrdy_SPEC>;
2211 impl Pipe0Nrdy {
2212 #[doc = "No NRDY interrupt occurred"]
2213 pub const _0: Self = Self::new(0);
2214 #[doc = "NRDY interrupt occurred"]
2215 pub const _1: Self = Self::new(1);
2216 }
2217 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2218 pub struct Pipe4Nrdy_SPEC;
2219 pub type Pipe4Nrdy = crate::EnumBitfieldStruct<u8, Pipe4Nrdy_SPEC>;
2220 impl Pipe4Nrdy {
2221 #[doc = "No NRDY interrupt occurred"]
2222 pub const _0: Self = Self::new(0);
2223 #[doc = "NRDY interrupt occurred"]
2224 pub const _1: Self = Self::new(1);
2225 }
2226 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2227 pub struct Pipe5Nrdy_SPEC;
2228 pub type Pipe5Nrdy = crate::EnumBitfieldStruct<u8, Pipe5Nrdy_SPEC>;
2229 impl Pipe5Nrdy {
2230 #[doc = "No NRDY interrupt occurred"]
2231 pub const _0: Self = Self::new(0);
2232 #[doc = "NRDY interrupt occurred"]
2233 pub const _1: Self = Self::new(1);
2234 }
2235 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2236 pub struct Pipe6Nrdy_SPEC;
2237 pub type Pipe6Nrdy = crate::EnumBitfieldStruct<u8, Pipe6Nrdy_SPEC>;
2238 impl Pipe6Nrdy {
2239 #[doc = "No NRDY interrupt occurred"]
2240 pub const _0: Self = Self::new(0);
2241 #[doc = "NRDY interrupt occurred"]
2242 pub const _1: Self = Self::new(1);
2243 }
2244 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2245 pub struct Pipe7Nrdy_SPEC;
2246 pub type Pipe7Nrdy = crate::EnumBitfieldStruct<u8, Pipe7Nrdy_SPEC>;
2247 impl Pipe7Nrdy {
2248 #[doc = "No NRDY interrupt occurred"]
2249 pub const _0: Self = Self::new(0);
2250 #[doc = "NRDY interrupt occurred"]
2251 pub const _1: Self = Self::new(1);
2252 }
2253}
2254#[doc(hidden)]
2255#[derive(Copy, Clone, Eq, PartialEq)]
2256pub struct Bempsts_SPEC;
2257impl crate::sealed::RegSpec for Bempsts_SPEC {
2258 type DataType = u16;
2259}
2260#[doc = "BEMP Interrupt Status Register"]
2261pub type Bempsts = crate::RegValueT<Bempsts_SPEC>;
2262
2263impl Bempsts {
2264 #[doc = "BEMP Interrupt Status for Pipe 0"]
2265 #[inline(always)]
2266 pub fn pipe0bemp(
2267 self,
2268 ) -> crate::common::RegisterField<
2269 0,
2270 0x1,
2271 1,
2272 0,
2273 bempsts::Pipe0Bemp,
2274 Bempsts_SPEC,
2275 crate::common::RW,
2276 > {
2277 crate::common::RegisterField::<
2278 0,
2279 0x1,
2280 1,
2281 0,
2282 bempsts::Pipe0Bemp,
2283 Bempsts_SPEC,
2284 crate::common::RW,
2285 >::from_register(self, 0)
2286 }
2287 #[doc = "BEMP Interrupt Status for Pipe 4"]
2288 #[inline(always)]
2289 pub fn pipe4bemp(
2290 self,
2291 ) -> crate::common::RegisterField<
2292 4,
2293 0x1,
2294 1,
2295 0,
2296 bempsts::Pipe4Bemp,
2297 Bempsts_SPEC,
2298 crate::common::RW,
2299 > {
2300 crate::common::RegisterField::<
2301 4,
2302 0x1,
2303 1,
2304 0,
2305 bempsts::Pipe4Bemp,
2306 Bempsts_SPEC,
2307 crate::common::RW,
2308 >::from_register(self, 0)
2309 }
2310 #[doc = "BEMP Interrupt Status for Pipe 5"]
2311 #[inline(always)]
2312 pub fn pipe5bemp(
2313 self,
2314 ) -> crate::common::RegisterField<
2315 5,
2316 0x1,
2317 1,
2318 0,
2319 bempsts::Pipe5Bemp,
2320 Bempsts_SPEC,
2321 crate::common::RW,
2322 > {
2323 crate::common::RegisterField::<
2324 5,
2325 0x1,
2326 1,
2327 0,
2328 bempsts::Pipe5Bemp,
2329 Bempsts_SPEC,
2330 crate::common::RW,
2331 >::from_register(self, 0)
2332 }
2333 #[doc = "BEMP Interrupt Status for Pipe 6"]
2334 #[inline(always)]
2335 pub fn pipe6bemp(
2336 self,
2337 ) -> crate::common::RegisterField<
2338 6,
2339 0x1,
2340 1,
2341 0,
2342 bempsts::Pipe6Bemp,
2343 Bempsts_SPEC,
2344 crate::common::RW,
2345 > {
2346 crate::common::RegisterField::<
2347 6,
2348 0x1,
2349 1,
2350 0,
2351 bempsts::Pipe6Bemp,
2352 Bempsts_SPEC,
2353 crate::common::RW,
2354 >::from_register(self, 0)
2355 }
2356 #[doc = "BEMP Interrupt Status for Pipe 7"]
2357 #[inline(always)]
2358 pub fn pipe7bemp(
2359 self,
2360 ) -> crate::common::RegisterField<
2361 7,
2362 0x1,
2363 1,
2364 0,
2365 bempsts::Pipe7Bemp,
2366 Bempsts_SPEC,
2367 crate::common::RW,
2368 > {
2369 crate::common::RegisterField::<
2370 7,
2371 0x1,
2372 1,
2373 0,
2374 bempsts::Pipe7Bemp,
2375 Bempsts_SPEC,
2376 crate::common::RW,
2377 >::from_register(self, 0)
2378 }
2379}
2380impl ::core::default::Default for Bempsts {
2381 #[inline(always)]
2382 fn default() -> Bempsts {
2383 <crate::RegValueT<Bempsts_SPEC> as RegisterValue<_>>::new(0)
2384 }
2385}
2386pub mod bempsts {
2387
2388 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2389 pub struct Pipe0Bemp_SPEC;
2390 pub type Pipe0Bemp = crate::EnumBitfieldStruct<u8, Pipe0Bemp_SPEC>;
2391 impl Pipe0Bemp {
2392 #[doc = "No BEMP interrupt occurred"]
2393 pub const _0: Self = Self::new(0);
2394 #[doc = "BEMP interrupt occurred"]
2395 pub const _1: Self = Self::new(1);
2396 }
2397 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2398 pub struct Pipe4Bemp_SPEC;
2399 pub type Pipe4Bemp = crate::EnumBitfieldStruct<u8, Pipe4Bemp_SPEC>;
2400 impl Pipe4Bemp {
2401 #[doc = "No BEMP interrupt occurred"]
2402 pub const _0: Self = Self::new(0);
2403 #[doc = "BEMP interrupt occurred"]
2404 pub const _1: Self = Self::new(1);
2405 }
2406 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2407 pub struct Pipe5Bemp_SPEC;
2408 pub type Pipe5Bemp = crate::EnumBitfieldStruct<u8, Pipe5Bemp_SPEC>;
2409 impl Pipe5Bemp {
2410 #[doc = "No BEMP interrupt occurred"]
2411 pub const _0: Self = Self::new(0);
2412 #[doc = "BEMP interrupt occurred"]
2413 pub const _1: Self = Self::new(1);
2414 }
2415 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2416 pub struct Pipe6Bemp_SPEC;
2417 pub type Pipe6Bemp = crate::EnumBitfieldStruct<u8, Pipe6Bemp_SPEC>;
2418 impl Pipe6Bemp {
2419 #[doc = "No BEMP interrupt occurred"]
2420 pub const _0: Self = Self::new(0);
2421 #[doc = "BEMP interrupt occurred"]
2422 pub const _1: Self = Self::new(1);
2423 }
2424 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2425 pub struct Pipe7Bemp_SPEC;
2426 pub type Pipe7Bemp = crate::EnumBitfieldStruct<u8, Pipe7Bemp_SPEC>;
2427 impl Pipe7Bemp {
2428 #[doc = "No BEMP interrupt occurred"]
2429 pub const _0: Self = Self::new(0);
2430 #[doc = "BEMP interrupt occurred"]
2431 pub const _1: Self = Self::new(1);
2432 }
2433}
2434#[doc(hidden)]
2435#[derive(Copy, Clone, Eq, PartialEq)]
2436pub struct Frmnum_SPEC;
2437impl crate::sealed::RegSpec for Frmnum_SPEC {
2438 type DataType = u16;
2439}
2440#[doc = "Frame Number Register"]
2441pub type Frmnum = crate::RegValueT<Frmnum_SPEC>;
2442
2443impl Frmnum {
2444 #[doc = "Frame Number"]
2445 #[inline(always)]
2446 pub fn frnm(
2447 self,
2448 ) -> crate::common::RegisterField<0, 0x7ff, 1, 0, u16, Frmnum_SPEC, crate::common::R> {
2449 crate::common::RegisterField::<0,0x7ff,1,0,u16, Frmnum_SPEC,crate::common::R>::from_register(self,0)
2450 }
2451}
2452impl ::core::default::Default for Frmnum {
2453 #[inline(always)]
2454 fn default() -> Frmnum {
2455 <crate::RegValueT<Frmnum_SPEC> as RegisterValue<_>>::new(0)
2456 }
2457}
2458
2459#[doc(hidden)]
2460#[derive(Copy, Clone, Eq, PartialEq)]
2461pub struct Dvchgr_SPEC;
2462impl crate::sealed::RegSpec for Dvchgr_SPEC {
2463 type DataType = u16;
2464}
2465#[doc = "Device State Change Register"]
2466pub type Dvchgr = crate::RegValueT<Dvchgr_SPEC>;
2467
2468impl Dvchgr {
2469 #[doc = "Device State Change"]
2470 #[inline(always)]
2471 pub fn dvchg(
2472 self,
2473 ) -> crate::common::RegisterField<15, 0x1, 1, 0, dvchgr::Dvchg, Dvchgr_SPEC, crate::common::RW>
2474 {
2475 crate::common::RegisterField::<15,0x1,1,0,dvchgr::Dvchg, Dvchgr_SPEC,crate::common::RW>::from_register(self,0)
2476 }
2477}
2478impl ::core::default::Default for Dvchgr {
2479 #[inline(always)]
2480 fn default() -> Dvchgr {
2481 <crate::RegValueT<Dvchgr_SPEC> as RegisterValue<_>>::new(0)
2482 }
2483}
2484pub mod dvchgr {
2485
2486 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2487 pub struct Dvchg_SPEC;
2488 pub type Dvchg = crate::EnumBitfieldStruct<u8, Dvchg_SPEC>;
2489 impl Dvchg {
2490 #[doc = "Disable writes to the USBADDR.STSRECOV\\[3:0\\] and USBADDR.USBADDR\\[6:0\\] bits"]
2491 pub const _0: Self = Self::new(0);
2492 #[doc = "Enable writes to the USBADDR.STSRECOV\\[3:0\\] and USBADDR.USBADDR\\[6:0\\] bits"]
2493 pub const _1: Self = Self::new(1);
2494 }
2495}
2496#[doc(hidden)]
2497#[derive(Copy, Clone, Eq, PartialEq)]
2498pub struct Usbaddr_SPEC;
2499impl crate::sealed::RegSpec for Usbaddr_SPEC {
2500 type DataType = u16;
2501}
2502#[doc = "USB Address Register"]
2503pub type Usbaddr = crate::RegValueT<Usbaddr_SPEC>;
2504
2505impl Usbaddr {
2506 #[doc = "USB Address"]
2507 #[inline(always)]
2508 pub fn usbaddr(
2509 self,
2510 ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, Usbaddr_SPEC, crate::common::RW> {
2511 crate::common::RegisterField::<0,0x7f,1,0,u8, Usbaddr_SPEC,crate::common::RW>::from_register(self,0)
2512 }
2513 #[doc = "Status Recovery"]
2514 #[inline(always)]
2515 pub fn stsrecov(
2516 self,
2517 ) -> crate::common::RegisterField<
2518 8,
2519 0xf,
2520 1,
2521 0,
2522 usbaddr::Stsrecov,
2523 Usbaddr_SPEC,
2524 crate::common::RW,
2525 > {
2526 crate::common::RegisterField::<
2527 8,
2528 0xf,
2529 1,
2530 0,
2531 usbaddr::Stsrecov,
2532 Usbaddr_SPEC,
2533 crate::common::RW,
2534 >::from_register(self, 0)
2535 }
2536}
2537impl ::core::default::Default for Usbaddr {
2538 #[inline(always)]
2539 fn default() -> Usbaddr {
2540 <crate::RegValueT<Usbaddr_SPEC> as RegisterValue<_>>::new(0)
2541 }
2542}
2543pub mod usbaddr {
2544
2545 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2546 pub struct Stsrecov_SPEC;
2547 pub type Stsrecov = crate::EnumBitfieldStruct<u8, Stsrecov_SPEC>;
2548 impl Stsrecov {
2549 #[doc = "Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 001b (default state)"]
2550 pub const _0_X_9: Self = Self::new(9);
2551 #[doc = "Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 010b (address state)"]
2552 pub const _0_X_A: Self = Self::new(10);
2553 #[doc = "Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 011b (configured state)"]
2554 pub const _0_X_B: Self = Self::new(11);
2555 #[doc = "Setting prohibited"]
2556 pub const OTHERS: Self = Self::new(0);
2557 }
2558}
2559#[doc(hidden)]
2560#[derive(Copy, Clone, Eq, PartialEq)]
2561pub struct Usbreq_SPEC;
2562impl crate::sealed::RegSpec for Usbreq_SPEC {
2563 type DataType = u16;
2564}
2565#[doc = "USB Request Type Register"]
2566pub type Usbreq = crate::RegValueT<Usbreq_SPEC>;
2567
2568impl Usbreq {
2569 #[doc = "Request Type"]
2570 #[inline(always)]
2571 pub fn bmrequesttype(
2572 self,
2573 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, Usbreq_SPEC, crate::common::R> {
2574 crate::common::RegisterField::<0,0xff,1,0,u8, Usbreq_SPEC,crate::common::R>::from_register(self,0)
2575 }
2576 #[doc = "Request"]
2577 #[inline(always)]
2578 pub fn brequest(
2579 self,
2580 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, Usbreq_SPEC, crate::common::R> {
2581 crate::common::RegisterField::<8,0xff,1,0,u8, Usbreq_SPEC,crate::common::R>::from_register(self,0)
2582 }
2583}
2584impl ::core::default::Default for Usbreq {
2585 #[inline(always)]
2586 fn default() -> Usbreq {
2587 <crate::RegValueT<Usbreq_SPEC> as RegisterValue<_>>::new(0)
2588 }
2589}
2590
2591#[doc(hidden)]
2592#[derive(Copy, Clone, Eq, PartialEq)]
2593pub struct Usbval_SPEC;
2594impl crate::sealed::RegSpec for Usbval_SPEC {
2595 type DataType = u16;
2596}
2597#[doc = "USB Request Value Register"]
2598pub type Usbval = crate::RegValueT<Usbval_SPEC>;
2599
2600impl Usbval {
2601 #[doc = "Value"]
2602 #[inline(always)]
2603 pub fn wvalue(
2604 self,
2605 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, Usbval_SPEC, crate::common::R> {
2606 crate::common::RegisterField::<0,0xffff,1,0,u16, Usbval_SPEC,crate::common::R>::from_register(self,0)
2607 }
2608}
2609impl ::core::default::Default for Usbval {
2610 #[inline(always)]
2611 fn default() -> Usbval {
2612 <crate::RegValueT<Usbval_SPEC> as RegisterValue<_>>::new(0)
2613 }
2614}
2615
2616#[doc(hidden)]
2617#[derive(Copy, Clone, Eq, PartialEq)]
2618pub struct Usbindx_SPEC;
2619impl crate::sealed::RegSpec for Usbindx_SPEC {
2620 type DataType = u16;
2621}
2622#[doc = "USB Request Index Register"]
2623pub type Usbindx = crate::RegValueT<Usbindx_SPEC>;
2624
2625impl Usbindx {
2626 #[doc = "Index"]
2627 #[inline(always)]
2628 pub fn windex(
2629 self,
2630 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, Usbindx_SPEC, crate::common::R> {
2631 crate::common::RegisterField::<0,0xffff,1,0,u16, Usbindx_SPEC,crate::common::R>::from_register(self,0)
2632 }
2633}
2634impl ::core::default::Default for Usbindx {
2635 #[inline(always)]
2636 fn default() -> Usbindx {
2637 <crate::RegValueT<Usbindx_SPEC> as RegisterValue<_>>::new(0)
2638 }
2639}
2640
2641#[doc(hidden)]
2642#[derive(Copy, Clone, Eq, PartialEq)]
2643pub struct Usbleng_SPEC;
2644impl crate::sealed::RegSpec for Usbleng_SPEC {
2645 type DataType = u16;
2646}
2647#[doc = "USB Request Length Register"]
2648pub type Usbleng = crate::RegValueT<Usbleng_SPEC>;
2649
2650impl Usbleng {
2651 #[doc = "Length"]
2652 #[inline(always)]
2653 pub fn wlentuh(
2654 self,
2655 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, Usbleng_SPEC, crate::common::R> {
2656 crate::common::RegisterField::<0,0xffff,1,0,u16, Usbleng_SPEC,crate::common::R>::from_register(self,0)
2657 }
2658}
2659impl ::core::default::Default for Usbleng {
2660 #[inline(always)]
2661 fn default() -> Usbleng {
2662 <crate::RegValueT<Usbleng_SPEC> as RegisterValue<_>>::new(0)
2663 }
2664}
2665
2666#[doc(hidden)]
2667#[derive(Copy, Clone, Eq, PartialEq)]
2668pub struct Dcpcfg_SPEC;
2669impl crate::sealed::RegSpec for Dcpcfg_SPEC {
2670 type DataType = u16;
2671}
2672#[doc = "DCP Configuration Register"]
2673pub type Dcpcfg = crate::RegValueT<Dcpcfg_SPEC>;
2674
2675impl Dcpcfg {
2676 #[doc = "Pipe Disabled at End of Transfer"]
2677 #[inline(always)]
2678 pub fn shtnak(
2679 self,
2680 ) -> crate::common::RegisterField<7, 0x1, 1, 0, dcpcfg::Shtnak, Dcpcfg_SPEC, crate::common::RW>
2681 {
2682 crate::common::RegisterField::<7,0x1,1,0,dcpcfg::Shtnak, Dcpcfg_SPEC,crate::common::RW>::from_register(self,0)
2683 }
2684}
2685impl ::core::default::Default for Dcpcfg {
2686 #[inline(always)]
2687 fn default() -> Dcpcfg {
2688 <crate::RegValueT<Dcpcfg_SPEC> as RegisterValue<_>>::new(0)
2689 }
2690}
2691pub mod dcpcfg {
2692
2693 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2694 pub struct Shtnak_SPEC;
2695 pub type Shtnak = crate::EnumBitfieldStruct<u8, Shtnak_SPEC>;
2696 impl Shtnak {
2697 #[doc = "Keep pipe open after transfer ends"]
2698 pub const _0: Self = Self::new(0);
2699 #[doc = "Disable pipe after transfer ends"]
2700 pub const _1: Self = Self::new(1);
2701 }
2702}
2703#[doc(hidden)]
2704#[derive(Copy, Clone, Eq, PartialEq)]
2705pub struct Dcpmaxp_SPEC;
2706impl crate::sealed::RegSpec for Dcpmaxp_SPEC {
2707 type DataType = u16;
2708}
2709#[doc = "DCP Maximum Packet Size Register"]
2710pub type Dcpmaxp = crate::RegValueT<Dcpmaxp_SPEC>;
2711
2712impl Dcpmaxp {
2713 #[doc = "Maximum Packet Size"]
2714 #[inline(always)]
2715 pub fn mxps(
2716 self,
2717 ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, Dcpmaxp_SPEC, crate::common::RW> {
2718 crate::common::RegisterField::<0,0x7f,1,0,u8, Dcpmaxp_SPEC,crate::common::RW>::from_register(self,0)
2719 }
2720}
2721impl ::core::default::Default for Dcpmaxp {
2722 #[inline(always)]
2723 fn default() -> Dcpmaxp {
2724 <crate::RegValueT<Dcpmaxp_SPEC> as RegisterValue<_>>::new(64)
2725 }
2726}
2727
2728#[doc(hidden)]
2729#[derive(Copy, Clone, Eq, PartialEq)]
2730pub struct Dcpctr_SPEC;
2731impl crate::sealed::RegSpec for Dcpctr_SPEC {
2732 type DataType = u16;
2733}
2734#[doc = "DCP Control Register"]
2735pub type Dcpctr = crate::RegValueT<Dcpctr_SPEC>;
2736
2737impl Dcpctr {
2738 #[doc = "Response PID"]
2739 #[inline(always)]
2740 pub fn pid(
2741 self,
2742 ) -> crate::common::RegisterField<0, 0x3, 1, 0, dcpctr::Pid, Dcpctr_SPEC, crate::common::RW>
2743 {
2744 crate::common::RegisterField::<0,0x3,1,0,dcpctr::Pid, Dcpctr_SPEC,crate::common::RW>::from_register(self,0)
2745 }
2746 #[doc = "Control Transfer End Enable"]
2747 #[inline(always)]
2748 pub fn ccpl(
2749 self,
2750 ) -> crate::common::RegisterField<2, 0x1, 1, 0, dcpctr::Ccpl, Dcpctr_SPEC, crate::common::RW>
2751 {
2752 crate::common::RegisterField::<2,0x1,1,0,dcpctr::Ccpl, Dcpctr_SPEC,crate::common::RW>::from_register(self,0)
2753 }
2754 #[doc = "Pipe Busy"]
2755 #[inline(always)]
2756 pub fn pbusy(
2757 self,
2758 ) -> crate::common::RegisterField<5, 0x1, 1, 0, dcpctr::Pbusy, Dcpctr_SPEC, crate::common::R>
2759 {
2760 crate::common::RegisterField::<5,0x1,1,0,dcpctr::Pbusy, Dcpctr_SPEC,crate::common::R>::from_register(self,0)
2761 }
2762 #[doc = "Sequence Toggle Bit Monitor"]
2763 #[inline(always)]
2764 pub fn sqmon(
2765 self,
2766 ) -> crate::common::RegisterField<6, 0x1, 1, 0, dcpctr::Sqmon, Dcpctr_SPEC, crate::common::R>
2767 {
2768 crate::common::RegisterField::<6,0x1,1,0,dcpctr::Sqmon, Dcpctr_SPEC,crate::common::R>::from_register(self,0)
2769 }
2770 #[doc = "Sequence Toggle Bit Set"]
2771 #[inline(always)]
2772 pub fn sqset(
2773 self,
2774 ) -> crate::common::RegisterField<7, 0x1, 1, 0, dcpctr::Sqset, Dcpctr_SPEC, crate::common::RW>
2775 {
2776 crate::common::RegisterField::<7,0x1,1,0,dcpctr::Sqset, Dcpctr_SPEC,crate::common::RW>::from_register(self,0)
2777 }
2778 #[doc = "Sequence Toggle Bit Clear"]
2779 #[inline(always)]
2780 pub fn sqclr(
2781 self,
2782 ) -> crate::common::RegisterField<8, 0x1, 1, 0, dcpctr::Sqclr, Dcpctr_SPEC, crate::common::RW>
2783 {
2784 crate::common::RegisterField::<8,0x1,1,0,dcpctr::Sqclr, Dcpctr_SPEC,crate::common::RW>::from_register(self,0)
2785 }
2786 #[doc = "Buffer Status"]
2787 #[inline(always)]
2788 pub fn bsts(
2789 self,
2790 ) -> crate::common::RegisterField<15, 0x1, 1, 0, dcpctr::Bsts, Dcpctr_SPEC, crate::common::R>
2791 {
2792 crate::common::RegisterField::<15,0x1,1,0,dcpctr::Bsts, Dcpctr_SPEC,crate::common::R>::from_register(self,0)
2793 }
2794}
2795impl ::core::default::Default for Dcpctr {
2796 #[inline(always)]
2797 fn default() -> Dcpctr {
2798 <crate::RegValueT<Dcpctr_SPEC> as RegisterValue<_>>::new(64)
2799 }
2800}
2801pub mod dcpctr {
2802
2803 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2804 pub struct Pid_SPEC;
2805 pub type Pid = crate::EnumBitfieldStruct<u8, Pid_SPEC>;
2806 impl Pid {
2807 #[doc = "NAK response"]
2808 pub const _00: Self = Self::new(0);
2809 #[doc = "BUF response (depends on the buffer state)"]
2810 pub const _01: Self = Self::new(1);
2811 #[doc = "STALL response"]
2812 pub const _10: Self = Self::new(2);
2813 #[doc = "STALL response"]
2814 pub const _11: Self = Self::new(3);
2815 }
2816 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2817 pub struct Ccpl_SPEC;
2818 pub type Ccpl = crate::EnumBitfieldStruct<u8, Ccpl_SPEC>;
2819 impl Ccpl {
2820 #[doc = "Disable control transfer completion"]
2821 pub const _0: Self = Self::new(0);
2822 #[doc = "Enable control transfer completion"]
2823 pub const _1: Self = Self::new(1);
2824 }
2825 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2826 pub struct Pbusy_SPEC;
2827 pub type Pbusy = crate::EnumBitfieldStruct<u8, Pbusy_SPEC>;
2828 impl Pbusy {
2829 #[doc = "DCP not used for the USB bus"]
2830 pub const _0: Self = Self::new(0);
2831 #[doc = "DCP in use for the USB bus"]
2832 pub const _1: Self = Self::new(1);
2833 }
2834 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2835 pub struct Sqmon_SPEC;
2836 pub type Sqmon = crate::EnumBitfieldStruct<u8, Sqmon_SPEC>;
2837 impl Sqmon {
2838 #[doc = "DATA0"]
2839 pub const _0: Self = Self::new(0);
2840 #[doc = "DATA1"]
2841 pub const _1: Self = Self::new(1);
2842 }
2843 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2844 pub struct Sqset_SPEC;
2845 pub type Sqset = crate::EnumBitfieldStruct<u8, Sqset_SPEC>;
2846 impl Sqset {
2847 #[doc = "Invalid (writing 0 has no effect)"]
2848 pub const _0: Self = Self::new(0);
2849 #[doc = "Set the expected value for the next transaction to DATA1"]
2850 pub const _1: Self = Self::new(1);
2851 }
2852 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2853 pub struct Sqclr_SPEC;
2854 pub type Sqclr = crate::EnumBitfieldStruct<u8, Sqclr_SPEC>;
2855 impl Sqclr {
2856 #[doc = "Invalid (writing 0 has no effect)"]
2857 pub const _0: Self = Self::new(0);
2858 #[doc = "Clear the expected value for the next transaction to DATA0"]
2859 pub const _1: Self = Self::new(1);
2860 }
2861 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2862 pub struct Bsts_SPEC;
2863 pub type Bsts = crate::EnumBitfieldStruct<u8, Bsts_SPEC>;
2864 impl Bsts {
2865 #[doc = "Buffer access disabled"]
2866 pub const _0: Self = Self::new(0);
2867 #[doc = "Buffer access enabled"]
2868 pub const _1: Self = Self::new(1);
2869 }
2870}
2871#[doc(hidden)]
2872#[derive(Copy, Clone, Eq, PartialEq)]
2873pub struct Pipesel_SPEC;
2874impl crate::sealed::RegSpec for Pipesel_SPEC {
2875 type DataType = u16;
2876}
2877#[doc = "Pipe Window Select Register"]
2878pub type Pipesel = crate::RegValueT<Pipesel_SPEC>;
2879
2880impl Pipesel {
2881 #[doc = "Pipe Window Select"]
2882 #[inline(always)]
2883 pub fn pipesel(
2884 self,
2885 ) -> crate::common::RegisterField<0, 0xf, 1, 0, pipesel::Pipesel, Pipesel_SPEC, crate::common::RW>
2886 {
2887 crate::common::RegisterField::<
2888 0,
2889 0xf,
2890 1,
2891 0,
2892 pipesel::Pipesel,
2893 Pipesel_SPEC,
2894 crate::common::RW,
2895 >::from_register(self, 0)
2896 }
2897}
2898impl ::core::default::Default for Pipesel {
2899 #[inline(always)]
2900 fn default() -> Pipesel {
2901 <crate::RegValueT<Pipesel_SPEC> as RegisterValue<_>>::new(0)
2902 }
2903}
2904pub mod pipesel {
2905
2906 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2907 pub struct Pipesel_SPEC;
2908 pub type Pipesel = crate::EnumBitfieldStruct<u8, Pipesel_SPEC>;
2909 impl Pipesel {
2910 #[doc = "No pipe selected"]
2911 pub const _0_X_0: Self = Self::new(0);
2912 #[doc = "Pipe 4"]
2913 pub const _0_X_4: Self = Self::new(4);
2914 #[doc = "Pipe 5"]
2915 pub const _0_X_5: Self = Self::new(5);
2916 #[doc = "Pipe 6"]
2917 pub const _0_X_6: Self = Self::new(6);
2918 #[doc = "Pipe 7"]
2919 pub const _0_X_7: Self = Self::new(7);
2920 #[doc = "Setting prohibited"]
2921 pub const OTHERS: Self = Self::new(0);
2922 }
2923}
2924#[doc(hidden)]
2925#[derive(Copy, Clone, Eq, PartialEq)]
2926pub struct Pipecfg_SPEC;
2927impl crate::sealed::RegSpec for Pipecfg_SPEC {
2928 type DataType = u16;
2929}
2930#[doc = "Pipe Configuration Register"]
2931pub type Pipecfg = crate::RegValueT<Pipecfg_SPEC>;
2932
2933impl Pipecfg {
2934 #[doc = "Endpoint Number"]
2935 #[inline(always)]
2936 pub fn epnum(
2937 self,
2938 ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, Pipecfg_SPEC, crate::common::RW> {
2939 crate::common::RegisterField::<0,0xf,1,0,u8, Pipecfg_SPEC,crate::common::RW>::from_register(self,0)
2940 }
2941 #[doc = "Transfer Direction"]
2942 #[inline(always)]
2943 pub fn dir(
2944 self,
2945 ) -> crate::common::RegisterField<4, 0x1, 1, 0, pipecfg::Dir, Pipecfg_SPEC, crate::common::RW>
2946 {
2947 crate::common::RegisterField::<4,0x1,1,0,pipecfg::Dir, Pipecfg_SPEC,crate::common::RW>::from_register(self,0)
2948 }
2949 #[doc = "Pipe Disabled at End of Transfer"]
2950 #[inline(always)]
2951 pub fn shtnak(
2952 self,
2953 ) -> crate::common::RegisterField<7, 0x1, 1, 0, pipecfg::Shtnak, Pipecfg_SPEC, crate::common::RW>
2954 {
2955 crate::common::RegisterField::<7,0x1,1,0,pipecfg::Shtnak, Pipecfg_SPEC,crate::common::RW>::from_register(self,0)
2956 }
2957 #[doc = "Double Buffer Mode"]
2958 #[inline(always)]
2959 pub fn dblb(
2960 self,
2961 ) -> crate::common::RegisterField<9, 0x1, 1, 0, pipecfg::Dblb, Pipecfg_SPEC, crate::common::RW>
2962 {
2963 crate::common::RegisterField::<9,0x1,1,0,pipecfg::Dblb, Pipecfg_SPEC,crate::common::RW>::from_register(self,0)
2964 }
2965 #[doc = "BRDY Interrupt Operation Specification"]
2966 #[inline(always)]
2967 pub fn bfre(
2968 self,
2969 ) -> crate::common::RegisterField<10, 0x1, 1, 0, pipecfg::Bfre, Pipecfg_SPEC, crate::common::RW>
2970 {
2971 crate::common::RegisterField::<10,0x1,1,0,pipecfg::Bfre, Pipecfg_SPEC,crate::common::RW>::from_register(self,0)
2972 }
2973 #[doc = "Transfer Type"]
2974 #[inline(always)]
2975 pub fn r#type(
2976 self,
2977 ) -> crate::common::RegisterField<14, 0x3, 1, 0, pipecfg::Type, Pipecfg_SPEC, crate::common::RW>
2978 {
2979 crate::common::RegisterField::<14,0x3,1,0,pipecfg::Type, Pipecfg_SPEC,crate::common::RW>::from_register(self,0)
2980 }
2981}
2982impl ::core::default::Default for Pipecfg {
2983 #[inline(always)]
2984 fn default() -> Pipecfg {
2985 <crate::RegValueT<Pipecfg_SPEC> as RegisterValue<_>>::new(0)
2986 }
2987}
2988pub mod pipecfg {
2989
2990 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2991 pub struct Dir_SPEC;
2992 pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
2993 impl Dir {
2994 #[doc = "Receiving direction"]
2995 pub const _0: Self = Self::new(0);
2996 #[doc = "Transmitting direction"]
2997 pub const _1: Self = Self::new(1);
2998 }
2999 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3000 pub struct Shtnak_SPEC;
3001 pub type Shtnak = crate::EnumBitfieldStruct<u8, Shtnak_SPEC>;
3002 impl Shtnak {
3003 #[doc = "Continue pipe operation after transfer ends"]
3004 pub const _0: Self = Self::new(0);
3005 #[doc = "Disable pipe after transfer ends"]
3006 pub const _1: Self = Self::new(1);
3007 }
3008 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3009 pub struct Dblb_SPEC;
3010 pub type Dblb = crate::EnumBitfieldStruct<u8, Dblb_SPEC>;
3011 impl Dblb {
3012 #[doc = "Single buffer"]
3013 pub const _0: Self = Self::new(0);
3014 #[doc = "Double buffer"]
3015 pub const _1: Self = Self::new(1);
3016 }
3017 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3018 pub struct Bfre_SPEC;
3019 pub type Bfre = crate::EnumBitfieldStruct<u8, Bfre_SPEC>;
3020 impl Bfre {
3021 #[doc = "Generate BRDY interrupt on transmitting or receiving data"]
3022 pub const _0: Self = Self::new(0);
3023 #[doc = "Generate BRDY interrupt on completion of reading data"]
3024 pub const _1: Self = Self::new(1);
3025 }
3026 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3027 pub struct Type_SPEC;
3028 pub type Type = crate::EnumBitfieldStruct<u8, Type_SPEC>;
3029 impl Type {
3030 #[doc = "Pipe not used"]
3031 pub const _00: Self = Self::new(0);
3032 #[doc = "Pipes 4 and 5: Bulk transfer Pipes 6 and 7: Setting prohibited"]
3033 pub const _01: Self = Self::new(1);
3034 #[doc = "Pipes 4 and 5: Setting prohibited Pipes 6 and 7: Interrupt transfer"]
3035 pub const _10: Self = Self::new(2);
3036 #[doc = "Pipes 4 and 5: Setting prohibited Pipes 6 and 7: Setting prohibited"]
3037 pub const _11: Self = Self::new(3);
3038 }
3039}
3040#[doc(hidden)]
3041#[derive(Copy, Clone, Eq, PartialEq)]
3042pub struct Pipemaxp_SPEC;
3043impl crate::sealed::RegSpec for Pipemaxp_SPEC {
3044 type DataType = u16;
3045}
3046#[doc = "Pipe Maximum Packet Size Register"]
3047pub type Pipemaxp = crate::RegValueT<Pipemaxp_SPEC>;
3048
3049impl Pipemaxp {
3050 #[doc = "Maximum Packet Size"]
3051 #[inline(always)]
3052 pub fn mxps(
3053 self,
3054 ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, Pipemaxp_SPEC, crate::common::RW> {
3055 crate::common::RegisterField::<0,0x1ff,1,0,u16, Pipemaxp_SPEC,crate::common::RW>::from_register(self,0)
3056 }
3057}
3058impl ::core::default::Default for Pipemaxp {
3059 #[inline(always)]
3060 fn default() -> Pipemaxp {
3061 <crate::RegValueT<Pipemaxp_SPEC> as RegisterValue<_>>::new(0)
3062 }
3063}
3064
3065#[doc(hidden)]
3066#[derive(Copy, Clone, Eq, PartialEq)]
3067pub struct Pipectr_SPEC;
3068impl crate::sealed::RegSpec for Pipectr_SPEC {
3069 type DataType = u16;
3070}
3071#[doc = "PIPE%s Control Registers"]
3072pub type Pipectr = crate::RegValueT<Pipectr_SPEC>;
3073
3074impl Pipectr {
3075 #[doc = "Response PID"]
3076 #[inline(always)]
3077 pub fn pid(
3078 self,
3079 ) -> crate::common::RegisterField<0, 0x3, 1, 0, pipectr::Pid, Pipectr_SPEC, crate::common::RW>
3080 {
3081 crate::common::RegisterField::<0,0x3,1,0,pipectr::Pid, Pipectr_SPEC,crate::common::RW>::from_register(self,0)
3082 }
3083 #[doc = "Pipe Busy"]
3084 #[inline(always)]
3085 pub fn pbusy(
3086 self,
3087 ) -> crate::common::RegisterField<5, 0x1, 1, 0, pipectr::Pbusy, Pipectr_SPEC, crate::common::R>
3088 {
3089 crate::common::RegisterField::<5,0x1,1,0,pipectr::Pbusy, Pipectr_SPEC,crate::common::R>::from_register(self,0)
3090 }
3091 #[doc = "Sequence Toggle Bit Confirmation"]
3092 #[inline(always)]
3093 pub fn sqmon(
3094 self,
3095 ) -> crate::common::RegisterField<6, 0x1, 1, 0, pipectr::Sqmon, Pipectr_SPEC, crate::common::R>
3096 {
3097 crate::common::RegisterField::<6,0x1,1,0,pipectr::Sqmon, Pipectr_SPEC,crate::common::R>::from_register(self,0)
3098 }
3099 #[doc = "Sequence Toggle Bit Set"]
3100 #[inline(always)]
3101 pub fn sqset(
3102 self,
3103 ) -> crate::common::RegisterField<7, 0x1, 1, 0, pipectr::Sqset, Pipectr_SPEC, crate::common::W>
3104 {
3105 crate::common::RegisterField::<7,0x1,1,0,pipectr::Sqset, Pipectr_SPEC,crate::common::W>::from_register(self,0)
3106 }
3107 #[doc = "Sequence Toggle Bit Clear"]
3108 #[inline(always)]
3109 pub fn sqclr(
3110 self,
3111 ) -> crate::common::RegisterField<8, 0x1, 1, 0, pipectr::Sqclr, Pipectr_SPEC, crate::common::W>
3112 {
3113 crate::common::RegisterField::<8,0x1,1,0,pipectr::Sqclr, Pipectr_SPEC,crate::common::W>::from_register(self,0)
3114 }
3115 #[doc = "Auto Buffer Clear Mode"]
3116 #[inline(always)]
3117 pub fn aclrm(
3118 self,
3119 ) -> crate::common::RegisterField<9, 0x1, 1, 0, pipectr::Aclrm, Pipectr_SPEC, crate::common::RW>
3120 {
3121 crate::common::RegisterField::<9,0x1,1,0,pipectr::Aclrm, Pipectr_SPEC,crate::common::RW>::from_register(self,0)
3122 }
3123 #[doc = "Buffer Status"]
3124 #[inline(always)]
3125 pub fn bsts(
3126 self,
3127 ) -> crate::common::RegisterField<15, 0x1, 1, 0, pipectr::Bsts, Pipectr_SPEC, crate::common::R>
3128 {
3129 crate::common::RegisterField::<15,0x1,1,0,pipectr::Bsts, Pipectr_SPEC,crate::common::R>::from_register(self,0)
3130 }
3131}
3132impl ::core::default::Default for Pipectr {
3133 #[inline(always)]
3134 fn default() -> Pipectr {
3135 <crate::RegValueT<Pipectr_SPEC> as RegisterValue<_>>::new(0)
3136 }
3137}
3138pub mod pipectr {
3139
3140 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3141 pub struct Pid_SPEC;
3142 pub type Pid = crate::EnumBitfieldStruct<u8, Pid_SPEC>;
3143 impl Pid {
3144 #[doc = "NAK response"]
3145 pub const _00: Self = Self::new(0);
3146 #[doc = "BUF response (depends buffer state)"]
3147 pub const _01: Self = Self::new(1);
3148 #[doc = "STALL response"]
3149 pub const _10: Self = Self::new(2);
3150 #[doc = "STALL response"]
3151 pub const _11: Self = Self::new(3);
3152 }
3153 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3154 pub struct Pbusy_SPEC;
3155 pub type Pbusy = crate::EnumBitfieldStruct<u8, Pbusy_SPEC>;
3156 impl Pbusy {
3157 #[doc = "Pipe n not in use for the transaction"]
3158 pub const _0: Self = Self::new(0);
3159 #[doc = "Pipe n in use for the transaction"]
3160 pub const _1: Self = Self::new(1);
3161 }
3162 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3163 pub struct Sqmon_SPEC;
3164 pub type Sqmon = crate::EnumBitfieldStruct<u8, Sqmon_SPEC>;
3165 impl Sqmon {
3166 #[doc = "DATA0"]
3167 pub const _0: Self = Self::new(0);
3168 #[doc = "DATA1"]
3169 pub const _1: Self = Self::new(1);
3170 }
3171 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3172 pub struct Sqset_SPEC;
3173 pub type Sqset = crate::EnumBitfieldStruct<u8, Sqset_SPEC>;
3174 impl Sqset {
3175 #[doc = "Invalid (writing 0 has no effect)"]
3176 pub const _0: Self = Self::new(0);
3177 #[doc = "Set the expected value for the next transaction to DATA0"]
3178 pub const _1: Self = Self::new(1);
3179 }
3180 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3181 pub struct Sqclr_SPEC;
3182 pub type Sqclr = crate::EnumBitfieldStruct<u8, Sqclr_SPEC>;
3183 impl Sqclr {
3184 #[doc = "Invalid (writing 0 has no effect)"]
3185 pub const _0: Self = Self::new(0);
3186 #[doc = "Clear the expected value for the next transaction to DATA0"]
3187 pub const _1: Self = Self::new(1);
3188 }
3189 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3190 pub struct Aclrm_SPEC;
3191 pub type Aclrm = crate::EnumBitfieldStruct<u8, Aclrm_SPEC>;
3192 impl Aclrm {
3193 #[doc = "Disable"]
3194 pub const _0: Self = Self::new(0);
3195 #[doc = "Enable (all buffers initialized)"]
3196 pub const _1: Self = Self::new(1);
3197 }
3198 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3199 pub struct Bsts_SPEC;
3200 pub type Bsts = crate::EnumBitfieldStruct<u8, Bsts_SPEC>;
3201 impl Bsts {
3202 #[doc = "Buffer access disabled"]
3203 pub const _0: Self = Self::new(0);
3204 #[doc = "Buffer access enabled"]
3205 pub const _1: Self = Self::new(1);
3206 }
3207}
3208#[doc(hidden)]
3209#[derive(Copy, Clone, Eq, PartialEq)]
3210pub struct Pipetre_SPEC;
3211impl crate::sealed::RegSpec for Pipetre_SPEC {
3212 type DataType = u16;
3213}
3214#[doc = "PIPE%s Transaction Counter Enable Register"]
3215pub type Pipetre = crate::RegValueT<Pipetre_SPEC>;
3216
3217impl Pipetre {
3218 #[doc = "Transaction Counter Clear"]
3219 #[inline(always)]
3220 pub fn trclr(
3221 self,
3222 ) -> crate::common::RegisterField<8, 0x1, 1, 0, pipetre::Trclr, Pipetre_SPEC, crate::common::RW>
3223 {
3224 crate::common::RegisterField::<8,0x1,1,0,pipetre::Trclr, Pipetre_SPEC,crate::common::RW>::from_register(self,0)
3225 }
3226 #[doc = "Transaction Counter Enable"]
3227 #[inline(always)]
3228 pub fn trenb(
3229 self,
3230 ) -> crate::common::RegisterField<9, 0x1, 1, 0, pipetre::Trenb, Pipetre_SPEC, crate::common::RW>
3231 {
3232 crate::common::RegisterField::<9,0x1,1,0,pipetre::Trenb, Pipetre_SPEC,crate::common::RW>::from_register(self,0)
3233 }
3234}
3235impl ::core::default::Default for Pipetre {
3236 #[inline(always)]
3237 fn default() -> Pipetre {
3238 <crate::RegValueT<Pipetre_SPEC> as RegisterValue<_>>::new(0)
3239 }
3240}
3241pub mod pipetre {
3242
3243 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3244 pub struct Trclr_SPEC;
3245 pub type Trclr = crate::EnumBitfieldStruct<u8, Trclr_SPEC>;
3246 impl Trclr {
3247 #[doc = "Invalid (writing 0 has no effect)"]
3248 pub const _0: Self = Self::new(0);
3249 #[doc = "Clear counter value"]
3250 pub const _1: Self = Self::new(1);
3251 }
3252 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3253 pub struct Trenb_SPEC;
3254 pub type Trenb = crate::EnumBitfieldStruct<u8, Trenb_SPEC>;
3255 impl Trenb {
3256 #[doc = "Disable transaction counter"]
3257 pub const _0: Self = Self::new(0);
3258 #[doc = "Enable transaction counter"]
3259 pub const _1: Self = Self::new(1);
3260 }
3261}
3262#[doc(hidden)]
3263#[derive(Copy, Clone, Eq, PartialEq)]
3264pub struct Pipetrn_SPEC;
3265impl crate::sealed::RegSpec for Pipetrn_SPEC {
3266 type DataType = u16;
3267}
3268#[doc = "PIPE%s Transaction Counter Register"]
3269pub type Pipetrn = crate::RegValueT<Pipetrn_SPEC>;
3270
3271impl Pipetrn {
3272 #[doc = "Transaction Counter"]
3273 #[inline(always)]
3274 pub fn trncnt(
3275 self,
3276 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, Pipetrn_SPEC, crate::common::RW> {
3277 crate::common::RegisterField::<0,0xffff,1,0,u16, Pipetrn_SPEC,crate::common::RW>::from_register(self,0)
3278 }
3279}
3280impl ::core::default::Default for Pipetrn {
3281 #[inline(always)]
3282 fn default() -> Pipetrn {
3283 <crate::RegValueT<Pipetrn_SPEC> as RegisterValue<_>>::new(0)
3284 }
3285}
3286
3287#[doc(hidden)]
3288#[derive(Copy, Clone, Eq, PartialEq)]
3289pub struct Physectrl_SPEC;
3290impl crate::sealed::RegSpec for Physectrl_SPEC {
3291 type DataType = u32;
3292}
3293#[doc = "PHY Single-ended Receiver Control Register"]
3294pub type Physectrl = crate::RegValueT<Physectrl_SPEC>;
3295
3296impl Physectrl {
3297 #[doc = "Single-ended Receiver Enable"]
3298 #[inline(always)]
3299 pub fn cnen(
3300 self,
3301 ) -> crate::common::RegisterField<
3302 4,
3303 0x1,
3304 1,
3305 0,
3306 physectrl::Cnen,
3307 Physectrl_SPEC,
3308 crate::common::RW,
3309 > {
3310 crate::common::RegisterField::<
3311 4,
3312 0x1,
3313 1,
3314 0,
3315 physectrl::Cnen,
3316 Physectrl_SPEC,
3317 crate::common::RW,
3318 >::from_register(self, 0)
3319 }
3320}
3321impl ::core::default::Default for Physectrl {
3322 #[inline(always)]
3323 fn default() -> Physectrl {
3324 <crate::RegValueT<Physectrl_SPEC> as RegisterValue<_>>::new(0)
3325 }
3326}
3327pub mod physectrl {
3328
3329 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3330 pub struct Cnen_SPEC;
3331 pub type Cnen = crate::EnumBitfieldStruct<u8, Cnen_SPEC>;
3332 impl Cnen {
3333 #[doc = "Single-ended receiver operation is disabled"]
3334 pub const _0: Self = Self::new(0);
3335 #[doc = "Single-ended receiver operation is enabled"]
3336 pub const _1: Self = Self::new(1);
3337 }
3338}
3339#[doc(hidden)]
3340#[derive(Copy, Clone, Eq, PartialEq)]
3341pub struct Dpusr0R_SPEC;
3342impl crate::sealed::RegSpec for Dpusr0R_SPEC {
3343 type DataType = u32;
3344}
3345#[doc = "Deep Software Standby USB Transceiver Control/Pin Monitor Register"]
3346pub type Dpusr0R = crate::RegValueT<Dpusr0R_SPEC>;
3347
3348impl Dpusr0R {
3349 #[doc = "USB Single-ended Receiver Control"]
3350 #[inline(always)]
3351 pub fn srpc0(
3352 self,
3353 ) -> crate::common::RegisterField<0, 0x1, 1, 0, dpusr0r::Srpc0, Dpusr0R_SPEC, crate::common::RW>
3354 {
3355 crate::common::RegisterField::<0,0x1,1,0,dpusr0r::Srpc0, Dpusr0R_SPEC,crate::common::RW>::from_register(self,0)
3356 }
3357 #[doc = "DP Pull-Up Resistor Control"]
3358 #[inline(always)]
3359 pub fn rpue0(
3360 self,
3361 ) -> crate::common::RegisterField<1, 0x1, 1, 0, dpusr0r::Rpue0, Dpusr0R_SPEC, crate::common::RW>
3362 {
3363 crate::common::RegisterField::<1,0x1,1,0,dpusr0r::Rpue0, Dpusr0R_SPEC,crate::common::RW>::from_register(self,0)
3364 }
3365 #[doc = "USB Transceiver Output Fix"]
3366 #[inline(always)]
3367 pub fn fixphy0(
3368 self,
3369 ) -> crate::common::RegisterField<4, 0x1, 1, 0, dpusr0r::Fixphy0, Dpusr0R_SPEC, crate::common::RW>
3370 {
3371 crate::common::RegisterField::<
3372 4,
3373 0x1,
3374 1,
3375 0,
3376 dpusr0r::Fixphy0,
3377 Dpusr0R_SPEC,
3378 crate::common::RW,
3379 >::from_register(self, 0)
3380 }
3381 #[doc = "USB D+ Input"]
3382 #[inline(always)]
3383 pub fn dp0(self) -> crate::common::RegisterFieldBool<16, 1, 0, Dpusr0R_SPEC, crate::common::R> {
3384 crate::common::RegisterFieldBool::<16, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
3385 self, 0,
3386 )
3387 }
3388 #[doc = "USB D- Input"]
3389 #[inline(always)]
3390 pub fn dm0(self) -> crate::common::RegisterFieldBool<17, 1, 0, Dpusr0R_SPEC, crate::common::R> {
3391 crate::common::RegisterFieldBool::<17, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
3392 self, 0,
3393 )
3394 }
3395 #[doc = "USB VBUS Input"]
3396 #[inline(always)]
3397 pub fn dvbsts0(
3398 self,
3399 ) -> crate::common::RegisterFieldBool<23, 1, 0, Dpusr0R_SPEC, crate::common::R> {
3400 crate::common::RegisterFieldBool::<23, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
3401 self, 0,
3402 )
3403 }
3404}
3405impl ::core::default::Default for Dpusr0R {
3406 #[inline(always)]
3407 fn default() -> Dpusr0R {
3408 <crate::RegValueT<Dpusr0R_SPEC> as RegisterValue<_>>::new(0)
3409 }
3410}
3411pub mod dpusr0r {
3412
3413 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3414 pub struct Srpc0_SPEC;
3415 pub type Srpc0 = crate::EnumBitfieldStruct<u8, Srpc0_SPEC>;
3416 impl Srpc0 {
3417 #[doc = "Disable input through DP and DM inputs"]
3418 pub const _0: Self = Self::new(0);
3419 #[doc = "Enable input through DP and DM inputs"]
3420 pub const _1: Self = Self::new(1);
3421 }
3422 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3423 pub struct Rpue0_SPEC;
3424 pub type Rpue0 = crate::EnumBitfieldStruct<u8, Rpue0_SPEC>;
3425 impl Rpue0 {
3426 #[doc = "Disable DP pull-up resistor"]
3427 pub const _0: Self = Self::new(0);
3428 #[doc = "Enable DP pull-up resistor"]
3429 pub const _1: Self = Self::new(1);
3430 }
3431 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3432 pub struct Fixphy0_SPEC;
3433 pub type Fixphy0 = crate::EnumBitfieldStruct<u8, Fixphy0_SPEC>;
3434 impl Fixphy0 {
3435 #[doc = "Fix outputs in Normal mode and on return from Deep Software Standby mode"]
3436 pub const _0: Self = Self::new(0);
3437 #[doc = "Fix outputs on transition to Deep Software Standby mode"]
3438 pub const _1: Self = Self::new(1);
3439 }
3440}
3441#[doc(hidden)]
3442#[derive(Copy, Clone, Eq, PartialEq)]
3443pub struct Dpusr1R_SPEC;
3444impl crate::sealed::RegSpec for Dpusr1R_SPEC {
3445 type DataType = u32;
3446}
3447#[doc = "Deep Software Standby USB Suspend/Resume Interrupt Register"]
3448pub type Dpusr1R = crate::RegValueT<Dpusr1R_SPEC>;
3449
3450impl Dpusr1R {
3451 #[doc = "USB DP Interrupt Enable/Clear"]
3452 #[inline(always)]
3453 pub fn dpinte0(
3454 self,
3455 ) -> crate::common::RegisterField<0, 0x1, 1, 0, dpusr1r::Dpinte0, Dpusr1R_SPEC, crate::common::RW>
3456 {
3457 crate::common::RegisterField::<
3458 0,
3459 0x1,
3460 1,
3461 0,
3462 dpusr1r::Dpinte0,
3463 Dpusr1R_SPEC,
3464 crate::common::RW,
3465 >::from_register(self, 0)
3466 }
3467 #[doc = "USB DM Interrupt Enable/Clear"]
3468 #[inline(always)]
3469 pub fn dminte0(
3470 self,
3471 ) -> crate::common::RegisterField<1, 0x1, 1, 0, dpusr1r::Dminte0, Dpusr1R_SPEC, crate::common::RW>
3472 {
3473 crate::common::RegisterField::<
3474 1,
3475 0x1,
3476 1,
3477 0,
3478 dpusr1r::Dminte0,
3479 Dpusr1R_SPEC,
3480 crate::common::RW,
3481 >::from_register(self, 0)
3482 }
3483 #[doc = "USB VBUS Interrupt Enable/Clear"]
3484 #[inline(always)]
3485 pub fn dvbse0(
3486 self,
3487 ) -> crate::common::RegisterField<7, 0x1, 1, 0, dpusr1r::Dvbse0, Dpusr1R_SPEC, crate::common::RW>
3488 {
3489 crate::common::RegisterField::<7,0x1,1,0,dpusr1r::Dvbse0, Dpusr1R_SPEC,crate::common::RW>::from_register(self,0)
3490 }
3491 #[doc = "USB DP Interrupt Source Recovery"]
3492 #[inline(always)]
3493 pub fn dpint0(
3494 self,
3495 ) -> crate::common::RegisterField<16, 0x1, 1, 0, dpusr1r::Dpint0, Dpusr1R_SPEC, crate::common::R>
3496 {
3497 crate::common::RegisterField::<16,0x1,1,0,dpusr1r::Dpint0, Dpusr1R_SPEC,crate::common::R>::from_register(self,0)
3498 }
3499 #[doc = "USB DM Interrupt Source Recovery"]
3500 #[inline(always)]
3501 pub fn dmint0(
3502 self,
3503 ) -> crate::common::RegisterField<17, 0x1, 1, 0, dpusr1r::Dmint0, Dpusr1R_SPEC, crate::common::R>
3504 {
3505 crate::common::RegisterField::<17,0x1,1,0,dpusr1r::Dmint0, Dpusr1R_SPEC,crate::common::R>::from_register(self,0)
3506 }
3507 #[doc = "USB VBUS Interrupt Source Recovery"]
3508 #[inline(always)]
3509 pub fn dvbint0(
3510 self,
3511 ) -> crate::common::RegisterField<23, 0x1, 1, 0, dpusr1r::Dvbint0, Dpusr1R_SPEC, crate::common::R>
3512 {
3513 crate::common::RegisterField::<
3514 23,
3515 0x1,
3516 1,
3517 0,
3518 dpusr1r::Dvbint0,
3519 Dpusr1R_SPEC,
3520 crate::common::R,
3521 >::from_register(self, 0)
3522 }
3523}
3524impl ::core::default::Default for Dpusr1R {
3525 #[inline(always)]
3526 fn default() -> Dpusr1R {
3527 <crate::RegValueT<Dpusr1R_SPEC> as RegisterValue<_>>::new(0)
3528 }
3529}
3530pub mod dpusr1r {
3531
3532 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3533 pub struct Dpinte0_SPEC;
3534 pub type Dpinte0 = crate::EnumBitfieldStruct<u8, Dpinte0_SPEC>;
3535 impl Dpinte0 {
3536 #[doc = "Disable recovery from Deep Software Standby mode by DP input"]
3537 pub const _0: Self = Self::new(0);
3538 #[doc = "Enable recovery from Deep Software Standby mode by DP input"]
3539 pub const _1: Self = Self::new(1);
3540 }
3541 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3542 pub struct Dminte0_SPEC;
3543 pub type Dminte0 = crate::EnumBitfieldStruct<u8, Dminte0_SPEC>;
3544 impl Dminte0 {
3545 #[doc = "Disable recovery from Deep Software Standby mode by DM input"]
3546 pub const _0: Self = Self::new(0);
3547 #[doc = "Enable recovery from Deep Software Standby mode by DM input"]
3548 pub const _1: Self = Self::new(1);
3549 }
3550 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3551 pub struct Dvbse0_SPEC;
3552 pub type Dvbse0 = crate::EnumBitfieldStruct<u8, Dvbse0_SPEC>;
3553 impl Dvbse0 {
3554 #[doc = "Disable recovery from Deep Software Standby mode by VBUS input"]
3555 pub const _0: Self = Self::new(0);
3556 #[doc = "Enable recovery from Deep Software Standby mode by VBUS input"]
3557 pub const _1: Self = Self::new(1);
3558 }
3559 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3560 pub struct Dpint0_SPEC;
3561 pub type Dpint0 = crate::EnumBitfieldStruct<u8, Dpint0_SPEC>;
3562 impl Dpint0 {
3563 #[doc = "System has not recovered from Deep Software Standby mode"]
3564 pub const _0: Self = Self::new(0);
3565 #[doc = "System recovered from Deep Software Standby mode because of DP"]
3566 pub const _1: Self = Self::new(1);
3567 }
3568 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3569 pub struct Dmint0_SPEC;
3570 pub type Dmint0 = crate::EnumBitfieldStruct<u8, Dmint0_SPEC>;
3571 impl Dmint0 {
3572 #[doc = "System has not recovered from Deep Software Standby mode"]
3573 pub const _0: Self = Self::new(0);
3574 #[doc = "System recovered from Deep Software Standby mode because of DM input"]
3575 pub const _1: Self = Self::new(1);
3576 }
3577 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3578 pub struct Dvbint0_SPEC;
3579 pub type Dvbint0 = crate::EnumBitfieldStruct<u8, Dvbint0_SPEC>;
3580 impl Dvbint0 {
3581 #[doc = "System has not recovered from Deep Software Standby mode"]
3582 pub const _0: Self = Self::new(0);
3583 #[doc = "System recovered from Deep Software Standby mode because of VBUS input"]
3584 pub const _1: Self = Self::new(1);
3585 }
3586}