ra4e1/icu/
delsr.rs

1#[doc = "Register `DELSR%s` reader"]
2pub struct R(crate::R<DELSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DELSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DELSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DELSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DELSR%s` writer"]
17pub struct W(crate::W<DELSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DELSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DELSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DELSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DELS` reader - DMAC Event Link Select"]
38pub type DELS_R = crate::FieldReader<u16, DELS_A>;
39#[doc = "DMAC Event Link Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u16)]
42pub enum DELS_A {
43    #[doc = "0: Disable interrupts to the associated DMAC module."]
44    _0X00 = 0,
45}
46impl From<DELS_A> for u16 {
47    #[inline(always)]
48    fn from(variant: DELS_A) -> Self {
49        variant as _
50    }
51}
52impl DELS_R {
53    #[doc = "Get enumerated values variant"]
54    #[inline(always)]
55    pub fn variant(&self) -> Option<DELS_A> {
56        match self.bits {
57            0 => Some(DELS_A::_0X00),
58            _ => None,
59        }
60    }
61    #[doc = "Checks if the value of the field is `_0X00`"]
62    #[inline(always)]
63    pub fn is_0x00(&self) -> bool {
64        *self == DELS_A::_0X00
65    }
66}
67#[doc = "Field `DELS` writer - DMAC Event Link Select"]
68pub type DELS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DELSR_SPEC, u16, DELS_A, 9, O>;
69impl<'a, const O: u8> DELS_W<'a, O> {
70    #[doc = "Disable interrupts to the associated DMAC module."]
71    #[inline(always)]
72    pub fn _0x00(self) -> &'a mut W {
73        self.variant(DELS_A::_0X00)
74    }
75}
76#[doc = "Field `IR` reader - DMAC Activation Request Status Flag"]
77pub type IR_R = crate::BitReader<IR_A>;
78#[doc = "DMAC Activation Request Status Flag\n\nValue on reset: 0"]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80pub enum IR_A {
81    #[doc = "0: No DMAC activation request occurred."]
82    _0 = 0,
83    #[doc = "1: DMAC activation request occurred."]
84    _1 = 1,
85}
86impl From<IR_A> for bool {
87    #[inline(always)]
88    fn from(variant: IR_A) -> Self {
89        variant as u8 != 0
90    }
91}
92impl IR_R {
93    #[doc = "Get enumerated values variant"]
94    #[inline(always)]
95    pub fn variant(&self) -> IR_A {
96        match self.bits {
97            false => IR_A::_0,
98            true => IR_A::_1,
99        }
100    }
101    #[doc = "Checks if the value of the field is `_0`"]
102    #[inline(always)]
103    pub fn is_0(&self) -> bool {
104        *self == IR_A::_0
105    }
106    #[doc = "Checks if the value of the field is `_1`"]
107    #[inline(always)]
108    pub fn is_1(&self) -> bool {
109        *self == IR_A::_1
110    }
111}
112#[doc = "Field `IR` writer - DMAC Activation Request Status Flag"]
113pub type IR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DELSR_SPEC, IR_A, O>;
114impl<'a, const O: u8> IR_W<'a, O> {
115    #[doc = "No DMAC activation request occurred."]
116    #[inline(always)]
117    pub fn _0(self) -> &'a mut W {
118        self.variant(IR_A::_0)
119    }
120    #[doc = "DMAC activation request occurred."]
121    #[inline(always)]
122    pub fn _1(self) -> &'a mut W {
123        self.variant(IR_A::_1)
124    }
125}
126impl R {
127    #[doc = "Bits 0:8 - DMAC Event Link Select"]
128    #[inline(always)]
129    pub fn dels(&self) -> DELS_R {
130        DELS_R::new((self.bits & 0x01ff) as u16)
131    }
132    #[doc = "Bit 16 - DMAC Activation Request Status Flag"]
133    #[inline(always)]
134    pub fn ir(&self) -> IR_R {
135        IR_R::new(((self.bits >> 16) & 1) != 0)
136    }
137}
138impl W {
139    #[doc = "Bits 0:8 - DMAC Event Link Select"]
140    #[inline(always)]
141    #[must_use]
142    pub fn dels(&mut self) -> DELS_W<0> {
143        DELS_W::new(self)
144    }
145    #[doc = "Bit 16 - DMAC Activation Request Status Flag"]
146    #[inline(always)]
147    #[must_use]
148    pub fn ir(&mut self) -> IR_W<16> {
149        IR_W::new(self)
150    }
151    #[doc = "Writes raw bits to the register."]
152    #[inline(always)]
153    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
154        self.0.bits(bits);
155        self
156    }
157}
158#[doc = "DMAC Event Link Setting Register %s\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [delsr](index.html) module"]
159pub struct DELSR_SPEC;
160impl crate::RegisterSpec for DELSR_SPEC {
161    type Ux = u32;
162}
163#[doc = "`read()` method returns [delsr::R](R) reader structure"]
164impl crate::Readable for DELSR_SPEC {
165    type Reader = R;
166}
167#[doc = "`write(|w| ..)` method takes [delsr::W](W) writer structure"]
168impl crate::Writable for DELSR_SPEC {
169    type Writer = W;
170    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
171    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
172}
173#[doc = "`reset()` method sets DELSR%s to value 0"]
174impl crate::Resettable for DELSR_SPEC {
175    const RESET_VALUE: Self::Ux = 0;
176}
ra4e1/icu/delsr.rs

ra4e1/icu/
delsr.rs
