ra4e1/gpt164/
gtsecsr.rs

1#[doc = "Register `GTSECSR` reader"]
2pub struct R(crate::R<GTSECSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<GTSECSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<GTSECSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<GTSECSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `GTSECSR` writer"]
17pub struct W(crate::W<GTSECSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<GTSECSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<GTSECSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<GTSECSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SECSEL0` reader - Channel 0 Operation Enable Bit Simultaneous Control Channel Select"]
38pub type SECSEL0_R = crate::BitReader<SECSEL0_A>;
39#[doc = "Channel 0 Operation Enable Bit Simultaneous Control Channel Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum SECSEL0_A {
42    #[doc = "0: Disable simultaneous control"]
43    _0 = 0,
44    #[doc = "1: Enable simultaneous control"]
45    _1 = 1,
46}
47impl From<SECSEL0_A> for bool {
48    #[inline(always)]
49    fn from(variant: SECSEL0_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl SECSEL0_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> SECSEL0_A {
57        match self.bits {
58            false => SECSEL0_A::_0,
59            true => SECSEL0_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == SECSEL0_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == SECSEL0_A::_1
71    }
72}
73#[doc = "Field `SECSEL0` writer - Channel 0 Operation Enable Bit Simultaneous Control Channel Select"]
74pub type SECSEL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GTSECSR_SPEC, SECSEL0_A, O>;
75impl<'a, const O: u8> SECSEL0_W<'a, O> {
76    #[doc = "Disable simultaneous control"]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(SECSEL0_A::_0)
80    }
81    #[doc = "Enable simultaneous control"]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(SECSEL0_A::_1)
85    }
86}
87#[doc = "Field `SECSEL1` reader - Channel 1 Operation Enable Bit Simultaneous Control Channel Select"]
88pub type SECSEL1_R = crate::BitReader<SECSEL1_A>;
89#[doc = "Channel 1 Operation Enable Bit Simultaneous Control Channel Select\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum SECSEL1_A {
92    #[doc = "0: Disable simultaneous control"]
93    _0 = 0,
94    #[doc = "1: Enable simultaneous control"]
95    _1 = 1,
96}
97impl From<SECSEL1_A> for bool {
98    #[inline(always)]
99    fn from(variant: SECSEL1_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl SECSEL1_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> SECSEL1_A {
107        match self.bits {
108            false => SECSEL1_A::_0,
109            true => SECSEL1_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == SECSEL1_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == SECSEL1_A::_1
121    }
122}
123#[doc = "Field `SECSEL1` writer - Channel 1 Operation Enable Bit Simultaneous Control Channel Select"]
124pub type SECSEL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GTSECSR_SPEC, SECSEL1_A, O>;
125impl<'a, const O: u8> SECSEL1_W<'a, O> {
126    #[doc = "Disable simultaneous control"]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(SECSEL1_A::_0)
130    }
131    #[doc = "Enable simultaneous control"]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(SECSEL1_A::_1)
135    }
136}
137#[doc = "Field `SECSEL2` reader - Channel 2 Operation Enable Bit Simultaneous Control Channel Select"]
138pub type SECSEL2_R = crate::BitReader<SECSEL2_A>;
139#[doc = "Channel 2 Operation Enable Bit Simultaneous Control Channel Select\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum SECSEL2_A {
142    #[doc = "0: Disable simultaneous control"]
143    _0 = 0,
144    #[doc = "1: Enable simultaneous control"]
145    _1 = 1,
146}
147impl From<SECSEL2_A> for bool {
148    #[inline(always)]
149    fn from(variant: SECSEL2_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl SECSEL2_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> SECSEL2_A {
157        match self.bits {
158            false => SECSEL2_A::_0,
159            true => SECSEL2_A::_1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `_0`"]
163    #[inline(always)]
164    pub fn is_0(&self) -> bool {
165        *self == SECSEL2_A::_0
166    }
167    #[doc = "Checks if the value of the field is `_1`"]
168    #[inline(always)]
169    pub fn is_1(&self) -> bool {
170        *self == SECSEL2_A::_1
171    }
172}
173#[doc = "Field `SECSEL2` writer - Channel 2 Operation Enable Bit Simultaneous Control Channel Select"]
174pub type SECSEL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GTSECSR_SPEC, SECSEL2_A, O>;
175impl<'a, const O: u8> SECSEL2_W<'a, O> {
176    #[doc = "Disable simultaneous control"]
177    #[inline(always)]
178    pub fn _0(self) -> &'a mut W {
179        self.variant(SECSEL2_A::_0)
180    }
181    #[doc = "Enable simultaneous control"]
182    #[inline(always)]
183    pub fn _1(self) -> &'a mut W {
184        self.variant(SECSEL2_A::_1)
185    }
186}
187#[doc = "Field `SECSEL3` reader - Channel 3 Operation Enable Bit Simultaneous Control Channel Select"]
188pub type SECSEL3_R = crate::BitReader<SECSEL3_A>;
189#[doc = "Channel 3 Operation Enable Bit Simultaneous Control Channel Select\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum SECSEL3_A {
192    #[doc = "0: Disable simultaneous control"]
193    _0 = 0,
194    #[doc = "1: Enable simultaneous control"]
195    _1 = 1,
196}
197impl From<SECSEL3_A> for bool {
198    #[inline(always)]
199    fn from(variant: SECSEL3_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl SECSEL3_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> SECSEL3_A {
207        match self.bits {
208            false => SECSEL3_A::_0,
209            true => SECSEL3_A::_1,
210        }
211    }
212    #[doc = "Checks if the value of the field is `_0`"]
213    #[inline(always)]
214    pub fn is_0(&self) -> bool {
215        *self == SECSEL3_A::_0
216    }
217    #[doc = "Checks if the value of the field is `_1`"]
218    #[inline(always)]
219    pub fn is_1(&self) -> bool {
220        *self == SECSEL3_A::_1
221    }
222}
223#[doc = "Field `SECSEL3` writer - Channel 3 Operation Enable Bit Simultaneous Control Channel Select"]
224pub type SECSEL3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GTSECSR_SPEC, SECSEL3_A, O>;
225impl<'a, const O: u8> SECSEL3_W<'a, O> {
226    #[doc = "Disable simultaneous control"]
227    #[inline(always)]
228    pub fn _0(self) -> &'a mut W {
229        self.variant(SECSEL3_A::_0)
230    }
231    #[doc = "Enable simultaneous control"]
232    #[inline(always)]
233    pub fn _1(self) -> &'a mut W {
234        self.variant(SECSEL3_A::_1)
235    }
236}
237#[doc = "Field `SECSEL4` reader - Channel 4 Operation Enable Bit Simultaneous Control Channel Select"]
238pub type SECSEL4_R = crate::BitReader<SECSEL4_A>;
239#[doc = "Channel 4 Operation Enable Bit Simultaneous Control Channel Select\n\nValue on reset: 0"]
240#[derive(Clone, Copy, Debug, PartialEq, Eq)]
241pub enum SECSEL4_A {
242    #[doc = "0: Disable simultaneous control"]
243    _0 = 0,
244    #[doc = "1: Enable simultaneous control"]
245    _1 = 1,
246}
247impl From<SECSEL4_A> for bool {
248    #[inline(always)]
249    fn from(variant: SECSEL4_A) -> Self {
250        variant as u8 != 0
251    }
252}
253impl SECSEL4_R {
254    #[doc = "Get enumerated values variant"]
255    #[inline(always)]
256    pub fn variant(&self) -> SECSEL4_A {
257        match self.bits {
258            false => SECSEL4_A::_0,
259            true => SECSEL4_A::_1,
260        }
261    }
262    #[doc = "Checks if the value of the field is `_0`"]
263    #[inline(always)]
264    pub fn is_0(&self) -> bool {
265        *self == SECSEL4_A::_0
266    }
267    #[doc = "Checks if the value of the field is `_1`"]
268    #[inline(always)]
269    pub fn is_1(&self) -> bool {
270        *self == SECSEL4_A::_1
271    }
272}
273#[doc = "Field `SECSEL4` writer - Channel 4 Operation Enable Bit Simultaneous Control Channel Select"]
274pub type SECSEL4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GTSECSR_SPEC, SECSEL4_A, O>;
275impl<'a, const O: u8> SECSEL4_W<'a, O> {
276    #[doc = "Disable simultaneous control"]
277    #[inline(always)]
278    pub fn _0(self) -> &'a mut W {
279        self.variant(SECSEL4_A::_0)
280    }
281    #[doc = "Enable simultaneous control"]
282    #[inline(always)]
283    pub fn _1(self) -> &'a mut W {
284        self.variant(SECSEL4_A::_1)
285    }
286}
287#[doc = "Field `SECSEL5` reader - Channel 5 Operation Enable Bit Simultaneous Control Channel Select"]
288pub type SECSEL5_R = crate::BitReader<SECSEL5_A>;
289#[doc = "Channel 5 Operation Enable Bit Simultaneous Control Channel Select\n\nValue on reset: 0"]
290#[derive(Clone, Copy, Debug, PartialEq, Eq)]
291pub enum SECSEL5_A {
292    #[doc = "0: Disable simultaneous control"]
293    _0 = 0,
294    #[doc = "1: Enable simultaneous control"]
295    _1 = 1,
296}
297impl From<SECSEL5_A> for bool {
298    #[inline(always)]
299    fn from(variant: SECSEL5_A) -> Self {
300        variant as u8 != 0
301    }
302}
303impl SECSEL5_R {
304    #[doc = "Get enumerated values variant"]
305    #[inline(always)]
306    pub fn variant(&self) -> SECSEL5_A {
307        match self.bits {
308            false => SECSEL5_A::_0,
309            true => SECSEL5_A::_1,
310        }
311    }
312    #[doc = "Checks if the value of the field is `_0`"]
313    #[inline(always)]
314    pub fn is_0(&self) -> bool {
315        *self == SECSEL5_A::_0
316    }
317    #[doc = "Checks if the value of the field is `_1`"]
318    #[inline(always)]
319    pub fn is_1(&self) -> bool {
320        *self == SECSEL5_A::_1
321    }
322}
323#[doc = "Field `SECSEL5` writer - Channel 5 Operation Enable Bit Simultaneous Control Channel Select"]
324pub type SECSEL5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GTSECSR_SPEC, SECSEL5_A, O>;
325impl<'a, const O: u8> SECSEL5_W<'a, O> {
326    #[doc = "Disable simultaneous control"]
327    #[inline(always)]
328    pub fn _0(self) -> &'a mut W {
329        self.variant(SECSEL5_A::_0)
330    }
331    #[doc = "Enable simultaneous control"]
332    #[inline(always)]
333    pub fn _1(self) -> &'a mut W {
334        self.variant(SECSEL5_A::_1)
335    }
336}
337#[doc = "Field `SECSEL6` reader - Channel 6 Operation Enable Bit Simultaneous Control Channel Select"]
338pub type SECSEL6_R = crate::BitReader<SECSEL6_A>;
339#[doc = "Channel 6 Operation Enable Bit Simultaneous Control Channel Select\n\nValue on reset: 0"]
340#[derive(Clone, Copy, Debug, PartialEq, Eq)]
341pub enum SECSEL6_A {
342    #[doc = "0: Disable simultaneous control"]
343    _0 = 0,
344    #[doc = "1: Enable simultaneous control"]
345    _1 = 1,
346}
347impl From<SECSEL6_A> for bool {
348    #[inline(always)]
349    fn from(variant: SECSEL6_A) -> Self {
350        variant as u8 != 0
351    }
352}
353impl SECSEL6_R {
354    #[doc = "Get enumerated values variant"]
355    #[inline(always)]
356    pub fn variant(&self) -> SECSEL6_A {
357        match self.bits {
358            false => SECSEL6_A::_0,
359            true => SECSEL6_A::_1,
360        }
361    }
362    #[doc = "Checks if the value of the field is `_0`"]
363    #[inline(always)]
364    pub fn is_0(&self) -> bool {
365        *self == SECSEL6_A::_0
366    }
367    #[doc = "Checks if the value of the field is `_1`"]
368    #[inline(always)]
369    pub fn is_1(&self) -> bool {
370        *self == SECSEL6_A::_1
371    }
372}
373#[doc = "Field `SECSEL6` writer - Channel 6 Operation Enable Bit Simultaneous Control Channel Select"]
374pub type SECSEL6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GTSECSR_SPEC, SECSEL6_A, O>;
375impl<'a, const O: u8> SECSEL6_W<'a, O> {
376    #[doc = "Disable simultaneous control"]
377    #[inline(always)]
378    pub fn _0(self) -> &'a mut W {
379        self.variant(SECSEL6_A::_0)
380    }
381    #[doc = "Enable simultaneous control"]
382    #[inline(always)]
383    pub fn _1(self) -> &'a mut W {
384        self.variant(SECSEL6_A::_1)
385    }
386}
387#[doc = "Field `SECSEL7` reader - Channel 7 Operation Enable Bit Simultaneous Control Channel Select"]
388pub type SECSEL7_R = crate::BitReader<SECSEL7_A>;
389#[doc = "Channel 7 Operation Enable Bit Simultaneous Control Channel Select\n\nValue on reset: 0"]
390#[derive(Clone, Copy, Debug, PartialEq, Eq)]
391pub enum SECSEL7_A {
392    #[doc = "0: Disable simultaneous control"]
393    _0 = 0,
394    #[doc = "1: Enable simultaneous control"]
395    _1 = 1,
396}
397impl From<SECSEL7_A> for bool {
398    #[inline(always)]
399    fn from(variant: SECSEL7_A) -> Self {
400        variant as u8 != 0
401    }
402}
403impl SECSEL7_R {
404    #[doc = "Get enumerated values variant"]
405    #[inline(always)]
406    pub fn variant(&self) -> SECSEL7_A {
407        match self.bits {
408            false => SECSEL7_A::_0,
409            true => SECSEL7_A::_1,
410        }
411    }
412    #[doc = "Checks if the value of the field is `_0`"]
413    #[inline(always)]
414    pub fn is_0(&self) -> bool {
415        *self == SECSEL7_A::_0
416    }
417    #[doc = "Checks if the value of the field is `_1`"]
418    #[inline(always)]
419    pub fn is_1(&self) -> bool {
420        *self == SECSEL7_A::_1
421    }
422}
423#[doc = "Field `SECSEL7` writer - Channel 7 Operation Enable Bit Simultaneous Control Channel Select"]
424pub type SECSEL7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GTSECSR_SPEC, SECSEL7_A, O>;
425impl<'a, const O: u8> SECSEL7_W<'a, O> {
426    #[doc = "Disable simultaneous control"]
427    #[inline(always)]
428    pub fn _0(self) -> &'a mut W {
429        self.variant(SECSEL7_A::_0)
430    }
431    #[doc = "Enable simultaneous control"]
432    #[inline(always)]
433    pub fn _1(self) -> &'a mut W {
434        self.variant(SECSEL7_A::_1)
435    }
436}
437impl R {
438    #[doc = "Bit 0 - Channel 0 Operation Enable Bit Simultaneous Control Channel Select"]
439    #[inline(always)]
440    pub fn secsel0(&self) -> SECSEL0_R {
441        SECSEL0_R::new((self.bits & 1) != 0)
442    }
443    #[doc = "Bit 1 - Channel 1 Operation Enable Bit Simultaneous Control Channel Select"]
444    #[inline(always)]
445    pub fn secsel1(&self) -> SECSEL1_R {
446        SECSEL1_R::new(((self.bits >> 1) & 1) != 0)
447    }
448    #[doc = "Bit 2 - Channel 2 Operation Enable Bit Simultaneous Control Channel Select"]
449    #[inline(always)]
450    pub fn secsel2(&self) -> SECSEL2_R {
451        SECSEL2_R::new(((self.bits >> 2) & 1) != 0)
452    }
453    #[doc = "Bit 3 - Channel 3 Operation Enable Bit Simultaneous Control Channel Select"]
454    #[inline(always)]
455    pub fn secsel3(&self) -> SECSEL3_R {
456        SECSEL3_R::new(((self.bits >> 3) & 1) != 0)
457    }
458    #[doc = "Bit 4 - Channel 4 Operation Enable Bit Simultaneous Control Channel Select"]
459    #[inline(always)]
460    pub fn secsel4(&self) -> SECSEL4_R {
461        SECSEL4_R::new(((self.bits >> 4) & 1) != 0)
462    }
463    #[doc = "Bit 5 - Channel 5 Operation Enable Bit Simultaneous Control Channel Select"]
464    #[inline(always)]
465    pub fn secsel5(&self) -> SECSEL5_R {
466        SECSEL5_R::new(((self.bits >> 5) & 1) != 0)
467    }
468    #[doc = "Bit 6 - Channel 6 Operation Enable Bit Simultaneous Control Channel Select"]
469    #[inline(always)]
470    pub fn secsel6(&self) -> SECSEL6_R {
471        SECSEL6_R::new(((self.bits >> 6) & 1) != 0)
472    }
473    #[doc = "Bit 7 - Channel 7 Operation Enable Bit Simultaneous Control Channel Select"]
474    #[inline(always)]
475    pub fn secsel7(&self) -> SECSEL7_R {
476        SECSEL7_R::new(((self.bits >> 7) & 1) != 0)
477    }
478}
479impl W {
480    #[doc = "Bit 0 - Channel 0 Operation Enable Bit Simultaneous Control Channel Select"]
481    #[inline(always)]
482    #[must_use]
483    pub fn secsel0(&mut self) -> SECSEL0_W<0> {
484        SECSEL0_W::new(self)
485    }
486    #[doc = "Bit 1 - Channel 1 Operation Enable Bit Simultaneous Control Channel Select"]
487    #[inline(always)]
488    #[must_use]
489    pub fn secsel1(&mut self) -> SECSEL1_W<1> {
490        SECSEL1_W::new(self)
491    }
492    #[doc = "Bit 2 - Channel 2 Operation Enable Bit Simultaneous Control Channel Select"]
493    #[inline(always)]
494    #[must_use]
495    pub fn secsel2(&mut self) -> SECSEL2_W<2> {
496        SECSEL2_W::new(self)
497    }
498    #[doc = "Bit 3 - Channel 3 Operation Enable Bit Simultaneous Control Channel Select"]
499    #[inline(always)]
500    #[must_use]
501    pub fn secsel3(&mut self) -> SECSEL3_W<3> {
502        SECSEL3_W::new(self)
503    }
504    #[doc = "Bit 4 - Channel 4 Operation Enable Bit Simultaneous Control Channel Select"]
505    #[inline(always)]
506    #[must_use]
507    pub fn secsel4(&mut self) -> SECSEL4_W<4> {
508        SECSEL4_W::new(self)
509    }
510    #[doc = "Bit 5 - Channel 5 Operation Enable Bit Simultaneous Control Channel Select"]
511    #[inline(always)]
512    #[must_use]
513    pub fn secsel5(&mut self) -> SECSEL5_W<5> {
514        SECSEL5_W::new(self)
515    }
516    #[doc = "Bit 6 - Channel 6 Operation Enable Bit Simultaneous Control Channel Select"]
517    #[inline(always)]
518    #[must_use]
519    pub fn secsel6(&mut self) -> SECSEL6_W<6> {
520        SECSEL6_W::new(self)
521    }
522    #[doc = "Bit 7 - Channel 7 Operation Enable Bit Simultaneous Control Channel Select"]
523    #[inline(always)]
524    #[must_use]
525    pub fn secsel7(&mut self) -> SECSEL7_W<7> {
526        SECSEL7_W::new(self)
527    }
528    #[doc = "Writes raw bits to the register."]
529    #[inline(always)]
530    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
531        self.0.bits(bits);
532        self
533    }
534}
535#[doc = "General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gtsecsr](index.html) module"]
536pub struct GTSECSR_SPEC;
537impl crate::RegisterSpec for GTSECSR_SPEC {
538    type Ux = u32;
539}
540#[doc = "`read()` method returns [gtsecsr::R](R) reader structure"]
541impl crate::Readable for GTSECSR_SPEC {
542    type Reader = R;
543}
544#[doc = "`write(|w| ..)` method takes [gtsecsr::W](W) writer structure"]
545impl crate::Writable for GTSECSR_SPEC {
546    type Writer = W;
547    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
548    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
549}
550#[doc = "`reset()` method sets GTSECSR to value 0"]
551impl crate::Resettable for GTSECSR_SPEC {
552    const RESET_VALUE: Self::Ux = 0;
553}
ra4e1/gpt164/gtsecsr.rs

ra4e1/gpt164/
gtsecsr.rs
