1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Quad Serial Peripheral Interface"]
28unsafe impl ::core::marker::Send for super::Qspi {}
29unsafe impl ::core::marker::Sync for super::Qspi {}
30impl super::Qspi {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "Transfer Mode Control Register"]
38 #[inline(always)]
39 pub const fn sfmsmd(
40 &self,
41 ) -> &'static crate::common::Reg<self::Sfmsmd_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::Sfmsmd_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(0usize),
45 )
46 }
47 }
48
49 #[doc = "Chip Selection Control Register"]
50 #[inline(always)]
51 pub const fn sfmssc(
52 &self,
53 ) -> &'static crate::common::Reg<self::Sfmssc_SPEC, crate::common::RW> {
54 unsafe {
55 crate::common::Reg::<self::Sfmssc_SPEC, crate::common::RW>::from_ptr(
56 self._svd2pac_as_ptr().add(4usize),
57 )
58 }
59 }
60
61 #[doc = "Clock Control Register"]
62 #[inline(always)]
63 pub const fn sfmskc(
64 &self,
65 ) -> &'static crate::common::Reg<self::Sfmskc_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::Sfmskc_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(8usize),
69 )
70 }
71 }
72
73 #[doc = "Status Register"]
74 #[inline(always)]
75 pub const fn sfmsst(&self) -> &'static crate::common::Reg<self::Sfmsst_SPEC, crate::common::R> {
76 unsafe {
77 crate::common::Reg::<self::Sfmsst_SPEC, crate::common::R>::from_ptr(
78 self._svd2pac_as_ptr().add(12usize),
79 )
80 }
81 }
82
83 #[doc = "Communication Port Register"]
84 #[inline(always)]
85 pub const fn sfmcom(
86 &self,
87 ) -> &'static crate::common::Reg<self::Sfmcom_SPEC, crate::common::RW> {
88 unsafe {
89 crate::common::Reg::<self::Sfmcom_SPEC, crate::common::RW>::from_ptr(
90 self._svd2pac_as_ptr().add(16usize),
91 )
92 }
93 }
94
95 #[doc = "Communication Mode Control Register"]
96 #[inline(always)]
97 pub const fn sfmcmd(
98 &self,
99 ) -> &'static crate::common::Reg<self::Sfmcmd_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Sfmcmd_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(20usize),
103 )
104 }
105 }
106
107 #[doc = "Communication Status Register"]
108 #[inline(always)]
109 pub const fn sfmcst(
110 &self,
111 ) -> &'static crate::common::Reg<self::Sfmcst_SPEC, crate::common::RW> {
112 unsafe {
113 crate::common::Reg::<self::Sfmcst_SPEC, crate::common::RW>::from_ptr(
114 self._svd2pac_as_ptr().add(24usize),
115 )
116 }
117 }
118
119 #[doc = "Instruction Code Register"]
120 #[inline(always)]
121 pub const fn sfmsic(
122 &self,
123 ) -> &'static crate::common::Reg<self::Sfmsic_SPEC, crate::common::RW> {
124 unsafe {
125 crate::common::Reg::<self::Sfmsic_SPEC, crate::common::RW>::from_ptr(
126 self._svd2pac_as_ptr().add(32usize),
127 )
128 }
129 }
130
131 #[doc = "Address Mode Control Register"]
132 #[inline(always)]
133 pub const fn sfmsac(
134 &self,
135 ) -> &'static crate::common::Reg<self::Sfmsac_SPEC, crate::common::RW> {
136 unsafe {
137 crate::common::Reg::<self::Sfmsac_SPEC, crate::common::RW>::from_ptr(
138 self._svd2pac_as_ptr().add(36usize),
139 )
140 }
141 }
142
143 #[doc = "Dummy Cycle Control Register"]
144 #[inline(always)]
145 pub const fn sfmsdc(
146 &self,
147 ) -> &'static crate::common::Reg<self::Sfmsdc_SPEC, crate::common::RW> {
148 unsafe {
149 crate::common::Reg::<self::Sfmsdc_SPEC, crate::common::RW>::from_ptr(
150 self._svd2pac_as_ptr().add(40usize),
151 )
152 }
153 }
154
155 #[doc = "SPI Protocol Control Register"]
156 #[inline(always)]
157 pub const fn sfmspc(
158 &self,
159 ) -> &'static crate::common::Reg<self::Sfmspc_SPEC, crate::common::RW> {
160 unsafe {
161 crate::common::Reg::<self::Sfmspc_SPEC, crate::common::RW>::from_ptr(
162 self._svd2pac_as_ptr().add(48usize),
163 )
164 }
165 }
166
167 #[doc = "Port Control Register"]
168 #[inline(always)]
169 pub const fn sfmpmd(
170 &self,
171 ) -> &'static crate::common::Reg<self::Sfmpmd_SPEC, crate::common::RW> {
172 unsafe {
173 crate::common::Reg::<self::Sfmpmd_SPEC, crate::common::RW>::from_ptr(
174 self._svd2pac_as_ptr().add(52usize),
175 )
176 }
177 }
178
179 #[doc = "External QSPI Address Register"]
180 #[inline(always)]
181 pub const fn sfmcnt1(
182 &self,
183 ) -> &'static crate::common::Reg<self::Sfmcnt1_SPEC, crate::common::RW> {
184 unsafe {
185 crate::common::Reg::<self::Sfmcnt1_SPEC, crate::common::RW>::from_ptr(
186 self._svd2pac_as_ptr().add(2052usize),
187 )
188 }
189 }
190}
191#[doc(hidden)]
192#[derive(Copy, Clone, Eq, PartialEq)]
193pub struct Sfmsmd_SPEC;
194impl crate::sealed::RegSpec for Sfmsmd_SPEC {
195 type DataType = u32;
196}
197
198#[doc = "Transfer Mode Control Register"]
199pub type Sfmsmd = crate::RegValueT<Sfmsmd_SPEC>;
200
201impl Sfmsmd {
202 #[doc = "Serial interface read mode select"]
203 #[inline(always)]
204 pub fn sfmrm(
205 self,
206 ) -> crate::common::RegisterField<
207 0,
208 0x7,
209 1,
210 0,
211 sfmsmd::Sfmrm,
212 sfmsmd::Sfmrm,
213 Sfmsmd_SPEC,
214 crate::common::RW,
215 > {
216 crate::common::RegisterField::<
217 0,
218 0x7,
219 1,
220 0,
221 sfmsmd::Sfmrm,
222 sfmsmd::Sfmrm,
223 Sfmsmd_SPEC,
224 crate::common::RW,
225 >::from_register(self, 0)
226 }
227
228 #[doc = "QSSL extension function select after SPI bus access"]
229 #[inline(always)]
230 pub fn sfmse(
231 self,
232 ) -> crate::common::RegisterField<
233 4,
234 0x3,
235 1,
236 0,
237 sfmsmd::Sfmse,
238 sfmsmd::Sfmse,
239 Sfmsmd_SPEC,
240 crate::common::RW,
241 > {
242 crate::common::RegisterField::<
243 4,
244 0x3,
245 1,
246 0,
247 sfmsmd::Sfmse,
248 sfmsmd::Sfmse,
249 Sfmsmd_SPEC,
250 crate::common::RW,
251 >::from_register(self, 0)
252 }
253
254 #[doc = "Prefetch function select"]
255 #[inline(always)]
256 pub fn sfmpfe(
257 self,
258 ) -> crate::common::RegisterField<
259 6,
260 0x1,
261 1,
262 0,
263 sfmsmd::Sfmpfe,
264 sfmsmd::Sfmpfe,
265 Sfmsmd_SPEC,
266 crate::common::RW,
267 > {
268 crate::common::RegisterField::<
269 6,
270 0x1,
271 1,
272 0,
273 sfmsmd::Sfmpfe,
274 sfmsmd::Sfmpfe,
275 Sfmsmd_SPEC,
276 crate::common::RW,
277 >::from_register(self, 0)
278 }
279
280 #[doc = "Function select for stopping prefetch at locations other than on byte boundaries"]
281 #[inline(always)]
282 pub fn sfmpae(
283 self,
284 ) -> crate::common::RegisterField<
285 7,
286 0x1,
287 1,
288 0,
289 sfmsmd::Sfmpae,
290 sfmsmd::Sfmpae,
291 Sfmsmd_SPEC,
292 crate::common::RW,
293 > {
294 crate::common::RegisterField::<
295 7,
296 0x1,
297 1,
298 0,
299 sfmsmd::Sfmpae,
300 sfmsmd::Sfmpae,
301 Sfmsmd_SPEC,
302 crate::common::RW,
303 >::from_register(self, 0)
304 }
305
306 #[doc = "SPI mode select."]
307 #[inline(always)]
308 pub fn sfmmd3(
309 self,
310 ) -> crate::common::RegisterField<
311 8,
312 0x1,
313 1,
314 0,
315 sfmsmd::Sfmmd3,
316 sfmsmd::Sfmmd3,
317 Sfmsmd_SPEC,
318 crate::common::RW,
319 > {
320 crate::common::RegisterField::<
321 8,
322 0x1,
323 1,
324 0,
325 sfmsmd::Sfmmd3,
326 sfmsmd::Sfmmd3,
327 Sfmsmd_SPEC,
328 crate::common::RW,
329 >::from_register(self, 0)
330 }
331
332 #[doc = "Extension select for the I/O buffer output enable signal for the serial interface"]
333 #[inline(always)]
334 pub fn sfmoex(
335 self,
336 ) -> crate::common::RegisterField<
337 9,
338 0x1,
339 1,
340 0,
341 sfmsmd::Sfmoex,
342 sfmsmd::Sfmoex,
343 Sfmsmd_SPEC,
344 crate::common::RW,
345 > {
346 crate::common::RegisterField::<
347 9,
348 0x1,
349 1,
350 0,
351 sfmsmd::Sfmoex,
352 sfmsmd::Sfmoex,
353 Sfmsmd_SPEC,
354 crate::common::RW,
355 >::from_register(self, 0)
356 }
357
358 #[doc = "Hold time adjustment for serial transmission"]
359 #[inline(always)]
360 pub fn sfmohw(
361 self,
362 ) -> crate::common::RegisterField<
363 10,
364 0x1,
365 1,
366 0,
367 sfmsmd::Sfmohw,
368 sfmsmd::Sfmohw,
369 Sfmsmd_SPEC,
370 crate::common::RW,
371 > {
372 crate::common::RegisterField::<
373 10,
374 0x1,
375 1,
376 0,
377 sfmsmd::Sfmohw,
378 sfmsmd::Sfmohw,
379 Sfmsmd_SPEC,
380 crate::common::RW,
381 >::from_register(self, 0)
382 }
383
384 #[doc = "Setup time adjustment for serial transmission"]
385 #[inline(always)]
386 pub fn sfmosw(
387 self,
388 ) -> crate::common::RegisterField<
389 11,
390 0x1,
391 1,
392 0,
393 sfmsmd::Sfmosw,
394 sfmsmd::Sfmosw,
395 Sfmsmd_SPEC,
396 crate::common::RW,
397 > {
398 crate::common::RegisterField::<
399 11,
400 0x1,
401 1,
402 0,
403 sfmsmd::Sfmosw,
404 sfmsmd::Sfmosw,
405 Sfmsmd_SPEC,
406 crate::common::RW,
407 >::from_register(self, 0)
408 }
409
410 #[doc = "Read instruction code select"]
411 #[inline(always)]
412 pub fn sfmcce(
413 self,
414 ) -> crate::common::RegisterField<
415 15,
416 0x1,
417 1,
418 0,
419 sfmsmd::Sfmcce,
420 sfmsmd::Sfmcce,
421 Sfmsmd_SPEC,
422 crate::common::RW,
423 > {
424 crate::common::RegisterField::<
425 15,
426 0x1,
427 1,
428 0,
429 sfmsmd::Sfmcce,
430 sfmsmd::Sfmcce,
431 Sfmsmd_SPEC,
432 crate::common::RW,
433 >::from_register(self, 0)
434 }
435}
436impl ::core::default::Default for Sfmsmd {
437 #[inline(always)]
438 fn default() -> Sfmsmd {
439 <crate::RegValueT<Sfmsmd_SPEC> as RegisterValue<_>>::new(0)
440 }
441}
442pub mod sfmsmd {
443
444 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
445 pub struct Sfmrm_SPEC;
446 pub type Sfmrm = crate::EnumBitfieldStruct<u8, Sfmrm_SPEC>;
447 impl Sfmrm {
448 #[doc = "Standard Read"]
449 pub const _000: Self = Self::new(0);
450
451 #[doc = "Fast Read"]
452 pub const _001: Self = Self::new(1);
453
454 #[doc = "Fast Read Dual Output"]
455 pub const _010: Self = Self::new(2);
456
457 #[doc = "Fast Read Dual I/O"]
458 pub const _011: Self = Self::new(3);
459
460 #[doc = "Fast Read Quad Output"]
461 pub const _100: Self = Self::new(4);
462
463 #[doc = "Fast Read Quad I/O"]
464 pub const _101: Self = Self::new(5);
465 }
466 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
467 pub struct Sfmse_SPEC;
468 pub type Sfmse = crate::EnumBitfieldStruct<u8, Sfmse_SPEC>;
469 impl Sfmse {
470 #[doc = "Do not extend QSSL"]
471 pub const _00: Self = Self::new(0);
472
473 #[doc = "Extend QSSL by 33 QSPCLK"]
474 pub const _01: Self = Self::new(1);
475
476 #[doc = "Extend QSSL by 129 QSPCLK"]
477 pub const _10: Self = Self::new(2);
478
479 #[doc = "Extend QSSL infinitely"]
480 pub const _11: Self = Self::new(3);
481 }
482 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
483 pub struct Sfmpfe_SPEC;
484 pub type Sfmpfe = crate::EnumBitfieldStruct<u8, Sfmpfe_SPEC>;
485 impl Sfmpfe {
486 #[doc = "Disable function"]
487 pub const _0: Self = Self::new(0);
488
489 #[doc = "Enable function"]
490 pub const _1: Self = Self::new(1);
491 }
492 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
493 pub struct Sfmpae_SPEC;
494 pub type Sfmpae = crate::EnumBitfieldStruct<u8, Sfmpae_SPEC>;
495 impl Sfmpae {
496 #[doc = "Disable function"]
497 pub const _0: Self = Self::new(0);
498
499 #[doc = "Enable function"]
500 pub const _1: Self = Self::new(1);
501 }
502 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
503 pub struct Sfmmd3_SPEC;
504 pub type Sfmmd3 = crate::EnumBitfieldStruct<u8, Sfmmd3_SPEC>;
505 impl Sfmmd3 {
506 #[doc = "SPI mode 0"]
507 pub const _0: Self = Self::new(0);
508
509 #[doc = "SPI mode 3"]
510 pub const _1: Self = Self::new(1);
511 }
512 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
513 pub struct Sfmoex_SPEC;
514 pub type Sfmoex = crate::EnumBitfieldStruct<u8, Sfmoex_SPEC>;
515 impl Sfmoex {
516 #[doc = "Do not extend"]
517 pub const _0: Self = Self::new(0);
518
519 #[doc = "Extend by 1 QSPCLK"]
520 pub const _1: Self = Self::new(1);
521 }
522 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
523 pub struct Sfmohw_SPEC;
524 pub type Sfmohw = crate::EnumBitfieldStruct<u8, Sfmohw_SPEC>;
525 impl Sfmohw {
526 #[doc = "Do not extend high-level width of QSPCLK during transmission"]
527 pub const _0: Self = Self::new(0);
528
529 #[doc = "Extend high-level width of QSPCLK by 1 PCLKA during transmission"]
530 pub const _1: Self = Self::new(1);
531 }
532 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
533 pub struct Sfmosw_SPEC;
534 pub type Sfmosw = crate::EnumBitfieldStruct<u8, Sfmosw_SPEC>;
535 impl Sfmosw {
536 #[doc = "Do not extend low-level width of QSPCLK during transmission"]
537 pub const _0: Self = Self::new(0);
538
539 #[doc = "Extend low-level width of QSPCLK by 1 PCLKA during transmission"]
540 pub const _1: Self = Self::new(1);
541 }
542 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
543 pub struct Sfmcce_SPEC;
544 pub type Sfmcce = crate::EnumBitfieldStruct<u8, Sfmcce_SPEC>;
545 impl Sfmcce {
546 #[doc = "Uses automatically generated SPI instruction code"]
547 pub const _0: Self = Self::new(0);
548
549 #[doc = "Use instruction code in the SFMSIC register"]
550 pub const _1: Self = Self::new(1);
551 }
552}
553#[doc(hidden)]
554#[derive(Copy, Clone, Eq, PartialEq)]
555pub struct Sfmssc_SPEC;
556impl crate::sealed::RegSpec for Sfmssc_SPEC {
557 type DataType = u32;
558}
559
560#[doc = "Chip Selection Control Register"]
561pub type Sfmssc = crate::RegValueT<Sfmssc_SPEC>;
562
563impl Sfmssc {
564 #[doc = "Minimum High-level Width Select for QSSL Signal"]
565 #[inline(always)]
566 pub fn sfmsw(
567 self,
568 ) -> crate::common::RegisterField<
569 0,
570 0xf,
571 1,
572 0,
573 sfmssc::Sfmsw,
574 sfmssc::Sfmsw,
575 Sfmssc_SPEC,
576 crate::common::RW,
577 > {
578 crate::common::RegisterField::<
579 0,
580 0xf,
581 1,
582 0,
583 sfmssc::Sfmsw,
584 sfmssc::Sfmsw,
585 Sfmssc_SPEC,
586 crate::common::RW,
587 >::from_register(self, 0)
588 }
589
590 #[doc = "QSSL Signal Hold Time"]
591 #[inline(always)]
592 pub fn sfmshd(
593 self,
594 ) -> crate::common::RegisterField<
595 4,
596 0x1,
597 1,
598 0,
599 sfmssc::Sfmshd,
600 sfmssc::Sfmshd,
601 Sfmssc_SPEC,
602 crate::common::RW,
603 > {
604 crate::common::RegisterField::<
605 4,
606 0x1,
607 1,
608 0,
609 sfmssc::Sfmshd,
610 sfmssc::Sfmshd,
611 Sfmssc_SPEC,
612 crate::common::RW,
613 >::from_register(self, 0)
614 }
615
616 #[doc = "QSSL Signal Setup Time"]
617 #[inline(always)]
618 pub fn sfmsld(
619 self,
620 ) -> crate::common::RegisterField<
621 5,
622 0x1,
623 1,
624 0,
625 sfmssc::Sfmsld,
626 sfmssc::Sfmsld,
627 Sfmssc_SPEC,
628 crate::common::RW,
629 > {
630 crate::common::RegisterField::<
631 5,
632 0x1,
633 1,
634 0,
635 sfmssc::Sfmsld,
636 sfmssc::Sfmsld,
637 Sfmssc_SPEC,
638 crate::common::RW,
639 >::from_register(self, 0)
640 }
641}
642impl ::core::default::Default for Sfmssc {
643 #[inline(always)]
644 fn default() -> Sfmssc {
645 <crate::RegValueT<Sfmssc_SPEC> as RegisterValue<_>>::new(55)
646 }
647}
648pub mod sfmssc {
649
650 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
651 pub struct Sfmsw_SPEC;
652 pub type Sfmsw = crate::EnumBitfieldStruct<u8, Sfmsw_SPEC>;
653 impl Sfmsw {
654 #[doc = "1 QSPCLK"]
655 pub const _0_X_0: Self = Self::new(0);
656
657 #[doc = "2 QSPCLK"]
658 pub const _0_X_1: Self = Self::new(1);
659
660 #[doc = "3 QSPCLK"]
661 pub const _0_X_2: Self = Self::new(2);
662
663 #[doc = "4 QSPCLK"]
664 pub const _0_X_3: Self = Self::new(3);
665
666 #[doc = "5 QSPCLK"]
667 pub const _0_X_4: Self = Self::new(4);
668
669 #[doc = "6 QSPCLK"]
670 pub const _0_X_5: Self = Self::new(5);
671
672 #[doc = "7 QSPCLK"]
673 pub const _0_X_6: Self = Self::new(6);
674
675 #[doc = "8 QSPCLK"]
676 pub const _0_X_7: Self = Self::new(7);
677
678 #[doc = "9 QSPCLK"]
679 pub const _0_X_8: Self = Self::new(8);
680
681 #[doc = "10 QSPCLK"]
682 pub const _0_X_9: Self = Self::new(9);
683
684 #[doc = "11 QSPCLK"]
685 pub const _0_X_A: Self = Self::new(10);
686
687 #[doc = "12 QSPCLK"]
688 pub const _0_X_B: Self = Self::new(11);
689
690 #[doc = "13 QSPCLK"]
691 pub const _0_X_C: Self = Self::new(12);
692
693 #[doc = "14 QSPCLK"]
694 pub const _0_X_D: Self = Self::new(13);
695
696 #[doc = "15 QSPCLK"]
697 pub const _0_X_E: Self = Self::new(14);
698
699 #[doc = "16 QSPCLK"]
700 pub const _0_X_F: Self = Self::new(15);
701 }
702 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
703 pub struct Sfmshd_SPEC;
704 pub type Sfmshd = crate::EnumBitfieldStruct<u8, Sfmshd_SPEC>;
705 impl Sfmshd {
706 #[doc = "QSSL outputs high after 0.5 QSPCLK cycles from the last rising edge of QSPCLK."]
707 pub const _0: Self = Self::new(0);
708
709 #[doc = "QSSL outputs high after 1.5 QSPCLK cycles from the last rising edge of QSPCLK."]
710 pub const _1: Self = Self::new(1);
711 }
712 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
713 pub struct Sfmsld_SPEC;
714 pub type Sfmsld = crate::EnumBitfieldStruct<u8, Sfmsld_SPEC>;
715 impl Sfmsld {
716 #[doc = "QSSL outputs low before 0.5 QSPCLK cycles from the first rising edge of QSPCLK."]
717 pub const _0: Self = Self::new(0);
718
719 #[doc = "QSSL outputs low before 1.5 QSPCLK cycles from the first rising edge of QSPCLK."]
720 pub const _1: Self = Self::new(1);
721 }
722}
723#[doc(hidden)]
724#[derive(Copy, Clone, Eq, PartialEq)]
725pub struct Sfmskc_SPEC;
726impl crate::sealed::RegSpec for Sfmskc_SPEC {
727 type DataType = u32;
728}
729
730#[doc = "Clock Control Register"]
731pub type Sfmskc = crate::RegValueT<Sfmskc_SPEC>;
732
733impl Sfmskc {
734 #[doc = "Serial interface reference cycle select. (Pay attention to irregularities.)"]
735 #[inline(always)]
736 pub fn sfmdv(
737 self,
738 ) -> crate::common::RegisterField<
739 0,
740 0x1f,
741 1,
742 0,
743 sfmskc::Sfmdv,
744 sfmskc::Sfmdv,
745 Sfmskc_SPEC,
746 crate::common::RW,
747 > {
748 crate::common::RegisterField::<
749 0,
750 0x1f,
751 1,
752 0,
753 sfmskc::Sfmdv,
754 sfmskc::Sfmdv,
755 Sfmskc_SPEC,
756 crate::common::RW,
757 >::from_register(self, 0)
758 }
759
760 #[doc = "Duty ratio correction function select for the QSPCLK signal when divided by an odd number"]
761 #[inline(always)]
762 pub fn sfmdty(
763 self,
764 ) -> crate::common::RegisterField<
765 5,
766 0x1,
767 1,
768 0,
769 sfmskc::Sfmdty,
770 sfmskc::Sfmdty,
771 Sfmskc_SPEC,
772 crate::common::RW,
773 > {
774 crate::common::RegisterField::<
775 5,
776 0x1,
777 1,
778 0,
779 sfmskc::Sfmdty,
780 sfmskc::Sfmdty,
781 Sfmskc_SPEC,
782 crate::common::RW,
783 >::from_register(self, 0)
784 }
785}
786impl ::core::default::Default for Sfmskc {
787 #[inline(always)]
788 fn default() -> Sfmskc {
789 <crate::RegValueT<Sfmskc_SPEC> as RegisterValue<_>>::new(8)
790 }
791}
792pub mod sfmskc {
793
794 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
795 pub struct Sfmdv_SPEC;
796 pub type Sfmdv = crate::EnumBitfieldStruct<u8, Sfmdv_SPEC>;
797 impl Sfmdv {
798 #[doc = "2 PCLKA"]
799 pub const _0_X_00: Self = Self::new(0);
800
801 #[doc = "3 PCLKA (divided by an odd number)"]
802 pub const _0_X_01: Self = Self::new(1);
803
804 #[doc = "4 PCLKA"]
805 pub const _0_X_02: Self = Self::new(2);
806
807 #[doc = "5 PCLKA (divided by an odd number)"]
808 pub const _0_X_03: Self = Self::new(3);
809
810 #[doc = "6 PCLKA"]
811 pub const _0_X_04: Self = Self::new(4);
812
813 #[doc = "7 PCLKA (divided by an odd number)"]
814 pub const _0_X_05: Self = Self::new(5);
815
816 #[doc = "8 PCLKA"]
817 pub const _0_X_06: Self = Self::new(6);
818
819 #[doc = "9 PCLKA (divided by an odd number)"]
820 pub const _0_X_07: Self = Self::new(7);
821
822 #[doc = "10 PCLKA"]
823 pub const _0_X_08: Self = Self::new(8);
824
825 #[doc = "11 PCLKA (divided by an odd number)"]
826 pub const _0_X_09: Self = Self::new(9);
827
828 #[doc = "12 PCLKA"]
829 pub const _0_X_0_A: Self = Self::new(10);
830
831 #[doc = "13 PCLKA (divided by an odd number)"]
832 pub const _0_X_0_B: Self = Self::new(11);
833
834 #[doc = "14 PCLKA"]
835 pub const _0_X_0_C: Self = Self::new(12);
836
837 #[doc = "15 PCLKA (divided by an odd number)"]
838 pub const _0_X_0_D: Self = Self::new(13);
839
840 #[doc = "16 PCLKA"]
841 pub const _0_X_0_E: Self = Self::new(14);
842
843 #[doc = "17 PCLKA (divided by an odd number)"]
844 pub const _0_X_0_F: Self = Self::new(15);
845
846 #[doc = "18 PCLKA"]
847 pub const _0_X_10: Self = Self::new(16);
848
849 #[doc = "20 PCLKA"]
850 pub const _0_X_11: Self = Self::new(17);
851
852 #[doc = "22 PCLKA"]
853 pub const _0_X_12: Self = Self::new(18);
854
855 #[doc = "24 PCLKA"]
856 pub const _0_X_13: Self = Self::new(19);
857
858 #[doc = "26 PCLKA"]
859 pub const _0_X_14: Self = Self::new(20);
860
861 #[doc = "28 PCLKA"]
862 pub const _0_X_15: Self = Self::new(21);
863
864 #[doc = "30 PCLKA"]
865 pub const _0_X_16: Self = Self::new(22);
866
867 #[doc = "32 PCLKA"]
868 pub const _0_X_17: Self = Self::new(23);
869
870 #[doc = "34 PCLKA"]
871 pub const _0_X_18: Self = Self::new(24);
872
873 #[doc = "36 PCLKA"]
874 pub const _0_X_19: Self = Self::new(25);
875
876 #[doc = "38 PCLKA"]
877 pub const _0_X_1_A: Self = Self::new(26);
878
879 #[doc = "40 PCLKA"]
880 pub const _0_X_1_B: Self = Self::new(27);
881
882 #[doc = "42 PCLKA"]
883 pub const _0_X_1_C: Self = Self::new(28);
884
885 #[doc = "44 PCLKA"]
886 pub const _0_X_1_D: Self = Self::new(29);
887
888 #[doc = "46 PCLKA"]
889 pub const _0_X_1_E: Self = Self::new(30);
890
891 #[doc = "48 PCLKA"]
892 pub const _0_X_1_F: Self = Self::new(31);
893 }
894 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
895 pub struct Sfmdty_SPEC;
896 pub type Sfmdty = crate::EnumBitfieldStruct<u8, Sfmdty_SPEC>;
897 impl Sfmdty {
898 #[doc = "Make no correction"]
899 pub const _0: Self = Self::new(0);
900
901 #[doc = "Make correction"]
902 pub const _1: Self = Self::new(1);
903 }
904}
905#[doc(hidden)]
906#[derive(Copy, Clone, Eq, PartialEq)]
907pub struct Sfmsst_SPEC;
908impl crate::sealed::RegSpec for Sfmsst_SPEC {
909 type DataType = u32;
910}
911
912#[doc = "Status Register"]
913pub type Sfmsst = crate::RegValueT<Sfmsst_SPEC>;
914
915impl Sfmsst {
916 #[doc = "Number of bytes of prefetched data"]
917 #[inline(always)]
918 pub fn pfcnt(
919 self,
920 ) -> crate::common::RegisterField<
921 0,
922 0x1f,
923 1,
924 0,
925 sfmsst::Pfcnt,
926 sfmsst::Pfcnt,
927 Sfmsst_SPEC,
928 crate::common::R,
929 > {
930 crate::common::RegisterField::<
931 0,
932 0x1f,
933 1,
934 0,
935 sfmsst::Pfcnt,
936 sfmsst::Pfcnt,
937 Sfmsst_SPEC,
938 crate::common::R,
939 >::from_register(self, 0)
940 }
941
942 #[doc = "Prefetch buffer state"]
943 #[inline(always)]
944 pub fn pfful(
945 self,
946 ) -> crate::common::RegisterField<
947 6,
948 0x1,
949 1,
950 0,
951 sfmsst::Pfful,
952 sfmsst::Pfful,
953 Sfmsst_SPEC,
954 crate::common::R,
955 > {
956 crate::common::RegisterField::<
957 6,
958 0x1,
959 1,
960 0,
961 sfmsst::Pfful,
962 sfmsst::Pfful,
963 Sfmsst_SPEC,
964 crate::common::R,
965 >::from_register(self, 0)
966 }
967
968 #[doc = "Prefetch function operating state"]
969 #[inline(always)]
970 pub fn pfoff(
971 self,
972 ) -> crate::common::RegisterField<
973 7,
974 0x1,
975 1,
976 0,
977 sfmsst::Pfoff,
978 sfmsst::Pfoff,
979 Sfmsst_SPEC,
980 crate::common::R,
981 > {
982 crate::common::RegisterField::<
983 7,
984 0x1,
985 1,
986 0,
987 sfmsst::Pfoff,
988 sfmsst::Pfoff,
989 Sfmsst_SPEC,
990 crate::common::R,
991 >::from_register(self, 0)
992 }
993}
994impl ::core::default::Default for Sfmsst {
995 #[inline(always)]
996 fn default() -> Sfmsst {
997 <crate::RegValueT<Sfmsst_SPEC> as RegisterValue<_>>::new(128)
998 }
999}
1000pub mod sfmsst {
1001
1002 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1003 pub struct Pfcnt_SPEC;
1004 pub type Pfcnt = crate::EnumBitfieldStruct<u8, Pfcnt_SPEC>;
1005 impl Pfcnt {
1006 #[doc = "0 byte"]
1007 pub const _0_X_00: Self = Self::new(0);
1008
1009 #[doc = "1 byte"]
1010 pub const _0_X_01: Self = Self::new(1);
1011
1012 #[doc = "2 bytes"]
1013 pub const _0_X_02: Self = Self::new(2);
1014
1015 #[doc = "3 bytes"]
1016 pub const _0_X_03: Self = Self::new(3);
1017
1018 #[doc = "4 bytes"]
1019 pub const _0_X_04: Self = Self::new(4);
1020
1021 #[doc = "5 bytes"]
1022 pub const _0_X_05: Self = Self::new(5);
1023
1024 #[doc = "6 bytes"]
1025 pub const _0_X_06: Self = Self::new(6);
1026
1027 #[doc = "7 bytes"]
1028 pub const _0_X_07: Self = Self::new(7);
1029
1030 #[doc = "8 bytes"]
1031 pub const _0_X_08: Self = Self::new(8);
1032
1033 #[doc = "9 bytes"]
1034 pub const _0_X_09: Self = Self::new(9);
1035
1036 #[doc = "10 bytes"]
1037 pub const _0_X_0_A: Self = Self::new(10);
1038
1039 #[doc = "11 bytes"]
1040 pub const _0_X_0_B: Self = Self::new(11);
1041
1042 #[doc = "12 bytes"]
1043 pub const _0_X_0_C: Self = Self::new(12);
1044
1045 #[doc = "13 bytes"]
1046 pub const _0_X_0_D: Self = Self::new(13);
1047
1048 #[doc = "14 bytes"]
1049 pub const _0_X_0_E: Self = Self::new(14);
1050
1051 #[doc = "15 bytes"]
1052 pub const _0_X_0_F: Self = Self::new(15);
1053
1054 #[doc = "16 bytes"]
1055 pub const _0_X_10: Self = Self::new(16);
1056
1057 #[doc = "17 bytes"]
1058 pub const _0_X_11: Self = Self::new(17);
1059
1060 #[doc = "18 bytes"]
1061 pub const _0_X_12: Self = Self::new(18);
1062 }
1063 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1064 pub struct Pfful_SPEC;
1065 pub type Pfful = crate::EnumBitfieldStruct<u8, Pfful_SPEC>;
1066 impl Pfful {
1067 #[doc = "Prefetch buffer has free space"]
1068 pub const _0: Self = Self::new(0);
1069
1070 #[doc = "Prefetch buffer is full"]
1071 pub const _1: Self = Self::new(1);
1072 }
1073 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1074 pub struct Pfoff_SPEC;
1075 pub type Pfoff = crate::EnumBitfieldStruct<u8, Pfoff_SPEC>;
1076 impl Pfoff {
1077 #[doc = "Prefetch function operating"]
1078 pub const _0: Self = Self::new(0);
1079
1080 #[doc = "Prefetch function not enabled or not operating"]
1081 pub const _1: Self = Self::new(1);
1082 }
1083}
1084#[doc(hidden)]
1085#[derive(Copy, Clone, Eq, PartialEq)]
1086pub struct Sfmcom_SPEC;
1087impl crate::sealed::RegSpec for Sfmcom_SPEC {
1088 type DataType = u32;
1089}
1090
1091#[doc = "Communication Port Register"]
1092pub type Sfmcom = crate::RegValueT<Sfmcom_SPEC>;
1093
1094impl Sfmcom {
1095 #[doc = "Port for direct communication with the SPI bus"]
1096 #[inline(always)]
1097 pub fn sfmd(
1098 self,
1099 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Sfmcom_SPEC, crate::common::RW> {
1100 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Sfmcom_SPEC,crate::common::RW>::from_register(self,0)
1101 }
1102}
1103impl ::core::default::Default for Sfmcom {
1104 #[inline(always)]
1105 fn default() -> Sfmcom {
1106 <crate::RegValueT<Sfmcom_SPEC> as RegisterValue<_>>::new(0)
1107 }
1108}
1109
1110#[doc(hidden)]
1111#[derive(Copy, Clone, Eq, PartialEq)]
1112pub struct Sfmcmd_SPEC;
1113impl crate::sealed::RegSpec for Sfmcmd_SPEC {
1114 type DataType = u32;
1115}
1116
1117#[doc = "Communication Mode Control Register"]
1118pub type Sfmcmd = crate::RegValueT<Sfmcmd_SPEC>;
1119
1120impl Sfmcmd {
1121 #[doc = "Mode select for communication with the SPI bus"]
1122 #[inline(always)]
1123 pub fn dcom(
1124 self,
1125 ) -> crate::common::RegisterField<
1126 0,
1127 0x1,
1128 1,
1129 0,
1130 sfmcmd::Dcom,
1131 sfmcmd::Dcom,
1132 Sfmcmd_SPEC,
1133 crate::common::RW,
1134 > {
1135 crate::common::RegisterField::<
1136 0,
1137 0x1,
1138 1,
1139 0,
1140 sfmcmd::Dcom,
1141 sfmcmd::Dcom,
1142 Sfmcmd_SPEC,
1143 crate::common::RW,
1144 >::from_register(self, 0)
1145 }
1146}
1147impl ::core::default::Default for Sfmcmd {
1148 #[inline(always)]
1149 fn default() -> Sfmcmd {
1150 <crate::RegValueT<Sfmcmd_SPEC> as RegisterValue<_>>::new(0)
1151 }
1152}
1153pub mod sfmcmd {
1154
1155 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1156 pub struct Dcom_SPEC;
1157 pub type Dcom = crate::EnumBitfieldStruct<u8, Dcom_SPEC>;
1158 impl Dcom {
1159 #[doc = "ROM access mode"]
1160 pub const _0: Self = Self::new(0);
1161
1162 #[doc = "Direct communication mode"]
1163 pub const _1: Self = Self::new(1);
1164 }
1165}
1166#[doc(hidden)]
1167#[derive(Copy, Clone, Eq, PartialEq)]
1168pub struct Sfmcst_SPEC;
1169impl crate::sealed::RegSpec for Sfmcst_SPEC {
1170 type DataType = u32;
1171}
1172
1173#[doc = "Communication Status Register"]
1174pub type Sfmcst = crate::RegValueT<Sfmcst_SPEC>;
1175
1176impl Sfmcst {
1177 #[doc = "SPI bus cycle completion state in direct communication"]
1178 #[inline(always)]
1179 pub fn combsy(
1180 self,
1181 ) -> crate::common::RegisterField<
1182 0,
1183 0x1,
1184 1,
1185 0,
1186 sfmcst::Combsy,
1187 sfmcst::Combsy,
1188 Sfmcst_SPEC,
1189 crate::common::R,
1190 > {
1191 crate::common::RegisterField::<
1192 0,
1193 0x1,
1194 1,
1195 0,
1196 sfmcst::Combsy,
1197 sfmcst::Combsy,
1198 Sfmcst_SPEC,
1199 crate::common::R,
1200 >::from_register(self, 0)
1201 }
1202
1203 #[doc = "ROM access detection status in direct communication mode"]
1204 #[inline(always)]
1205 pub fn eromr(
1206 self,
1207 ) -> crate::common::RegisterField<
1208 7,
1209 0x1,
1210 1,
1211 0,
1212 sfmcst::Eromr,
1213 sfmcst::Eromr,
1214 Sfmcst_SPEC,
1215 crate::common::RW,
1216 > {
1217 crate::common::RegisterField::<
1218 7,
1219 0x1,
1220 1,
1221 0,
1222 sfmcst::Eromr,
1223 sfmcst::Eromr,
1224 Sfmcst_SPEC,
1225 crate::common::RW,
1226 >::from_register(self, 0)
1227 }
1228}
1229impl ::core::default::Default for Sfmcst {
1230 #[inline(always)]
1231 fn default() -> Sfmcst {
1232 <crate::RegValueT<Sfmcst_SPEC> as RegisterValue<_>>::new(0)
1233 }
1234}
1235pub mod sfmcst {
1236
1237 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1238 pub struct Combsy_SPEC;
1239 pub type Combsy = crate::EnumBitfieldStruct<u8, Combsy_SPEC>;
1240 impl Combsy {
1241 #[doc = "No serial transfer being processed"]
1242 pub const _0: Self = Self::new(0);
1243
1244 #[doc = "Serial transfer being processed"]
1245 pub const _1: Self = Self::new(1);
1246 }
1247 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1248 pub struct Eromr_SPEC;
1249 pub type Eromr = crate::EnumBitfieldStruct<u8, Eromr_SPEC>;
1250 impl Eromr {
1251 #[doc = "ROM access not detected"]
1252 pub const _0: Self = Self::new(0);
1253
1254 #[doc = "ROM access detected"]
1255 pub const _1: Self = Self::new(1);
1256 }
1257}
1258#[doc(hidden)]
1259#[derive(Copy, Clone, Eq, PartialEq)]
1260pub struct Sfmsic_SPEC;
1261impl crate::sealed::RegSpec for Sfmsic_SPEC {
1262 type DataType = u32;
1263}
1264
1265#[doc = "Instruction Code Register"]
1266pub type Sfmsic = crate::RegValueT<Sfmsic_SPEC>;
1267
1268impl Sfmsic {
1269 #[doc = "Serial flash instruction code to substitute"]
1270 #[inline(always)]
1271 pub fn sfmcic(
1272 self,
1273 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Sfmsic_SPEC, crate::common::RW> {
1274 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Sfmsic_SPEC,crate::common::RW>::from_register(self,0)
1275 }
1276}
1277impl ::core::default::Default for Sfmsic {
1278 #[inline(always)]
1279 fn default() -> Sfmsic {
1280 <crate::RegValueT<Sfmsic_SPEC> as RegisterValue<_>>::new(0)
1281 }
1282}
1283
1284#[doc(hidden)]
1285#[derive(Copy, Clone, Eq, PartialEq)]
1286pub struct Sfmsac_SPEC;
1287impl crate::sealed::RegSpec for Sfmsac_SPEC {
1288 type DataType = u32;
1289}
1290
1291#[doc = "Address Mode Control Register"]
1292pub type Sfmsac = crate::RegValueT<Sfmsac_SPEC>;
1293
1294impl Sfmsac {
1295 #[doc = "Number of address bytes select for the serial interface"]
1296 #[inline(always)]
1297 pub fn sfmas(
1298 self,
1299 ) -> crate::common::RegisterField<
1300 0,
1301 0x3,
1302 1,
1303 0,
1304 sfmsac::Sfmas,
1305 sfmsac::Sfmas,
1306 Sfmsac_SPEC,
1307 crate::common::RW,
1308 > {
1309 crate::common::RegisterField::<
1310 0,
1311 0x3,
1312 1,
1313 0,
1314 sfmsac::Sfmas,
1315 sfmsac::Sfmas,
1316 Sfmsac_SPEC,
1317 crate::common::RW,
1318 >::from_register(self, 0)
1319 }
1320
1321 #[doc = "Selection of instruction code automatically generated when the serial interface address width is 4 bytes"]
1322 #[inline(always)]
1323 pub fn sfm4bc(
1324 self,
1325 ) -> crate::common::RegisterField<
1326 4,
1327 0x1,
1328 1,
1329 0,
1330 sfmsac::Sfm4Bc,
1331 sfmsac::Sfm4Bc,
1332 Sfmsac_SPEC,
1333 crate::common::RW,
1334 > {
1335 crate::common::RegisterField::<
1336 4,
1337 0x1,
1338 1,
1339 0,
1340 sfmsac::Sfm4Bc,
1341 sfmsac::Sfm4Bc,
1342 Sfmsac_SPEC,
1343 crate::common::RW,
1344 >::from_register(self, 0)
1345 }
1346}
1347impl ::core::default::Default for Sfmsac {
1348 #[inline(always)]
1349 fn default() -> Sfmsac {
1350 <crate::RegValueT<Sfmsac_SPEC> as RegisterValue<_>>::new(2)
1351 }
1352}
1353pub mod sfmsac {
1354
1355 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1356 pub struct Sfmas_SPEC;
1357 pub type Sfmas = crate::EnumBitfieldStruct<u8, Sfmas_SPEC>;
1358 impl Sfmas {
1359 #[doc = "1 byte"]
1360 pub const _00: Self = Self::new(0);
1361
1362 #[doc = "2 bytes"]
1363 pub const _01: Self = Self::new(1);
1364
1365 #[doc = "3 bytes"]
1366 pub const _10: Self = Self::new(2);
1367
1368 #[doc = "4 bytes"]
1369 pub const _11: Self = Self::new(3);
1370 }
1371 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1372 pub struct Sfm4Bc_SPEC;
1373 pub type Sfm4Bc = crate::EnumBitfieldStruct<u8, Sfm4Bc_SPEC>;
1374 impl Sfm4Bc {
1375 #[doc = "Do not use 4-byte address read instruction code"]
1376 pub const _0: Self = Self::new(0);
1377
1378 #[doc = "Use 4-byte address read instruction code"]
1379 pub const _1: Self = Self::new(1);
1380 }
1381}
1382#[doc(hidden)]
1383#[derive(Copy, Clone, Eq, PartialEq)]
1384pub struct Sfmsdc_SPEC;
1385impl crate::sealed::RegSpec for Sfmsdc_SPEC {
1386 type DataType = u32;
1387}
1388
1389#[doc = "Dummy Cycle Control Register"]
1390pub type Sfmsdc = crate::RegValueT<Sfmsdc_SPEC>;
1391
1392impl Sfmsdc {
1393 #[doc = "Number of dummy cycles select for Fast Read instructions"]
1394 #[inline(always)]
1395 pub fn sfmdn(
1396 self,
1397 ) -> crate::common::RegisterField<
1398 0,
1399 0xf,
1400 1,
1401 0,
1402 sfmsdc::Sfmdn,
1403 sfmsdc::Sfmdn,
1404 Sfmsdc_SPEC,
1405 crate::common::RW,
1406 > {
1407 crate::common::RegisterField::<
1408 0,
1409 0xf,
1410 1,
1411 0,
1412 sfmsdc::Sfmdn,
1413 sfmsdc::Sfmdn,
1414 Sfmsdc_SPEC,
1415 crate::common::RW,
1416 >::from_register(self, 0)
1417 }
1418
1419 #[doc = "XIP mode status"]
1420 #[inline(always)]
1421 pub fn sfmxst(
1422 self,
1423 ) -> crate::common::RegisterField<
1424 6,
1425 0x1,
1426 1,
1427 0,
1428 sfmsdc::Sfmxst,
1429 sfmsdc::Sfmxst,
1430 Sfmsdc_SPEC,
1431 crate::common::R,
1432 > {
1433 crate::common::RegisterField::<
1434 6,
1435 0x1,
1436 1,
1437 0,
1438 sfmsdc::Sfmxst,
1439 sfmsdc::Sfmxst,
1440 Sfmsdc_SPEC,
1441 crate::common::R,
1442 >::from_register(self, 0)
1443 }
1444
1445 #[doc = "XIP mode permission"]
1446 #[inline(always)]
1447 pub fn sfmxen(
1448 self,
1449 ) -> crate::common::RegisterField<
1450 7,
1451 0x1,
1452 1,
1453 0,
1454 sfmsdc::Sfmxen,
1455 sfmsdc::Sfmxen,
1456 Sfmsdc_SPEC,
1457 crate::common::RW,
1458 > {
1459 crate::common::RegisterField::<
1460 7,
1461 0x1,
1462 1,
1463 0,
1464 sfmsdc::Sfmxen,
1465 sfmsdc::Sfmxen,
1466 Sfmsdc_SPEC,
1467 crate::common::RW,
1468 >::from_register(self, 0)
1469 }
1470
1471 #[doc = "Mode data for serial flash (Controls XIP mode.)"]
1472 #[inline(always)]
1473 pub fn sfmxd(
1474 self,
1475 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Sfmsdc_SPEC, crate::common::RW> {
1476 crate::common::RegisterField::<8,0xff,1,0,u8,u8,Sfmsdc_SPEC,crate::common::RW>::from_register(self,0)
1477 }
1478}
1479impl ::core::default::Default for Sfmsdc {
1480 #[inline(always)]
1481 fn default() -> Sfmsdc {
1482 <crate::RegValueT<Sfmsdc_SPEC> as RegisterValue<_>>::new(65280)
1483 }
1484}
1485pub mod sfmsdc {
1486
1487 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1488 pub struct Sfmdn_SPEC;
1489 pub type Sfmdn = crate::EnumBitfieldStruct<u8, Sfmdn_SPEC>;
1490 impl Sfmdn {
1491 #[doc = "Default dummy cycles for each instruction: - Fast Read Quad I/O: 6 QSPCLK - Fast Read Quad Output: 8 QSPCLK - Fast Read Dual I/O: 4 QSPCLK - Fast Read Dual Output: 8 QSPCLK - Fast Read: 8 QSPCLK"]
1492 pub const _0_X_0: Self = Self::new(0);
1493
1494 #[doc = "3 QSPCLK"]
1495 pub const _0_X_1: Self = Self::new(1);
1496
1497 #[doc = "4 QSPCLK"]
1498 pub const _0_X_2: Self = Self::new(2);
1499
1500 #[doc = "5 QSPCLK"]
1501 pub const _0_X_3: Self = Self::new(3);
1502
1503 #[doc = "6 QSPCLK"]
1504 pub const _0_X_4: Self = Self::new(4);
1505
1506 #[doc = "7 QSPCLK"]
1507 pub const _0_X_5: Self = Self::new(5);
1508
1509 #[doc = "8 QSPCLK"]
1510 pub const _0_X_6: Self = Self::new(6);
1511
1512 #[doc = "9 QSPCLK"]
1513 pub const _0_X_7: Self = Self::new(7);
1514
1515 #[doc = "10 QSPCLK"]
1516 pub const _0_X_8: Self = Self::new(8);
1517
1518 #[doc = "11 QSPCLK"]
1519 pub const _0_X_9: Self = Self::new(9);
1520
1521 #[doc = "12 QSPCLK"]
1522 pub const _0_X_A: Self = Self::new(10);
1523
1524 #[doc = "13 QSPCLK"]
1525 pub const _0_X_B: Self = Self::new(11);
1526
1527 #[doc = "14 QSPCLK"]
1528 pub const _0_X_C: Self = Self::new(12);
1529
1530 #[doc = "15 QSPCLK"]
1531 pub const _0_X_D: Self = Self::new(13);
1532
1533 #[doc = "16 QSPCLK"]
1534 pub const _0_X_E: Self = Self::new(14);
1535
1536 #[doc = "17 QSPCLK"]
1537 pub const _0_X_F: Self = Self::new(15);
1538 }
1539 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1540 pub struct Sfmxst_SPEC;
1541 pub type Sfmxst = crate::EnumBitfieldStruct<u8, Sfmxst_SPEC>;
1542 impl Sfmxst {
1543 #[doc = "Normal (non-XIP) mode"]
1544 pub const _0: Self = Self::new(0);
1545
1546 #[doc = "XIP mode"]
1547 pub const _1: Self = Self::new(1);
1548 }
1549 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1550 pub struct Sfmxen_SPEC;
1551 pub type Sfmxen = crate::EnumBitfieldStruct<u8, Sfmxen_SPEC>;
1552 impl Sfmxen {
1553 #[doc = "Prohibit XIP mode"]
1554 pub const _0: Self = Self::new(0);
1555
1556 #[doc = "Permit XIP mode"]
1557 pub const _1: Self = Self::new(1);
1558 }
1559}
1560#[doc(hidden)]
1561#[derive(Copy, Clone, Eq, PartialEq)]
1562pub struct Sfmspc_SPEC;
1563impl crate::sealed::RegSpec for Sfmspc_SPEC {
1564 type DataType = u32;
1565}
1566
1567#[doc = "SPI Protocol Control Register"]
1568pub type Sfmspc = crate::RegValueT<Sfmspc_SPEC>;
1569
1570impl Sfmspc {
1571 #[doc = "SPI protocol select"]
1572 #[inline(always)]
1573 pub fn sfmspi(
1574 self,
1575 ) -> crate::common::RegisterField<
1576 0,
1577 0x3,
1578 1,
1579 0,
1580 sfmspc::Sfmspi,
1581 sfmspc::Sfmspi,
1582 Sfmspc_SPEC,
1583 crate::common::RW,
1584 > {
1585 crate::common::RegisterField::<
1586 0,
1587 0x3,
1588 1,
1589 0,
1590 sfmspc::Sfmspi,
1591 sfmspc::Sfmspi,
1592 Sfmspc_SPEC,
1593 crate::common::RW,
1594 >::from_register(self, 0)
1595 }
1596
1597 #[doc = "QSPCLK extended selection bit when switching I/O of QIOn pin"]
1598 #[inline(always)]
1599 pub fn sfmsde(
1600 self,
1601 ) -> crate::common::RegisterField<
1602 4,
1603 0x1,
1604 1,
1605 0,
1606 sfmspc::Sfmsde,
1607 sfmspc::Sfmsde,
1608 Sfmspc_SPEC,
1609 crate::common::RW,
1610 > {
1611 crate::common::RegisterField::<
1612 4,
1613 0x1,
1614 1,
1615 0,
1616 sfmspc::Sfmsde,
1617 sfmspc::Sfmsde,
1618 Sfmspc_SPEC,
1619 crate::common::RW,
1620 >::from_register(self, 0)
1621 }
1622}
1623impl ::core::default::Default for Sfmspc {
1624 #[inline(always)]
1625 fn default() -> Sfmspc {
1626 <crate::RegValueT<Sfmspc_SPEC> as RegisterValue<_>>::new(16)
1627 }
1628}
1629pub mod sfmspc {
1630
1631 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1632 pub struct Sfmspi_SPEC;
1633 pub type Sfmspi = crate::EnumBitfieldStruct<u8, Sfmspi_SPEC>;
1634 impl Sfmspi {
1635 #[doc = "Single SPI Protocol, Extended SPI protocol"]
1636 pub const _00: Self = Self::new(0);
1637
1638 #[doc = "Dual SPI protocol"]
1639 pub const _01: Self = Self::new(1);
1640
1641 #[doc = "Quad SPI protocol"]
1642 pub const _10: Self = Self::new(2);
1643
1644 #[doc = "Setting prohibited"]
1645 pub const _11: Self = Self::new(3);
1646 }
1647 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1648 pub struct Sfmsde_SPEC;
1649 pub type Sfmsde = crate::EnumBitfieldStruct<u8, Sfmsde_SPEC>;
1650 impl Sfmsde {
1651 #[doc = "No QSPCLK extension"]
1652 pub const _0: Self = Self::new(0);
1653
1654 #[doc = "QSPCLK expansion when switching I/O direction of QIOn pin"]
1655 pub const _1: Self = Self::new(1);
1656 }
1657}
1658#[doc(hidden)]
1659#[derive(Copy, Clone, Eq, PartialEq)]
1660pub struct Sfmpmd_SPEC;
1661impl crate::sealed::RegSpec for Sfmpmd_SPEC {
1662 type DataType = u32;
1663}
1664
1665#[doc = "Port Control Register"]
1666pub type Sfmpmd = crate::RegValueT<Sfmpmd_SPEC>;
1667
1668impl Sfmpmd {
1669 #[doc = "WP pin level specification"]
1670 #[inline(always)]
1671 pub fn sfmwpl(
1672 self,
1673 ) -> crate::common::RegisterField<
1674 2,
1675 0x1,
1676 1,
1677 0,
1678 sfmpmd::Sfmwpl,
1679 sfmpmd::Sfmwpl,
1680 Sfmpmd_SPEC,
1681 crate::common::RW,
1682 > {
1683 crate::common::RegisterField::<
1684 2,
1685 0x1,
1686 1,
1687 0,
1688 sfmpmd::Sfmwpl,
1689 sfmpmd::Sfmwpl,
1690 Sfmpmd_SPEC,
1691 crate::common::RW,
1692 >::from_register(self, 0)
1693 }
1694}
1695impl ::core::default::Default for Sfmpmd {
1696 #[inline(always)]
1697 fn default() -> Sfmpmd {
1698 <crate::RegValueT<Sfmpmd_SPEC> as RegisterValue<_>>::new(0)
1699 }
1700}
1701pub mod sfmpmd {
1702
1703 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1704 pub struct Sfmwpl_SPEC;
1705 pub type Sfmwpl = crate::EnumBitfieldStruct<u8, Sfmwpl_SPEC>;
1706 impl Sfmwpl {
1707 #[doc = "Low level"]
1708 pub const _0: Self = Self::new(0);
1709
1710 #[doc = "High level"]
1711 pub const _1: Self = Self::new(1);
1712 }
1713}
1714#[doc(hidden)]
1715#[derive(Copy, Clone, Eq, PartialEq)]
1716pub struct Sfmcnt1_SPEC;
1717impl crate::sealed::RegSpec for Sfmcnt1_SPEC {
1718 type DataType = u32;
1719}
1720
1721#[doc = "External QSPI Address Register"]
1722pub type Sfmcnt1 = crate::RegValueT<Sfmcnt1_SPEC>;
1723
1724impl Sfmcnt1 {
1725 #[doc = "Bank switching address"]
1726 #[inline(always)]
1727 pub fn qspi_ext(
1728 self,
1729 ) -> crate::common::RegisterField<26, 0x3f, 1, 0, u8, u8, Sfmcnt1_SPEC, crate::common::RW> {
1730 crate::common::RegisterField::<26,0x3f,1,0,u8,u8,Sfmcnt1_SPEC,crate::common::RW>::from_register(self,0)
1731 }
1732}
1733impl ::core::default::Default for Sfmcnt1 {
1734 #[inline(always)]
1735 fn default() -> Sfmcnt1 {
1736 <crate::RegValueT<Sfmcnt1_SPEC> as RegisterValue<_>>::new(0)
1737 }
1738}