1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"ICU for CPU"]
28unsafe impl ::core::marker::Send for super::Icu {}
29unsafe impl ::core::marker::Sync for super::Icu {}
30impl super::Icu {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "IRQ Control Register %s"]
38 #[inline(always)]
39 pub const fn irqcr(
40 &self,
41 ) -> &'static crate::common::ClusterRegisterArray<
42 crate::common::Reg<self::Irqcr_SPEC, crate::common::RW>,
43 8,
44 0x1,
45 > {
46 unsafe {
47 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
48 }
49 }
50 #[inline(always)]
51 pub const fn irqcr0(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
52 unsafe {
53 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
54 self._svd2pac_as_ptr().add(0x0usize),
55 )
56 }
57 }
58 #[inline(always)]
59 pub const fn irqcr1(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(0x1usize),
63 )
64 }
65 }
66 #[inline(always)]
67 pub const fn irqcr2(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
68 unsafe {
69 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
70 self._svd2pac_as_ptr().add(0x2usize),
71 )
72 }
73 }
74 #[inline(always)]
75 pub const fn irqcr3(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
76 unsafe {
77 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
78 self._svd2pac_as_ptr().add(0x3usize),
79 )
80 }
81 }
82 #[inline(always)]
83 pub const fn irqcr4(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
84 unsafe {
85 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
86 self._svd2pac_as_ptr().add(0x4usize),
87 )
88 }
89 }
90 #[inline(always)]
91 pub const fn irqcr5(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
92 unsafe {
93 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
94 self._svd2pac_as_ptr().add(0x5usize),
95 )
96 }
97 }
98 #[inline(always)]
99 pub const fn irqcr6(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(0x6usize),
103 )
104 }
105 }
106 #[inline(always)]
107 pub const fn irqcr7(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
108 unsafe {
109 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
110 self._svd2pac_as_ptr().add(0x7usize),
111 )
112 }
113 }
114
115 #[doc = "NMI Pin Interrupt Control Register"]
116 #[inline(always)]
117 pub const fn nmicr(&self) -> &'static crate::common::Reg<self::Nmicr_SPEC, crate::common::RW> {
118 unsafe {
119 crate::common::Reg::<self::Nmicr_SPEC, crate::common::RW>::from_ptr(
120 self._svd2pac_as_ptr().add(256usize),
121 )
122 }
123 }
124
125 #[doc = "Non-Maskable Interrupt Enable Register"]
126 #[inline(always)]
127 pub const fn nmier(&self) -> &'static crate::common::Reg<self::Nmier_SPEC, crate::common::RW> {
128 unsafe {
129 crate::common::Reg::<self::Nmier_SPEC, crate::common::RW>::from_ptr(
130 self._svd2pac_as_ptr().add(288usize),
131 )
132 }
133 }
134
135 #[doc = "Non-Maskable Interrupt Status Clear Register"]
136 #[inline(always)]
137 pub const fn nmiclr(
138 &self,
139 ) -> &'static crate::common::Reg<self::Nmiclr_SPEC, crate::common::RW> {
140 unsafe {
141 crate::common::Reg::<self::Nmiclr_SPEC, crate::common::RW>::from_ptr(
142 self._svd2pac_as_ptr().add(304usize),
143 )
144 }
145 }
146
147 #[doc = "Non-Maskable Interrupt Status Register"]
148 #[inline(always)]
149 pub const fn nmisr(&self) -> &'static crate::common::Reg<self::Nmisr_SPEC, crate::common::R> {
150 unsafe {
151 crate::common::Reg::<self::Nmisr_SPEC, crate::common::R>::from_ptr(
152 self._svd2pac_as_ptr().add(320usize),
153 )
154 }
155 }
156
157 #[doc = "Wake Up Interrupt Enable Register"]
158 #[inline(always)]
159 pub const fn wupen(&self) -> &'static crate::common::Reg<self::Wupen_SPEC, crate::common::RW> {
160 unsafe {
161 crate::common::Reg::<self::Wupen_SPEC, crate::common::RW>::from_ptr(
162 self._svd2pac_as_ptr().add(416usize),
163 )
164 }
165 }
166
167 #[doc = "ICU event Enable Register"]
168 #[inline(always)]
169 pub const fn ielen(&self) -> &'static crate::common::Reg<self::Ielen_SPEC, crate::common::RW> {
170 unsafe {
171 crate::common::Reg::<self::Ielen_SPEC, crate::common::RW>::from_ptr(
172 self._svd2pac_as_ptr().add(448usize),
173 )
174 }
175 }
176
177 #[doc = "SYS Event Link Setting Register"]
178 #[inline(always)]
179 pub const fn selsr0(
180 &self,
181 ) -> &'static crate::common::Reg<self::Selsr0_SPEC, crate::common::RW> {
182 unsafe {
183 crate::common::Reg::<self::Selsr0_SPEC, crate::common::RW>::from_ptr(
184 self._svd2pac_as_ptr().add(512usize),
185 )
186 }
187 }
188
189 #[doc = "ICU Event Link Setting Register %s"]
190 #[inline(always)]
191 pub const fn ielsr(
192 &self,
193 ) -> &'static crate::common::ClusterRegisterArray<
194 crate::common::Reg<self::Ielsr_SPEC, crate::common::RW>,
195 32,
196 0x4,
197 > {
198 unsafe {
199 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x300usize))
200 }
201 }
202 #[inline(always)]
203 pub const fn ielsr0(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
204 unsafe {
205 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
206 self._svd2pac_as_ptr().add(0x300usize),
207 )
208 }
209 }
210 #[inline(always)]
211 pub const fn ielsr1(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
212 unsafe {
213 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
214 self._svd2pac_as_ptr().add(0x304usize),
215 )
216 }
217 }
218 #[inline(always)]
219 pub const fn ielsr2(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
220 unsafe {
221 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
222 self._svd2pac_as_ptr().add(0x308usize),
223 )
224 }
225 }
226 #[inline(always)]
227 pub const fn ielsr3(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
228 unsafe {
229 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
230 self._svd2pac_as_ptr().add(0x30cusize),
231 )
232 }
233 }
234 #[inline(always)]
235 pub const fn ielsr4(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
236 unsafe {
237 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
238 self._svd2pac_as_ptr().add(0x310usize),
239 )
240 }
241 }
242 #[inline(always)]
243 pub const fn ielsr5(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
244 unsafe {
245 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
246 self._svd2pac_as_ptr().add(0x314usize),
247 )
248 }
249 }
250 #[inline(always)]
251 pub const fn ielsr6(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
252 unsafe {
253 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
254 self._svd2pac_as_ptr().add(0x318usize),
255 )
256 }
257 }
258 #[inline(always)]
259 pub const fn ielsr7(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
260 unsafe {
261 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
262 self._svd2pac_as_ptr().add(0x31cusize),
263 )
264 }
265 }
266 #[inline(always)]
267 pub const fn ielsr8(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
268 unsafe {
269 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
270 self._svd2pac_as_ptr().add(0x320usize),
271 )
272 }
273 }
274 #[inline(always)]
275 pub const fn ielsr9(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
276 unsafe {
277 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
278 self._svd2pac_as_ptr().add(0x324usize),
279 )
280 }
281 }
282 #[inline(always)]
283 pub const fn ielsr10(
284 &self,
285 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
286 unsafe {
287 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
288 self._svd2pac_as_ptr().add(0x328usize),
289 )
290 }
291 }
292 #[inline(always)]
293 pub const fn ielsr11(
294 &self,
295 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
296 unsafe {
297 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
298 self._svd2pac_as_ptr().add(0x32cusize),
299 )
300 }
301 }
302 #[inline(always)]
303 pub const fn ielsr12(
304 &self,
305 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
306 unsafe {
307 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
308 self._svd2pac_as_ptr().add(0x330usize),
309 )
310 }
311 }
312 #[inline(always)]
313 pub const fn ielsr13(
314 &self,
315 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
316 unsafe {
317 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
318 self._svd2pac_as_ptr().add(0x334usize),
319 )
320 }
321 }
322 #[inline(always)]
323 pub const fn ielsr14(
324 &self,
325 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
326 unsafe {
327 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
328 self._svd2pac_as_ptr().add(0x338usize),
329 )
330 }
331 }
332 #[inline(always)]
333 pub const fn ielsr15(
334 &self,
335 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
336 unsafe {
337 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
338 self._svd2pac_as_ptr().add(0x33cusize),
339 )
340 }
341 }
342 #[inline(always)]
343 pub const fn ielsr16(
344 &self,
345 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
346 unsafe {
347 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
348 self._svd2pac_as_ptr().add(0x340usize),
349 )
350 }
351 }
352 #[inline(always)]
353 pub const fn ielsr17(
354 &self,
355 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
356 unsafe {
357 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
358 self._svd2pac_as_ptr().add(0x344usize),
359 )
360 }
361 }
362 #[inline(always)]
363 pub const fn ielsr18(
364 &self,
365 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
366 unsafe {
367 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
368 self._svd2pac_as_ptr().add(0x348usize),
369 )
370 }
371 }
372 #[inline(always)]
373 pub const fn ielsr19(
374 &self,
375 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
376 unsafe {
377 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
378 self._svd2pac_as_ptr().add(0x34cusize),
379 )
380 }
381 }
382 #[inline(always)]
383 pub const fn ielsr20(
384 &self,
385 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
386 unsafe {
387 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
388 self._svd2pac_as_ptr().add(0x350usize),
389 )
390 }
391 }
392 #[inline(always)]
393 pub const fn ielsr21(
394 &self,
395 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
396 unsafe {
397 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
398 self._svd2pac_as_ptr().add(0x354usize),
399 )
400 }
401 }
402 #[inline(always)]
403 pub const fn ielsr22(
404 &self,
405 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
406 unsafe {
407 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
408 self._svd2pac_as_ptr().add(0x358usize),
409 )
410 }
411 }
412 #[inline(always)]
413 pub const fn ielsr23(
414 &self,
415 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
416 unsafe {
417 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
418 self._svd2pac_as_ptr().add(0x35cusize),
419 )
420 }
421 }
422 #[inline(always)]
423 pub const fn ielsr24(
424 &self,
425 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
426 unsafe {
427 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
428 self._svd2pac_as_ptr().add(0x360usize),
429 )
430 }
431 }
432 #[inline(always)]
433 pub const fn ielsr25(
434 &self,
435 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
436 unsafe {
437 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
438 self._svd2pac_as_ptr().add(0x364usize),
439 )
440 }
441 }
442 #[inline(always)]
443 pub const fn ielsr26(
444 &self,
445 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
446 unsafe {
447 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
448 self._svd2pac_as_ptr().add(0x368usize),
449 )
450 }
451 }
452 #[inline(always)]
453 pub const fn ielsr27(
454 &self,
455 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
456 unsafe {
457 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
458 self._svd2pac_as_ptr().add(0x36cusize),
459 )
460 }
461 }
462 #[inline(always)]
463 pub const fn ielsr28(
464 &self,
465 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
466 unsafe {
467 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
468 self._svd2pac_as_ptr().add(0x370usize),
469 )
470 }
471 }
472 #[inline(always)]
473 pub const fn ielsr29(
474 &self,
475 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
476 unsafe {
477 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
478 self._svd2pac_as_ptr().add(0x374usize),
479 )
480 }
481 }
482 #[inline(always)]
483 pub const fn ielsr30(
484 &self,
485 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
486 unsafe {
487 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
488 self._svd2pac_as_ptr().add(0x378usize),
489 )
490 }
491 }
492 #[inline(always)]
493 pub const fn ielsr31(
494 &self,
495 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
496 unsafe {
497 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
498 self._svd2pac_as_ptr().add(0x37cusize),
499 )
500 }
501 }
502}
503#[doc(hidden)]
504#[derive(Copy, Clone, Eq, PartialEq)]
505pub struct Irqcr_SPEC;
506impl crate::sealed::RegSpec for Irqcr_SPEC {
507 type DataType = u8;
508}
509
510#[doc = "IRQ Control Register %s"]
511pub type Irqcr = crate::RegValueT<Irqcr_SPEC>;
512
513impl Irqcr {
514 #[doc = "IRQi Detection Sense Select"]
515 #[inline(always)]
516 pub fn irqmd(
517 self,
518 ) -> crate::common::RegisterField<
519 0,
520 0x3,
521 1,
522 0,
523 irqcr::Irqmd,
524 irqcr::Irqmd,
525 Irqcr_SPEC,
526 crate::common::RW,
527 > {
528 crate::common::RegisterField::<
529 0,
530 0x3,
531 1,
532 0,
533 irqcr::Irqmd,
534 irqcr::Irqmd,
535 Irqcr_SPEC,
536 crate::common::RW,
537 >::from_register(self, 0)
538 }
539
540 #[doc = "IRQi Digital Filter Sampling Clock Select"]
541 #[inline(always)]
542 pub fn fclksel(
543 self,
544 ) -> crate::common::RegisterField<
545 4,
546 0x3,
547 1,
548 0,
549 irqcr::Fclksel,
550 irqcr::Fclksel,
551 Irqcr_SPEC,
552 crate::common::RW,
553 > {
554 crate::common::RegisterField::<
555 4,
556 0x3,
557 1,
558 0,
559 irqcr::Fclksel,
560 irqcr::Fclksel,
561 Irqcr_SPEC,
562 crate::common::RW,
563 >::from_register(self, 0)
564 }
565
566 #[doc = "IRQi Digital Filter Enable"]
567 #[inline(always)]
568 pub fn flten(
569 self,
570 ) -> crate::common::RegisterField<
571 7,
572 0x1,
573 1,
574 0,
575 irqcr::Flten,
576 irqcr::Flten,
577 Irqcr_SPEC,
578 crate::common::RW,
579 > {
580 crate::common::RegisterField::<
581 7,
582 0x1,
583 1,
584 0,
585 irqcr::Flten,
586 irqcr::Flten,
587 Irqcr_SPEC,
588 crate::common::RW,
589 >::from_register(self, 0)
590 }
591}
592impl ::core::default::Default for Irqcr {
593 #[inline(always)]
594 fn default() -> Irqcr {
595 <crate::RegValueT<Irqcr_SPEC> as RegisterValue<_>>::new(0)
596 }
597}
598pub mod irqcr {
599
600 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
601 pub struct Irqmd_SPEC;
602 pub type Irqmd = crate::EnumBitfieldStruct<u8, Irqmd_SPEC>;
603 impl Irqmd {
604 #[doc = "Falling edge"]
605 pub const _00: Self = Self::new(0);
606
607 #[doc = "Rising edge"]
608 pub const _01: Self = Self::new(1);
609
610 #[doc = "Rising and falling edges"]
611 pub const _10: Self = Self::new(2);
612
613 #[doc = "Low level"]
614 pub const _11: Self = Self::new(3);
615 }
616 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
617 pub struct Fclksel_SPEC;
618 pub type Fclksel = crate::EnumBitfieldStruct<u8, Fclksel_SPEC>;
619 impl Fclksel {
620 #[doc = "PCLKB"]
621 pub const _00: Self = Self::new(0);
622
623 #[doc = "PCLKB/8"]
624 pub const _01: Self = Self::new(1);
625
626 #[doc = "PCLKB/32"]
627 pub const _10: Self = Self::new(2);
628
629 #[doc = "PCLKB/64"]
630 pub const _11: Self = Self::new(3);
631 }
632 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
633 pub struct Flten_SPEC;
634 pub type Flten = crate::EnumBitfieldStruct<u8, Flten_SPEC>;
635 impl Flten {
636 #[doc = "Digital filter is disabled"]
637 pub const _0: Self = Self::new(0);
638
639 #[doc = "Digital filter is enabled."]
640 pub const _1: Self = Self::new(1);
641 }
642}
643#[doc(hidden)]
644#[derive(Copy, Clone, Eq, PartialEq)]
645pub struct Nmicr_SPEC;
646impl crate::sealed::RegSpec for Nmicr_SPEC {
647 type DataType = u8;
648}
649
650#[doc = "NMI Pin Interrupt Control Register"]
651pub type Nmicr = crate::RegValueT<Nmicr_SPEC>;
652
653impl Nmicr {
654 #[doc = "NMI Detection Set"]
655 #[inline(always)]
656 pub fn nmimd(
657 self,
658 ) -> crate::common::RegisterField<
659 0,
660 0x1,
661 1,
662 0,
663 nmicr::Nmimd,
664 nmicr::Nmimd,
665 Nmicr_SPEC,
666 crate::common::RW,
667 > {
668 crate::common::RegisterField::<
669 0,
670 0x1,
671 1,
672 0,
673 nmicr::Nmimd,
674 nmicr::Nmimd,
675 Nmicr_SPEC,
676 crate::common::RW,
677 >::from_register(self, 0)
678 }
679
680 #[doc = "NMI Digital Filter Sampling Clock Select"]
681 #[inline(always)]
682 pub fn nfclksel(
683 self,
684 ) -> crate::common::RegisterField<
685 4,
686 0x3,
687 1,
688 0,
689 nmicr::Nfclksel,
690 nmicr::Nfclksel,
691 Nmicr_SPEC,
692 crate::common::RW,
693 > {
694 crate::common::RegisterField::<
695 4,
696 0x3,
697 1,
698 0,
699 nmicr::Nfclksel,
700 nmicr::Nfclksel,
701 Nmicr_SPEC,
702 crate::common::RW,
703 >::from_register(self, 0)
704 }
705
706 #[doc = "NMI Digital Filter Enable"]
707 #[inline(always)]
708 pub fn nflten(
709 self,
710 ) -> crate::common::RegisterField<
711 7,
712 0x1,
713 1,
714 0,
715 nmicr::Nflten,
716 nmicr::Nflten,
717 Nmicr_SPEC,
718 crate::common::RW,
719 > {
720 crate::common::RegisterField::<
721 7,
722 0x1,
723 1,
724 0,
725 nmicr::Nflten,
726 nmicr::Nflten,
727 Nmicr_SPEC,
728 crate::common::RW,
729 >::from_register(self, 0)
730 }
731}
732impl ::core::default::Default for Nmicr {
733 #[inline(always)]
734 fn default() -> Nmicr {
735 <crate::RegValueT<Nmicr_SPEC> as RegisterValue<_>>::new(0)
736 }
737}
738pub mod nmicr {
739
740 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
741 pub struct Nmimd_SPEC;
742 pub type Nmimd = crate::EnumBitfieldStruct<u8, Nmimd_SPEC>;
743 impl Nmimd {
744 #[doc = "Falling edge"]
745 pub const _0: Self = Self::new(0);
746
747 #[doc = "Rising edge"]
748 pub const _1: Self = Self::new(1);
749 }
750 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
751 pub struct Nfclksel_SPEC;
752 pub type Nfclksel = crate::EnumBitfieldStruct<u8, Nfclksel_SPEC>;
753 impl Nfclksel {
754 #[doc = "PCLKB"]
755 pub const _00: Self = Self::new(0);
756
757 #[doc = "PCLKB/8"]
758 pub const _01: Self = Self::new(1);
759
760 #[doc = "PCLKB/32"]
761 pub const _10: Self = Self::new(2);
762
763 #[doc = "PCLKB/64"]
764 pub const _11: Self = Self::new(3);
765 }
766 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
767 pub struct Nflten_SPEC;
768 pub type Nflten = crate::EnumBitfieldStruct<u8, Nflten_SPEC>;
769 impl Nflten {
770 #[doc = "Disabled."]
771 pub const _0: Self = Self::new(0);
772
773 #[doc = "Enabled."]
774 pub const _1: Self = Self::new(1);
775 }
776}
777#[doc(hidden)]
778#[derive(Copy, Clone, Eq, PartialEq)]
779pub struct Nmier_SPEC;
780impl crate::sealed::RegSpec for Nmier_SPEC {
781 type DataType = u16;
782}
783
784#[doc = "Non-Maskable Interrupt Enable Register"]
785pub type Nmier = crate::RegValueT<Nmier_SPEC>;
786
787impl Nmier {
788 #[doc = "IWDT Underflow/Refresh Error Interrupt Enable"]
789 #[inline(always)]
790 pub fn iwdten(
791 self,
792 ) -> crate::common::RegisterField<
793 0,
794 0x1,
795 1,
796 0,
797 nmier::Iwdten,
798 nmier::Iwdten,
799 Nmier_SPEC,
800 crate::common::RW,
801 > {
802 crate::common::RegisterField::<
803 0,
804 0x1,
805 1,
806 0,
807 nmier::Iwdten,
808 nmier::Iwdten,
809 Nmier_SPEC,
810 crate::common::RW,
811 >::from_register(self, 0)
812 }
813
814 #[doc = "WDT Underflow/Refresh Error Interrupt Enable"]
815 #[inline(always)]
816 pub fn wdten(
817 self,
818 ) -> crate::common::RegisterField<
819 1,
820 0x1,
821 1,
822 0,
823 nmier::Wdten,
824 nmier::Wdten,
825 Nmier_SPEC,
826 crate::common::RW,
827 > {
828 crate::common::RegisterField::<
829 1,
830 0x1,
831 1,
832 0,
833 nmier::Wdten,
834 nmier::Wdten,
835 Nmier_SPEC,
836 crate::common::RW,
837 >::from_register(self, 0)
838 }
839
840 #[doc = "Voltage monitor 1 Interrupt Enable"]
841 #[inline(always)]
842 pub fn lvd1en(
843 self,
844 ) -> crate::common::RegisterField<
845 2,
846 0x1,
847 1,
848 0,
849 nmier::Lvd1En,
850 nmier::Lvd1En,
851 Nmier_SPEC,
852 crate::common::RW,
853 > {
854 crate::common::RegisterField::<
855 2,
856 0x1,
857 1,
858 0,
859 nmier::Lvd1En,
860 nmier::Lvd1En,
861 Nmier_SPEC,
862 crate::common::RW,
863 >::from_register(self, 0)
864 }
865
866 #[doc = "Voltage monitor 2 Interrupt Enable"]
867 #[inline(always)]
868 pub fn lvd2en(
869 self,
870 ) -> crate::common::RegisterField<
871 3,
872 0x1,
873 1,
874 0,
875 nmier::Lvd2En,
876 nmier::Lvd2En,
877 Nmier_SPEC,
878 crate::common::RW,
879 > {
880 crate::common::RegisterField::<
881 3,
882 0x1,
883 1,
884 0,
885 nmier::Lvd2En,
886 nmier::Lvd2En,
887 Nmier_SPEC,
888 crate::common::RW,
889 >::from_register(self, 0)
890 }
891
892 #[doc = "Main Clock Oscillation Stop Detection Interrupt Enable"]
893 #[inline(always)]
894 pub fn osten(
895 self,
896 ) -> crate::common::RegisterField<
897 6,
898 0x1,
899 1,
900 0,
901 nmier::Osten,
902 nmier::Osten,
903 Nmier_SPEC,
904 crate::common::RW,
905 > {
906 crate::common::RegisterField::<
907 6,
908 0x1,
909 1,
910 0,
911 nmier::Osten,
912 nmier::Osten,
913 Nmier_SPEC,
914 crate::common::RW,
915 >::from_register(self, 0)
916 }
917
918 #[doc = "NMI Pin Interrupt Enable"]
919 #[inline(always)]
920 pub fn nmien(
921 self,
922 ) -> crate::common::RegisterField<
923 7,
924 0x1,
925 1,
926 0,
927 nmier::Nmien,
928 nmier::Nmien,
929 Nmier_SPEC,
930 crate::common::RW,
931 > {
932 crate::common::RegisterField::<
933 7,
934 0x1,
935 1,
936 0,
937 nmier::Nmien,
938 nmier::Nmien,
939 Nmier_SPEC,
940 crate::common::RW,
941 >::from_register(self, 0)
942 }
943
944 #[doc = "SRAM Parity Error Interrupt Enable"]
945 #[inline(always)]
946 pub fn rpeen(
947 self,
948 ) -> crate::common::RegisterField<
949 8,
950 0x1,
951 1,
952 0,
953 nmier::Rpeen,
954 nmier::Rpeen,
955 Nmier_SPEC,
956 crate::common::RW,
957 > {
958 crate::common::RegisterField::<
959 8,
960 0x1,
961 1,
962 0,
963 nmier::Rpeen,
964 nmier::Rpeen,
965 Nmier_SPEC,
966 crate::common::RW,
967 >::from_register(self, 0)
968 }
969
970 #[doc = "SRAM ECC Error Interrupt Enable"]
971 #[inline(always)]
972 pub fn reccen(
973 self,
974 ) -> crate::common::RegisterField<
975 9,
976 0x1,
977 1,
978 0,
979 nmier::Reccen,
980 nmier::Reccen,
981 Nmier_SPEC,
982 crate::common::RW,
983 > {
984 crate::common::RegisterField::<
985 9,
986 0x1,
987 1,
988 0,
989 nmier::Reccen,
990 nmier::Reccen,
991 Nmier_SPEC,
992 crate::common::RW,
993 >::from_register(self, 0)
994 }
995
996 #[doc = "Bus Slave MPU Error Interrupt Enable"]
997 #[inline(always)]
998 pub fn bussen(
999 self,
1000 ) -> crate::common::RegisterField<
1001 10,
1002 0x1,
1003 1,
1004 0,
1005 nmier::Bussen,
1006 nmier::Bussen,
1007 Nmier_SPEC,
1008 crate::common::RW,
1009 > {
1010 crate::common::RegisterField::<
1011 10,
1012 0x1,
1013 1,
1014 0,
1015 nmier::Bussen,
1016 nmier::Bussen,
1017 Nmier_SPEC,
1018 crate::common::RW,
1019 >::from_register(self, 0)
1020 }
1021
1022 #[doc = "Bus Master MPU Error Interrupt Enable"]
1023 #[inline(always)]
1024 pub fn busmen(
1025 self,
1026 ) -> crate::common::RegisterField<
1027 11,
1028 0x1,
1029 1,
1030 0,
1031 nmier::Busmen,
1032 nmier::Busmen,
1033 Nmier_SPEC,
1034 crate::common::RW,
1035 > {
1036 crate::common::RegisterField::<
1037 11,
1038 0x1,
1039 1,
1040 0,
1041 nmier::Busmen,
1042 nmier::Busmen,
1043 Nmier_SPEC,
1044 crate::common::RW,
1045 >::from_register(self, 0)
1046 }
1047
1048 #[doc = "CPU Stack Pointer Monitor Interrupt Enable"]
1049 #[inline(always)]
1050 pub fn speen(
1051 self,
1052 ) -> crate::common::RegisterField<
1053 12,
1054 0x1,
1055 1,
1056 0,
1057 nmier::Speen,
1058 nmier::Speen,
1059 Nmier_SPEC,
1060 crate::common::RW,
1061 > {
1062 crate::common::RegisterField::<
1063 12,
1064 0x1,
1065 1,
1066 0,
1067 nmier::Speen,
1068 nmier::Speen,
1069 Nmier_SPEC,
1070 crate::common::RW,
1071 >::from_register(self, 0)
1072 }
1073}
1074impl ::core::default::Default for Nmier {
1075 #[inline(always)]
1076 fn default() -> Nmier {
1077 <crate::RegValueT<Nmier_SPEC> as RegisterValue<_>>::new(0)
1078 }
1079}
1080pub mod nmier {
1081
1082 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1083 pub struct Iwdten_SPEC;
1084 pub type Iwdten = crate::EnumBitfieldStruct<u8, Iwdten_SPEC>;
1085 impl Iwdten {
1086 #[doc = "Disabled"]
1087 pub const _0: Self = Self::new(0);
1088
1089 #[doc = "Enabled."]
1090 pub const _1: Self = Self::new(1);
1091 }
1092 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1093 pub struct Wdten_SPEC;
1094 pub type Wdten = crate::EnumBitfieldStruct<u8, Wdten_SPEC>;
1095 impl Wdten {
1096 #[doc = "Disabled"]
1097 pub const _0: Self = Self::new(0);
1098
1099 #[doc = "Enabled"]
1100 pub const _1: Self = Self::new(1);
1101 }
1102 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1103 pub struct Lvd1En_SPEC;
1104 pub type Lvd1En = crate::EnumBitfieldStruct<u8, Lvd1En_SPEC>;
1105 impl Lvd1En {
1106 #[doc = "Disabled"]
1107 pub const _0: Self = Self::new(0);
1108
1109 #[doc = "Enabled"]
1110 pub const _1: Self = Self::new(1);
1111 }
1112 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1113 pub struct Lvd2En_SPEC;
1114 pub type Lvd2En = crate::EnumBitfieldStruct<u8, Lvd2En_SPEC>;
1115 impl Lvd2En {
1116 #[doc = "Disabled"]
1117 pub const _0: Self = Self::new(0);
1118
1119 #[doc = "Enabled"]
1120 pub const _1: Self = Self::new(1);
1121 }
1122 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1123 pub struct Osten_SPEC;
1124 pub type Osten = crate::EnumBitfieldStruct<u8, Osten_SPEC>;
1125 impl Osten {
1126 #[doc = "Disabled"]
1127 pub const _0: Self = Self::new(0);
1128
1129 #[doc = "Enabled"]
1130 pub const _1: Self = Self::new(1);
1131 }
1132 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1133 pub struct Nmien_SPEC;
1134 pub type Nmien = crate::EnumBitfieldStruct<u8, Nmien_SPEC>;
1135 impl Nmien {
1136 #[doc = "Disabled"]
1137 pub const _0: Self = Self::new(0);
1138
1139 #[doc = "Enabled"]
1140 pub const _1: Self = Self::new(1);
1141 }
1142 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1143 pub struct Rpeen_SPEC;
1144 pub type Rpeen = crate::EnumBitfieldStruct<u8, Rpeen_SPEC>;
1145 impl Rpeen {
1146 #[doc = "Disabled"]
1147 pub const _0: Self = Self::new(0);
1148
1149 #[doc = "Enabled"]
1150 pub const _1: Self = Self::new(1);
1151 }
1152 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1153 pub struct Reccen_SPEC;
1154 pub type Reccen = crate::EnumBitfieldStruct<u8, Reccen_SPEC>;
1155 impl Reccen {
1156 #[doc = "Disabled"]
1157 pub const _0: Self = Self::new(0);
1158
1159 #[doc = "Enabled"]
1160 pub const _1: Self = Self::new(1);
1161 }
1162 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1163 pub struct Bussen_SPEC;
1164 pub type Bussen = crate::EnumBitfieldStruct<u8, Bussen_SPEC>;
1165 impl Bussen {
1166 #[doc = "Disabled"]
1167 pub const _0: Self = Self::new(0);
1168
1169 #[doc = "Enabled"]
1170 pub const _1: Self = Self::new(1);
1171 }
1172 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1173 pub struct Busmen_SPEC;
1174 pub type Busmen = crate::EnumBitfieldStruct<u8, Busmen_SPEC>;
1175 impl Busmen {
1176 #[doc = "Disabled"]
1177 pub const _0: Self = Self::new(0);
1178
1179 #[doc = "Enabled"]
1180 pub const _1: Self = Self::new(1);
1181 }
1182 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1183 pub struct Speen_SPEC;
1184 pub type Speen = crate::EnumBitfieldStruct<u8, Speen_SPEC>;
1185 impl Speen {
1186 #[doc = "Disabled"]
1187 pub const _0: Self = Self::new(0);
1188
1189 #[doc = "Enabled"]
1190 pub const _1: Self = Self::new(1);
1191 }
1192}
1193#[doc(hidden)]
1194#[derive(Copy, Clone, Eq, PartialEq)]
1195pub struct Nmiclr_SPEC;
1196impl crate::sealed::RegSpec for Nmiclr_SPEC {
1197 type DataType = u16;
1198}
1199
1200#[doc = "Non-Maskable Interrupt Status Clear Register"]
1201pub type Nmiclr = crate::RegValueT<Nmiclr_SPEC>;
1202
1203impl Nmiclr {
1204 #[doc = "IWDT Underflow/Refresh Error Interrupt Status Flag Clear"]
1205 #[inline(always)]
1206 pub fn iwdtclr(
1207 self,
1208 ) -> crate::common::RegisterField<
1209 0,
1210 0x1,
1211 1,
1212 0,
1213 nmiclr::Iwdtclr,
1214 nmiclr::Iwdtclr,
1215 Nmiclr_SPEC,
1216 crate::common::RW,
1217 > {
1218 crate::common::RegisterField::<
1219 0,
1220 0x1,
1221 1,
1222 0,
1223 nmiclr::Iwdtclr,
1224 nmiclr::Iwdtclr,
1225 Nmiclr_SPEC,
1226 crate::common::RW,
1227 >::from_register(self, 0)
1228 }
1229
1230 #[doc = "WDT Underflow/Refresh Error Interrupt Status Flag Clear"]
1231 #[inline(always)]
1232 pub fn wdtclr(
1233 self,
1234 ) -> crate::common::RegisterField<
1235 1,
1236 0x1,
1237 1,
1238 0,
1239 nmiclr::Wdtclr,
1240 nmiclr::Wdtclr,
1241 Nmiclr_SPEC,
1242 crate::common::RW,
1243 > {
1244 crate::common::RegisterField::<
1245 1,
1246 0x1,
1247 1,
1248 0,
1249 nmiclr::Wdtclr,
1250 nmiclr::Wdtclr,
1251 Nmiclr_SPEC,
1252 crate::common::RW,
1253 >::from_register(self, 0)
1254 }
1255
1256 #[doc = "Voltage Monitor 1 Interrupt Status Flag Clear"]
1257 #[inline(always)]
1258 pub fn lvd1clr(
1259 self,
1260 ) -> crate::common::RegisterField<
1261 2,
1262 0x1,
1263 1,
1264 0,
1265 nmiclr::Lvd1Clr,
1266 nmiclr::Lvd1Clr,
1267 Nmiclr_SPEC,
1268 crate::common::RW,
1269 > {
1270 crate::common::RegisterField::<
1271 2,
1272 0x1,
1273 1,
1274 0,
1275 nmiclr::Lvd1Clr,
1276 nmiclr::Lvd1Clr,
1277 Nmiclr_SPEC,
1278 crate::common::RW,
1279 >::from_register(self, 0)
1280 }
1281
1282 #[doc = "Voltage Monitor 2 Interrupt Status Flag Clear"]
1283 #[inline(always)]
1284 pub fn lvd2clr(
1285 self,
1286 ) -> crate::common::RegisterField<
1287 3,
1288 0x1,
1289 1,
1290 0,
1291 nmiclr::Lvd2Clr,
1292 nmiclr::Lvd2Clr,
1293 Nmiclr_SPEC,
1294 crate::common::RW,
1295 > {
1296 crate::common::RegisterField::<
1297 3,
1298 0x1,
1299 1,
1300 0,
1301 nmiclr::Lvd2Clr,
1302 nmiclr::Lvd2Clr,
1303 Nmiclr_SPEC,
1304 crate::common::RW,
1305 >::from_register(self, 0)
1306 }
1307
1308 #[doc = "Oscillation Stop Detection Interrupt Status Flag Clear"]
1309 #[inline(always)]
1310 pub fn ostclr(
1311 self,
1312 ) -> crate::common::RegisterField<
1313 6,
1314 0x1,
1315 1,
1316 0,
1317 nmiclr::Ostclr,
1318 nmiclr::Ostclr,
1319 Nmiclr_SPEC,
1320 crate::common::RW,
1321 > {
1322 crate::common::RegisterField::<
1323 6,
1324 0x1,
1325 1,
1326 0,
1327 nmiclr::Ostclr,
1328 nmiclr::Ostclr,
1329 Nmiclr_SPEC,
1330 crate::common::RW,
1331 >::from_register(self, 0)
1332 }
1333
1334 #[doc = "NMI Pin Interrupt Status Flag Clear"]
1335 #[inline(always)]
1336 pub fn nmiclr(
1337 self,
1338 ) -> crate::common::RegisterField<
1339 7,
1340 0x1,
1341 1,
1342 0,
1343 nmiclr::Nmiclr,
1344 nmiclr::Nmiclr,
1345 Nmiclr_SPEC,
1346 crate::common::RW,
1347 > {
1348 crate::common::RegisterField::<
1349 7,
1350 0x1,
1351 1,
1352 0,
1353 nmiclr::Nmiclr,
1354 nmiclr::Nmiclr,
1355 Nmiclr_SPEC,
1356 crate::common::RW,
1357 >::from_register(self, 0)
1358 }
1359
1360 #[doc = "SRAM Parity Error Interrupt Status Flag Clear"]
1361 #[inline(always)]
1362 pub fn rpeclr(
1363 self,
1364 ) -> crate::common::RegisterField<
1365 8,
1366 0x1,
1367 1,
1368 0,
1369 nmiclr::Rpeclr,
1370 nmiclr::Rpeclr,
1371 Nmiclr_SPEC,
1372 crate::common::RW,
1373 > {
1374 crate::common::RegisterField::<
1375 8,
1376 0x1,
1377 1,
1378 0,
1379 nmiclr::Rpeclr,
1380 nmiclr::Rpeclr,
1381 Nmiclr_SPEC,
1382 crate::common::RW,
1383 >::from_register(self, 0)
1384 }
1385
1386 #[doc = "SRAM ECC Error Interrupt Status Flag Clear"]
1387 #[inline(always)]
1388 pub fn reccclr(
1389 self,
1390 ) -> crate::common::RegisterField<
1391 9,
1392 0x1,
1393 1,
1394 0,
1395 nmiclr::Reccclr,
1396 nmiclr::Reccclr,
1397 Nmiclr_SPEC,
1398 crate::common::RW,
1399 > {
1400 crate::common::RegisterField::<
1401 9,
1402 0x1,
1403 1,
1404 0,
1405 nmiclr::Reccclr,
1406 nmiclr::Reccclr,
1407 Nmiclr_SPEC,
1408 crate::common::RW,
1409 >::from_register(self, 0)
1410 }
1411
1412 #[doc = "Bus Slave MPU Error Interrupt Status Flag Clear"]
1413 #[inline(always)]
1414 pub fn bussclr(
1415 self,
1416 ) -> crate::common::RegisterField<
1417 10,
1418 0x1,
1419 1,
1420 0,
1421 nmiclr::Bussclr,
1422 nmiclr::Bussclr,
1423 Nmiclr_SPEC,
1424 crate::common::RW,
1425 > {
1426 crate::common::RegisterField::<
1427 10,
1428 0x1,
1429 1,
1430 0,
1431 nmiclr::Bussclr,
1432 nmiclr::Bussclr,
1433 Nmiclr_SPEC,
1434 crate::common::RW,
1435 >::from_register(self, 0)
1436 }
1437
1438 #[doc = "Bus Master MPU Error Interrupt Status Flag Clear"]
1439 #[inline(always)]
1440 pub fn busmclr(
1441 self,
1442 ) -> crate::common::RegisterField<
1443 11,
1444 0x1,
1445 1,
1446 0,
1447 nmiclr::Busmclr,
1448 nmiclr::Busmclr,
1449 Nmiclr_SPEC,
1450 crate::common::RW,
1451 > {
1452 crate::common::RegisterField::<
1453 11,
1454 0x1,
1455 1,
1456 0,
1457 nmiclr::Busmclr,
1458 nmiclr::Busmclr,
1459 Nmiclr_SPEC,
1460 crate::common::RW,
1461 >::from_register(self, 0)
1462 }
1463
1464 #[doc = "CPU Stack Pointer Monitor Interrupt Status Flag Clear"]
1465 #[inline(always)]
1466 pub fn speclr(
1467 self,
1468 ) -> crate::common::RegisterField<
1469 12,
1470 0x1,
1471 1,
1472 0,
1473 nmiclr::Speclr,
1474 nmiclr::Speclr,
1475 Nmiclr_SPEC,
1476 crate::common::RW,
1477 > {
1478 crate::common::RegisterField::<
1479 12,
1480 0x1,
1481 1,
1482 0,
1483 nmiclr::Speclr,
1484 nmiclr::Speclr,
1485 Nmiclr_SPEC,
1486 crate::common::RW,
1487 >::from_register(self, 0)
1488 }
1489}
1490impl ::core::default::Default for Nmiclr {
1491 #[inline(always)]
1492 fn default() -> Nmiclr {
1493 <crate::RegValueT<Nmiclr_SPEC> as RegisterValue<_>>::new(0)
1494 }
1495}
1496pub mod nmiclr {
1497
1498 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1499 pub struct Iwdtclr_SPEC;
1500 pub type Iwdtclr = crate::EnumBitfieldStruct<u8, Iwdtclr_SPEC>;
1501 impl Iwdtclr {
1502 #[doc = "No effect"]
1503 pub const _0: Self = Self::new(0);
1504
1505 #[doc = "Clear the NMISR.IWDTST flag"]
1506 pub const _1: Self = Self::new(1);
1507 }
1508 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1509 pub struct Wdtclr_SPEC;
1510 pub type Wdtclr = crate::EnumBitfieldStruct<u8, Wdtclr_SPEC>;
1511 impl Wdtclr {
1512 #[doc = "No effect"]
1513 pub const _0: Self = Self::new(0);
1514
1515 #[doc = "Clear the NMISR.WDTST flag"]
1516 pub const _1: Self = Self::new(1);
1517 }
1518 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1519 pub struct Lvd1Clr_SPEC;
1520 pub type Lvd1Clr = crate::EnumBitfieldStruct<u8, Lvd1Clr_SPEC>;
1521 impl Lvd1Clr {
1522 #[doc = "No effect"]
1523 pub const _0: Self = Self::new(0);
1524
1525 #[doc = "Clear the NMISR.LVD1ST flag"]
1526 pub const _1: Self = Self::new(1);
1527 }
1528 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1529 pub struct Lvd2Clr_SPEC;
1530 pub type Lvd2Clr = crate::EnumBitfieldStruct<u8, Lvd2Clr_SPEC>;
1531 impl Lvd2Clr {
1532 #[doc = "No effect"]
1533 pub const _0: Self = Self::new(0);
1534
1535 #[doc = "Clear the NMISR.LVD2ST flag."]
1536 pub const _1: Self = Self::new(1);
1537 }
1538 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1539 pub struct Ostclr_SPEC;
1540 pub type Ostclr = crate::EnumBitfieldStruct<u8, Ostclr_SPEC>;
1541 impl Ostclr {
1542 #[doc = "No effect"]
1543 pub const _0: Self = Self::new(0);
1544
1545 #[doc = "Clear the NMISR.OSTST flag"]
1546 pub const _1: Self = Self::new(1);
1547 }
1548 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1549 pub struct Nmiclr_SPEC;
1550 pub type Nmiclr = crate::EnumBitfieldStruct<u8, Nmiclr_SPEC>;
1551 impl Nmiclr {
1552 #[doc = "No effect"]
1553 pub const _0: Self = Self::new(0);
1554
1555 #[doc = "Clear the NMISR.NMIST flag"]
1556 pub const _1: Self = Self::new(1);
1557 }
1558 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1559 pub struct Rpeclr_SPEC;
1560 pub type Rpeclr = crate::EnumBitfieldStruct<u8, Rpeclr_SPEC>;
1561 impl Rpeclr {
1562 #[doc = "No effect"]
1563 pub const _0: Self = Self::new(0);
1564
1565 #[doc = "Clear the NMISR.RPEST flag"]
1566 pub const _1: Self = Self::new(1);
1567 }
1568 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1569 pub struct Reccclr_SPEC;
1570 pub type Reccclr = crate::EnumBitfieldStruct<u8, Reccclr_SPEC>;
1571 impl Reccclr {
1572 #[doc = "No effect"]
1573 pub const _0: Self = Self::new(0);
1574
1575 #[doc = "Clear the NMISR.RECCST flag"]
1576 pub const _1: Self = Self::new(1);
1577 }
1578 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1579 pub struct Bussclr_SPEC;
1580 pub type Bussclr = crate::EnumBitfieldStruct<u8, Bussclr_SPEC>;
1581 impl Bussclr {
1582 #[doc = "No effect"]
1583 pub const _0: Self = Self::new(0);
1584
1585 #[doc = "Clear the NMISR.BUSSST flag"]
1586 pub const _1: Self = Self::new(1);
1587 }
1588 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1589 pub struct Busmclr_SPEC;
1590 pub type Busmclr = crate::EnumBitfieldStruct<u8, Busmclr_SPEC>;
1591 impl Busmclr {
1592 #[doc = "No effect"]
1593 pub const _0: Self = Self::new(0);
1594
1595 #[doc = "Clear the NMISR.BUSMST flag"]
1596 pub const _1: Self = Self::new(1);
1597 }
1598 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1599 pub struct Speclr_SPEC;
1600 pub type Speclr = crate::EnumBitfieldStruct<u8, Speclr_SPEC>;
1601 impl Speclr {
1602 #[doc = "No effect"]
1603 pub const _0: Self = Self::new(0);
1604
1605 #[doc = "Clear the NMISR.SPEST flag"]
1606 pub const _1: Self = Self::new(1);
1607 }
1608}
1609#[doc(hidden)]
1610#[derive(Copy, Clone, Eq, PartialEq)]
1611pub struct Nmisr_SPEC;
1612impl crate::sealed::RegSpec for Nmisr_SPEC {
1613 type DataType = u16;
1614}
1615
1616#[doc = "Non-Maskable Interrupt Status Register"]
1617pub type Nmisr = crate::RegValueT<Nmisr_SPEC>;
1618
1619impl Nmisr {
1620 #[doc = "IWDT Underflow/Refresh Error Interrupt Status Flag"]
1621 #[inline(always)]
1622 pub fn iwdtst(
1623 self,
1624 ) -> crate::common::RegisterField<
1625 0,
1626 0x1,
1627 1,
1628 0,
1629 nmisr::Iwdtst,
1630 nmisr::Iwdtst,
1631 Nmisr_SPEC,
1632 crate::common::R,
1633 > {
1634 crate::common::RegisterField::<
1635 0,
1636 0x1,
1637 1,
1638 0,
1639 nmisr::Iwdtst,
1640 nmisr::Iwdtst,
1641 Nmisr_SPEC,
1642 crate::common::R,
1643 >::from_register(self, 0)
1644 }
1645
1646 #[doc = "WDT Underflow/Refresh Error Interrupt Status Flag"]
1647 #[inline(always)]
1648 pub fn wdtst(
1649 self,
1650 ) -> crate::common::RegisterField<
1651 1,
1652 0x1,
1653 1,
1654 0,
1655 nmisr::Wdtst,
1656 nmisr::Wdtst,
1657 Nmisr_SPEC,
1658 crate::common::R,
1659 > {
1660 crate::common::RegisterField::<
1661 1,
1662 0x1,
1663 1,
1664 0,
1665 nmisr::Wdtst,
1666 nmisr::Wdtst,
1667 Nmisr_SPEC,
1668 crate::common::R,
1669 >::from_register(self, 0)
1670 }
1671
1672 #[doc = "Voltage Monitor 1 Interrupt Status Flag"]
1673 #[inline(always)]
1674 pub fn lvd1st(
1675 self,
1676 ) -> crate::common::RegisterField<
1677 2,
1678 0x1,
1679 1,
1680 0,
1681 nmisr::Lvd1St,
1682 nmisr::Lvd1St,
1683 Nmisr_SPEC,
1684 crate::common::R,
1685 > {
1686 crate::common::RegisterField::<
1687 2,
1688 0x1,
1689 1,
1690 0,
1691 nmisr::Lvd1St,
1692 nmisr::Lvd1St,
1693 Nmisr_SPEC,
1694 crate::common::R,
1695 >::from_register(self, 0)
1696 }
1697
1698 #[doc = "Voltage Monitor 2 Interrupt Status Flag"]
1699 #[inline(always)]
1700 pub fn lvd2st(
1701 self,
1702 ) -> crate::common::RegisterField<
1703 3,
1704 0x1,
1705 1,
1706 0,
1707 nmisr::Lvd2St,
1708 nmisr::Lvd2St,
1709 Nmisr_SPEC,
1710 crate::common::R,
1711 > {
1712 crate::common::RegisterField::<
1713 3,
1714 0x1,
1715 1,
1716 0,
1717 nmisr::Lvd2St,
1718 nmisr::Lvd2St,
1719 Nmisr_SPEC,
1720 crate::common::R,
1721 >::from_register(self, 0)
1722 }
1723
1724 #[doc = "Main Clock Oscillation Stop Detection Interrupt Status Flag"]
1725 #[inline(always)]
1726 pub fn ostst(
1727 self,
1728 ) -> crate::common::RegisterField<
1729 6,
1730 0x1,
1731 1,
1732 0,
1733 nmisr::Ostst,
1734 nmisr::Ostst,
1735 Nmisr_SPEC,
1736 crate::common::R,
1737 > {
1738 crate::common::RegisterField::<
1739 6,
1740 0x1,
1741 1,
1742 0,
1743 nmisr::Ostst,
1744 nmisr::Ostst,
1745 Nmisr_SPEC,
1746 crate::common::R,
1747 >::from_register(self, 0)
1748 }
1749
1750 #[doc = "NMI Pin Interrupt Status Flag"]
1751 #[inline(always)]
1752 pub fn nmist(
1753 self,
1754 ) -> crate::common::RegisterField<
1755 7,
1756 0x1,
1757 1,
1758 0,
1759 nmisr::Nmist,
1760 nmisr::Nmist,
1761 Nmisr_SPEC,
1762 crate::common::R,
1763 > {
1764 crate::common::RegisterField::<
1765 7,
1766 0x1,
1767 1,
1768 0,
1769 nmisr::Nmist,
1770 nmisr::Nmist,
1771 Nmisr_SPEC,
1772 crate::common::R,
1773 >::from_register(self, 0)
1774 }
1775
1776 #[doc = "SRAM Parity Error Interrupt Status Flag"]
1777 #[inline(always)]
1778 pub fn rpest(
1779 self,
1780 ) -> crate::common::RegisterField<
1781 8,
1782 0x1,
1783 1,
1784 0,
1785 nmisr::Rpest,
1786 nmisr::Rpest,
1787 Nmisr_SPEC,
1788 crate::common::R,
1789 > {
1790 crate::common::RegisterField::<
1791 8,
1792 0x1,
1793 1,
1794 0,
1795 nmisr::Rpest,
1796 nmisr::Rpest,
1797 Nmisr_SPEC,
1798 crate::common::R,
1799 >::from_register(self, 0)
1800 }
1801
1802 #[doc = "SRAM ECC Error Interrupt Status Flag"]
1803 #[inline(always)]
1804 pub fn reccst(
1805 self,
1806 ) -> crate::common::RegisterField<
1807 9,
1808 0x1,
1809 1,
1810 0,
1811 nmisr::Reccst,
1812 nmisr::Reccst,
1813 Nmisr_SPEC,
1814 crate::common::R,
1815 > {
1816 crate::common::RegisterField::<
1817 9,
1818 0x1,
1819 1,
1820 0,
1821 nmisr::Reccst,
1822 nmisr::Reccst,
1823 Nmisr_SPEC,
1824 crate::common::R,
1825 >::from_register(self, 0)
1826 }
1827
1828 #[doc = "Bus Slave MPU Error Interrupt Status Flag"]
1829 #[inline(always)]
1830 pub fn bussst(
1831 self,
1832 ) -> crate::common::RegisterField<
1833 10,
1834 0x1,
1835 1,
1836 0,
1837 nmisr::Bussst,
1838 nmisr::Bussst,
1839 Nmisr_SPEC,
1840 crate::common::R,
1841 > {
1842 crate::common::RegisterField::<
1843 10,
1844 0x1,
1845 1,
1846 0,
1847 nmisr::Bussst,
1848 nmisr::Bussst,
1849 Nmisr_SPEC,
1850 crate::common::R,
1851 >::from_register(self, 0)
1852 }
1853
1854 #[doc = "Bus Master MPU Error Interrupt Status Flag"]
1855 #[inline(always)]
1856 pub fn busmst(
1857 self,
1858 ) -> crate::common::RegisterField<
1859 11,
1860 0x1,
1861 1,
1862 0,
1863 nmisr::Busmst,
1864 nmisr::Busmst,
1865 Nmisr_SPEC,
1866 crate::common::R,
1867 > {
1868 crate::common::RegisterField::<
1869 11,
1870 0x1,
1871 1,
1872 0,
1873 nmisr::Busmst,
1874 nmisr::Busmst,
1875 Nmisr_SPEC,
1876 crate::common::R,
1877 >::from_register(self, 0)
1878 }
1879
1880 #[doc = "CPU Stack Pointer Monitor Interrupt Status Flag"]
1881 #[inline(always)]
1882 pub fn spest(
1883 self,
1884 ) -> crate::common::RegisterField<
1885 12,
1886 0x1,
1887 1,
1888 0,
1889 nmisr::Spest,
1890 nmisr::Spest,
1891 Nmisr_SPEC,
1892 crate::common::R,
1893 > {
1894 crate::common::RegisterField::<
1895 12,
1896 0x1,
1897 1,
1898 0,
1899 nmisr::Spest,
1900 nmisr::Spest,
1901 Nmisr_SPEC,
1902 crate::common::R,
1903 >::from_register(self, 0)
1904 }
1905}
1906impl ::core::default::Default for Nmisr {
1907 #[inline(always)]
1908 fn default() -> Nmisr {
1909 <crate::RegValueT<Nmisr_SPEC> as RegisterValue<_>>::new(0)
1910 }
1911}
1912pub mod nmisr {
1913
1914 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1915 pub struct Iwdtst_SPEC;
1916 pub type Iwdtst = crate::EnumBitfieldStruct<u8, Iwdtst_SPEC>;
1917 impl Iwdtst {
1918 #[doc = "Interrupt not requested"]
1919 pub const _0: Self = Self::new(0);
1920
1921 #[doc = "Interrupt requested"]
1922 pub const _1: Self = Self::new(1);
1923 }
1924 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1925 pub struct Wdtst_SPEC;
1926 pub type Wdtst = crate::EnumBitfieldStruct<u8, Wdtst_SPEC>;
1927 impl Wdtst {
1928 #[doc = "Interrupt not requested"]
1929 pub const _0: Self = Self::new(0);
1930
1931 #[doc = "Interrupt requested"]
1932 pub const _1: Self = Self::new(1);
1933 }
1934 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1935 pub struct Lvd1St_SPEC;
1936 pub type Lvd1St = crate::EnumBitfieldStruct<u8, Lvd1St_SPEC>;
1937 impl Lvd1St {
1938 #[doc = "Interrupt not requested"]
1939 pub const _0: Self = Self::new(0);
1940
1941 #[doc = "Interrupt requested"]
1942 pub const _1: Self = Self::new(1);
1943 }
1944 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1945 pub struct Lvd2St_SPEC;
1946 pub type Lvd2St = crate::EnumBitfieldStruct<u8, Lvd2St_SPEC>;
1947 impl Lvd2St {
1948 #[doc = "Interrupt not requested"]
1949 pub const _0: Self = Self::new(0);
1950
1951 #[doc = "Interrupt requested"]
1952 pub const _1: Self = Self::new(1);
1953 }
1954 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1955 pub struct Ostst_SPEC;
1956 pub type Ostst = crate::EnumBitfieldStruct<u8, Ostst_SPEC>;
1957 impl Ostst {
1958 #[doc = "Interrupt not requested for main clock oscillation stop"]
1959 pub const _0: Self = Self::new(0);
1960
1961 #[doc = "Interrupt requested for main clock oscillation stop"]
1962 pub const _1: Self = Self::new(1);
1963 }
1964 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1965 pub struct Nmist_SPEC;
1966 pub type Nmist = crate::EnumBitfieldStruct<u8, Nmist_SPEC>;
1967 impl Nmist {
1968 #[doc = "Interrupt not requested"]
1969 pub const _0: Self = Self::new(0);
1970
1971 #[doc = "Interrupt requested"]
1972 pub const _1: Self = Self::new(1);
1973 }
1974 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1975 pub struct Rpest_SPEC;
1976 pub type Rpest = crate::EnumBitfieldStruct<u8, Rpest_SPEC>;
1977 impl Rpest {
1978 #[doc = "Interrupt not requested"]
1979 pub const _0: Self = Self::new(0);
1980
1981 #[doc = "Interrupt requested"]
1982 pub const _1: Self = Self::new(1);
1983 }
1984 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1985 pub struct Reccst_SPEC;
1986 pub type Reccst = crate::EnumBitfieldStruct<u8, Reccst_SPEC>;
1987 impl Reccst {
1988 #[doc = "Interrupt not requested"]
1989 pub const _0: Self = Self::new(0);
1990
1991 #[doc = "Interrupt requested"]
1992 pub const _1: Self = Self::new(1);
1993 }
1994 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1995 pub struct Bussst_SPEC;
1996 pub type Bussst = crate::EnumBitfieldStruct<u8, Bussst_SPEC>;
1997 impl Bussst {
1998 #[doc = "Interrupt not requested"]
1999 pub const _0: Self = Self::new(0);
2000
2001 #[doc = "Interrupt requested."]
2002 pub const _1: Self = Self::new(1);
2003 }
2004 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2005 pub struct Busmst_SPEC;
2006 pub type Busmst = crate::EnumBitfieldStruct<u8, Busmst_SPEC>;
2007 impl Busmst {
2008 #[doc = "Interrupt not requested"]
2009 pub const _0: Self = Self::new(0);
2010
2011 #[doc = "Interrupt requested"]
2012 pub const _1: Self = Self::new(1);
2013 }
2014 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2015 pub struct Spest_SPEC;
2016 pub type Spest = crate::EnumBitfieldStruct<u8, Spest_SPEC>;
2017 impl Spest {
2018 #[doc = "Interrupt not requested"]
2019 pub const _0: Self = Self::new(0);
2020
2021 #[doc = "Interrupt requested"]
2022 pub const _1: Self = Self::new(1);
2023 }
2024}
2025#[doc(hidden)]
2026#[derive(Copy, Clone, Eq, PartialEq)]
2027pub struct Wupen_SPEC;
2028impl crate::sealed::RegSpec for Wupen_SPEC {
2029 type DataType = u32;
2030}
2031
2032#[doc = "Wake Up Interrupt Enable Register"]
2033pub type Wupen = crate::RegValueT<Wupen_SPEC>;
2034
2035impl Wupen {
2036 #[doc = "IRQ Interrupt Software Standby/Snooze Mode Returns Enable"]
2037 #[inline(always)]
2038 pub fn irqwupen(
2039 self,
2040 ) -> crate::common::RegisterField<
2041 0,
2042 0xff,
2043 1,
2044 0,
2045 wupen::Irqwupen,
2046 wupen::Irqwupen,
2047 Wupen_SPEC,
2048 crate::common::RW,
2049 > {
2050 crate::common::RegisterField::<
2051 0,
2052 0xff,
2053 1,
2054 0,
2055 wupen::Irqwupen,
2056 wupen::Irqwupen,
2057 Wupen_SPEC,
2058 crate::common::RW,
2059 >::from_register(self, 0)
2060 }
2061
2062 #[doc = "IWDT Interrupt Software Standby/Snooze Mode Returns Enable"]
2063 #[inline(always)]
2064 pub fn iwdtwupen(
2065 self,
2066 ) -> crate::common::RegisterField<
2067 16,
2068 0x1,
2069 1,
2070 0,
2071 wupen::Iwdtwupen,
2072 wupen::Iwdtwupen,
2073 Wupen_SPEC,
2074 crate::common::RW,
2075 > {
2076 crate::common::RegisterField::<
2077 16,
2078 0x1,
2079 1,
2080 0,
2081 wupen::Iwdtwupen,
2082 wupen::Iwdtwupen,
2083 Wupen_SPEC,
2084 crate::common::RW,
2085 >::from_register(self, 0)
2086 }
2087
2088 #[doc = "Key Interrupt Software Standby/Snooze Mode Returns Enable"]
2089 #[inline(always)]
2090 pub fn keywupen(
2091 self,
2092 ) -> crate::common::RegisterField<
2093 17,
2094 0x1,
2095 1,
2096 0,
2097 wupen::Keywupen,
2098 wupen::Keywupen,
2099 Wupen_SPEC,
2100 crate::common::RW,
2101 > {
2102 crate::common::RegisterField::<
2103 17,
2104 0x1,
2105 1,
2106 0,
2107 wupen::Keywupen,
2108 wupen::Keywupen,
2109 Wupen_SPEC,
2110 crate::common::RW,
2111 >::from_register(self, 0)
2112 }
2113
2114 #[doc = "LVD1 Interrupt Software Standby/Snooze Mode Returns Enable"]
2115 #[inline(always)]
2116 pub fn lvd1wupen(
2117 self,
2118 ) -> crate::common::RegisterField<
2119 18,
2120 0x1,
2121 1,
2122 0,
2123 wupen::Lvd1Wupen,
2124 wupen::Lvd1Wupen,
2125 Wupen_SPEC,
2126 crate::common::RW,
2127 > {
2128 crate::common::RegisterField::<
2129 18,
2130 0x1,
2131 1,
2132 0,
2133 wupen::Lvd1Wupen,
2134 wupen::Lvd1Wupen,
2135 Wupen_SPEC,
2136 crate::common::RW,
2137 >::from_register(self, 0)
2138 }
2139
2140 #[doc = "LVD2 Interrupt Software Standby/Snooze Mode Returns Enable"]
2141 #[inline(always)]
2142 pub fn lvd2wupen(
2143 self,
2144 ) -> crate::common::RegisterField<
2145 19,
2146 0x1,
2147 1,
2148 0,
2149 wupen::Lvd2Wupen,
2150 wupen::Lvd2Wupen,
2151 Wupen_SPEC,
2152 crate::common::RW,
2153 > {
2154 crate::common::RegisterField::<
2155 19,
2156 0x1,
2157 1,
2158 0,
2159 wupen::Lvd2Wupen,
2160 wupen::Lvd2Wupen,
2161 Wupen_SPEC,
2162 crate::common::RW,
2163 >::from_register(self, 0)
2164 }
2165
2166 #[doc = "ACMPLP0 Interrupt Software Standby/Snooze Mode Returns Enable"]
2167 #[inline(always)]
2168 pub fn acmplp0wupen(
2169 self,
2170 ) -> crate::common::RegisterField<
2171 23,
2172 0x1,
2173 1,
2174 0,
2175 wupen::Acmplp0Wupen,
2176 wupen::Acmplp0Wupen,
2177 Wupen_SPEC,
2178 crate::common::RW,
2179 > {
2180 crate::common::RegisterField::<
2181 23,
2182 0x1,
2183 1,
2184 0,
2185 wupen::Acmplp0Wupen,
2186 wupen::Acmplp0Wupen,
2187 Wupen_SPEC,
2188 crate::common::RW,
2189 >::from_register(self, 0)
2190 }
2191
2192 #[doc = "RTC Alarm Interrupt Software Standby/Snooze Mode Returns Enable"]
2193 #[inline(always)]
2194 pub fn rtcalmwupen(
2195 self,
2196 ) -> crate::common::RegisterField<
2197 24,
2198 0x1,
2199 1,
2200 0,
2201 wupen::Rtcalmwupen,
2202 wupen::Rtcalmwupen,
2203 Wupen_SPEC,
2204 crate::common::RW,
2205 > {
2206 crate::common::RegisterField::<
2207 24,
2208 0x1,
2209 1,
2210 0,
2211 wupen::Rtcalmwupen,
2212 wupen::Rtcalmwupen,
2213 Wupen_SPEC,
2214 crate::common::RW,
2215 >::from_register(self, 0)
2216 }
2217
2218 #[doc = "RTC Period Interrupt Software Standby/Snooze Mode Returns Enable"]
2219 #[inline(always)]
2220 pub fn rtcprdwupen(
2221 self,
2222 ) -> crate::common::RegisterField<
2223 25,
2224 0x1,
2225 1,
2226 0,
2227 wupen::Rtcprdwupen,
2228 wupen::Rtcprdwupen,
2229 Wupen_SPEC,
2230 crate::common::RW,
2231 > {
2232 crate::common::RegisterField::<
2233 25,
2234 0x1,
2235 1,
2236 0,
2237 wupen::Rtcprdwupen,
2238 wupen::Rtcprdwupen,
2239 Wupen_SPEC,
2240 crate::common::RW,
2241 >::from_register(self, 0)
2242 }
2243
2244 #[doc = "AGT1 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
2245 #[inline(always)]
2246 pub fn agt1udwupen(
2247 self,
2248 ) -> crate::common::RegisterField<
2249 28,
2250 0x1,
2251 1,
2252 0,
2253 wupen::Agt1Udwupen,
2254 wupen::Agt1Udwupen,
2255 Wupen_SPEC,
2256 crate::common::RW,
2257 > {
2258 crate::common::RegisterField::<
2259 28,
2260 0x1,
2261 1,
2262 0,
2263 wupen::Agt1Udwupen,
2264 wupen::Agt1Udwupen,
2265 Wupen_SPEC,
2266 crate::common::RW,
2267 >::from_register(self, 0)
2268 }
2269
2270 #[doc = "AGT1 Compare Match A Interrupt Software Standby/Snooze Mode Returns Enable"]
2271 #[inline(always)]
2272 pub fn agt1cawupen(
2273 self,
2274 ) -> crate::common::RegisterField<
2275 29,
2276 0x1,
2277 1,
2278 0,
2279 wupen::Agt1Cawupen,
2280 wupen::Agt1Cawupen,
2281 Wupen_SPEC,
2282 crate::common::RW,
2283 > {
2284 crate::common::RegisterField::<
2285 29,
2286 0x1,
2287 1,
2288 0,
2289 wupen::Agt1Cawupen,
2290 wupen::Agt1Cawupen,
2291 Wupen_SPEC,
2292 crate::common::RW,
2293 >::from_register(self, 0)
2294 }
2295
2296 #[doc = "AGT1 Compare Match B Interrupt Software Standby/Snooze Mode Returns Enable"]
2297 #[inline(always)]
2298 pub fn agt1cbwupen(
2299 self,
2300 ) -> crate::common::RegisterField<
2301 30,
2302 0x1,
2303 1,
2304 0,
2305 wupen::Agt1Cbwupen,
2306 wupen::Agt1Cbwupen,
2307 Wupen_SPEC,
2308 crate::common::RW,
2309 > {
2310 crate::common::RegisterField::<
2311 30,
2312 0x1,
2313 1,
2314 0,
2315 wupen::Agt1Cbwupen,
2316 wupen::Agt1Cbwupen,
2317 Wupen_SPEC,
2318 crate::common::RW,
2319 >::from_register(self, 0)
2320 }
2321
2322 #[doc = "IIC0 Address Match Interrupt Software Standby/Snooze Mode Returns Enable"]
2323 #[inline(always)]
2324 pub fn iic0wupen(
2325 self,
2326 ) -> crate::common::RegisterField<
2327 31,
2328 0x1,
2329 1,
2330 0,
2331 wupen::Iic0Wupen,
2332 wupen::Iic0Wupen,
2333 Wupen_SPEC,
2334 crate::common::RW,
2335 > {
2336 crate::common::RegisterField::<
2337 31,
2338 0x1,
2339 1,
2340 0,
2341 wupen::Iic0Wupen,
2342 wupen::Iic0Wupen,
2343 Wupen_SPEC,
2344 crate::common::RW,
2345 >::from_register(self, 0)
2346 }
2347}
2348impl ::core::default::Default for Wupen {
2349 #[inline(always)]
2350 fn default() -> Wupen {
2351 <crate::RegValueT<Wupen_SPEC> as RegisterValue<_>>::new(0)
2352 }
2353}
2354pub mod wupen {
2355
2356 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2357 pub struct Irqwupen_SPEC;
2358 pub type Irqwupen = crate::EnumBitfieldStruct<u8, Irqwupen_SPEC>;
2359 impl Irqwupen {
2360 #[doc = "Software Standby/Snooze Mode returns by IRQn interrupt disabled"]
2361 pub const _0: Self = Self::new(0);
2362
2363 #[doc = "Software Standby/Snooze Mode returns by IRQn interrupt enabled"]
2364 pub const _1: Self = Self::new(1);
2365 }
2366 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2367 pub struct Iwdtwupen_SPEC;
2368 pub type Iwdtwupen = crate::EnumBitfieldStruct<u8, Iwdtwupen_SPEC>;
2369 impl Iwdtwupen {
2370 #[doc = "Software Standby/Snooze Mode returns by IWDT interrupt disabled"]
2371 pub const _0: Self = Self::new(0);
2372
2373 #[doc = "Software Standby/Snooze Mode returns by IWDT interrupt enabled"]
2374 pub const _1: Self = Self::new(1);
2375 }
2376 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2377 pub struct Keywupen_SPEC;
2378 pub type Keywupen = crate::EnumBitfieldStruct<u8, Keywupen_SPEC>;
2379 impl Keywupen {
2380 #[doc = "Software Standby/Snooze Mode returns by KEY interrupt disabled"]
2381 pub const _0: Self = Self::new(0);
2382
2383 #[doc = "Software Standby/Snooze Mode returns by KEY interrupt enabled"]
2384 pub const _1: Self = Self::new(1);
2385 }
2386 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2387 pub struct Lvd1Wupen_SPEC;
2388 pub type Lvd1Wupen = crate::EnumBitfieldStruct<u8, Lvd1Wupen_SPEC>;
2389 impl Lvd1Wupen {
2390 #[doc = "Software Standby/Snooze Mode returns by LVD1 interrupt disabled"]
2391 pub const _0: Self = Self::new(0);
2392
2393 #[doc = "Software Standby/Snooze Mode returns by LVD1 interrupt enabled"]
2394 pub const _1: Self = Self::new(1);
2395 }
2396 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2397 pub struct Lvd2Wupen_SPEC;
2398 pub type Lvd2Wupen = crate::EnumBitfieldStruct<u8, Lvd2Wupen_SPEC>;
2399 impl Lvd2Wupen {
2400 #[doc = "Software Standby/Snooze Mode returns by LVD2 interrupt disabled"]
2401 pub const _0: Self = Self::new(0);
2402
2403 #[doc = "Software Standby/Snooze Mode returns by LVD2 interrupt enabled"]
2404 pub const _1: Self = Self::new(1);
2405 }
2406 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2407 pub struct Acmplp0Wupen_SPEC;
2408 pub type Acmplp0Wupen = crate::EnumBitfieldStruct<u8, Acmplp0Wupen_SPEC>;
2409 impl Acmplp0Wupen {
2410 #[doc = "Software Standby/Snooze Mode returns by ACMPLP0 interrupt disabled"]
2411 pub const _0: Self = Self::new(0);
2412
2413 #[doc = "Software Standby/Snooze Mode returns by ACMPLP0 interrupt enabled"]
2414 pub const _1: Self = Self::new(1);
2415 }
2416 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2417 pub struct Rtcalmwupen_SPEC;
2418 pub type Rtcalmwupen = crate::EnumBitfieldStruct<u8, Rtcalmwupen_SPEC>;
2419 impl Rtcalmwupen {
2420 #[doc = "Software Standby/Snooze Mode returns by RTC alarm interrupt disabled"]
2421 pub const _0: Self = Self::new(0);
2422
2423 #[doc = "Software Standby/Snooze Mode returns by RTC alarm interrupt enabled."]
2424 pub const _1: Self = Self::new(1);
2425 }
2426 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2427 pub struct Rtcprdwupen_SPEC;
2428 pub type Rtcprdwupen = crate::EnumBitfieldStruct<u8, Rtcprdwupen_SPEC>;
2429 impl Rtcprdwupen {
2430 #[doc = "Software Standby/Snooze Mode returns by RTC period interrupt disabled"]
2431 pub const _0: Self = Self::new(0);
2432
2433 #[doc = "Software Standby/Snooze Mode returns by RTC period interrupt enabled"]
2434 pub const _1: Self = Self::new(1);
2435 }
2436 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2437 pub struct Agt1Udwupen_SPEC;
2438 pub type Agt1Udwupen = crate::EnumBitfieldStruct<u8, Agt1Udwupen_SPEC>;
2439 impl Agt1Udwupen {
2440 #[doc = "Software Standby/Snooze Mode returns by AGT1 underflow interrupt disabled"]
2441 pub const _0: Self = Self::new(0);
2442
2443 #[doc = "Software Standby/Snooze Mode returns by AGT1 underflow"]
2444 pub const _1: Self = Self::new(1);
2445 }
2446 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2447 pub struct Agt1Cawupen_SPEC;
2448 pub type Agt1Cawupen = crate::EnumBitfieldStruct<u8, Agt1Cawupen_SPEC>;
2449 impl Agt1Cawupen {
2450 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match A interrupt disabled."]
2451 pub const _0: Self = Self::new(0);
2452
2453 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match A interrupt enabled."]
2454 pub const _1: Self = Self::new(1);
2455 }
2456 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2457 pub struct Agt1Cbwupen_SPEC;
2458 pub type Agt1Cbwupen = crate::EnumBitfieldStruct<u8, Agt1Cbwupen_SPEC>;
2459 impl Agt1Cbwupen {
2460 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match B interrupt disabled."]
2461 pub const _0: Self = Self::new(0);
2462
2463 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match B interrupt enabled."]
2464 pub const _1: Self = Self::new(1);
2465 }
2466 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2467 pub struct Iic0Wupen_SPEC;
2468 pub type Iic0Wupen = crate::EnumBitfieldStruct<u8, Iic0Wupen_SPEC>;
2469 impl Iic0Wupen {
2470 #[doc = "Software Standby/Snooze Mode returns by IIC0 address match interrupt disabled"]
2471 pub const _0: Self = Self::new(0);
2472
2473 #[doc = "Software Standby/Snooze Mode returns by IIC0 address match interrupt enabled"]
2474 pub const _1: Self = Self::new(1);
2475 }
2476}
2477#[doc(hidden)]
2478#[derive(Copy, Clone, Eq, PartialEq)]
2479pub struct Ielen_SPEC;
2480impl crate::sealed::RegSpec for Ielen_SPEC {
2481 type DataType = u8;
2482}
2483
2484#[doc = "ICU event Enable Register"]
2485pub type Ielen = crate::RegValueT<Ielen_SPEC>;
2486
2487impl Ielen {
2488 #[doc = "RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit = 1)"]
2489 #[inline(always)]
2490 pub fn rtcinten(
2491 self,
2492 ) -> crate::common::RegisterField<
2493 0,
2494 0x1,
2495 1,
2496 0,
2497 ielen::Rtcinten,
2498 ielen::Rtcinten,
2499 Ielen_SPEC,
2500 crate::common::RW,
2501 > {
2502 crate::common::RegisterField::<
2503 0,
2504 0x1,
2505 1,
2506 0,
2507 ielen::Rtcinten,
2508 ielen::Rtcinten,
2509 Ielen_SPEC,
2510 crate::common::RW,
2511 >::from_register(self, 0)
2512 }
2513
2514 #[doc = "Parts Asynchronous Interrupts Enable except RTC (when LPOPTEN bit = 1)"]
2515 #[inline(always)]
2516 pub fn ielen(
2517 self,
2518 ) -> crate::common::RegisterField<
2519 1,
2520 0x1,
2521 1,
2522 0,
2523 ielen::Ielen,
2524 ielen::Ielen,
2525 Ielen_SPEC,
2526 crate::common::RW,
2527 > {
2528 crate::common::RegisterField::<
2529 1,
2530 0x1,
2531 1,
2532 0,
2533 ielen::Ielen,
2534 ielen::Ielen,
2535 Ielen_SPEC,
2536 crate::common::RW,
2537 >::from_register(self, 0)
2538 }
2539}
2540impl ::core::default::Default for Ielen {
2541 #[inline(always)]
2542 fn default() -> Ielen {
2543 <crate::RegValueT<Ielen_SPEC> as RegisterValue<_>>::new(0)
2544 }
2545}
2546pub mod ielen {
2547
2548 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2549 pub struct Rtcinten_SPEC;
2550 pub type Rtcinten = crate::EnumBitfieldStruct<u8, Rtcinten_SPEC>;
2551 impl Rtcinten {
2552 #[doc = "Disabled"]
2553 pub const _0: Self = Self::new(0);
2554
2555 #[doc = "Enabled"]
2556 pub const _1: Self = Self::new(1);
2557 }
2558 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2559 pub struct Ielen_SPEC;
2560 pub type Ielen = crate::EnumBitfieldStruct<u8, Ielen_SPEC>;
2561 impl Ielen {
2562 #[doc = "Disabled"]
2563 pub const _0: Self = Self::new(0);
2564
2565 #[doc = "Enabled"]
2566 pub const _1: Self = Self::new(1);
2567 }
2568}
2569#[doc(hidden)]
2570#[derive(Copy, Clone, Eq, PartialEq)]
2571pub struct Selsr0_SPEC;
2572impl crate::sealed::RegSpec for Selsr0_SPEC {
2573 type DataType = u16;
2574}
2575
2576#[doc = "SYS Event Link Setting Register"]
2577pub type Selsr0 = crate::RegValueT<Selsr0_SPEC>;
2578
2579impl NoBitfieldReg<Selsr0_SPEC> for Selsr0 {}
2580impl ::core::default::Default for Selsr0 {
2581 #[inline(always)]
2582 fn default() -> Selsr0 {
2583 <crate::RegValueT<Selsr0_SPEC> as RegisterValue<_>>::new(0)
2584 }
2585}
2586
2587#[doc(hidden)]
2588#[derive(Copy, Clone, Eq, PartialEq)]
2589pub struct Ielsr_SPEC;
2590impl crate::sealed::RegSpec for Ielsr_SPEC {
2591 type DataType = u32;
2592}
2593
2594#[doc = "ICU Event Link Setting Register %s"]
2595pub type Ielsr = crate::RegValueT<Ielsr_SPEC>;
2596
2597impl NoBitfieldReg<Ielsr_SPEC> for Ielsr {}
2598impl ::core::default::Default for Ielsr {
2599 #[inline(always)]
2600 fn default() -> Ielsr {
2601 <crate::RegValueT<Ielsr_SPEC> as RegisterValue<_>>::new(0)
2602 }
2603}