1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"System Control"]
28unsafe impl ::core::marker::Send for super::Sysc {}
29unsafe impl ::core::marker::Sync for super::Sysc {}
30impl super::Sysc {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "Standby Control Register"]
38 #[inline(always)]
39 pub const fn sbycr(&self) -> &'static crate::common::Reg<self::Sbycr_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Sbycr_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(12usize),
43 )
44 }
45 }
46
47 #[doc = "Module Stop Control Register A"]
48 #[inline(always)]
49 pub const fn mstpcra(
50 &self,
51 ) -> &'static crate::common::Reg<self::Mstpcra_SPEC, crate::common::RW> {
52 unsafe {
53 crate::common::Reg::<self::Mstpcra_SPEC, crate::common::RW>::from_ptr(
54 self._svd2pac_as_ptr().add(28usize),
55 )
56 }
57 }
58
59 #[doc = "System Clock Division Control Register"]
60 #[inline(always)]
61 pub const fn sckdivcr(
62 &self,
63 ) -> &'static crate::common::Reg<self::Sckdivcr_SPEC, crate::common::RW> {
64 unsafe {
65 crate::common::Reg::<self::Sckdivcr_SPEC, crate::common::RW>::from_ptr(
66 self._svd2pac_as_ptr().add(32usize),
67 )
68 }
69 }
70
71 #[doc = "System Clock Source Control Register"]
72 #[inline(always)]
73 pub const fn sckscr(
74 &self,
75 ) -> &'static crate::common::Reg<self::Sckscr_SPEC, crate::common::RW> {
76 unsafe {
77 crate::common::Reg::<self::Sckscr_SPEC, crate::common::RW>::from_ptr(
78 self._svd2pac_as_ptr().add(38usize),
79 )
80 }
81 }
82
83 #[doc = "Memory Wait Cycle Control Register for Code Flash"]
84 #[inline(always)]
85 pub const fn memwait(
86 &self,
87 ) -> &'static crate::common::Reg<self::Memwait_SPEC, crate::common::RW> {
88 unsafe {
89 crate::common::Reg::<self::Memwait_SPEC, crate::common::RW>::from_ptr(
90 self._svd2pac_as_ptr().add(49usize),
91 )
92 }
93 }
94
95 #[doc = "Main Clock Oscillator Control Register"]
96 #[inline(always)]
97 pub const fn mosccr(
98 &self,
99 ) -> &'static crate::common::Reg<self::Mosccr_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Mosccr_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(50usize),
103 )
104 }
105 }
106
107 #[doc = "High-Speed On-Chip Oscillator Control Register"]
108 #[inline(always)]
109 pub const fn hococr(
110 &self,
111 ) -> &'static crate::common::Reg<self::Hococr_SPEC, crate::common::RW> {
112 unsafe {
113 crate::common::Reg::<self::Hococr_SPEC, crate::common::RW>::from_ptr(
114 self._svd2pac_as_ptr().add(54usize),
115 )
116 }
117 }
118
119 #[doc = "Middle-Speed On-Chip Oscillator Control Register"]
120 #[inline(always)]
121 pub const fn mococr(
122 &self,
123 ) -> &'static crate::common::Reg<self::Mococr_SPEC, crate::common::RW> {
124 unsafe {
125 crate::common::Reg::<self::Mococr_SPEC, crate::common::RW>::from_ptr(
126 self._svd2pac_as_ptr().add(56usize),
127 )
128 }
129 }
130
131 #[doc = "Oscillation Stabilization Flag Register"]
132 #[inline(always)]
133 pub const fn oscsf(&self) -> &'static crate::common::Reg<self::Oscsf_SPEC, crate::common::R> {
134 unsafe {
135 crate::common::Reg::<self::Oscsf_SPEC, crate::common::R>::from_ptr(
136 self._svd2pac_as_ptr().add(60usize),
137 )
138 }
139 }
140
141 #[doc = "Clock Out Control Register"]
142 #[inline(always)]
143 pub const fn ckocr(&self) -> &'static crate::common::Reg<self::Ckocr_SPEC, crate::common::RW> {
144 unsafe {
145 crate::common::Reg::<self::Ckocr_SPEC, crate::common::RW>::from_ptr(
146 self._svd2pac_as_ptr().add(62usize),
147 )
148 }
149 }
150
151 #[doc = "Oscillation Stop Detection Control Register"]
152 #[inline(always)]
153 pub const fn ostdcr(
154 &self,
155 ) -> &'static crate::common::Reg<self::Ostdcr_SPEC, crate::common::RW> {
156 unsafe {
157 crate::common::Reg::<self::Ostdcr_SPEC, crate::common::RW>::from_ptr(
158 self._svd2pac_as_ptr().add(64usize),
159 )
160 }
161 }
162
163 #[doc = "Oscillation Stop Detection Status Register"]
164 #[inline(always)]
165 pub const fn ostdsr(
166 &self,
167 ) -> &'static crate::common::Reg<self::Ostdsr_SPEC, crate::common::RW> {
168 unsafe {
169 crate::common::Reg::<self::Ostdsr_SPEC, crate::common::RW>::from_ptr(
170 self._svd2pac_as_ptr().add(65usize),
171 )
172 }
173 }
174
175 #[doc = "Lower Power Operation Control Register"]
176 #[inline(always)]
177 pub const fn lpopt(&self) -> &'static crate::common::Reg<self::Lpopt_SPEC, crate::common::RW> {
178 unsafe {
179 crate::common::Reg::<self::Lpopt_SPEC, crate::common::RW>::from_ptr(
180 self._svd2pac_as_ptr().add(76usize),
181 )
182 }
183 }
184
185 #[doc = "MOCO User Trimming Control Register"]
186 #[inline(always)]
187 pub const fn mocoutcr(
188 &self,
189 ) -> &'static crate::common::Reg<self::Mocoutcr_SPEC, crate::common::RW> {
190 unsafe {
191 crate::common::Reg::<self::Mocoutcr_SPEC, crate::common::RW>::from_ptr(
192 self._svd2pac_as_ptr().add(97usize),
193 )
194 }
195 }
196
197 #[doc = "HOCO User Trimming Control Register"]
198 #[inline(always)]
199 pub const fn hocoutcr(
200 &self,
201 ) -> &'static crate::common::Reg<self::Hocoutcr_SPEC, crate::common::RW> {
202 unsafe {
203 crate::common::Reg::<self::Hocoutcr_SPEC, crate::common::RW>::from_ptr(
204 self._svd2pac_as_ptr().add(98usize),
205 )
206 }
207 }
208
209 #[doc = "Snooze Control Register"]
210 #[inline(always)]
211 pub const fn snzcr(&self) -> &'static crate::common::Reg<self::Snzcr_SPEC, crate::common::RW> {
212 unsafe {
213 crate::common::Reg::<self::Snzcr_SPEC, crate::common::RW>::from_ptr(
214 self._svd2pac_as_ptr().add(146usize),
215 )
216 }
217 }
218
219 #[doc = "Snooze End Control Register 0"]
220 #[inline(always)]
221 pub const fn snzedcr0(
222 &self,
223 ) -> &'static crate::common::Reg<self::Snzedcr0_SPEC, crate::common::RW> {
224 unsafe {
225 crate::common::Reg::<self::Snzedcr0_SPEC, crate::common::RW>::from_ptr(
226 self._svd2pac_as_ptr().add(148usize),
227 )
228 }
229 }
230
231 #[doc = "Snooze Request Control Register 0"]
232 #[inline(always)]
233 pub const fn snzreqcr0(
234 &self,
235 ) -> &'static crate::common::Reg<self::Snzreqcr0_SPEC, crate::common::RW> {
236 unsafe {
237 crate::common::Reg::<self::Snzreqcr0_SPEC, crate::common::RW>::from_ptr(
238 self._svd2pac_as_ptr().add(152usize),
239 )
240 }
241 }
242
243 #[doc = "Power Save Memory Control Register"]
244 #[inline(always)]
245 pub const fn psmcr(&self) -> &'static crate::common::Reg<self::Psmcr_SPEC, crate::common::RW> {
246 unsafe {
247 crate::common::Reg::<self::Psmcr_SPEC, crate::common::RW>::from_ptr(
248 self._svd2pac_as_ptr().add(159usize),
249 )
250 }
251 }
252
253 #[doc = "Operating Power Control Register"]
254 #[inline(always)]
255 pub const fn opccr(&self) -> &'static crate::common::Reg<self::Opccr_SPEC, crate::common::RW> {
256 unsafe {
257 crate::common::Reg::<self::Opccr_SPEC, crate::common::RW>::from_ptr(
258 self._svd2pac_as_ptr().add(160usize),
259 )
260 }
261 }
262
263 #[doc = "Main Clock Oscillator Wait Control Register"]
264 #[inline(always)]
265 pub const fn moscwtcr(
266 &self,
267 ) -> &'static crate::common::Reg<self::Moscwtcr_SPEC, crate::common::RW> {
268 unsafe {
269 crate::common::Reg::<self::Moscwtcr_SPEC, crate::common::RW>::from_ptr(
270 self._svd2pac_as_ptr().add(162usize),
271 )
272 }
273 }
274
275 #[doc = "Sub Operating Power Control Register"]
276 #[inline(always)]
277 pub const fn sopccr(
278 &self,
279 ) -> &'static crate::common::Reg<self::Sopccr_SPEC, crate::common::RW> {
280 unsafe {
281 crate::common::Reg::<self::Sopccr_SPEC, crate::common::RW>::from_ptr(
282 self._svd2pac_as_ptr().add(170usize),
283 )
284 }
285 }
286
287 #[doc = "Reset Status Register 1"]
288 #[inline(always)]
289 pub const fn rstsr1(
290 &self,
291 ) -> &'static crate::common::Reg<self::Rstsr1_SPEC, crate::common::RW> {
292 unsafe {
293 crate::common::Reg::<self::Rstsr1_SPEC, crate::common::RW>::from_ptr(
294 self._svd2pac_as_ptr().add(192usize),
295 )
296 }
297 }
298
299 #[doc = "Voltage Monitor 1 Circuit Control Register"]
300 #[inline(always)]
301 pub const fn lvd1cr1(
302 &self,
303 ) -> &'static crate::common::Reg<self::Lvd1Cr1_SPEC, crate::common::RW> {
304 unsafe {
305 crate::common::Reg::<self::Lvd1Cr1_SPEC, crate::common::RW>::from_ptr(
306 self._svd2pac_as_ptr().add(224usize),
307 )
308 }
309 }
310
311 #[doc = "Voltage Monitor 1 Circuit Status Register"]
312 #[inline(always)]
313 pub const fn lvd1sr(
314 &self,
315 ) -> &'static crate::common::Reg<self::Lvd1Sr_SPEC, crate::common::RW> {
316 unsafe {
317 crate::common::Reg::<self::Lvd1Sr_SPEC, crate::common::RW>::from_ptr(
318 self._svd2pac_as_ptr().add(225usize),
319 )
320 }
321 }
322
323 #[doc = "Voltage Monitor 2 Circuit Control Register 1"]
324 #[inline(always)]
325 pub const fn lvd2cr1(
326 &self,
327 ) -> &'static crate::common::Reg<self::Lvd2Cr1_SPEC, crate::common::RW> {
328 unsafe {
329 crate::common::Reg::<self::Lvd2Cr1_SPEC, crate::common::RW>::from_ptr(
330 self._svd2pac_as_ptr().add(226usize),
331 )
332 }
333 }
334
335 #[doc = "Voltage Monitor 2 Circuit Status Register"]
336 #[inline(always)]
337 pub const fn lvd2sr(
338 &self,
339 ) -> &'static crate::common::Reg<self::Lvd2Sr_SPEC, crate::common::RW> {
340 unsafe {
341 crate::common::Reg::<self::Lvd2Sr_SPEC, crate::common::RW>::from_ptr(
342 self._svd2pac_as_ptr().add(227usize),
343 )
344 }
345 }
346
347 #[doc = "Protect Register"]
348 #[inline(always)]
349 pub const fn prcr(&self) -> &'static crate::common::Reg<self::Prcr_SPEC, crate::common::RW> {
350 unsafe {
351 crate::common::Reg::<self::Prcr_SPEC, crate::common::RW>::from_ptr(
352 self._svd2pac_as_ptr().add(1022usize),
353 )
354 }
355 }
356
357 #[doc = "System Control OCD Control Register"]
358 #[inline(always)]
359 pub const fn syocdcr(
360 &self,
361 ) -> &'static crate::common::Reg<self::Syocdcr_SPEC, crate::common::RW> {
362 unsafe {
363 crate::common::Reg::<self::Syocdcr_SPEC, crate::common::RW>::from_ptr(
364 self._svd2pac_as_ptr().add(1038usize),
365 )
366 }
367 }
368
369 #[doc = "Reset Status Register 0"]
370 #[inline(always)]
371 pub const fn rstsr0(
372 &self,
373 ) -> &'static crate::common::Reg<self::Rstsr0_SPEC, crate::common::RW> {
374 unsafe {
375 crate::common::Reg::<self::Rstsr0_SPEC, crate::common::RW>::from_ptr(
376 self._svd2pac_as_ptr().add(1040usize),
377 )
378 }
379 }
380
381 #[doc = "Reset Status Register 2"]
382 #[inline(always)]
383 pub const fn rstsr2(
384 &self,
385 ) -> &'static crate::common::Reg<self::Rstsr2_SPEC, crate::common::RW> {
386 unsafe {
387 crate::common::Reg::<self::Rstsr2_SPEC, crate::common::RW>::from_ptr(
388 self._svd2pac_as_ptr().add(1041usize),
389 )
390 }
391 }
392
393 #[doc = "Main Clock Oscillator Mode Oscillation Control Register"]
394 #[inline(always)]
395 pub const fn momcr(&self) -> &'static crate::common::Reg<self::Momcr_SPEC, crate::common::RW> {
396 unsafe {
397 crate::common::Reg::<self::Momcr_SPEC, crate::common::RW>::from_ptr(
398 self._svd2pac_as_ptr().add(1043usize),
399 )
400 }
401 }
402
403 #[doc = "Voltage Monitor Circuit Control Register"]
404 #[inline(always)]
405 pub const fn lvcmpcr(
406 &self,
407 ) -> &'static crate::common::Reg<self::Lvcmpcr_SPEC, crate::common::RW> {
408 unsafe {
409 crate::common::Reg::<self::Lvcmpcr_SPEC, crate::common::RW>::from_ptr(
410 self._svd2pac_as_ptr().add(1047usize),
411 )
412 }
413 }
414
415 #[doc = "Voltage Detection Level Select Register"]
416 #[inline(always)]
417 pub const fn lvdlvlr(
418 &self,
419 ) -> &'static crate::common::Reg<self::Lvdlvlr_SPEC, crate::common::RW> {
420 unsafe {
421 crate::common::Reg::<self::Lvdlvlr_SPEC, crate::common::RW>::from_ptr(
422 self._svd2pac_as_ptr().add(1048usize),
423 )
424 }
425 }
426
427 #[doc = "Voltage Monitor 1 Circuit Control Register 0"]
428 #[inline(always)]
429 pub const fn lvd1cr0(
430 &self,
431 ) -> &'static crate::common::Reg<self::Lvd1Cr0_SPEC, crate::common::RW> {
432 unsafe {
433 crate::common::Reg::<self::Lvd1Cr0_SPEC, crate::common::RW>::from_ptr(
434 self._svd2pac_as_ptr().add(1050usize),
435 )
436 }
437 }
438
439 #[doc = "Voltage Monitor 2 Circuit Control Register 0"]
440 #[inline(always)]
441 pub const fn lvd2cr0(
442 &self,
443 ) -> &'static crate::common::Reg<self::Lvd2Cr0_SPEC, crate::common::RW> {
444 unsafe {
445 crate::common::Reg::<self::Lvd2Cr0_SPEC, crate::common::RW>::from_ptr(
446 self._svd2pac_as_ptr().add(1051usize),
447 )
448 }
449 }
450
451 #[doc = "DCDC/LDO Control Register"]
452 #[inline(always)]
453 pub const fn dcdcctl(
454 &self,
455 ) -> &'static crate::common::Reg<self::Dcdcctl_SPEC, crate::common::RW> {
456 unsafe {
457 crate::common::Reg::<self::Dcdcctl_SPEC, crate::common::RW>::from_ptr(
458 self._svd2pac_as_ptr().add(1088usize),
459 )
460 }
461 }
462
463 #[doc = "Voltage Level Selection Control Register"]
464 #[inline(always)]
465 pub const fn vccsel(
466 &self,
467 ) -> &'static crate::common::Reg<self::Vccsel_SPEC, crate::common::RW> {
468 unsafe {
469 crate::common::Reg::<self::Vccsel_SPEC, crate::common::RW>::from_ptr(
470 self._svd2pac_as_ptr().add(1089usize),
471 )
472 }
473 }
474
475 #[doc = "Sub-Clock Oscillator Control Register"]
476 #[inline(always)]
477 pub const fn sosccr(
478 &self,
479 ) -> &'static crate::common::Reg<self::Sosccr_SPEC, crate::common::RW> {
480 unsafe {
481 crate::common::Reg::<self::Sosccr_SPEC, crate::common::RW>::from_ptr(
482 self._svd2pac_as_ptr().add(1152usize),
483 )
484 }
485 }
486
487 #[doc = "Sub-Clock Oscillator Mode Control Register"]
488 #[inline(always)]
489 pub const fn somcr(&self) -> &'static crate::common::Reg<self::Somcr_SPEC, crate::common::RW> {
490 unsafe {
491 crate::common::Reg::<self::Somcr_SPEC, crate::common::RW>::from_ptr(
492 self._svd2pac_as_ptr().add(1153usize),
493 )
494 }
495 }
496
497 #[doc = "Sub-Clock Oscillator Margin Check Register"]
498 #[inline(always)]
499 pub const fn somrg(&self) -> &'static crate::common::Reg<self::Somrg_SPEC, crate::common::RW> {
500 unsafe {
501 crate::common::Reg::<self::Somrg_SPEC, crate::common::RW>::from_ptr(
502 self._svd2pac_as_ptr().add(1154usize),
503 )
504 }
505 }
506
507 #[doc = "Low-Speed On-Chip Oscillator Control Register"]
508 #[inline(always)]
509 pub const fn lococr(
510 &self,
511 ) -> &'static crate::common::Reg<self::Lococr_SPEC, crate::common::RW> {
512 unsafe {
513 crate::common::Reg::<self::Lococr_SPEC, crate::common::RW>::from_ptr(
514 self._svd2pac_as_ptr().add(1168usize),
515 )
516 }
517 }
518
519 #[doc = "LOCO User Trimming Control Register"]
520 #[inline(always)]
521 pub const fn locoutcr(
522 &self,
523 ) -> &'static crate::common::Reg<self::Locoutcr_SPEC, crate::common::RW> {
524 unsafe {
525 crate::common::Reg::<self::Locoutcr_SPEC, crate::common::RW>::from_ptr(
526 self._svd2pac_as_ptr().add(1170usize),
527 )
528 }
529 }
530}
531#[doc(hidden)]
532#[derive(Copy, Clone, Eq, PartialEq)]
533pub struct Sbycr_SPEC;
534impl crate::sealed::RegSpec for Sbycr_SPEC {
535 type DataType = u16;
536}
537
538#[doc = "Standby Control Register"]
539pub type Sbycr = crate::RegValueT<Sbycr_SPEC>;
540
541impl Sbycr {
542 #[doc = "Software Standby Mode Select"]
543 #[inline(always)]
544 pub fn ssby(
545 self,
546 ) -> crate::common::RegisterField<
547 15,
548 0x1,
549 1,
550 0,
551 sbycr::Ssby,
552 sbycr::Ssby,
553 Sbycr_SPEC,
554 crate::common::RW,
555 > {
556 crate::common::RegisterField::<
557 15,
558 0x1,
559 1,
560 0,
561 sbycr::Ssby,
562 sbycr::Ssby,
563 Sbycr_SPEC,
564 crate::common::RW,
565 >::from_register(self, 0)
566 }
567}
568impl ::core::default::Default for Sbycr {
569 #[inline(always)]
570 fn default() -> Sbycr {
571 <crate::RegValueT<Sbycr_SPEC> as RegisterValue<_>>::new(0)
572 }
573}
574pub mod sbycr {
575
576 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
577 pub struct Ssby_SPEC;
578 pub type Ssby = crate::EnumBitfieldStruct<u8, Ssby_SPEC>;
579 impl Ssby {
580 #[doc = "Sleep mode"]
581 pub const _0: Self = Self::new(0);
582
583 #[doc = "Software Standby mode."]
584 pub const _1: Self = Self::new(1);
585 }
586}
587#[doc(hidden)]
588#[derive(Copy, Clone, Eq, PartialEq)]
589pub struct Mstpcra_SPEC;
590impl crate::sealed::RegSpec for Mstpcra_SPEC {
591 type DataType = u32;
592}
593
594#[doc = "Module Stop Control Register A"]
595pub type Mstpcra = crate::RegValueT<Mstpcra_SPEC>;
596
597impl Mstpcra {
598 #[doc = "DTC Module Stop"]
599 #[inline(always)]
600 pub fn mstpa22(
601 self,
602 ) -> crate::common::RegisterField<
603 22,
604 0x1,
605 1,
606 0,
607 mstpcra::Mstpa22,
608 mstpcra::Mstpa22,
609 Mstpcra_SPEC,
610 crate::common::RW,
611 > {
612 crate::common::RegisterField::<
613 22,
614 0x1,
615 1,
616 0,
617 mstpcra::Mstpa22,
618 mstpcra::Mstpa22,
619 Mstpcra_SPEC,
620 crate::common::RW,
621 >::from_register(self, 0)
622 }
623}
624impl ::core::default::Default for Mstpcra {
625 #[inline(always)]
626 fn default() -> Mstpcra {
627 <crate::RegValueT<Mstpcra_SPEC> as RegisterValue<_>>::new(4290772991)
628 }
629}
630pub mod mstpcra {
631
632 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
633 pub struct Mstpa22_SPEC;
634 pub type Mstpa22 = crate::EnumBitfieldStruct<u8, Mstpa22_SPEC>;
635 impl Mstpa22 {
636 #[doc = "Cancel the module-stop state"]
637 pub const _0: Self = Self::new(0);
638
639 #[doc = "Enter the module-stop state"]
640 pub const _1: Self = Self::new(1);
641 }
642}
643#[doc(hidden)]
644#[derive(Copy, Clone, Eq, PartialEq)]
645pub struct Sckdivcr_SPEC;
646impl crate::sealed::RegSpec for Sckdivcr_SPEC {
647 type DataType = u32;
648}
649
650#[doc = "System Clock Division Control Register"]
651pub type Sckdivcr = crate::RegValueT<Sckdivcr_SPEC>;
652
653impl Sckdivcr {
654 #[doc = "Peripheral Module Clock D (PCLKD) Select"]
655 #[inline(always)]
656 pub fn pckd(
657 self,
658 ) -> crate::common::RegisterField<
659 0,
660 0x7,
661 1,
662 0,
663 sckdivcr::Pckd,
664 sckdivcr::Pckd,
665 Sckdivcr_SPEC,
666 crate::common::RW,
667 > {
668 crate::common::RegisterField::<
669 0,
670 0x7,
671 1,
672 0,
673 sckdivcr::Pckd,
674 sckdivcr::Pckd,
675 Sckdivcr_SPEC,
676 crate::common::RW,
677 >::from_register(self, 0)
678 }
679
680 #[doc = "Peripheral Module Clock B (PCLKB) Select"]
681 #[inline(always)]
682 pub fn pckb(
683 self,
684 ) -> crate::common::RegisterField<
685 8,
686 0x7,
687 1,
688 0,
689 sckdivcr::Pckb,
690 sckdivcr::Pckb,
691 Sckdivcr_SPEC,
692 crate::common::RW,
693 > {
694 crate::common::RegisterField::<
695 8,
696 0x7,
697 1,
698 0,
699 sckdivcr::Pckb,
700 sckdivcr::Pckb,
701 Sckdivcr_SPEC,
702 crate::common::RW,
703 >::from_register(self, 0)
704 }
705
706 #[doc = "System Clock (ICLK) Select"]
707 #[inline(always)]
708 pub fn ick(
709 self,
710 ) -> crate::common::RegisterField<
711 24,
712 0x7,
713 1,
714 0,
715 sckdivcr::Ick,
716 sckdivcr::Ick,
717 Sckdivcr_SPEC,
718 crate::common::RW,
719 > {
720 crate::common::RegisterField::<
721 24,
722 0x7,
723 1,
724 0,
725 sckdivcr::Ick,
726 sckdivcr::Ick,
727 Sckdivcr_SPEC,
728 crate::common::RW,
729 >::from_register(self, 0)
730 }
731}
732impl ::core::default::Default for Sckdivcr {
733 #[inline(always)]
734 fn default() -> Sckdivcr {
735 <crate::RegValueT<Sckdivcr_SPEC> as RegisterValue<_>>::new(67109892)
736 }
737}
738pub mod sckdivcr {
739
740 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
741 pub struct Pckd_SPEC;
742 pub type Pckd = crate::EnumBitfieldStruct<u8, Pckd_SPEC>;
743 impl Pckd {
744 #[doc = "x 1/1"]
745 pub const _000: Self = Self::new(0);
746
747 #[doc = "x 1/2"]
748 pub const _001: Self = Self::new(1);
749
750 #[doc = "x 1/4"]
751 pub const _010: Self = Self::new(2);
752
753 #[doc = "x 1/8"]
754 pub const _011: Self = Self::new(3);
755
756 #[doc = "x 1/16"]
757 pub const _100: Self = Self::new(4);
758
759 #[doc = "x 1/32"]
760 pub const _101: Self = Self::new(5);
761
762 #[doc = "x 1/64"]
763 pub const _110: Self = Self::new(6);
764 }
765 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
766 pub struct Pckb_SPEC;
767 pub type Pckb = crate::EnumBitfieldStruct<u8, Pckb_SPEC>;
768 impl Pckb {
769 #[doc = "x 1/1"]
770 pub const _000: Self = Self::new(0);
771
772 #[doc = "x 1/2"]
773 pub const _001: Self = Self::new(1);
774
775 #[doc = "x 1/4"]
776 pub const _010: Self = Self::new(2);
777
778 #[doc = "x 1/8"]
779 pub const _011: Self = Self::new(3);
780
781 #[doc = "x 1/16"]
782 pub const _100: Self = Self::new(4);
783
784 #[doc = "x 1/32"]
785 pub const _101: Self = Self::new(5);
786
787 #[doc = "x 1/64"]
788 pub const _110: Self = Self::new(6);
789 }
790 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
791 pub struct Ick_SPEC;
792 pub type Ick = crate::EnumBitfieldStruct<u8, Ick_SPEC>;
793 impl Ick {
794 #[doc = "x 1/1"]
795 pub const _000: Self = Self::new(0);
796
797 #[doc = "x 1/2"]
798 pub const _001: Self = Self::new(1);
799
800 #[doc = "x 1/4"]
801 pub const _010: Self = Self::new(2);
802
803 #[doc = "x 1/8"]
804 pub const _011: Self = Self::new(3);
805
806 #[doc = "x 1/16"]
807 pub const _100: Self = Self::new(4);
808
809 #[doc = "x 1/32"]
810 pub const _101: Self = Self::new(5);
811
812 #[doc = "x 1/64"]
813 pub const _110: Self = Self::new(6);
814 }
815}
816#[doc(hidden)]
817#[derive(Copy, Clone, Eq, PartialEq)]
818pub struct Sckscr_SPEC;
819impl crate::sealed::RegSpec for Sckscr_SPEC {
820 type DataType = u8;
821}
822
823#[doc = "System Clock Source Control Register"]
824pub type Sckscr = crate::RegValueT<Sckscr_SPEC>;
825
826impl Sckscr {
827 #[doc = "Clock Source Select"]
828 #[inline(always)]
829 pub fn cksel(
830 self,
831 ) -> crate::common::RegisterField<
832 0,
833 0x7,
834 1,
835 0,
836 sckscr::Cksel,
837 sckscr::Cksel,
838 Sckscr_SPEC,
839 crate::common::RW,
840 > {
841 crate::common::RegisterField::<
842 0,
843 0x7,
844 1,
845 0,
846 sckscr::Cksel,
847 sckscr::Cksel,
848 Sckscr_SPEC,
849 crate::common::RW,
850 >::from_register(self, 0)
851 }
852}
853impl ::core::default::Default for Sckscr {
854 #[inline(always)]
855 fn default() -> Sckscr {
856 <crate::RegValueT<Sckscr_SPEC> as RegisterValue<_>>::new(1)
857 }
858}
859pub mod sckscr {
860
861 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
862 pub struct Cksel_SPEC;
863 pub type Cksel = crate::EnumBitfieldStruct<u8, Cksel_SPEC>;
864 impl Cksel {
865 #[doc = "HOCO"]
866 pub const _000: Self = Self::new(0);
867
868 #[doc = "MOCO"]
869 pub const _001: Self = Self::new(1);
870
871 #[doc = "LOCO"]
872 pub const _010: Self = Self::new(2);
873
874 #[doc = "Main clock oscillator (MOSC)"]
875 pub const _011: Self = Self::new(3);
876
877 #[doc = "Sub-clock oscillator (SOSC)"]
878 pub const _100: Self = Self::new(4);
879
880 #[doc = "Setting prohibited"]
881 pub const _101: Self = Self::new(5);
882
883 #[doc = "Setting prohibited"]
884 pub const _110: Self = Self::new(6);
885
886 #[doc = "Setting prohibited"]
887 pub const _111: Self = Self::new(7);
888 }
889}
890#[doc(hidden)]
891#[derive(Copy, Clone, Eq, PartialEq)]
892pub struct Memwait_SPEC;
893impl crate::sealed::RegSpec for Memwait_SPEC {
894 type DataType = u8;
895}
896
897#[doc = "Memory Wait Cycle Control Register for Code Flash"]
898pub type Memwait = crate::RegValueT<Memwait_SPEC>;
899
900impl Memwait {
901 #[doc = "Memory Wait Cycle Select for Code Flash"]
902 #[inline(always)]
903 pub fn memwait(
904 self,
905 ) -> crate::common::RegisterField<
906 0,
907 0x1,
908 1,
909 0,
910 memwait::Memwait,
911 memwait::Memwait,
912 Memwait_SPEC,
913 crate::common::RW,
914 > {
915 crate::common::RegisterField::<
916 0,
917 0x1,
918 1,
919 0,
920 memwait::Memwait,
921 memwait::Memwait,
922 Memwait_SPEC,
923 crate::common::RW,
924 >::from_register(self, 0)
925 }
926}
927impl ::core::default::Default for Memwait {
928 #[inline(always)]
929 fn default() -> Memwait {
930 <crate::RegValueT<Memwait_SPEC> as RegisterValue<_>>::new(0)
931 }
932}
933pub mod memwait {
934
935 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
936 pub struct Memwait_SPEC;
937 pub type Memwait = crate::EnumBitfieldStruct<u8, Memwait_SPEC>;
938 impl Memwait {
939 #[doc = "No wait"]
940 pub const _0: Self = Self::new(0);
941
942 #[doc = "Wait"]
943 pub const _1: Self = Self::new(1);
944 }
945}
946#[doc(hidden)]
947#[derive(Copy, Clone, Eq, PartialEq)]
948pub struct Mosccr_SPEC;
949impl crate::sealed::RegSpec for Mosccr_SPEC {
950 type DataType = u8;
951}
952
953#[doc = "Main Clock Oscillator Control Register"]
954pub type Mosccr = crate::RegValueT<Mosccr_SPEC>;
955
956impl Mosccr {
957 #[doc = "Main Clock Oscillator Stop"]
958 #[inline(always)]
959 pub fn mostp(
960 self,
961 ) -> crate::common::RegisterField<
962 0,
963 0x1,
964 1,
965 0,
966 mosccr::Mostp,
967 mosccr::Mostp,
968 Mosccr_SPEC,
969 crate::common::RW,
970 > {
971 crate::common::RegisterField::<
972 0,
973 0x1,
974 1,
975 0,
976 mosccr::Mostp,
977 mosccr::Mostp,
978 Mosccr_SPEC,
979 crate::common::RW,
980 >::from_register(self, 0)
981 }
982}
983impl ::core::default::Default for Mosccr {
984 #[inline(always)]
985 fn default() -> Mosccr {
986 <crate::RegValueT<Mosccr_SPEC> as RegisterValue<_>>::new(1)
987 }
988}
989pub mod mosccr {
990
991 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
992 pub struct Mostp_SPEC;
993 pub type Mostp = crate::EnumBitfieldStruct<u8, Mostp_SPEC>;
994 impl Mostp {
995 #[doc = "Operate the main clock oscillator"]
996 pub const _0: Self = Self::new(0);
997
998 #[doc = "Stop the main clock oscillator"]
999 pub const _1: Self = Self::new(1);
1000 }
1001}
1002#[doc(hidden)]
1003#[derive(Copy, Clone, Eq, PartialEq)]
1004pub struct Hococr_SPEC;
1005impl crate::sealed::RegSpec for Hococr_SPEC {
1006 type DataType = u8;
1007}
1008
1009#[doc = "High-Speed On-Chip Oscillator Control Register"]
1010pub type Hococr = crate::RegValueT<Hococr_SPEC>;
1011
1012impl Hococr {
1013 #[doc = "HOCO Stop"]
1014 #[inline(always)]
1015 pub fn hcstp(
1016 self,
1017 ) -> crate::common::RegisterField<
1018 0,
1019 0x1,
1020 1,
1021 0,
1022 hococr::Hcstp,
1023 hococr::Hcstp,
1024 Hococr_SPEC,
1025 crate::common::RW,
1026 > {
1027 crate::common::RegisterField::<
1028 0,
1029 0x1,
1030 1,
1031 0,
1032 hococr::Hcstp,
1033 hococr::Hcstp,
1034 Hococr_SPEC,
1035 crate::common::RW,
1036 >::from_register(self, 0)
1037 }
1038}
1039impl ::core::default::Default for Hococr {
1040 #[inline(always)]
1041 fn default() -> Hococr {
1042 <crate::RegValueT<Hococr_SPEC> as RegisterValue<_>>::new(0)
1043 }
1044}
1045pub mod hococr {
1046
1047 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1048 pub struct Hcstp_SPEC;
1049 pub type Hcstp = crate::EnumBitfieldStruct<u8, Hcstp_SPEC>;
1050 impl Hcstp {
1051 #[doc = "Operate the HOCO clock"]
1052 pub const _0: Self = Self::new(0);
1053
1054 #[doc = "Stop the HOCO clock"]
1055 pub const _1: Self = Self::new(1);
1056 }
1057}
1058#[doc(hidden)]
1059#[derive(Copy, Clone, Eq, PartialEq)]
1060pub struct Mococr_SPEC;
1061impl crate::sealed::RegSpec for Mococr_SPEC {
1062 type DataType = u8;
1063}
1064
1065#[doc = "Middle-Speed On-Chip Oscillator Control Register"]
1066pub type Mococr = crate::RegValueT<Mococr_SPEC>;
1067
1068impl Mococr {
1069 #[doc = "MOCO Stop"]
1070 #[inline(always)]
1071 pub fn mcstp(
1072 self,
1073 ) -> crate::common::RegisterField<
1074 0,
1075 0x1,
1076 1,
1077 0,
1078 mococr::Mcstp,
1079 mococr::Mcstp,
1080 Mococr_SPEC,
1081 crate::common::RW,
1082 > {
1083 crate::common::RegisterField::<
1084 0,
1085 0x1,
1086 1,
1087 0,
1088 mococr::Mcstp,
1089 mococr::Mcstp,
1090 Mococr_SPEC,
1091 crate::common::RW,
1092 >::from_register(self, 0)
1093 }
1094}
1095impl ::core::default::Default for Mococr {
1096 #[inline(always)]
1097 fn default() -> Mococr {
1098 <crate::RegValueT<Mococr_SPEC> as RegisterValue<_>>::new(0)
1099 }
1100}
1101pub mod mococr {
1102
1103 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1104 pub struct Mcstp_SPEC;
1105 pub type Mcstp = crate::EnumBitfieldStruct<u8, Mcstp_SPEC>;
1106 impl Mcstp {
1107 #[doc = "MOCO clock is operating"]
1108 pub const _0: Self = Self::new(0);
1109
1110 #[doc = "MOCO clock is stopped"]
1111 pub const _1: Self = Self::new(1);
1112 }
1113}
1114#[doc(hidden)]
1115#[derive(Copy, Clone, Eq, PartialEq)]
1116pub struct Oscsf_SPEC;
1117impl crate::sealed::RegSpec for Oscsf_SPEC {
1118 type DataType = u8;
1119}
1120
1121#[doc = "Oscillation Stabilization Flag Register"]
1122pub type Oscsf = crate::RegValueT<Oscsf_SPEC>;
1123
1124impl Oscsf {
1125 #[doc = "HOCO Clock Oscillation Stabilization Flag"]
1126 #[inline(always)]
1127 pub fn hocosf(
1128 self,
1129 ) -> crate::common::RegisterField<
1130 0,
1131 0x1,
1132 1,
1133 0,
1134 oscsf::Hocosf,
1135 oscsf::Hocosf,
1136 Oscsf_SPEC,
1137 crate::common::R,
1138 > {
1139 crate::common::RegisterField::<
1140 0,
1141 0x1,
1142 1,
1143 0,
1144 oscsf::Hocosf,
1145 oscsf::Hocosf,
1146 Oscsf_SPEC,
1147 crate::common::R,
1148 >::from_register(self, 0)
1149 }
1150
1151 #[doc = "Main Clock Oscillation Stabilization Flag"]
1152 #[inline(always)]
1153 pub fn moscsf(
1154 self,
1155 ) -> crate::common::RegisterField<
1156 3,
1157 0x1,
1158 1,
1159 0,
1160 oscsf::Moscsf,
1161 oscsf::Moscsf,
1162 Oscsf_SPEC,
1163 crate::common::R,
1164 > {
1165 crate::common::RegisterField::<
1166 3,
1167 0x1,
1168 1,
1169 0,
1170 oscsf::Moscsf,
1171 oscsf::Moscsf,
1172 Oscsf_SPEC,
1173 crate::common::R,
1174 >::from_register(self, 0)
1175 }
1176}
1177impl ::core::default::Default for Oscsf {
1178 #[inline(always)]
1179 fn default() -> Oscsf {
1180 <crate::RegValueT<Oscsf_SPEC> as RegisterValue<_>>::new(0)
1181 }
1182}
1183pub mod oscsf {
1184
1185 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1186 pub struct Hocosf_SPEC;
1187 pub type Hocosf = crate::EnumBitfieldStruct<u8, Hocosf_SPEC>;
1188 impl Hocosf {
1189 #[doc = "The HOCO clock is stopped or is not yet stable"]
1190 pub const _0: Self = Self::new(0);
1191
1192 #[doc = "The HOCO clock is stable, so is available for use as the system clock"]
1193 pub const _1: Self = Self::new(1);
1194 }
1195 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1196 pub struct Moscsf_SPEC;
1197 pub type Moscsf = crate::EnumBitfieldStruct<u8, Moscsf_SPEC>;
1198 impl Moscsf {
1199 #[doc = "The main clock oscillator is stopped (MOSTP = 1) or is not yet stable"]
1200 pub const _0: Self = Self::new(0);
1201
1202 #[doc = "The main clock oscillator is stable, so is available for use as the system clock"]
1203 pub const _1: Self = Self::new(1);
1204 }
1205}
1206#[doc(hidden)]
1207#[derive(Copy, Clone, Eq, PartialEq)]
1208pub struct Ckocr_SPEC;
1209impl crate::sealed::RegSpec for Ckocr_SPEC {
1210 type DataType = u8;
1211}
1212
1213#[doc = "Clock Out Control Register"]
1214pub type Ckocr = crate::RegValueT<Ckocr_SPEC>;
1215
1216impl Ckocr {
1217 #[doc = "Clock Out Source Select"]
1218 #[inline(always)]
1219 pub fn ckosel(
1220 self,
1221 ) -> crate::common::RegisterField<
1222 0,
1223 0x7,
1224 1,
1225 0,
1226 ckocr::Ckosel,
1227 ckocr::Ckosel,
1228 Ckocr_SPEC,
1229 crate::common::RW,
1230 > {
1231 crate::common::RegisterField::<
1232 0,
1233 0x7,
1234 1,
1235 0,
1236 ckocr::Ckosel,
1237 ckocr::Ckosel,
1238 Ckocr_SPEC,
1239 crate::common::RW,
1240 >::from_register(self, 0)
1241 }
1242
1243 #[doc = "Clock Output Frequency Division Ratio"]
1244 #[inline(always)]
1245 pub fn ckodiv(
1246 self,
1247 ) -> crate::common::RegisterField<
1248 4,
1249 0x7,
1250 1,
1251 0,
1252 ckocr::Ckodiv,
1253 ckocr::Ckodiv,
1254 Ckocr_SPEC,
1255 crate::common::RW,
1256 > {
1257 crate::common::RegisterField::<
1258 4,
1259 0x7,
1260 1,
1261 0,
1262 ckocr::Ckodiv,
1263 ckocr::Ckodiv,
1264 Ckocr_SPEC,
1265 crate::common::RW,
1266 >::from_register(self, 0)
1267 }
1268
1269 #[doc = "Clock Out Enable"]
1270 #[inline(always)]
1271 pub fn ckoen(
1272 self,
1273 ) -> crate::common::RegisterField<
1274 7,
1275 0x1,
1276 1,
1277 0,
1278 ckocr::Ckoen,
1279 ckocr::Ckoen,
1280 Ckocr_SPEC,
1281 crate::common::RW,
1282 > {
1283 crate::common::RegisterField::<
1284 7,
1285 0x1,
1286 1,
1287 0,
1288 ckocr::Ckoen,
1289 ckocr::Ckoen,
1290 Ckocr_SPEC,
1291 crate::common::RW,
1292 >::from_register(self, 0)
1293 }
1294}
1295impl ::core::default::Default for Ckocr {
1296 #[inline(always)]
1297 fn default() -> Ckocr {
1298 <crate::RegValueT<Ckocr_SPEC> as RegisterValue<_>>::new(0)
1299 }
1300}
1301pub mod ckocr {
1302
1303 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1304 pub struct Ckosel_SPEC;
1305 pub type Ckosel = crate::EnumBitfieldStruct<u8, Ckosel_SPEC>;
1306 impl Ckosel {
1307 #[doc = "HOCO (value after reset)"]
1308 pub const _000: Self = Self::new(0);
1309
1310 #[doc = "MOCO"]
1311 pub const _001: Self = Self::new(1);
1312
1313 #[doc = "LOCO"]
1314 pub const _010: Self = Self::new(2);
1315
1316 #[doc = "MOSC"]
1317 pub const _011: Self = Self::new(3);
1318
1319 #[doc = "SOSC"]
1320 pub const _100: Self = Self::new(4);
1321
1322 #[doc = "Setting prohibited"]
1323 pub const _101: Self = Self::new(5);
1324 }
1325 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1326 pub struct Ckodiv_SPEC;
1327 pub type Ckodiv = crate::EnumBitfieldStruct<u8, Ckodiv_SPEC>;
1328 impl Ckodiv {
1329 #[doc = "x 1/1"]
1330 pub const _000: Self = Self::new(0);
1331
1332 #[doc = "x 1/2"]
1333 pub const _001: Self = Self::new(1);
1334
1335 #[doc = "x 1/4"]
1336 pub const _010: Self = Self::new(2);
1337
1338 #[doc = "x 1/8"]
1339 pub const _011: Self = Self::new(3);
1340
1341 #[doc = "x 1/16"]
1342 pub const _100: Self = Self::new(4);
1343
1344 #[doc = "x 1/32"]
1345 pub const _101: Self = Self::new(5);
1346
1347 #[doc = "x 1/64"]
1348 pub const _110: Self = Self::new(6);
1349
1350 #[doc = "x 1/128"]
1351 pub const _111: Self = Self::new(7);
1352 }
1353 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1354 pub struct Ckoen_SPEC;
1355 pub type Ckoen = crate::EnumBitfieldStruct<u8, Ckoen_SPEC>;
1356 impl Ckoen {
1357 #[doc = "Disable clock out"]
1358 pub const _0: Self = Self::new(0);
1359
1360 #[doc = "Enable clock out"]
1361 pub const _1: Self = Self::new(1);
1362 }
1363}
1364#[doc(hidden)]
1365#[derive(Copy, Clone, Eq, PartialEq)]
1366pub struct Ostdcr_SPEC;
1367impl crate::sealed::RegSpec for Ostdcr_SPEC {
1368 type DataType = u8;
1369}
1370
1371#[doc = "Oscillation Stop Detection Control Register"]
1372pub type Ostdcr = crate::RegValueT<Ostdcr_SPEC>;
1373
1374impl Ostdcr {
1375 #[doc = "Oscillation Stop Detection Interrupt Enable"]
1376 #[inline(always)]
1377 pub fn ostdie(
1378 self,
1379 ) -> crate::common::RegisterField<
1380 0,
1381 0x1,
1382 1,
1383 0,
1384 ostdcr::Ostdie,
1385 ostdcr::Ostdie,
1386 Ostdcr_SPEC,
1387 crate::common::RW,
1388 > {
1389 crate::common::RegisterField::<
1390 0,
1391 0x1,
1392 1,
1393 0,
1394 ostdcr::Ostdie,
1395 ostdcr::Ostdie,
1396 Ostdcr_SPEC,
1397 crate::common::RW,
1398 >::from_register(self, 0)
1399 }
1400
1401 #[doc = "Oscillation Stop Detection Function Enable"]
1402 #[inline(always)]
1403 pub fn ostde(
1404 self,
1405 ) -> crate::common::RegisterField<
1406 7,
1407 0x1,
1408 1,
1409 0,
1410 ostdcr::Ostde,
1411 ostdcr::Ostde,
1412 Ostdcr_SPEC,
1413 crate::common::RW,
1414 > {
1415 crate::common::RegisterField::<
1416 7,
1417 0x1,
1418 1,
1419 0,
1420 ostdcr::Ostde,
1421 ostdcr::Ostde,
1422 Ostdcr_SPEC,
1423 crate::common::RW,
1424 >::from_register(self, 0)
1425 }
1426}
1427impl ::core::default::Default for Ostdcr {
1428 #[inline(always)]
1429 fn default() -> Ostdcr {
1430 <crate::RegValueT<Ostdcr_SPEC> as RegisterValue<_>>::new(0)
1431 }
1432}
1433pub mod ostdcr {
1434
1435 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1436 pub struct Ostdie_SPEC;
1437 pub type Ostdie = crate::EnumBitfieldStruct<u8, Ostdie_SPEC>;
1438 impl Ostdie {
1439 #[doc = "Disable oscillation stop detection interrupt (do not notify the POEG)"]
1440 pub const _0: Self = Self::new(0);
1441
1442 #[doc = "Enable oscillation stop detection interrupt (notify the POEG)"]
1443 pub const _1: Self = Self::new(1);
1444 }
1445 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1446 pub struct Ostde_SPEC;
1447 pub type Ostde = crate::EnumBitfieldStruct<u8, Ostde_SPEC>;
1448 impl Ostde {
1449 #[doc = "Disable oscillation stop detection function"]
1450 pub const _0: Self = Self::new(0);
1451
1452 #[doc = "Enable oscillation stop detection function"]
1453 pub const _1: Self = Self::new(1);
1454 }
1455}
1456#[doc(hidden)]
1457#[derive(Copy, Clone, Eq, PartialEq)]
1458pub struct Ostdsr_SPEC;
1459impl crate::sealed::RegSpec for Ostdsr_SPEC {
1460 type DataType = u8;
1461}
1462
1463#[doc = "Oscillation Stop Detection Status Register"]
1464pub type Ostdsr = crate::RegValueT<Ostdsr_SPEC>;
1465
1466impl Ostdsr {
1467 #[doc = "Oscillation Stop Detection Flag"]
1468 #[inline(always)]
1469 pub fn ostdf(
1470 self,
1471 ) -> crate::common::RegisterField<
1472 0,
1473 0x1,
1474 1,
1475 0,
1476 ostdsr::Ostdf,
1477 ostdsr::Ostdf,
1478 Ostdsr_SPEC,
1479 crate::common::RW,
1480 > {
1481 crate::common::RegisterField::<
1482 0,
1483 0x1,
1484 1,
1485 0,
1486 ostdsr::Ostdf,
1487 ostdsr::Ostdf,
1488 Ostdsr_SPEC,
1489 crate::common::RW,
1490 >::from_register(self, 0)
1491 }
1492}
1493impl ::core::default::Default for Ostdsr {
1494 #[inline(always)]
1495 fn default() -> Ostdsr {
1496 <crate::RegValueT<Ostdsr_SPEC> as RegisterValue<_>>::new(0)
1497 }
1498}
1499pub mod ostdsr {
1500
1501 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1502 pub struct Ostdf_SPEC;
1503 pub type Ostdf = crate::EnumBitfieldStruct<u8, Ostdf_SPEC>;
1504 impl Ostdf {
1505 #[doc = "Main clock oscillation stop not detected"]
1506 pub const _0: Self = Self::new(0);
1507
1508 #[doc = "Main clock oscillation stop detected"]
1509 pub const _1: Self = Self::new(1);
1510 }
1511}
1512#[doc(hidden)]
1513#[derive(Copy, Clone, Eq, PartialEq)]
1514pub struct Lpopt_SPEC;
1515impl crate::sealed::RegSpec for Lpopt_SPEC {
1516 type DataType = u8;
1517}
1518
1519#[doc = "Lower Power Operation Control Register"]
1520pub type Lpopt = crate::RegValueT<Lpopt_SPEC>;
1521
1522impl Lpopt {
1523 #[doc = "MPU Clock Disable Control"]
1524 #[inline(always)]
1525 pub fn mpudis(
1526 self,
1527 ) -> crate::common::RegisterField<
1528 0,
1529 0x1,
1530 1,
1531 0,
1532 lpopt::Mpudis,
1533 lpopt::Mpudis,
1534 Lpopt_SPEC,
1535 crate::common::RW,
1536 > {
1537 crate::common::RegisterField::<
1538 0,
1539 0x1,
1540 1,
1541 0,
1542 lpopt::Mpudis,
1543 lpopt::Mpudis,
1544 Lpopt_SPEC,
1545 crate::common::RW,
1546 >::from_register(self, 0)
1547 }
1548
1549 #[doc = "Debug Clock Disable Control"]
1550 #[inline(always)]
1551 pub fn dclkdis(
1552 self,
1553 ) -> crate::common::RegisterField<
1554 1,
1555 0x3,
1556 1,
1557 0,
1558 lpopt::Dclkdis,
1559 lpopt::Dclkdis,
1560 Lpopt_SPEC,
1561 crate::common::RW,
1562 > {
1563 crate::common::RegisterField::<
1564 1,
1565 0x3,
1566 1,
1567 0,
1568 lpopt::Dclkdis,
1569 lpopt::Dclkdis,
1570 Lpopt_SPEC,
1571 crate::common::RW,
1572 >::from_register(self, 0)
1573 }
1574
1575 #[doc = "BPF Clock Disable Control"]
1576 #[inline(always)]
1577 pub fn bpfclkdis(
1578 self,
1579 ) -> crate::common::RegisterField<
1580 3,
1581 0x1,
1582 1,
1583 0,
1584 lpopt::Bpfclkdis,
1585 lpopt::Bpfclkdis,
1586 Lpopt_SPEC,
1587 crate::common::RW,
1588 > {
1589 crate::common::RegisterField::<
1590 3,
1591 0x1,
1592 1,
1593 0,
1594 lpopt::Bpfclkdis,
1595 lpopt::Bpfclkdis,
1596 Lpopt_SPEC,
1597 crate::common::RW,
1598 >::from_register(self, 0)
1599 }
1600
1601 #[doc = "Lower Power Operation Enable"]
1602 #[inline(always)]
1603 pub fn lpopten(
1604 self,
1605 ) -> crate::common::RegisterField<
1606 7,
1607 0x1,
1608 1,
1609 0,
1610 lpopt::Lpopten,
1611 lpopt::Lpopten,
1612 Lpopt_SPEC,
1613 crate::common::RW,
1614 > {
1615 crate::common::RegisterField::<
1616 7,
1617 0x1,
1618 1,
1619 0,
1620 lpopt::Lpopten,
1621 lpopt::Lpopten,
1622 Lpopt_SPEC,
1623 crate::common::RW,
1624 >::from_register(self, 0)
1625 }
1626}
1627impl ::core::default::Default for Lpopt {
1628 #[inline(always)]
1629 fn default() -> Lpopt {
1630 <crate::RegValueT<Lpopt_SPEC> as RegisterValue<_>>::new(64)
1631 }
1632}
1633pub mod lpopt {
1634
1635 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1636 pub struct Mpudis_SPEC;
1637 pub type Mpudis = crate::EnumBitfieldStruct<u8, Mpudis_SPEC>;
1638 impl Mpudis {
1639 #[doc = "MPU operates as normal"]
1640 pub const _0: Self = Self::new(0);
1641
1642 #[doc = "MPU operate clock stops (MPU function disable)."]
1643 pub const _1: Self = Self::new(1);
1644 }
1645 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1646 pub struct Dclkdis_SPEC;
1647 pub type Dclkdis = crate::EnumBitfieldStruct<u8, Dclkdis_SPEC>;
1648 impl Dclkdis {
1649 #[doc = "Debug clock does not stop"]
1650 pub const _00: Self = Self::new(0);
1651 }
1652 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1653 pub struct Bpfclkdis_SPEC;
1654 pub type Bpfclkdis = crate::EnumBitfieldStruct<u8, Bpfclkdis_SPEC>;
1655 impl Bpfclkdis {
1656 #[doc = "Flash register R/W clock operates as normal"]
1657 pub const _0: Self = Self::new(0);
1658
1659 #[doc = "Flash register R/W clock stops."]
1660 pub const _1: Self = Self::new(1);
1661 }
1662 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1663 pub struct Lpopten_SPEC;
1664 pub type Lpopten = crate::EnumBitfieldStruct<u8, Lpopten_SPEC>;
1665 impl Lpopten {
1666 #[doc = "All lower power counter measure disable"]
1667 pub const _0: Self = Self::new(0);
1668
1669 #[doc = "All lower power counter measure enable"]
1670 pub const _1: Self = Self::new(1);
1671 }
1672}
1673#[doc(hidden)]
1674#[derive(Copy, Clone, Eq, PartialEq)]
1675pub struct Mocoutcr_SPEC;
1676impl crate::sealed::RegSpec for Mocoutcr_SPEC {
1677 type DataType = u8;
1678}
1679
1680#[doc = "MOCO User Trimming Control Register"]
1681pub type Mocoutcr = crate::RegValueT<Mocoutcr_SPEC>;
1682
1683impl Mocoutcr {
1684 #[doc = "MOCO User Trimming"]
1685 #[inline(always)]
1686 pub fn mocoutrm(
1687 self,
1688 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Mocoutcr_SPEC, crate::common::RW> {
1689 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Mocoutcr_SPEC,crate::common::RW>::from_register(self,0)
1690 }
1691}
1692impl ::core::default::Default for Mocoutcr {
1693 #[inline(always)]
1694 fn default() -> Mocoutcr {
1695 <crate::RegValueT<Mocoutcr_SPEC> as RegisterValue<_>>::new(0)
1696 }
1697}
1698
1699#[doc(hidden)]
1700#[derive(Copy, Clone, Eq, PartialEq)]
1701pub struct Hocoutcr_SPEC;
1702impl crate::sealed::RegSpec for Hocoutcr_SPEC {
1703 type DataType = u8;
1704}
1705
1706#[doc = "HOCO User Trimming Control Register"]
1707pub type Hocoutcr = crate::RegValueT<Hocoutcr_SPEC>;
1708
1709impl Hocoutcr {
1710 #[doc = "HOCO User Trimming"]
1711 #[inline(always)]
1712 pub fn hocoutrm(
1713 self,
1714 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Hocoutcr_SPEC, crate::common::RW> {
1715 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Hocoutcr_SPEC,crate::common::RW>::from_register(self,0)
1716 }
1717}
1718impl ::core::default::Default for Hocoutcr {
1719 #[inline(always)]
1720 fn default() -> Hocoutcr {
1721 <crate::RegValueT<Hocoutcr_SPEC> as RegisterValue<_>>::new(0)
1722 }
1723}
1724
1725#[doc(hidden)]
1726#[derive(Copy, Clone, Eq, PartialEq)]
1727pub struct Snzcr_SPEC;
1728impl crate::sealed::RegSpec for Snzcr_SPEC {
1729 type DataType = u8;
1730}
1731
1732#[doc = "Snooze Control Register"]
1733pub type Snzcr = crate::RegValueT<Snzcr_SPEC>;
1734
1735impl Snzcr {
1736 #[doc = "RXD0 Snooze Request Enable"]
1737 #[inline(always)]
1738 pub fn rxdreqen(
1739 self,
1740 ) -> crate::common::RegisterField<
1741 0,
1742 0x1,
1743 1,
1744 0,
1745 snzcr::Rxdreqen,
1746 snzcr::Rxdreqen,
1747 Snzcr_SPEC,
1748 crate::common::RW,
1749 > {
1750 crate::common::RegisterField::<
1751 0,
1752 0x1,
1753 1,
1754 0,
1755 snzcr::Rxdreqen,
1756 snzcr::Rxdreqen,
1757 Snzcr_SPEC,
1758 crate::common::RW,
1759 >::from_register(self, 0)
1760 }
1761
1762 #[doc = "DTC Enable in Snooze mode"]
1763 #[inline(always)]
1764 pub fn snzdtcen(
1765 self,
1766 ) -> crate::common::RegisterField<
1767 1,
1768 0x1,
1769 1,
1770 0,
1771 snzcr::Snzdtcen,
1772 snzcr::Snzdtcen,
1773 Snzcr_SPEC,
1774 crate::common::RW,
1775 > {
1776 crate::common::RegisterField::<
1777 1,
1778 0x1,
1779 1,
1780 0,
1781 snzcr::Snzdtcen,
1782 snzcr::Snzdtcen,
1783 Snzcr_SPEC,
1784 crate::common::RW,
1785 >::from_register(self, 0)
1786 }
1787
1788 #[doc = "Snooze mode Enable"]
1789 #[inline(always)]
1790 pub fn snze(
1791 self,
1792 ) -> crate::common::RegisterField<
1793 7,
1794 0x1,
1795 1,
1796 0,
1797 snzcr::Snze,
1798 snzcr::Snze,
1799 Snzcr_SPEC,
1800 crate::common::RW,
1801 > {
1802 crate::common::RegisterField::<
1803 7,
1804 0x1,
1805 1,
1806 0,
1807 snzcr::Snze,
1808 snzcr::Snze,
1809 Snzcr_SPEC,
1810 crate::common::RW,
1811 >::from_register(self, 0)
1812 }
1813}
1814impl ::core::default::Default for Snzcr {
1815 #[inline(always)]
1816 fn default() -> Snzcr {
1817 <crate::RegValueT<Snzcr_SPEC> as RegisterValue<_>>::new(0)
1818 }
1819}
1820pub mod snzcr {
1821
1822 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1823 pub struct Rxdreqen_SPEC;
1824 pub type Rxdreqen = crate::EnumBitfieldStruct<u8, Rxdreqen_SPEC>;
1825 impl Rxdreqen {
1826 #[doc = "Ignore RXD0 falling edge in Software Standby mode"]
1827 pub const _0: Self = Self::new(0);
1828
1829 #[doc = "Detect RXD0 falling edge in Software Standby mode"]
1830 pub const _1: Self = Self::new(1);
1831 }
1832 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1833 pub struct Snzdtcen_SPEC;
1834 pub type Snzdtcen = crate::EnumBitfieldStruct<u8, Snzdtcen_SPEC>;
1835 impl Snzdtcen {
1836 #[doc = "Disable DTC operation"]
1837 pub const _0: Self = Self::new(0);
1838
1839 #[doc = "Enable DTC operation"]
1840 pub const _1: Self = Self::new(1);
1841 }
1842 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1843 pub struct Snze_SPEC;
1844 pub type Snze = crate::EnumBitfieldStruct<u8, Snze_SPEC>;
1845 impl Snze {
1846 #[doc = "Disable Snooze mode"]
1847 pub const _0: Self = Self::new(0);
1848
1849 #[doc = "Enable Snooze mode"]
1850 pub const _1: Self = Self::new(1);
1851 }
1852}
1853#[doc(hidden)]
1854#[derive(Copy, Clone, Eq, PartialEq)]
1855pub struct Snzedcr0_SPEC;
1856impl crate::sealed::RegSpec for Snzedcr0_SPEC {
1857 type DataType = u8;
1858}
1859
1860#[doc = "Snooze End Control Register 0"]
1861pub type Snzedcr0 = crate::RegValueT<Snzedcr0_SPEC>;
1862
1863impl Snzedcr0 {
1864 #[doc = "AGT1 Underflow Snooze End Enable"]
1865 #[inline(always)]
1866 pub fn agtunfed(
1867 self,
1868 ) -> crate::common::RegisterField<
1869 0,
1870 0x1,
1871 1,
1872 0,
1873 snzedcr0::Agtunfed,
1874 snzedcr0::Agtunfed,
1875 Snzedcr0_SPEC,
1876 crate::common::RW,
1877 > {
1878 crate::common::RegisterField::<
1879 0,
1880 0x1,
1881 1,
1882 0,
1883 snzedcr0::Agtunfed,
1884 snzedcr0::Agtunfed,
1885 Snzedcr0_SPEC,
1886 crate::common::RW,
1887 >::from_register(self, 0)
1888 }
1889
1890 #[doc = "Last DTC Transmission Completion Snooze End Enable"]
1891 #[inline(always)]
1892 pub fn dtczred(
1893 self,
1894 ) -> crate::common::RegisterField<
1895 1,
1896 0x1,
1897 1,
1898 0,
1899 snzedcr0::Dtczred,
1900 snzedcr0::Dtczred,
1901 Snzedcr0_SPEC,
1902 crate::common::RW,
1903 > {
1904 crate::common::RegisterField::<
1905 1,
1906 0x1,
1907 1,
1908 0,
1909 snzedcr0::Dtczred,
1910 snzedcr0::Dtczred,
1911 Snzedcr0_SPEC,
1912 crate::common::RW,
1913 >::from_register(self, 0)
1914 }
1915
1916 #[doc = "Not Last DTC Transmission Completion Snooze End Enable"]
1917 #[inline(always)]
1918 pub fn dtcnzred(
1919 self,
1920 ) -> crate::common::RegisterField<
1921 2,
1922 0x1,
1923 1,
1924 0,
1925 snzedcr0::Dtcnzred,
1926 snzedcr0::Dtcnzred,
1927 Snzedcr0_SPEC,
1928 crate::common::RW,
1929 > {
1930 crate::common::RegisterField::<
1931 2,
1932 0x1,
1933 1,
1934 0,
1935 snzedcr0::Dtcnzred,
1936 snzedcr0::Dtcnzred,
1937 Snzedcr0_SPEC,
1938 crate::common::RW,
1939 >::from_register(self, 0)
1940 }
1941
1942 #[doc = "ADC12 Compare Match Snooze End Enable"]
1943 #[inline(always)]
1944 pub fn ad0mated(
1945 self,
1946 ) -> crate::common::RegisterField<
1947 3,
1948 0x1,
1949 1,
1950 0,
1951 snzedcr0::Ad0Mated,
1952 snzedcr0::Ad0Mated,
1953 Snzedcr0_SPEC,
1954 crate::common::RW,
1955 > {
1956 crate::common::RegisterField::<
1957 3,
1958 0x1,
1959 1,
1960 0,
1961 snzedcr0::Ad0Mated,
1962 snzedcr0::Ad0Mated,
1963 Snzedcr0_SPEC,
1964 crate::common::RW,
1965 >::from_register(self, 0)
1966 }
1967
1968 #[doc = "ADC12 Compare Mismatch Snooze End Enable"]
1969 #[inline(always)]
1970 pub fn ad0umted(
1971 self,
1972 ) -> crate::common::RegisterField<
1973 4,
1974 0x1,
1975 1,
1976 0,
1977 snzedcr0::Ad0Umted,
1978 snzedcr0::Ad0Umted,
1979 Snzedcr0_SPEC,
1980 crate::common::RW,
1981 > {
1982 crate::common::RegisterField::<
1983 4,
1984 0x1,
1985 1,
1986 0,
1987 snzedcr0::Ad0Umted,
1988 snzedcr0::Ad0Umted,
1989 Snzedcr0_SPEC,
1990 crate::common::RW,
1991 >::from_register(self, 0)
1992 }
1993
1994 #[doc = "SCI0 Address Mismatch Snooze End Enable"]
1995 #[inline(always)]
1996 pub fn sci0umted(
1997 self,
1998 ) -> crate::common::RegisterField<
1999 7,
2000 0x1,
2001 1,
2002 0,
2003 snzedcr0::Sci0Umted,
2004 snzedcr0::Sci0Umted,
2005 Snzedcr0_SPEC,
2006 crate::common::RW,
2007 > {
2008 crate::common::RegisterField::<
2009 7,
2010 0x1,
2011 1,
2012 0,
2013 snzedcr0::Sci0Umted,
2014 snzedcr0::Sci0Umted,
2015 Snzedcr0_SPEC,
2016 crate::common::RW,
2017 >::from_register(self, 0)
2018 }
2019}
2020impl ::core::default::Default for Snzedcr0 {
2021 #[inline(always)]
2022 fn default() -> Snzedcr0 {
2023 <crate::RegValueT<Snzedcr0_SPEC> as RegisterValue<_>>::new(0)
2024 }
2025}
2026pub mod snzedcr0 {
2027
2028 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2029 pub struct Agtunfed_SPEC;
2030 pub type Agtunfed = crate::EnumBitfieldStruct<u8, Agtunfed_SPEC>;
2031 impl Agtunfed {
2032 #[doc = "Disable the snooze end request"]
2033 pub const _0: Self = Self::new(0);
2034
2035 #[doc = "Enable the snooze end request"]
2036 pub const _1: Self = Self::new(1);
2037 }
2038 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2039 pub struct Dtczred_SPEC;
2040 pub type Dtczred = crate::EnumBitfieldStruct<u8, Dtczred_SPEC>;
2041 impl Dtczred {
2042 #[doc = "Disable the snooze end request"]
2043 pub const _0: Self = Self::new(0);
2044
2045 #[doc = "Enable the snooze end request"]
2046 pub const _1: Self = Self::new(1);
2047 }
2048 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2049 pub struct Dtcnzred_SPEC;
2050 pub type Dtcnzred = crate::EnumBitfieldStruct<u8, Dtcnzred_SPEC>;
2051 impl Dtcnzred {
2052 #[doc = "Disable the snooze end request"]
2053 pub const _0: Self = Self::new(0);
2054
2055 #[doc = "Enable the snooze end request"]
2056 pub const _1: Self = Self::new(1);
2057 }
2058 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2059 pub struct Ad0Mated_SPEC;
2060 pub type Ad0Mated = crate::EnumBitfieldStruct<u8, Ad0Mated_SPEC>;
2061 impl Ad0Mated {
2062 #[doc = "Disable the snooze end request"]
2063 pub const _0: Self = Self::new(0);
2064
2065 #[doc = "Enable the snooze end request"]
2066 pub const _1: Self = Self::new(1);
2067 }
2068 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2069 pub struct Ad0Umted_SPEC;
2070 pub type Ad0Umted = crate::EnumBitfieldStruct<u8, Ad0Umted_SPEC>;
2071 impl Ad0Umted {
2072 #[doc = "Disable the snooze end request"]
2073 pub const _0: Self = Self::new(0);
2074
2075 #[doc = "Enable the snooze end request"]
2076 pub const _1: Self = Self::new(1);
2077 }
2078 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2079 pub struct Sci0Umted_SPEC;
2080 pub type Sci0Umted = crate::EnumBitfieldStruct<u8, Sci0Umted_SPEC>;
2081 impl Sci0Umted {
2082 #[doc = "Disable the snooze end request"]
2083 pub const _0: Self = Self::new(0);
2084
2085 #[doc = "Enable the snooze end request"]
2086 pub const _1: Self = Self::new(1);
2087 }
2088}
2089#[doc(hidden)]
2090#[derive(Copy, Clone, Eq, PartialEq)]
2091pub struct Snzreqcr0_SPEC;
2092impl crate::sealed::RegSpec for Snzreqcr0_SPEC {
2093 type DataType = u32;
2094}
2095
2096#[doc = "Snooze Request Control Register 0"]
2097pub type Snzreqcr0 = crate::RegValueT<Snzreqcr0_SPEC>;
2098
2099impl Snzreqcr0 {
2100 #[doc = "Enable IRQ0 pin snooze request"]
2101 #[inline(always)]
2102 pub fn snzreqen0(
2103 self,
2104 ) -> crate::common::RegisterField<
2105 0,
2106 0x1,
2107 1,
2108 0,
2109 snzreqcr0::Snzreqen0,
2110 snzreqcr0::Snzreqen0,
2111 Snzreqcr0_SPEC,
2112 crate::common::RW,
2113 > {
2114 crate::common::RegisterField::<
2115 0,
2116 0x1,
2117 1,
2118 0,
2119 snzreqcr0::Snzreqen0,
2120 snzreqcr0::Snzreqen0,
2121 Snzreqcr0_SPEC,
2122 crate::common::RW,
2123 >::from_register(self, 0)
2124 }
2125
2126 #[doc = "Enable IRQ1 pin snooze request"]
2127 #[inline(always)]
2128 pub fn snzreqen1(
2129 self,
2130 ) -> crate::common::RegisterField<
2131 1,
2132 0x1,
2133 1,
2134 0,
2135 snzreqcr0::Snzreqen1,
2136 snzreqcr0::Snzreqen1,
2137 Snzreqcr0_SPEC,
2138 crate::common::RW,
2139 > {
2140 crate::common::RegisterField::<
2141 1,
2142 0x1,
2143 1,
2144 0,
2145 snzreqcr0::Snzreqen1,
2146 snzreqcr0::Snzreqen1,
2147 Snzreqcr0_SPEC,
2148 crate::common::RW,
2149 >::from_register(self, 0)
2150 }
2151
2152 #[doc = "Enable IRQ2 pin snooze request"]
2153 #[inline(always)]
2154 pub fn snzreqen2(
2155 self,
2156 ) -> crate::common::RegisterField<
2157 2,
2158 0x1,
2159 1,
2160 0,
2161 snzreqcr0::Snzreqen2,
2162 snzreqcr0::Snzreqen2,
2163 Snzreqcr0_SPEC,
2164 crate::common::RW,
2165 > {
2166 crate::common::RegisterField::<
2167 2,
2168 0x1,
2169 1,
2170 0,
2171 snzreqcr0::Snzreqen2,
2172 snzreqcr0::Snzreqen2,
2173 Snzreqcr0_SPEC,
2174 crate::common::RW,
2175 >::from_register(self, 0)
2176 }
2177
2178 #[doc = "Enable IRQ3 pin snooze request"]
2179 #[inline(always)]
2180 pub fn snzreqen3(
2181 self,
2182 ) -> crate::common::RegisterField<
2183 3,
2184 0x1,
2185 1,
2186 0,
2187 snzreqcr0::Snzreqen3,
2188 snzreqcr0::Snzreqen3,
2189 Snzreqcr0_SPEC,
2190 crate::common::RW,
2191 > {
2192 crate::common::RegisterField::<
2193 3,
2194 0x1,
2195 1,
2196 0,
2197 snzreqcr0::Snzreqen3,
2198 snzreqcr0::Snzreqen3,
2199 Snzreqcr0_SPEC,
2200 crate::common::RW,
2201 >::from_register(self, 0)
2202 }
2203
2204 #[doc = "Enable IRQ4 pin snooze request"]
2205 #[inline(always)]
2206 pub fn snzreqen4(
2207 self,
2208 ) -> crate::common::RegisterField<
2209 4,
2210 0x1,
2211 1,
2212 0,
2213 snzreqcr0::Snzreqen4,
2214 snzreqcr0::Snzreqen4,
2215 Snzreqcr0_SPEC,
2216 crate::common::RW,
2217 > {
2218 crate::common::RegisterField::<
2219 4,
2220 0x1,
2221 1,
2222 0,
2223 snzreqcr0::Snzreqen4,
2224 snzreqcr0::Snzreqen4,
2225 Snzreqcr0_SPEC,
2226 crate::common::RW,
2227 >::from_register(self, 0)
2228 }
2229
2230 #[doc = "Enable IRQ5 pin snooze request"]
2231 #[inline(always)]
2232 pub fn snzreqen5(
2233 self,
2234 ) -> crate::common::RegisterField<
2235 5,
2236 0x1,
2237 1,
2238 0,
2239 snzreqcr0::Snzreqen5,
2240 snzreqcr0::Snzreqen5,
2241 Snzreqcr0_SPEC,
2242 crate::common::RW,
2243 > {
2244 crate::common::RegisterField::<
2245 5,
2246 0x1,
2247 1,
2248 0,
2249 snzreqcr0::Snzreqen5,
2250 snzreqcr0::Snzreqen5,
2251 Snzreqcr0_SPEC,
2252 crate::common::RW,
2253 >::from_register(self, 0)
2254 }
2255
2256 #[doc = "Enable IRQ6 pin snooze request"]
2257 #[inline(always)]
2258 pub fn snzreqen6(
2259 self,
2260 ) -> crate::common::RegisterField<
2261 6,
2262 0x1,
2263 1,
2264 0,
2265 snzreqcr0::Snzreqen6,
2266 snzreqcr0::Snzreqen6,
2267 Snzreqcr0_SPEC,
2268 crate::common::RW,
2269 > {
2270 crate::common::RegisterField::<
2271 6,
2272 0x1,
2273 1,
2274 0,
2275 snzreqcr0::Snzreqen6,
2276 snzreqcr0::Snzreqen6,
2277 Snzreqcr0_SPEC,
2278 crate::common::RW,
2279 >::from_register(self, 0)
2280 }
2281
2282 #[doc = "Enable IRQ7 pin snooze request"]
2283 #[inline(always)]
2284 pub fn snzreqen7(
2285 self,
2286 ) -> crate::common::RegisterField<
2287 7,
2288 0x1,
2289 1,
2290 0,
2291 snzreqcr0::Snzreqen7,
2292 snzreqcr0::Snzreqen7,
2293 Snzreqcr0_SPEC,
2294 crate::common::RW,
2295 > {
2296 crate::common::RegisterField::<
2297 7,
2298 0x1,
2299 1,
2300 0,
2301 snzreqcr0::Snzreqen7,
2302 snzreqcr0::Snzreqen7,
2303 Snzreqcr0_SPEC,
2304 crate::common::RW,
2305 >::from_register(self, 0)
2306 }
2307
2308 #[doc = "Enable KEY_INTKR snooze request"]
2309 #[inline(always)]
2310 pub fn snzreqen17(
2311 self,
2312 ) -> crate::common::RegisterField<
2313 17,
2314 0x1,
2315 1,
2316 0,
2317 snzreqcr0::Snzreqen17,
2318 snzreqcr0::Snzreqen17,
2319 Snzreqcr0_SPEC,
2320 crate::common::RW,
2321 > {
2322 crate::common::RegisterField::<
2323 17,
2324 0x1,
2325 1,
2326 0,
2327 snzreqcr0::Snzreqen17,
2328 snzreqcr0::Snzreqen17,
2329 Snzreqcr0_SPEC,
2330 crate::common::RW,
2331 >::from_register(self, 0)
2332 }
2333
2334 #[doc = "Enable ACMPLP snooze request"]
2335 #[inline(always)]
2336 pub fn snzreqen23(
2337 self,
2338 ) -> crate::common::RegisterField<
2339 23,
2340 0x1,
2341 1,
2342 0,
2343 snzreqcr0::Snzreqen23,
2344 snzreqcr0::Snzreqen23,
2345 Snzreqcr0_SPEC,
2346 crate::common::RW,
2347 > {
2348 crate::common::RegisterField::<
2349 23,
2350 0x1,
2351 1,
2352 0,
2353 snzreqcr0::Snzreqen23,
2354 snzreqcr0::Snzreqen23,
2355 Snzreqcr0_SPEC,
2356 crate::common::RW,
2357 >::from_register(self, 0)
2358 }
2359
2360 #[doc = "Enable RTC alarm snooze request"]
2361 #[inline(always)]
2362 pub fn snzreqen24(
2363 self,
2364 ) -> crate::common::RegisterField<
2365 24,
2366 0x1,
2367 1,
2368 0,
2369 snzreqcr0::Snzreqen24,
2370 snzreqcr0::Snzreqen24,
2371 Snzreqcr0_SPEC,
2372 crate::common::RW,
2373 > {
2374 crate::common::RegisterField::<
2375 24,
2376 0x1,
2377 1,
2378 0,
2379 snzreqcr0::Snzreqen24,
2380 snzreqcr0::Snzreqen24,
2381 Snzreqcr0_SPEC,
2382 crate::common::RW,
2383 >::from_register(self, 0)
2384 }
2385
2386 #[doc = "Enable RTC period snooze request"]
2387 #[inline(always)]
2388 pub fn snzreqen25(
2389 self,
2390 ) -> crate::common::RegisterField<
2391 25,
2392 0x1,
2393 1,
2394 0,
2395 snzreqcr0::Snzreqen25,
2396 snzreqcr0::Snzreqen25,
2397 Snzreqcr0_SPEC,
2398 crate::common::RW,
2399 > {
2400 crate::common::RegisterField::<
2401 25,
2402 0x1,
2403 1,
2404 0,
2405 snzreqcr0::Snzreqen25,
2406 snzreqcr0::Snzreqen25,
2407 Snzreqcr0_SPEC,
2408 crate::common::RW,
2409 >::from_register(self, 0)
2410 }
2411
2412 #[doc = "Enable AGT1 underflow snooze request"]
2413 #[inline(always)]
2414 pub fn snzreqen28(
2415 self,
2416 ) -> crate::common::RegisterField<
2417 28,
2418 0x1,
2419 1,
2420 0,
2421 snzreqcr0::Snzreqen28,
2422 snzreqcr0::Snzreqen28,
2423 Snzreqcr0_SPEC,
2424 crate::common::RW,
2425 > {
2426 crate::common::RegisterField::<
2427 28,
2428 0x1,
2429 1,
2430 0,
2431 snzreqcr0::Snzreqen28,
2432 snzreqcr0::Snzreqen28,
2433 Snzreqcr0_SPEC,
2434 crate::common::RW,
2435 >::from_register(self, 0)
2436 }
2437
2438 #[doc = "Enable AGT1 compare match A snooze request"]
2439 #[inline(always)]
2440 pub fn snzreqen29(
2441 self,
2442 ) -> crate::common::RegisterField<
2443 29,
2444 0x1,
2445 1,
2446 0,
2447 snzreqcr0::Snzreqen29,
2448 snzreqcr0::Snzreqen29,
2449 Snzreqcr0_SPEC,
2450 crate::common::RW,
2451 > {
2452 crate::common::RegisterField::<
2453 29,
2454 0x1,
2455 1,
2456 0,
2457 snzreqcr0::Snzreqen29,
2458 snzreqcr0::Snzreqen29,
2459 Snzreqcr0_SPEC,
2460 crate::common::RW,
2461 >::from_register(self, 0)
2462 }
2463
2464 #[doc = "Enable AGT1 compare match B snooze request"]
2465 #[inline(always)]
2466 pub fn snzreqen30(
2467 self,
2468 ) -> crate::common::RegisterField<
2469 30,
2470 0x1,
2471 1,
2472 0,
2473 snzreqcr0::Snzreqen30,
2474 snzreqcr0::Snzreqen30,
2475 Snzreqcr0_SPEC,
2476 crate::common::RW,
2477 > {
2478 crate::common::RegisterField::<
2479 30,
2480 0x1,
2481 1,
2482 0,
2483 snzreqcr0::Snzreqen30,
2484 snzreqcr0::Snzreqen30,
2485 Snzreqcr0_SPEC,
2486 crate::common::RW,
2487 >::from_register(self, 0)
2488 }
2489}
2490impl ::core::default::Default for Snzreqcr0 {
2491 #[inline(always)]
2492 fn default() -> Snzreqcr0 {
2493 <crate::RegValueT<Snzreqcr0_SPEC> as RegisterValue<_>>::new(0)
2494 }
2495}
2496pub mod snzreqcr0 {
2497
2498 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2499 pub struct Snzreqen0_SPEC;
2500 pub type Snzreqen0 = crate::EnumBitfieldStruct<u8, Snzreqen0_SPEC>;
2501 impl Snzreqen0 {
2502 #[doc = "Disable the snooze request"]
2503 pub const _0: Self = Self::new(0);
2504
2505 #[doc = "Enable the snooze request"]
2506 pub const _1: Self = Self::new(1);
2507 }
2508 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2509 pub struct Snzreqen1_SPEC;
2510 pub type Snzreqen1 = crate::EnumBitfieldStruct<u8, Snzreqen1_SPEC>;
2511 impl Snzreqen1 {
2512 #[doc = "Disable the snooze request"]
2513 pub const _0: Self = Self::new(0);
2514
2515 #[doc = "Enable the snooze request"]
2516 pub const _1: Self = Self::new(1);
2517 }
2518 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2519 pub struct Snzreqen2_SPEC;
2520 pub type Snzreqen2 = crate::EnumBitfieldStruct<u8, Snzreqen2_SPEC>;
2521 impl Snzreqen2 {
2522 #[doc = "Disable the snooze request"]
2523 pub const _0: Self = Self::new(0);
2524
2525 #[doc = "Enable the snooze request"]
2526 pub const _1: Self = Self::new(1);
2527 }
2528 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2529 pub struct Snzreqen3_SPEC;
2530 pub type Snzreqen3 = crate::EnumBitfieldStruct<u8, Snzreqen3_SPEC>;
2531 impl Snzreqen3 {
2532 #[doc = "Disable the snooze request"]
2533 pub const _0: Self = Self::new(0);
2534
2535 #[doc = "Enable the snooze request"]
2536 pub const _1: Self = Self::new(1);
2537 }
2538 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2539 pub struct Snzreqen4_SPEC;
2540 pub type Snzreqen4 = crate::EnumBitfieldStruct<u8, Snzreqen4_SPEC>;
2541 impl Snzreqen4 {
2542 #[doc = "Disable the snooze request"]
2543 pub const _0: Self = Self::new(0);
2544
2545 #[doc = "Enable the snooze request"]
2546 pub const _1: Self = Self::new(1);
2547 }
2548 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2549 pub struct Snzreqen5_SPEC;
2550 pub type Snzreqen5 = crate::EnumBitfieldStruct<u8, Snzreqen5_SPEC>;
2551 impl Snzreqen5 {
2552 #[doc = "Disable the snooze request"]
2553 pub const _0: Self = Self::new(0);
2554
2555 #[doc = "Enable the snooze request"]
2556 pub const _1: Self = Self::new(1);
2557 }
2558 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2559 pub struct Snzreqen6_SPEC;
2560 pub type Snzreqen6 = crate::EnumBitfieldStruct<u8, Snzreqen6_SPEC>;
2561 impl Snzreqen6 {
2562 #[doc = "Disable the snooze request"]
2563 pub const _0: Self = Self::new(0);
2564
2565 #[doc = "Enable the snooze request"]
2566 pub const _1: Self = Self::new(1);
2567 }
2568 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2569 pub struct Snzreqen7_SPEC;
2570 pub type Snzreqen7 = crate::EnumBitfieldStruct<u8, Snzreqen7_SPEC>;
2571 impl Snzreqen7 {
2572 #[doc = "Disable the snooze request"]
2573 pub const _0: Self = Self::new(0);
2574
2575 #[doc = "Enable the snooze request"]
2576 pub const _1: Self = Self::new(1);
2577 }
2578 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2579 pub struct Snzreqen17_SPEC;
2580 pub type Snzreqen17 = crate::EnumBitfieldStruct<u8, Snzreqen17_SPEC>;
2581 impl Snzreqen17 {
2582 #[doc = "Disable the snooze request"]
2583 pub const _0: Self = Self::new(0);
2584
2585 #[doc = "Enable the snooze request"]
2586 pub const _1: Self = Self::new(1);
2587 }
2588 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2589 pub struct Snzreqen23_SPEC;
2590 pub type Snzreqen23 = crate::EnumBitfieldStruct<u8, Snzreqen23_SPEC>;
2591 impl Snzreqen23 {
2592 #[doc = "Disable the snooze request"]
2593 pub const _0: Self = Self::new(0);
2594
2595 #[doc = "Enable the snooze request"]
2596 pub const _1: Self = Self::new(1);
2597 }
2598 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2599 pub struct Snzreqen24_SPEC;
2600 pub type Snzreqen24 = crate::EnumBitfieldStruct<u8, Snzreqen24_SPEC>;
2601 impl Snzreqen24 {
2602 #[doc = "Disable the snooze request"]
2603 pub const _0: Self = Self::new(0);
2604
2605 #[doc = "Enable the snooze request"]
2606 pub const _1: Self = Self::new(1);
2607 }
2608 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2609 pub struct Snzreqen25_SPEC;
2610 pub type Snzreqen25 = crate::EnumBitfieldStruct<u8, Snzreqen25_SPEC>;
2611 impl Snzreqen25 {
2612 #[doc = "Disable the snooze request"]
2613 pub const _0: Self = Self::new(0);
2614
2615 #[doc = "Enable the snooze request"]
2616 pub const _1: Self = Self::new(1);
2617 }
2618 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2619 pub struct Snzreqen28_SPEC;
2620 pub type Snzreqen28 = crate::EnumBitfieldStruct<u8, Snzreqen28_SPEC>;
2621 impl Snzreqen28 {
2622 #[doc = "Disable the snooze request"]
2623 pub const _0: Self = Self::new(0);
2624
2625 #[doc = "Enable the snooze request"]
2626 pub const _1: Self = Self::new(1);
2627 }
2628 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2629 pub struct Snzreqen29_SPEC;
2630 pub type Snzreqen29 = crate::EnumBitfieldStruct<u8, Snzreqen29_SPEC>;
2631 impl Snzreqen29 {
2632 #[doc = "Disable the snooze request"]
2633 pub const _0: Self = Self::new(0);
2634
2635 #[doc = "Enable the snooze request"]
2636 pub const _1: Self = Self::new(1);
2637 }
2638 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2639 pub struct Snzreqen30_SPEC;
2640 pub type Snzreqen30 = crate::EnumBitfieldStruct<u8, Snzreqen30_SPEC>;
2641 impl Snzreqen30 {
2642 #[doc = "Disable the snooze request"]
2643 pub const _0: Self = Self::new(0);
2644
2645 #[doc = "Enable the snooze request"]
2646 pub const _1: Self = Self::new(1);
2647 }
2648}
2649#[doc(hidden)]
2650#[derive(Copy, Clone, Eq, PartialEq)]
2651pub struct Psmcr_SPEC;
2652impl crate::sealed::RegSpec for Psmcr_SPEC {
2653 type DataType = u8;
2654}
2655
2656#[doc = "Power Save Memory Control Register"]
2657pub type Psmcr = crate::RegValueT<Psmcr_SPEC>;
2658
2659impl Psmcr {
2660 #[doc = "Power Save Memory Control"]
2661 #[inline(always)]
2662 pub fn psmc(
2663 self,
2664 ) -> crate::common::RegisterField<
2665 0,
2666 0x3,
2667 1,
2668 0,
2669 psmcr::Psmc,
2670 psmcr::Psmc,
2671 Psmcr_SPEC,
2672 crate::common::RW,
2673 > {
2674 crate::common::RegisterField::<
2675 0,
2676 0x3,
2677 1,
2678 0,
2679 psmcr::Psmc,
2680 psmcr::Psmc,
2681 Psmcr_SPEC,
2682 crate::common::RW,
2683 >::from_register(self, 0)
2684 }
2685}
2686impl ::core::default::Default for Psmcr {
2687 #[inline(always)]
2688 fn default() -> Psmcr {
2689 <crate::RegValueT<Psmcr_SPEC> as RegisterValue<_>>::new(0)
2690 }
2691}
2692pub mod psmcr {
2693
2694 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2695 pub struct Psmc_SPEC;
2696 pub type Psmc = crate::EnumBitfieldStruct<u8, Psmc_SPEC>;
2697 impl Psmc {
2698 #[doc = "All SRAMs are on in Software Standby mode"]
2699 pub const _00: Self = Self::new(0);
2700
2701 #[doc = "8 KB SRAM (0x2000_4000 to 0x2000_5FFF) is on in Software Standby mode"]
2702 pub const _01: Self = Self::new(1);
2703
2704 #[doc = "Setting prohibited"]
2705 pub const _10: Self = Self::new(2);
2706
2707 #[doc = "Setting prohibited"]
2708 pub const _11: Self = Self::new(3);
2709 }
2710}
2711#[doc(hidden)]
2712#[derive(Copy, Clone, Eq, PartialEq)]
2713pub struct Opccr_SPEC;
2714impl crate::sealed::RegSpec for Opccr_SPEC {
2715 type DataType = u8;
2716}
2717
2718#[doc = "Operating Power Control Register"]
2719pub type Opccr = crate::RegValueT<Opccr_SPEC>;
2720
2721impl Opccr {
2722 #[doc = "Operating Power Control Mode Select"]
2723 #[inline(always)]
2724 pub fn opcm(
2725 self,
2726 ) -> crate::common::RegisterField<
2727 0,
2728 0x3,
2729 1,
2730 0,
2731 opccr::Opcm,
2732 opccr::Opcm,
2733 Opccr_SPEC,
2734 crate::common::RW,
2735 > {
2736 crate::common::RegisterField::<
2737 0,
2738 0x3,
2739 1,
2740 0,
2741 opccr::Opcm,
2742 opccr::Opcm,
2743 Opccr_SPEC,
2744 crate::common::RW,
2745 >::from_register(self, 0)
2746 }
2747
2748 #[doc = "Operating Power Control Mode Transition Status Flag"]
2749 #[inline(always)]
2750 pub fn opcmtsf(
2751 self,
2752 ) -> crate::common::RegisterField<
2753 4,
2754 0x1,
2755 1,
2756 0,
2757 opccr::Opcmtsf,
2758 opccr::Opcmtsf,
2759 Opccr_SPEC,
2760 crate::common::R,
2761 > {
2762 crate::common::RegisterField::<
2763 4,
2764 0x1,
2765 1,
2766 0,
2767 opccr::Opcmtsf,
2768 opccr::Opcmtsf,
2769 Opccr_SPEC,
2770 crate::common::R,
2771 >::from_register(self, 0)
2772 }
2773}
2774impl ::core::default::Default for Opccr {
2775 #[inline(always)]
2776 fn default() -> Opccr {
2777 <crate::RegValueT<Opccr_SPEC> as RegisterValue<_>>::new(1)
2778 }
2779}
2780pub mod opccr {
2781
2782 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2783 pub struct Opcm_SPEC;
2784 pub type Opcm = crate::EnumBitfieldStruct<u8, Opcm_SPEC>;
2785 impl Opcm {
2786 #[doc = "High-speed mode"]
2787 pub const _00: Self = Self::new(0);
2788
2789 #[doc = "Middle-speed mode"]
2790 pub const _01: Self = Self::new(1);
2791
2792 #[doc = "Setting prohibited"]
2793 pub const _10: Self = Self::new(2);
2794
2795 #[doc = "Low-speed mode"]
2796 pub const _11: Self = Self::new(3);
2797 }
2798 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2799 pub struct Opcmtsf_SPEC;
2800 pub type Opcmtsf = crate::EnumBitfieldStruct<u8, Opcmtsf_SPEC>;
2801 impl Opcmtsf {
2802 #[doc = "Transition completed"]
2803 pub const _0: Self = Self::new(0);
2804
2805 #[doc = "During transition"]
2806 pub const _1: Self = Self::new(1);
2807 }
2808}
2809#[doc(hidden)]
2810#[derive(Copy, Clone, Eq, PartialEq)]
2811pub struct Moscwtcr_SPEC;
2812impl crate::sealed::RegSpec for Moscwtcr_SPEC {
2813 type DataType = u8;
2814}
2815
2816#[doc = "Main Clock Oscillator Wait Control Register"]
2817pub type Moscwtcr = crate::RegValueT<Moscwtcr_SPEC>;
2818
2819impl Moscwtcr {
2820 #[doc = "Main Clock Oscillator Wait Time Setting"]
2821 #[inline(always)]
2822 pub fn msts(
2823 self,
2824 ) -> crate::common::RegisterField<
2825 0,
2826 0xf,
2827 1,
2828 0,
2829 moscwtcr::Msts,
2830 moscwtcr::Msts,
2831 Moscwtcr_SPEC,
2832 crate::common::RW,
2833 > {
2834 crate::common::RegisterField::<
2835 0,
2836 0xf,
2837 1,
2838 0,
2839 moscwtcr::Msts,
2840 moscwtcr::Msts,
2841 Moscwtcr_SPEC,
2842 crate::common::RW,
2843 >::from_register(self, 0)
2844 }
2845}
2846impl ::core::default::Default for Moscwtcr {
2847 #[inline(always)]
2848 fn default() -> Moscwtcr {
2849 <crate::RegValueT<Moscwtcr_SPEC> as RegisterValue<_>>::new(5)
2850 }
2851}
2852pub mod moscwtcr {
2853
2854 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2855 pub struct Msts_SPEC;
2856 pub type Msts = crate::EnumBitfieldStruct<u8, Msts_SPEC>;
2857 impl Msts {
2858 #[doc = "Wait time = 2 cycles (0.25 us)"]
2859 pub const _0_X_0: Self = Self::new(0);
2860
2861 #[doc = "Wait time = 1024 cycles (128 us)"]
2862 pub const _0_X_1: Self = Self::new(1);
2863
2864 #[doc = "Wait time = 2048 cycles (256 us)"]
2865 pub const _0_X_2: Self = Self::new(2);
2866
2867 #[doc = "Wait time = 4096 cycles (512 us)"]
2868 pub const _0_X_3: Self = Self::new(3);
2869
2870 #[doc = "Wait time = 8192 cycles (1024 us)"]
2871 pub const _0_X_4: Self = Self::new(4);
2872
2873 #[doc = "Wait time = 16384 cycles (2048 us)"]
2874 pub const _0_X_5: Self = Self::new(5);
2875
2876 #[doc = "Wait time = 32768 cycles (4096 us)"]
2877 pub const _0_X_6: Self = Self::new(6);
2878
2879 #[doc = "Wait time = 65536 cycles (8192 us)"]
2880 pub const _0_X_7: Self = Self::new(7);
2881
2882 #[doc = "Wait time = 131072 cycles (16384 us)"]
2883 pub const _0_X_8: Self = Self::new(8);
2884
2885 #[doc = "Wait time = 262144 cycles (32768 us)"]
2886 pub const _0_X_9: Self = Self::new(9);
2887 }
2888}
2889#[doc(hidden)]
2890#[derive(Copy, Clone, Eq, PartialEq)]
2891pub struct Sopccr_SPEC;
2892impl crate::sealed::RegSpec for Sopccr_SPEC {
2893 type DataType = u8;
2894}
2895
2896#[doc = "Sub Operating Power Control Register"]
2897pub type Sopccr = crate::RegValueT<Sopccr_SPEC>;
2898
2899impl Sopccr {
2900 #[doc = "Sub Operating Power Control Mode Select"]
2901 #[inline(always)]
2902 pub fn sopcm(
2903 self,
2904 ) -> crate::common::RegisterField<
2905 0,
2906 0x1,
2907 1,
2908 0,
2909 sopccr::Sopcm,
2910 sopccr::Sopcm,
2911 Sopccr_SPEC,
2912 crate::common::RW,
2913 > {
2914 crate::common::RegisterField::<
2915 0,
2916 0x1,
2917 1,
2918 0,
2919 sopccr::Sopcm,
2920 sopccr::Sopcm,
2921 Sopccr_SPEC,
2922 crate::common::RW,
2923 >::from_register(self, 0)
2924 }
2925
2926 #[doc = "Operating Power Control Mode Transition Status Flag"]
2927 #[inline(always)]
2928 pub fn sopcmtsf(
2929 self,
2930 ) -> crate::common::RegisterField<
2931 4,
2932 0x1,
2933 1,
2934 0,
2935 sopccr::Sopcmtsf,
2936 sopccr::Sopcmtsf,
2937 Sopccr_SPEC,
2938 crate::common::R,
2939 > {
2940 crate::common::RegisterField::<
2941 4,
2942 0x1,
2943 1,
2944 0,
2945 sopccr::Sopcmtsf,
2946 sopccr::Sopcmtsf,
2947 Sopccr_SPEC,
2948 crate::common::R,
2949 >::from_register(self, 0)
2950 }
2951}
2952impl ::core::default::Default for Sopccr {
2953 #[inline(always)]
2954 fn default() -> Sopccr {
2955 <crate::RegValueT<Sopccr_SPEC> as RegisterValue<_>>::new(0)
2956 }
2957}
2958pub mod sopccr {
2959
2960 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2961 pub struct Sopcm_SPEC;
2962 pub type Sopcm = crate::EnumBitfieldStruct<u8, Sopcm_SPEC>;
2963 impl Sopcm {
2964 #[doc = "Other than Subosc-speed mode"]
2965 pub const _0: Self = Self::new(0);
2966
2967 #[doc = "Subosc-speed mode"]
2968 pub const _1: Self = Self::new(1);
2969 }
2970 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2971 pub struct Sopcmtsf_SPEC;
2972 pub type Sopcmtsf = crate::EnumBitfieldStruct<u8, Sopcmtsf_SPEC>;
2973 impl Sopcmtsf {
2974 #[doc = "Transition completed"]
2975 pub const _0: Self = Self::new(0);
2976
2977 #[doc = "During transition"]
2978 pub const _1: Self = Self::new(1);
2979 }
2980}
2981#[doc(hidden)]
2982#[derive(Copy, Clone, Eq, PartialEq)]
2983pub struct Rstsr1_SPEC;
2984impl crate::sealed::RegSpec for Rstsr1_SPEC {
2985 type DataType = u16;
2986}
2987
2988#[doc = "Reset Status Register 1"]
2989pub type Rstsr1 = crate::RegValueT<Rstsr1_SPEC>;
2990
2991impl Rstsr1 {
2992 #[doc = "Independent Watchdog Timer Reset Detect Flag"]
2993 #[inline(always)]
2994 pub fn iwdtrf(
2995 self,
2996 ) -> crate::common::RegisterField<
2997 0,
2998 0x1,
2999 1,
3000 0,
3001 rstsr1::Iwdtrf,
3002 rstsr1::Iwdtrf,
3003 Rstsr1_SPEC,
3004 crate::common::RW,
3005 > {
3006 crate::common::RegisterField::<
3007 0,
3008 0x1,
3009 1,
3010 0,
3011 rstsr1::Iwdtrf,
3012 rstsr1::Iwdtrf,
3013 Rstsr1_SPEC,
3014 crate::common::RW,
3015 >::from_register(self, 0)
3016 }
3017
3018 #[doc = "Watchdog Timer Reset Detect Flag"]
3019 #[inline(always)]
3020 pub fn wdtrf(
3021 self,
3022 ) -> crate::common::RegisterField<
3023 1,
3024 0x1,
3025 1,
3026 0,
3027 rstsr1::Wdtrf,
3028 rstsr1::Wdtrf,
3029 Rstsr1_SPEC,
3030 crate::common::RW,
3031 > {
3032 crate::common::RegisterField::<
3033 1,
3034 0x1,
3035 1,
3036 0,
3037 rstsr1::Wdtrf,
3038 rstsr1::Wdtrf,
3039 Rstsr1_SPEC,
3040 crate::common::RW,
3041 >::from_register(self, 0)
3042 }
3043
3044 #[doc = "Software Reset Detect Flag"]
3045 #[inline(always)]
3046 pub fn swrf(
3047 self,
3048 ) -> crate::common::RegisterField<
3049 2,
3050 0x1,
3051 1,
3052 0,
3053 rstsr1::Swrf,
3054 rstsr1::Swrf,
3055 Rstsr1_SPEC,
3056 crate::common::RW,
3057 > {
3058 crate::common::RegisterField::<
3059 2,
3060 0x1,
3061 1,
3062 0,
3063 rstsr1::Swrf,
3064 rstsr1::Swrf,
3065 Rstsr1_SPEC,
3066 crate::common::RW,
3067 >::from_register(self, 0)
3068 }
3069
3070 #[doc = "SRAM Parity Error Reset Detect Flag"]
3071 #[inline(always)]
3072 pub fn rperf(
3073 self,
3074 ) -> crate::common::RegisterField<
3075 8,
3076 0x1,
3077 1,
3078 0,
3079 rstsr1::Rperf,
3080 rstsr1::Rperf,
3081 Rstsr1_SPEC,
3082 crate::common::RW,
3083 > {
3084 crate::common::RegisterField::<
3085 8,
3086 0x1,
3087 1,
3088 0,
3089 rstsr1::Rperf,
3090 rstsr1::Rperf,
3091 Rstsr1_SPEC,
3092 crate::common::RW,
3093 >::from_register(self, 0)
3094 }
3095
3096 #[doc = "SRAM ECC Error Reset Detect Flag"]
3097 #[inline(always)]
3098 pub fn reerf(
3099 self,
3100 ) -> crate::common::RegisterField<
3101 9,
3102 0x1,
3103 1,
3104 0,
3105 rstsr1::Reerf,
3106 rstsr1::Reerf,
3107 Rstsr1_SPEC,
3108 crate::common::RW,
3109 > {
3110 crate::common::RegisterField::<
3111 9,
3112 0x1,
3113 1,
3114 0,
3115 rstsr1::Reerf,
3116 rstsr1::Reerf,
3117 Rstsr1_SPEC,
3118 crate::common::RW,
3119 >::from_register(self, 0)
3120 }
3121
3122 #[doc = "Bus Slave MPU Error Reset Detect Flag"]
3123 #[inline(always)]
3124 pub fn bussrf(
3125 self,
3126 ) -> crate::common::RegisterField<
3127 10,
3128 0x1,
3129 1,
3130 0,
3131 rstsr1::Bussrf,
3132 rstsr1::Bussrf,
3133 Rstsr1_SPEC,
3134 crate::common::RW,
3135 > {
3136 crate::common::RegisterField::<
3137 10,
3138 0x1,
3139 1,
3140 0,
3141 rstsr1::Bussrf,
3142 rstsr1::Bussrf,
3143 Rstsr1_SPEC,
3144 crate::common::RW,
3145 >::from_register(self, 0)
3146 }
3147
3148 #[doc = "Bus Master MPU Error Reset Detect Flag"]
3149 #[inline(always)]
3150 pub fn busmrf(
3151 self,
3152 ) -> crate::common::RegisterField<
3153 11,
3154 0x1,
3155 1,
3156 0,
3157 rstsr1::Busmrf,
3158 rstsr1::Busmrf,
3159 Rstsr1_SPEC,
3160 crate::common::RW,
3161 > {
3162 crate::common::RegisterField::<
3163 11,
3164 0x1,
3165 1,
3166 0,
3167 rstsr1::Busmrf,
3168 rstsr1::Busmrf,
3169 Rstsr1_SPEC,
3170 crate::common::RW,
3171 >::from_register(self, 0)
3172 }
3173
3174 #[doc = "CPU Stack Pointer Error Reset Detect Flag"]
3175 #[inline(always)]
3176 pub fn sperf(
3177 self,
3178 ) -> crate::common::RegisterField<
3179 12,
3180 0x1,
3181 1,
3182 0,
3183 rstsr1::Sperf,
3184 rstsr1::Sperf,
3185 Rstsr1_SPEC,
3186 crate::common::RW,
3187 > {
3188 crate::common::RegisterField::<
3189 12,
3190 0x1,
3191 1,
3192 0,
3193 rstsr1::Sperf,
3194 rstsr1::Sperf,
3195 Rstsr1_SPEC,
3196 crate::common::RW,
3197 >::from_register(self, 0)
3198 }
3199}
3200impl ::core::default::Default for Rstsr1 {
3201 #[inline(always)]
3202 fn default() -> Rstsr1 {
3203 <crate::RegValueT<Rstsr1_SPEC> as RegisterValue<_>>::new(0)
3204 }
3205}
3206pub mod rstsr1 {
3207
3208 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3209 pub struct Iwdtrf_SPEC;
3210 pub type Iwdtrf = crate::EnumBitfieldStruct<u8, Iwdtrf_SPEC>;
3211 impl Iwdtrf {
3212 #[doc = "Independent watchdog timer reset not detected"]
3213 pub const _0: Self = Self::new(0);
3214
3215 #[doc = "Independent watchdog timer reset detected"]
3216 pub const _1: Self = Self::new(1);
3217 }
3218 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3219 pub struct Wdtrf_SPEC;
3220 pub type Wdtrf = crate::EnumBitfieldStruct<u8, Wdtrf_SPEC>;
3221 impl Wdtrf {
3222 #[doc = "Watchdog timer reset not detected"]
3223 pub const _0: Self = Self::new(0);
3224
3225 #[doc = "Watchdog timer reset detected"]
3226 pub const _1: Self = Self::new(1);
3227 }
3228 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3229 pub struct Swrf_SPEC;
3230 pub type Swrf = crate::EnumBitfieldStruct<u8, Swrf_SPEC>;
3231 impl Swrf {
3232 #[doc = "Software reset not detected"]
3233 pub const _0: Self = Self::new(0);
3234
3235 #[doc = "Software reset detected"]
3236 pub const _1: Self = Self::new(1);
3237 }
3238 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3239 pub struct Rperf_SPEC;
3240 pub type Rperf = crate::EnumBitfieldStruct<u8, Rperf_SPEC>;
3241 impl Rperf {
3242 #[doc = "SRAM parity error reset not detected"]
3243 pub const _0: Self = Self::new(0);
3244
3245 #[doc = "SRAM parity error reset detected"]
3246 pub const _1: Self = Self::new(1);
3247 }
3248 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3249 pub struct Reerf_SPEC;
3250 pub type Reerf = crate::EnumBitfieldStruct<u8, Reerf_SPEC>;
3251 impl Reerf {
3252 #[doc = "SRAM ECC error reset not detected"]
3253 pub const _0: Self = Self::new(0);
3254
3255 #[doc = "SRAM ECC error reset detected"]
3256 pub const _1: Self = Self::new(1);
3257 }
3258 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3259 pub struct Bussrf_SPEC;
3260 pub type Bussrf = crate::EnumBitfieldStruct<u8, Bussrf_SPEC>;
3261 impl Bussrf {
3262 #[doc = "Bus slave MPU error reset not detected"]
3263 pub const _0: Self = Self::new(0);
3264
3265 #[doc = "Bus slave MPU error reset detected"]
3266 pub const _1: Self = Self::new(1);
3267 }
3268 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3269 pub struct Busmrf_SPEC;
3270 pub type Busmrf = crate::EnumBitfieldStruct<u8, Busmrf_SPEC>;
3271 impl Busmrf {
3272 #[doc = "Bus master MPU error reset not detected"]
3273 pub const _0: Self = Self::new(0);
3274
3275 #[doc = "Bus master MPU error reset detected"]
3276 pub const _1: Self = Self::new(1);
3277 }
3278 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3279 pub struct Sperf_SPEC;
3280 pub type Sperf = crate::EnumBitfieldStruct<u8, Sperf_SPEC>;
3281 impl Sperf {
3282 #[doc = "CPU stack pointer error reset not detected"]
3283 pub const _0: Self = Self::new(0);
3284
3285 #[doc = "CPU stack pointer error reset detected"]
3286 pub const _1: Self = Self::new(1);
3287 }
3288}
3289#[doc(hidden)]
3290#[derive(Copy, Clone, Eq, PartialEq)]
3291pub struct Lvd1Cr1_SPEC;
3292impl crate::sealed::RegSpec for Lvd1Cr1_SPEC {
3293 type DataType = u8;
3294}
3295
3296#[doc = "Voltage Monitor 1 Circuit Control Register"]
3297pub type Lvd1Cr1 = crate::RegValueT<Lvd1Cr1_SPEC>;
3298
3299impl Lvd1Cr1 {
3300 #[doc = "Voltage Monitor 1 Interrupt Generation Condition Select"]
3301 #[inline(always)]
3302 pub fn idtsel(
3303 self,
3304 ) -> crate::common::RegisterField<
3305 0,
3306 0x3,
3307 1,
3308 0,
3309 lvd1cr1::Idtsel,
3310 lvd1cr1::Idtsel,
3311 Lvd1Cr1_SPEC,
3312 crate::common::RW,
3313 > {
3314 crate::common::RegisterField::<
3315 0,
3316 0x3,
3317 1,
3318 0,
3319 lvd1cr1::Idtsel,
3320 lvd1cr1::Idtsel,
3321 Lvd1Cr1_SPEC,
3322 crate::common::RW,
3323 >::from_register(self, 0)
3324 }
3325
3326 #[doc = "Voltage Monitor 1 Interrupt Type Select"]
3327 #[inline(always)]
3328 pub fn irqsel(
3329 self,
3330 ) -> crate::common::RegisterField<
3331 2,
3332 0x1,
3333 1,
3334 0,
3335 lvd1cr1::Irqsel,
3336 lvd1cr1::Irqsel,
3337 Lvd1Cr1_SPEC,
3338 crate::common::RW,
3339 > {
3340 crate::common::RegisterField::<
3341 2,
3342 0x1,
3343 1,
3344 0,
3345 lvd1cr1::Irqsel,
3346 lvd1cr1::Irqsel,
3347 Lvd1Cr1_SPEC,
3348 crate::common::RW,
3349 >::from_register(self, 0)
3350 }
3351}
3352impl ::core::default::Default for Lvd1Cr1 {
3353 #[inline(always)]
3354 fn default() -> Lvd1Cr1 {
3355 <crate::RegValueT<Lvd1Cr1_SPEC> as RegisterValue<_>>::new(1)
3356 }
3357}
3358pub mod lvd1cr1 {
3359
3360 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3361 pub struct Idtsel_SPEC;
3362 pub type Idtsel = crate::EnumBitfieldStruct<u8, Idtsel_SPEC>;
3363 impl Idtsel {
3364 #[doc = "When VCC >= Vdet1 (rise) is detected"]
3365 pub const _00: Self = Self::new(0);
3366
3367 #[doc = "When VCC < Vdet1 (fall) is detected"]
3368 pub const _01: Self = Self::new(1);
3369
3370 #[doc = "When fall and rise are detected"]
3371 pub const _10: Self = Self::new(2);
3372
3373 #[doc = "Settings prohibited"]
3374 pub const _11: Self = Self::new(3);
3375 }
3376 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3377 pub struct Irqsel_SPEC;
3378 pub type Irqsel = crate::EnumBitfieldStruct<u8, Irqsel_SPEC>;
3379 impl Irqsel {
3380 #[doc = "Non-maskable interrupt"]
3381 pub const _0: Self = Self::new(0);
3382
3383 #[doc = "Maskable interrupt"]
3384 pub const _1: Self = Self::new(1);
3385 }
3386}
3387#[doc(hidden)]
3388#[derive(Copy, Clone, Eq, PartialEq)]
3389pub struct Lvd1Sr_SPEC;
3390impl crate::sealed::RegSpec for Lvd1Sr_SPEC {
3391 type DataType = u8;
3392}
3393
3394#[doc = "Voltage Monitor 1 Circuit Status Register"]
3395pub type Lvd1Sr = crate::RegValueT<Lvd1Sr_SPEC>;
3396
3397impl Lvd1Sr {
3398 #[doc = "Voltage Monitor 1 Voltage Variation Detection Flag"]
3399 #[inline(always)]
3400 pub fn det(
3401 self,
3402 ) -> crate::common::RegisterField<
3403 0,
3404 0x1,
3405 1,
3406 0,
3407 lvd1sr::Det,
3408 lvd1sr::Det,
3409 Lvd1Sr_SPEC,
3410 crate::common::RW,
3411 > {
3412 crate::common::RegisterField::<
3413 0,
3414 0x1,
3415 1,
3416 0,
3417 lvd1sr::Det,
3418 lvd1sr::Det,
3419 Lvd1Sr_SPEC,
3420 crate::common::RW,
3421 >::from_register(self, 0)
3422 }
3423
3424 #[doc = "Voltage Monitor 1 Signal Monitor Flag"]
3425 #[inline(always)]
3426 pub fn mon(
3427 self,
3428 ) -> crate::common::RegisterField<
3429 1,
3430 0x1,
3431 1,
3432 0,
3433 lvd1sr::Mon,
3434 lvd1sr::Mon,
3435 Lvd1Sr_SPEC,
3436 crate::common::R,
3437 > {
3438 crate::common::RegisterField::<
3439 1,
3440 0x1,
3441 1,
3442 0,
3443 lvd1sr::Mon,
3444 lvd1sr::Mon,
3445 Lvd1Sr_SPEC,
3446 crate::common::R,
3447 >::from_register(self, 0)
3448 }
3449}
3450impl ::core::default::Default for Lvd1Sr {
3451 #[inline(always)]
3452 fn default() -> Lvd1Sr {
3453 <crate::RegValueT<Lvd1Sr_SPEC> as RegisterValue<_>>::new(2)
3454 }
3455}
3456pub mod lvd1sr {
3457
3458 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3459 pub struct Det_SPEC;
3460 pub type Det = crate::EnumBitfieldStruct<u8, Det_SPEC>;
3461 impl Det {
3462 #[doc = "Not detected"]
3463 pub const _0: Self = Self::new(0);
3464
3465 #[doc = "Vdet1 crossing is detected"]
3466 pub const _1: Self = Self::new(1);
3467 }
3468 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3469 pub struct Mon_SPEC;
3470 pub type Mon = crate::EnumBitfieldStruct<u8, Mon_SPEC>;
3471 impl Mon {
3472 #[doc = "VCC < Vdet1"]
3473 pub const _0: Self = Self::new(0);
3474
3475 #[doc = "VCC >= Vdet1 or MON is disabled"]
3476 pub const _1: Self = Self::new(1);
3477 }
3478}
3479#[doc(hidden)]
3480#[derive(Copy, Clone, Eq, PartialEq)]
3481pub struct Lvd2Cr1_SPEC;
3482impl crate::sealed::RegSpec for Lvd2Cr1_SPEC {
3483 type DataType = u8;
3484}
3485
3486#[doc = "Voltage Monitor 2 Circuit Control Register 1"]
3487pub type Lvd2Cr1 = crate::RegValueT<Lvd2Cr1_SPEC>;
3488
3489impl Lvd2Cr1 {
3490 #[doc = "Voltage Monitor 2 Interrupt Generation Condition Select"]
3491 #[inline(always)]
3492 pub fn idtsel(
3493 self,
3494 ) -> crate::common::RegisterField<
3495 0,
3496 0x3,
3497 1,
3498 0,
3499 lvd2cr1::Idtsel,
3500 lvd2cr1::Idtsel,
3501 Lvd2Cr1_SPEC,
3502 crate::common::RW,
3503 > {
3504 crate::common::RegisterField::<
3505 0,
3506 0x3,
3507 1,
3508 0,
3509 lvd2cr1::Idtsel,
3510 lvd2cr1::Idtsel,
3511 Lvd2Cr1_SPEC,
3512 crate::common::RW,
3513 >::from_register(self, 0)
3514 }
3515
3516 #[doc = "Voltage Monitor 2 Interrupt Type Select"]
3517 #[inline(always)]
3518 pub fn irqsel(
3519 self,
3520 ) -> crate::common::RegisterField<
3521 2,
3522 0x1,
3523 1,
3524 0,
3525 lvd2cr1::Irqsel,
3526 lvd2cr1::Irqsel,
3527 Lvd2Cr1_SPEC,
3528 crate::common::RW,
3529 > {
3530 crate::common::RegisterField::<
3531 2,
3532 0x1,
3533 1,
3534 0,
3535 lvd2cr1::Irqsel,
3536 lvd2cr1::Irqsel,
3537 Lvd2Cr1_SPEC,
3538 crate::common::RW,
3539 >::from_register(self, 0)
3540 }
3541}
3542impl ::core::default::Default for Lvd2Cr1 {
3543 #[inline(always)]
3544 fn default() -> Lvd2Cr1 {
3545 <crate::RegValueT<Lvd2Cr1_SPEC> as RegisterValue<_>>::new(1)
3546 }
3547}
3548pub mod lvd2cr1 {
3549
3550 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3551 pub struct Idtsel_SPEC;
3552 pub type Idtsel = crate::EnumBitfieldStruct<u8, Idtsel_SPEC>;
3553 impl Idtsel {
3554 #[doc = "When VCC>= Vdet2 (rise) is detected"]
3555 pub const _00: Self = Self::new(0);
3556
3557 #[doc = "When VCC < Vdet2 (fall) is detected"]
3558 pub const _01: Self = Self::new(1);
3559
3560 #[doc = "When fall and rise are detected"]
3561 pub const _10: Self = Self::new(2);
3562
3563 #[doc = "Settings prohibited"]
3564 pub const _11: Self = Self::new(3);
3565 }
3566 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3567 pub struct Irqsel_SPEC;
3568 pub type Irqsel = crate::EnumBitfieldStruct<u8, Irqsel_SPEC>;
3569 impl Irqsel {
3570 #[doc = "Non-maskable interrupt"]
3571 pub const _0: Self = Self::new(0);
3572
3573 #[doc = "Maskable interrupt"]
3574 pub const _1: Self = Self::new(1);
3575 }
3576}
3577#[doc(hidden)]
3578#[derive(Copy, Clone, Eq, PartialEq)]
3579pub struct Lvd2Sr_SPEC;
3580impl crate::sealed::RegSpec for Lvd2Sr_SPEC {
3581 type DataType = u8;
3582}
3583
3584#[doc = "Voltage Monitor 2 Circuit Status Register"]
3585pub type Lvd2Sr = crate::RegValueT<Lvd2Sr_SPEC>;
3586
3587impl Lvd2Sr {
3588 #[doc = "Voltage Monitor 2 Voltage Variation Detection Flag"]
3589 #[inline(always)]
3590 pub fn det(
3591 self,
3592 ) -> crate::common::RegisterField<
3593 0,
3594 0x1,
3595 1,
3596 0,
3597 lvd2sr::Det,
3598 lvd2sr::Det,
3599 Lvd2Sr_SPEC,
3600 crate::common::RW,
3601 > {
3602 crate::common::RegisterField::<
3603 0,
3604 0x1,
3605 1,
3606 0,
3607 lvd2sr::Det,
3608 lvd2sr::Det,
3609 Lvd2Sr_SPEC,
3610 crate::common::RW,
3611 >::from_register(self, 0)
3612 }
3613
3614 #[doc = "Voltage Monitor 2 Signal Monitor Flag"]
3615 #[inline(always)]
3616 pub fn mon(
3617 self,
3618 ) -> crate::common::RegisterField<
3619 1,
3620 0x1,
3621 1,
3622 0,
3623 lvd2sr::Mon,
3624 lvd2sr::Mon,
3625 Lvd2Sr_SPEC,
3626 crate::common::R,
3627 > {
3628 crate::common::RegisterField::<
3629 1,
3630 0x1,
3631 1,
3632 0,
3633 lvd2sr::Mon,
3634 lvd2sr::Mon,
3635 Lvd2Sr_SPEC,
3636 crate::common::R,
3637 >::from_register(self, 0)
3638 }
3639}
3640impl ::core::default::Default for Lvd2Sr {
3641 #[inline(always)]
3642 fn default() -> Lvd2Sr {
3643 <crate::RegValueT<Lvd2Sr_SPEC> as RegisterValue<_>>::new(2)
3644 }
3645}
3646pub mod lvd2sr {
3647
3648 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3649 pub struct Det_SPEC;
3650 pub type Det = crate::EnumBitfieldStruct<u8, Det_SPEC>;
3651 impl Det {
3652 #[doc = "Not detected"]
3653 pub const _0: Self = Self::new(0);
3654
3655 #[doc = "Vdet2 crossing is detected"]
3656 pub const _1: Self = Self::new(1);
3657 }
3658 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3659 pub struct Mon_SPEC;
3660 pub type Mon = crate::EnumBitfieldStruct<u8, Mon_SPEC>;
3661 impl Mon {
3662 #[doc = "VCC < Vdet2"]
3663 pub const _0: Self = Self::new(0);
3664
3665 #[doc = "VCC>= Vdet2 or MON is disabled"]
3666 pub const _1: Self = Self::new(1);
3667 }
3668}
3669#[doc(hidden)]
3670#[derive(Copy, Clone, Eq, PartialEq)]
3671pub struct Prcr_SPEC;
3672impl crate::sealed::RegSpec for Prcr_SPEC {
3673 type DataType = u16;
3674}
3675
3676#[doc = "Protect Register"]
3677pub type Prcr = crate::RegValueT<Prcr_SPEC>;
3678
3679impl Prcr {
3680 #[doc = "Enable writing to the registers related to the clock generation circuit"]
3681 #[inline(always)]
3682 pub fn prc0(
3683 self,
3684 ) -> crate::common::RegisterField<
3685 0,
3686 0x1,
3687 1,
3688 0,
3689 prcr::Prc0,
3690 prcr::Prc0,
3691 Prcr_SPEC,
3692 crate::common::RW,
3693 > {
3694 crate::common::RegisterField::<
3695 0,
3696 0x1,
3697 1,
3698 0,
3699 prcr::Prc0,
3700 prcr::Prc0,
3701 Prcr_SPEC,
3702 crate::common::RW,
3703 >::from_register(self, 0)
3704 }
3705
3706 #[doc = "Enable writing to the registers related to the low power modes"]
3707 #[inline(always)]
3708 pub fn prc1(
3709 self,
3710 ) -> crate::common::RegisterField<
3711 1,
3712 0x1,
3713 1,
3714 0,
3715 prcr::Prc1,
3716 prcr::Prc1,
3717 Prcr_SPEC,
3718 crate::common::RW,
3719 > {
3720 crate::common::RegisterField::<
3721 1,
3722 0x1,
3723 1,
3724 0,
3725 prcr::Prc1,
3726 prcr::Prc1,
3727 Prcr_SPEC,
3728 crate::common::RW,
3729 >::from_register(self, 0)
3730 }
3731
3732 #[doc = "Enable writing to the registers related to the LVD"]
3733 #[inline(always)]
3734 pub fn prc3(
3735 self,
3736 ) -> crate::common::RegisterField<
3737 3,
3738 0x1,
3739 1,
3740 0,
3741 prcr::Prc3,
3742 prcr::Prc3,
3743 Prcr_SPEC,
3744 crate::common::RW,
3745 > {
3746 crate::common::RegisterField::<
3747 3,
3748 0x1,
3749 1,
3750 0,
3751 prcr::Prc3,
3752 prcr::Prc3,
3753 Prcr_SPEC,
3754 crate::common::RW,
3755 >::from_register(self, 0)
3756 }
3757
3758 #[doc = "PRC Key Code"]
3759 #[inline(always)]
3760 pub fn prkey(
3761 self,
3762 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Prcr_SPEC, crate::common::W> {
3763 crate::common::RegisterField::<8,0xff,1,0,u8,u8,Prcr_SPEC,crate::common::W>::from_register(self,0)
3764 }
3765}
3766impl ::core::default::Default for Prcr {
3767 #[inline(always)]
3768 fn default() -> Prcr {
3769 <crate::RegValueT<Prcr_SPEC> as RegisterValue<_>>::new(0)
3770 }
3771}
3772pub mod prcr {
3773
3774 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3775 pub struct Prc0_SPEC;
3776 pub type Prc0 = crate::EnumBitfieldStruct<u8, Prc0_SPEC>;
3777 impl Prc0 {
3778 #[doc = "Disable writes"]
3779 pub const _0: Self = Self::new(0);
3780
3781 #[doc = "Enable writes"]
3782 pub const _1: Self = Self::new(1);
3783 }
3784 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3785 pub struct Prc1_SPEC;
3786 pub type Prc1 = crate::EnumBitfieldStruct<u8, Prc1_SPEC>;
3787 impl Prc1 {
3788 #[doc = "Disable writes"]
3789 pub const _0: Self = Self::new(0);
3790
3791 #[doc = "Enable writes"]
3792 pub const _1: Self = Self::new(1);
3793 }
3794 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3795 pub struct Prc3_SPEC;
3796 pub type Prc3 = crate::EnumBitfieldStruct<u8, Prc3_SPEC>;
3797 impl Prc3 {
3798 #[doc = "Disable writes"]
3799 pub const _0: Self = Self::new(0);
3800
3801 #[doc = "Enable writes"]
3802 pub const _1: Self = Self::new(1);
3803 }
3804}
3805#[doc(hidden)]
3806#[derive(Copy, Clone, Eq, PartialEq)]
3807pub struct Syocdcr_SPEC;
3808impl crate::sealed::RegSpec for Syocdcr_SPEC {
3809 type DataType = u8;
3810}
3811
3812#[doc = "System Control OCD Control Register"]
3813pub type Syocdcr = crate::RegValueT<Syocdcr_SPEC>;
3814
3815impl Syocdcr {
3816 #[doc = "Debugger Enable bit"]
3817 #[inline(always)]
3818 pub fn dbgen(
3819 self,
3820 ) -> crate::common::RegisterField<
3821 7,
3822 0x1,
3823 1,
3824 0,
3825 syocdcr::Dbgen,
3826 syocdcr::Dbgen,
3827 Syocdcr_SPEC,
3828 crate::common::RW,
3829 > {
3830 crate::common::RegisterField::<
3831 7,
3832 0x1,
3833 1,
3834 0,
3835 syocdcr::Dbgen,
3836 syocdcr::Dbgen,
3837 Syocdcr_SPEC,
3838 crate::common::RW,
3839 >::from_register(self, 0)
3840 }
3841}
3842impl ::core::default::Default for Syocdcr {
3843 #[inline(always)]
3844 fn default() -> Syocdcr {
3845 <crate::RegValueT<Syocdcr_SPEC> as RegisterValue<_>>::new(0)
3846 }
3847}
3848pub mod syocdcr {
3849
3850 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3851 pub struct Dbgen_SPEC;
3852 pub type Dbgen = crate::EnumBitfieldStruct<u8, Dbgen_SPEC>;
3853 impl Dbgen {
3854 #[doc = "On-chip debugger is disabled"]
3855 pub const _0: Self = Self::new(0);
3856
3857 #[doc = "On-chip debugger is enabled"]
3858 pub const _1: Self = Self::new(1);
3859 }
3860}
3861#[doc(hidden)]
3862#[derive(Copy, Clone, Eq, PartialEq)]
3863pub struct Rstsr0_SPEC;
3864impl crate::sealed::RegSpec for Rstsr0_SPEC {
3865 type DataType = u8;
3866}
3867
3868#[doc = "Reset Status Register 0"]
3869pub type Rstsr0 = crate::RegValueT<Rstsr0_SPEC>;
3870
3871impl Rstsr0 {
3872 #[doc = "Power-On Reset Detect Flag"]
3873 #[inline(always)]
3874 pub fn porf(
3875 self,
3876 ) -> crate::common::RegisterField<
3877 0,
3878 0x1,
3879 1,
3880 0,
3881 rstsr0::Porf,
3882 rstsr0::Porf,
3883 Rstsr0_SPEC,
3884 crate::common::RW,
3885 > {
3886 crate::common::RegisterField::<
3887 0,
3888 0x1,
3889 1,
3890 0,
3891 rstsr0::Porf,
3892 rstsr0::Porf,
3893 Rstsr0_SPEC,
3894 crate::common::RW,
3895 >::from_register(self, 0)
3896 }
3897
3898 #[doc = "Voltage Monitor 0 Reset Detect Flag"]
3899 #[inline(always)]
3900 pub fn lvd0rf(
3901 self,
3902 ) -> crate::common::RegisterField<
3903 1,
3904 0x1,
3905 1,
3906 0,
3907 rstsr0::Lvd0Rf,
3908 rstsr0::Lvd0Rf,
3909 Rstsr0_SPEC,
3910 crate::common::RW,
3911 > {
3912 crate::common::RegisterField::<
3913 1,
3914 0x1,
3915 1,
3916 0,
3917 rstsr0::Lvd0Rf,
3918 rstsr0::Lvd0Rf,
3919 Rstsr0_SPEC,
3920 crate::common::RW,
3921 >::from_register(self, 0)
3922 }
3923
3924 #[doc = "Voltage Monitor 1 Reset Detect Flag"]
3925 #[inline(always)]
3926 pub fn lvd1rf(
3927 self,
3928 ) -> crate::common::RegisterField<
3929 2,
3930 0x1,
3931 1,
3932 0,
3933 rstsr0::Lvd1Rf,
3934 rstsr0::Lvd1Rf,
3935 Rstsr0_SPEC,
3936 crate::common::RW,
3937 > {
3938 crate::common::RegisterField::<
3939 2,
3940 0x1,
3941 1,
3942 0,
3943 rstsr0::Lvd1Rf,
3944 rstsr0::Lvd1Rf,
3945 Rstsr0_SPEC,
3946 crate::common::RW,
3947 >::from_register(self, 0)
3948 }
3949
3950 #[doc = "Voltage Monitor 2 Reset Detect Flag"]
3951 #[inline(always)]
3952 pub fn lvd2rf(
3953 self,
3954 ) -> crate::common::RegisterField<
3955 3,
3956 0x1,
3957 1,
3958 0,
3959 rstsr0::Lvd2Rf,
3960 rstsr0::Lvd2Rf,
3961 Rstsr0_SPEC,
3962 crate::common::RW,
3963 > {
3964 crate::common::RegisterField::<
3965 3,
3966 0x1,
3967 1,
3968 0,
3969 rstsr0::Lvd2Rf,
3970 rstsr0::Lvd2Rf,
3971 Rstsr0_SPEC,
3972 crate::common::RW,
3973 >::from_register(self, 0)
3974 }
3975}
3976impl ::core::default::Default for Rstsr0 {
3977 #[inline(always)]
3978 fn default() -> Rstsr0 {
3979 <crate::RegValueT<Rstsr0_SPEC> as RegisterValue<_>>::new(0)
3980 }
3981}
3982pub mod rstsr0 {
3983
3984 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3985 pub struct Porf_SPEC;
3986 pub type Porf = crate::EnumBitfieldStruct<u8, Porf_SPEC>;
3987 impl Porf {
3988 #[doc = "Power-on reset not detected"]
3989 pub const _0: Self = Self::new(0);
3990
3991 #[doc = "Power-on reset detected"]
3992 pub const _1: Self = Self::new(1);
3993 }
3994 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3995 pub struct Lvd0Rf_SPEC;
3996 pub type Lvd0Rf = crate::EnumBitfieldStruct<u8, Lvd0Rf_SPEC>;
3997 impl Lvd0Rf {
3998 #[doc = "Voltage monitor 0 reset not detected"]
3999 pub const _0: Self = Self::new(0);
4000
4001 #[doc = "Voltage monitor 0 reset detected"]
4002 pub const _1: Self = Self::new(1);
4003 }
4004 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4005 pub struct Lvd1Rf_SPEC;
4006 pub type Lvd1Rf = crate::EnumBitfieldStruct<u8, Lvd1Rf_SPEC>;
4007 impl Lvd1Rf {
4008 #[doc = "Voltage monitor 1 reset not detected"]
4009 pub const _0: Self = Self::new(0);
4010
4011 #[doc = "Voltage monitor 1 reset detected"]
4012 pub const _1: Self = Self::new(1);
4013 }
4014 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4015 pub struct Lvd2Rf_SPEC;
4016 pub type Lvd2Rf = crate::EnumBitfieldStruct<u8, Lvd2Rf_SPEC>;
4017 impl Lvd2Rf {
4018 #[doc = "Voltage monitor 2 reset not detected"]
4019 pub const _0: Self = Self::new(0);
4020
4021 #[doc = "Voltage monitor 2 reset detected"]
4022 pub const _1: Self = Self::new(1);
4023 }
4024}
4025#[doc(hidden)]
4026#[derive(Copy, Clone, Eq, PartialEq)]
4027pub struct Rstsr2_SPEC;
4028impl crate::sealed::RegSpec for Rstsr2_SPEC {
4029 type DataType = u8;
4030}
4031
4032#[doc = "Reset Status Register 2"]
4033pub type Rstsr2 = crate::RegValueT<Rstsr2_SPEC>;
4034
4035impl Rstsr2 {
4036 #[doc = "Cold/Warm Start Determination Flag"]
4037 #[inline(always)]
4038 pub fn cwsf(
4039 self,
4040 ) -> crate::common::RegisterField<
4041 0,
4042 0x1,
4043 1,
4044 0,
4045 rstsr2::Cwsf,
4046 rstsr2::Cwsf,
4047 Rstsr2_SPEC,
4048 crate::common::RW,
4049 > {
4050 crate::common::RegisterField::<
4051 0,
4052 0x1,
4053 1,
4054 0,
4055 rstsr2::Cwsf,
4056 rstsr2::Cwsf,
4057 Rstsr2_SPEC,
4058 crate::common::RW,
4059 >::from_register(self, 0)
4060 }
4061}
4062impl ::core::default::Default for Rstsr2 {
4063 #[inline(always)]
4064 fn default() -> Rstsr2 {
4065 <crate::RegValueT<Rstsr2_SPEC> as RegisterValue<_>>::new(0)
4066 }
4067}
4068pub mod rstsr2 {
4069
4070 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4071 pub struct Cwsf_SPEC;
4072 pub type Cwsf = crate::EnumBitfieldStruct<u8, Cwsf_SPEC>;
4073 impl Cwsf {
4074 #[doc = "Cold start"]
4075 pub const _0: Self = Self::new(0);
4076
4077 #[doc = "Warm start"]
4078 pub const _1: Self = Self::new(1);
4079 }
4080}
4081#[doc(hidden)]
4082#[derive(Copy, Clone, Eq, PartialEq)]
4083pub struct Momcr_SPEC;
4084impl crate::sealed::RegSpec for Momcr_SPEC {
4085 type DataType = u8;
4086}
4087
4088#[doc = "Main Clock Oscillator Mode Oscillation Control Register"]
4089pub type Momcr = crate::RegValueT<Momcr_SPEC>;
4090
4091impl Momcr {
4092 #[doc = "Main Clock Oscillator Drive Capability 1 Switching"]
4093 #[inline(always)]
4094 pub fn modrv1(
4095 self,
4096 ) -> crate::common::RegisterField<
4097 3,
4098 0x1,
4099 1,
4100 0,
4101 momcr::Modrv1,
4102 momcr::Modrv1,
4103 Momcr_SPEC,
4104 crate::common::RW,
4105 > {
4106 crate::common::RegisterField::<
4107 3,
4108 0x1,
4109 1,
4110 0,
4111 momcr::Modrv1,
4112 momcr::Modrv1,
4113 Momcr_SPEC,
4114 crate::common::RW,
4115 >::from_register(self, 0)
4116 }
4117
4118 #[doc = "Main Clock Oscillator Switching"]
4119 #[inline(always)]
4120 pub fn mosel(
4121 self,
4122 ) -> crate::common::RegisterField<
4123 6,
4124 0x1,
4125 1,
4126 0,
4127 momcr::Mosel,
4128 momcr::Mosel,
4129 Momcr_SPEC,
4130 crate::common::RW,
4131 > {
4132 crate::common::RegisterField::<
4133 6,
4134 0x1,
4135 1,
4136 0,
4137 momcr::Mosel,
4138 momcr::Mosel,
4139 Momcr_SPEC,
4140 crate::common::RW,
4141 >::from_register(self, 0)
4142 }
4143}
4144impl ::core::default::Default for Momcr {
4145 #[inline(always)]
4146 fn default() -> Momcr {
4147 <crate::RegValueT<Momcr_SPEC> as RegisterValue<_>>::new(0)
4148 }
4149}
4150pub mod momcr {
4151
4152 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4153 pub struct Modrv1_SPEC;
4154 pub type Modrv1 = crate::EnumBitfieldStruct<u8, Modrv1_SPEC>;
4155 impl Modrv1 {
4156 #[doc = "10 MHz to 20 MHz"]
4157 pub const _0: Self = Self::new(0);
4158
4159 #[doc = "1 MHz to 10 MHz"]
4160 pub const _1: Self = Self::new(1);
4161 }
4162 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4163 pub struct Mosel_SPEC;
4164 pub type Mosel = crate::EnumBitfieldStruct<u8, Mosel_SPEC>;
4165 impl Mosel {
4166 #[doc = "Resonator"]
4167 pub const _0: Self = Self::new(0);
4168
4169 #[doc = "External clock input"]
4170 pub const _1: Self = Self::new(1);
4171 }
4172}
4173#[doc(hidden)]
4174#[derive(Copy, Clone, Eq, PartialEq)]
4175pub struct Lvcmpcr_SPEC;
4176impl crate::sealed::RegSpec for Lvcmpcr_SPEC {
4177 type DataType = u8;
4178}
4179
4180#[doc = "Voltage Monitor Circuit Control Register"]
4181pub type Lvcmpcr = crate::RegValueT<Lvcmpcr_SPEC>;
4182
4183impl Lvcmpcr {
4184 #[doc = "Voltage Detection 1 Enable"]
4185 #[inline(always)]
4186 pub fn lvd1e(
4187 self,
4188 ) -> crate::common::RegisterField<
4189 5,
4190 0x1,
4191 1,
4192 0,
4193 lvcmpcr::Lvd1E,
4194 lvcmpcr::Lvd1E,
4195 Lvcmpcr_SPEC,
4196 crate::common::RW,
4197 > {
4198 crate::common::RegisterField::<
4199 5,
4200 0x1,
4201 1,
4202 0,
4203 lvcmpcr::Lvd1E,
4204 lvcmpcr::Lvd1E,
4205 Lvcmpcr_SPEC,
4206 crate::common::RW,
4207 >::from_register(self, 0)
4208 }
4209
4210 #[doc = "Voltage Detection 2 Enable"]
4211 #[inline(always)]
4212 pub fn lvd2e(
4213 self,
4214 ) -> crate::common::RegisterField<
4215 6,
4216 0x1,
4217 1,
4218 0,
4219 lvcmpcr::Lvd2E,
4220 lvcmpcr::Lvd2E,
4221 Lvcmpcr_SPEC,
4222 crate::common::RW,
4223 > {
4224 crate::common::RegisterField::<
4225 6,
4226 0x1,
4227 1,
4228 0,
4229 lvcmpcr::Lvd2E,
4230 lvcmpcr::Lvd2E,
4231 Lvcmpcr_SPEC,
4232 crate::common::RW,
4233 >::from_register(self, 0)
4234 }
4235}
4236impl ::core::default::Default for Lvcmpcr {
4237 #[inline(always)]
4238 fn default() -> Lvcmpcr {
4239 <crate::RegValueT<Lvcmpcr_SPEC> as RegisterValue<_>>::new(0)
4240 }
4241}
4242pub mod lvcmpcr {
4243
4244 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4245 pub struct Lvd1E_SPEC;
4246 pub type Lvd1E = crate::EnumBitfieldStruct<u8, Lvd1E_SPEC>;
4247 impl Lvd1E {
4248 #[doc = "Voltage detection 1 circuit disabled"]
4249 pub const _0: Self = Self::new(0);
4250
4251 #[doc = "Voltage detection 1 circuit enabled"]
4252 pub const _1: Self = Self::new(1);
4253 }
4254 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4255 pub struct Lvd2E_SPEC;
4256 pub type Lvd2E = crate::EnumBitfieldStruct<u8, Lvd2E_SPEC>;
4257 impl Lvd2E {
4258 #[doc = "Voltage detection 2 circuit disabled"]
4259 pub const _0: Self = Self::new(0);
4260
4261 #[doc = "Voltage detection 2 circuit enabled"]
4262 pub const _1: Self = Self::new(1);
4263 }
4264}
4265#[doc(hidden)]
4266#[derive(Copy, Clone, Eq, PartialEq)]
4267pub struct Lvdlvlr_SPEC;
4268impl crate::sealed::RegSpec for Lvdlvlr_SPEC {
4269 type DataType = u8;
4270}
4271
4272#[doc = "Voltage Detection Level Select Register"]
4273pub type Lvdlvlr = crate::RegValueT<Lvdlvlr_SPEC>;
4274
4275impl Lvdlvlr {
4276 #[doc = "Voltage Detection 1 Level Select (Standard voltage during fall in voltage)"]
4277 #[inline(always)]
4278 pub fn lvd1lvl(
4279 self,
4280 ) -> crate::common::RegisterField<
4281 0,
4282 0x1f,
4283 1,
4284 0,
4285 lvdlvlr::Lvd1Lvl,
4286 lvdlvlr::Lvd1Lvl,
4287 Lvdlvlr_SPEC,
4288 crate::common::RW,
4289 > {
4290 crate::common::RegisterField::<
4291 0,
4292 0x1f,
4293 1,
4294 0,
4295 lvdlvlr::Lvd1Lvl,
4296 lvdlvlr::Lvd1Lvl,
4297 Lvdlvlr_SPEC,
4298 crate::common::RW,
4299 >::from_register(self, 0)
4300 }
4301
4302 #[doc = "Voltage Detection 2 Level Select (Standard voltage during fall in voltage)"]
4303 #[inline(always)]
4304 pub fn lvd2lvl(
4305 self,
4306 ) -> crate::common::RegisterField<
4307 5,
4308 0x7,
4309 1,
4310 0,
4311 lvdlvlr::Lvd2Lvl,
4312 lvdlvlr::Lvd2Lvl,
4313 Lvdlvlr_SPEC,
4314 crate::common::RW,
4315 > {
4316 crate::common::RegisterField::<
4317 5,
4318 0x7,
4319 1,
4320 0,
4321 lvdlvlr::Lvd2Lvl,
4322 lvdlvlr::Lvd2Lvl,
4323 Lvdlvlr_SPEC,
4324 crate::common::RW,
4325 >::from_register(self, 0)
4326 }
4327}
4328impl ::core::default::Default for Lvdlvlr {
4329 #[inline(always)]
4330 fn default() -> Lvdlvlr {
4331 <crate::RegValueT<Lvdlvlr_SPEC> as RegisterValue<_>>::new(7)
4332 }
4333}
4334pub mod lvdlvlr {
4335
4336 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4337 pub struct Lvd1Lvl_SPEC;
4338 pub type Lvd1Lvl = crate::EnumBitfieldStruct<u8, Lvd1Lvl_SPEC>;
4339 impl Lvd1Lvl {
4340 #[doc = "Vdet1_0"]
4341 pub const _0_X_00: Self = Self::new(0);
4342
4343 #[doc = "Vdet1_1"]
4344 pub const _0_X_01: Self = Self::new(1);
4345
4346 #[doc = "Vdet1_2"]
4347 pub const _0_X_02: Self = Self::new(2);
4348
4349 #[doc = "Vdet1_3"]
4350 pub const _0_X_03: Self = Self::new(3);
4351
4352 #[doc = "Vdet1_4"]
4353 pub const _0_X_04: Self = Self::new(4);
4354
4355 #[doc = "Vdet1_5"]
4356 pub const _0_X_05: Self = Self::new(5);
4357
4358 #[doc = "Vdet1_6"]
4359 pub const _0_X_06: Self = Self::new(6);
4360
4361 #[doc = "Vdet1_7"]
4362 pub const _0_X_07: Self = Self::new(7);
4363
4364 #[doc = "Vdet1_8"]
4365 pub const _0_X_08: Self = Self::new(8);
4366
4367 #[doc = "Vdet1_9"]
4368 pub const _0_X_09: Self = Self::new(9);
4369
4370 #[doc = "Vdet1_A"]
4371 pub const _0_X_0_A: Self = Self::new(10);
4372
4373 #[doc = "Vdet1_B"]
4374 pub const _0_X_0_B: Self = Self::new(11);
4375
4376 #[doc = "Vdet1_C"]
4377 pub const _0_X_0_C: Self = Self::new(12);
4378
4379 #[doc = "Vdet1_D"]
4380 pub const _0_X_0_D: Self = Self::new(13);
4381
4382 #[doc = "Vdet1_E"]
4383 pub const _0_X_0_E: Self = Self::new(14);
4384
4385 #[doc = "Vdet1_F"]
4386 pub const _0_X_0_F: Self = Self::new(15);
4387 }
4388 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4389 pub struct Lvd2Lvl_SPEC;
4390 pub type Lvd2Lvl = crate::EnumBitfieldStruct<u8, Lvd2Lvl_SPEC>;
4391 impl Lvd2Lvl {
4392 #[doc = "Vdet2_0"]
4393 pub const _000: Self = Self::new(0);
4394
4395 #[doc = "Vdet2_1"]
4396 pub const _001: Self = Self::new(1);
4397
4398 #[doc = "Vdet2_2"]
4399 pub const _010: Self = Self::new(2);
4400
4401 #[doc = "Vdet2_3"]
4402 pub const _011: Self = Self::new(3);
4403 }
4404}
4405#[doc(hidden)]
4406#[derive(Copy, Clone, Eq, PartialEq)]
4407pub struct Lvd1Cr0_SPEC;
4408impl crate::sealed::RegSpec for Lvd1Cr0_SPEC {
4409 type DataType = u8;
4410}
4411
4412#[doc = "Voltage Monitor 1 Circuit Control Register 0"]
4413pub type Lvd1Cr0 = crate::RegValueT<Lvd1Cr0_SPEC>;
4414
4415impl Lvd1Cr0 {
4416 #[doc = "Voltage Monitor 1 Interrupt/Reset Enable"]
4417 #[inline(always)]
4418 pub fn rie(
4419 self,
4420 ) -> crate::common::RegisterField<
4421 0,
4422 0x1,
4423 1,
4424 0,
4425 lvd1cr0::Rie,
4426 lvd1cr0::Rie,
4427 Lvd1Cr0_SPEC,
4428 crate::common::RW,
4429 > {
4430 crate::common::RegisterField::<
4431 0,
4432 0x1,
4433 1,
4434 0,
4435 lvd1cr0::Rie,
4436 lvd1cr0::Rie,
4437 Lvd1Cr0_SPEC,
4438 crate::common::RW,
4439 >::from_register(self, 0)
4440 }
4441
4442 #[doc = "Voltage Monitor 1 Circuit Comparison Result Output Enable"]
4443 #[inline(always)]
4444 pub fn cmpe(
4445 self,
4446 ) -> crate::common::RegisterField<
4447 2,
4448 0x1,
4449 1,
4450 0,
4451 lvd1cr0::Cmpe,
4452 lvd1cr0::Cmpe,
4453 Lvd1Cr0_SPEC,
4454 crate::common::RW,
4455 > {
4456 crate::common::RegisterField::<
4457 2,
4458 0x1,
4459 1,
4460 0,
4461 lvd1cr0::Cmpe,
4462 lvd1cr0::Cmpe,
4463 Lvd1Cr0_SPEC,
4464 crate::common::RW,
4465 >::from_register(self, 0)
4466 }
4467
4468 #[doc = "Voltage Monitor 1 Circuit Mode Select"]
4469 #[inline(always)]
4470 pub fn ri(
4471 self,
4472 ) -> crate::common::RegisterField<
4473 6,
4474 0x1,
4475 1,
4476 0,
4477 lvd1cr0::Ri,
4478 lvd1cr0::Ri,
4479 Lvd1Cr0_SPEC,
4480 crate::common::RW,
4481 > {
4482 crate::common::RegisterField::<
4483 6,
4484 0x1,
4485 1,
4486 0,
4487 lvd1cr0::Ri,
4488 lvd1cr0::Ri,
4489 Lvd1Cr0_SPEC,
4490 crate::common::RW,
4491 >::from_register(self, 0)
4492 }
4493
4494 #[doc = "Voltage Monitor 1 Reset Negate Select"]
4495 #[inline(always)]
4496 pub fn rn(
4497 self,
4498 ) -> crate::common::RegisterField<
4499 7,
4500 0x1,
4501 1,
4502 0,
4503 lvd1cr0::Rn,
4504 lvd1cr0::Rn,
4505 Lvd1Cr0_SPEC,
4506 crate::common::RW,
4507 > {
4508 crate::common::RegisterField::<
4509 7,
4510 0x1,
4511 1,
4512 0,
4513 lvd1cr0::Rn,
4514 lvd1cr0::Rn,
4515 Lvd1Cr0_SPEC,
4516 crate::common::RW,
4517 >::from_register(self, 0)
4518 }
4519}
4520impl ::core::default::Default for Lvd1Cr0 {
4521 #[inline(always)]
4522 fn default() -> Lvd1Cr0 {
4523 <crate::RegValueT<Lvd1Cr0_SPEC> as RegisterValue<_>>::new(128)
4524 }
4525}
4526pub mod lvd1cr0 {
4527
4528 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4529 pub struct Rie_SPEC;
4530 pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
4531 impl Rie {
4532 #[doc = "Disable"]
4533 pub const _0: Self = Self::new(0);
4534
4535 #[doc = "Enable"]
4536 pub const _1: Self = Self::new(1);
4537 }
4538 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4539 pub struct Cmpe_SPEC;
4540 pub type Cmpe = crate::EnumBitfieldStruct<u8, Cmpe_SPEC>;
4541 impl Cmpe {
4542 #[doc = "Disable voltage monitor 1 circuit comparison result output"]
4543 pub const _0: Self = Self::new(0);
4544
4545 #[doc = "Enable voltage monitor 1 circuit comparison result output"]
4546 pub const _1: Self = Self::new(1);
4547 }
4548 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4549 pub struct Ri_SPEC;
4550 pub type Ri = crate::EnumBitfieldStruct<u8, Ri_SPEC>;
4551 impl Ri {
4552 #[doc = "Generate voltage monitor 1 interrupt on Vdet1 crossing"]
4553 pub const _0: Self = Self::new(0);
4554
4555 #[doc = "Enable voltage monitor 1 reset when the voltage falls to and below Vdet1"]
4556 pub const _1: Self = Self::new(1);
4557 }
4558 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4559 pub struct Rn_SPEC;
4560 pub type Rn = crate::EnumBitfieldStruct<u8, Rn_SPEC>;
4561 impl Rn {
4562 #[doc = "Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected"]
4563 pub const _0: Self = Self::new(0);
4564
4565 #[doc = "Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset"]
4566 pub const _1: Self = Self::new(1);
4567 }
4568}
4569#[doc(hidden)]
4570#[derive(Copy, Clone, Eq, PartialEq)]
4571pub struct Lvd2Cr0_SPEC;
4572impl crate::sealed::RegSpec for Lvd2Cr0_SPEC {
4573 type DataType = u8;
4574}
4575
4576#[doc = "Voltage Monitor 2 Circuit Control Register 0"]
4577pub type Lvd2Cr0 = crate::RegValueT<Lvd2Cr0_SPEC>;
4578
4579impl Lvd2Cr0 {
4580 #[doc = "Voltage Monitor 2 Interrupt/Reset Enable"]
4581 #[inline(always)]
4582 pub fn rie(
4583 self,
4584 ) -> crate::common::RegisterField<
4585 0,
4586 0x1,
4587 1,
4588 0,
4589 lvd2cr0::Rie,
4590 lvd2cr0::Rie,
4591 Lvd2Cr0_SPEC,
4592 crate::common::RW,
4593 > {
4594 crate::common::RegisterField::<
4595 0,
4596 0x1,
4597 1,
4598 0,
4599 lvd2cr0::Rie,
4600 lvd2cr0::Rie,
4601 Lvd2Cr0_SPEC,
4602 crate::common::RW,
4603 >::from_register(self, 0)
4604 }
4605
4606 #[doc = "Voltage Monitor 2 Circuit Comparison Result Output Enable"]
4607 #[inline(always)]
4608 pub fn cmpe(
4609 self,
4610 ) -> crate::common::RegisterField<
4611 2,
4612 0x1,
4613 1,
4614 0,
4615 lvd2cr0::Cmpe,
4616 lvd2cr0::Cmpe,
4617 Lvd2Cr0_SPEC,
4618 crate::common::RW,
4619 > {
4620 crate::common::RegisterField::<
4621 2,
4622 0x1,
4623 1,
4624 0,
4625 lvd2cr0::Cmpe,
4626 lvd2cr0::Cmpe,
4627 Lvd2Cr0_SPEC,
4628 crate::common::RW,
4629 >::from_register(self, 0)
4630 }
4631
4632 #[doc = "Voltage Monitor 2 Circuit Mode Select"]
4633 #[inline(always)]
4634 pub fn ri(
4635 self,
4636 ) -> crate::common::RegisterField<
4637 6,
4638 0x1,
4639 1,
4640 0,
4641 lvd2cr0::Ri,
4642 lvd2cr0::Ri,
4643 Lvd2Cr0_SPEC,
4644 crate::common::RW,
4645 > {
4646 crate::common::RegisterField::<
4647 6,
4648 0x1,
4649 1,
4650 0,
4651 lvd2cr0::Ri,
4652 lvd2cr0::Ri,
4653 Lvd2Cr0_SPEC,
4654 crate::common::RW,
4655 >::from_register(self, 0)
4656 }
4657
4658 #[doc = "Voltage Monitor 2 Reset Negate Select"]
4659 #[inline(always)]
4660 pub fn rn(
4661 self,
4662 ) -> crate::common::RegisterField<
4663 7,
4664 0x1,
4665 1,
4666 0,
4667 lvd2cr0::Rn,
4668 lvd2cr0::Rn,
4669 Lvd2Cr0_SPEC,
4670 crate::common::RW,
4671 > {
4672 crate::common::RegisterField::<
4673 7,
4674 0x1,
4675 1,
4676 0,
4677 lvd2cr0::Rn,
4678 lvd2cr0::Rn,
4679 Lvd2Cr0_SPEC,
4680 crate::common::RW,
4681 >::from_register(self, 0)
4682 }
4683}
4684impl ::core::default::Default for Lvd2Cr0 {
4685 #[inline(always)]
4686 fn default() -> Lvd2Cr0 {
4687 <crate::RegValueT<Lvd2Cr0_SPEC> as RegisterValue<_>>::new(128)
4688 }
4689}
4690pub mod lvd2cr0 {
4691
4692 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4693 pub struct Rie_SPEC;
4694 pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
4695 impl Rie {
4696 #[doc = "Disable"]
4697 pub const _0: Self = Self::new(0);
4698
4699 #[doc = "Enable"]
4700 pub const _1: Self = Self::new(1);
4701 }
4702 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4703 pub struct Cmpe_SPEC;
4704 pub type Cmpe = crate::EnumBitfieldStruct<u8, Cmpe_SPEC>;
4705 impl Cmpe {
4706 #[doc = "Disable voltage monitor 2 circuit comparison result output"]
4707 pub const _0: Self = Self::new(0);
4708
4709 #[doc = "Enable voltage monitor 2 circuit comparison result output"]
4710 pub const _1: Self = Self::new(1);
4711 }
4712 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4713 pub struct Ri_SPEC;
4714 pub type Ri = crate::EnumBitfieldStruct<u8, Ri_SPEC>;
4715 impl Ri {
4716 #[doc = "Generate voltage monitor 2 interrupt on Vdet2 crossing"]
4717 pub const _0: Self = Self::new(0);
4718
4719 #[doc = "Enable voltage monitor 2 reset when the voltage falls to and below Vdet2"]
4720 pub const _1: Self = Self::new(1);
4721 }
4722 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4723 pub struct Rn_SPEC;
4724 pub type Rn = crate::EnumBitfieldStruct<u8, Rn_SPEC>;
4725 impl Rn {
4726 #[doc = "Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected"]
4727 pub const _0: Self = Self::new(0);
4728
4729 #[doc = "Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset"]
4730 pub const _1: Self = Self::new(1);
4731 }
4732}
4733#[doc(hidden)]
4734#[derive(Copy, Clone, Eq, PartialEq)]
4735pub struct Dcdcctl_SPEC;
4736impl crate::sealed::RegSpec for Dcdcctl_SPEC {
4737 type DataType = u8;
4738}
4739
4740#[doc = "DCDC/LDO Control Register"]
4741pub type Dcdcctl = crate::RegValueT<Dcdcctl_SPEC>;
4742
4743impl Dcdcctl {
4744 #[doc = "LDO/DCDC on/off Control bit"]
4745 #[inline(always)]
4746 pub fn dcdcon(
4747 self,
4748 ) -> crate::common::RegisterField<
4749 0,
4750 0x1,
4751 1,
4752 0,
4753 dcdcctl::Dcdcon,
4754 dcdcctl::Dcdcon,
4755 Dcdcctl_SPEC,
4756 crate::common::RW,
4757 > {
4758 crate::common::RegisterField::<
4759 0,
4760 0x1,
4761 1,
4762 0,
4763 dcdcctl::Dcdcon,
4764 dcdcctl::Dcdcon,
4765 Dcdcctl_SPEC,
4766 crate::common::RW,
4767 >::from_register(self, 0)
4768 }
4769
4770 #[doc = "DCDC OCP Function Enable bit"]
4771 #[inline(always)]
4772 pub fn ocpen(
4773 self,
4774 ) -> crate::common::RegisterField<
4775 1,
4776 0x1,
4777 1,
4778 0,
4779 dcdcctl::Ocpen,
4780 dcdcctl::Ocpen,
4781 Dcdcctl_SPEC,
4782 crate::common::RW,
4783 > {
4784 crate::common::RegisterField::<
4785 1,
4786 0x1,
4787 1,
4788 0,
4789 dcdcctl::Ocpen,
4790 dcdcctl::Ocpen,
4791 Dcdcctl_SPEC,
4792 crate::common::RW,
4793 >::from_register(self, 0)
4794 }
4795
4796 #[doc = "DCDC IO Buffer Power Control bit"]
4797 #[inline(always)]
4798 pub fn stopza(
4799 self,
4800 ) -> crate::common::RegisterField<
4801 4,
4802 0x1,
4803 1,
4804 0,
4805 dcdcctl::Stopza,
4806 dcdcctl::Stopza,
4807 Dcdcctl_SPEC,
4808 crate::common::RW,
4809 > {
4810 crate::common::RegisterField::<
4811 4,
4812 0x1,
4813 1,
4814 0,
4815 dcdcctl::Stopza,
4816 dcdcctl::Stopza,
4817 Dcdcctl_SPEC,
4818 crate::common::RW,
4819 >::from_register(self, 0)
4820 }
4821
4822 #[doc = "LDO LCBOOST Mode Control bit"]
4823 #[inline(always)]
4824 pub fn lcboost(
4825 self,
4826 ) -> crate::common::RegisterField<
4827 5,
4828 0x1,
4829 1,
4830 0,
4831 dcdcctl::Lcboost,
4832 dcdcctl::Lcboost,
4833 Dcdcctl_SPEC,
4834 crate::common::RW,
4835 > {
4836 crate::common::RegisterField::<
4837 5,
4838 0x1,
4839 1,
4840 0,
4841 dcdcctl::Lcboost,
4842 dcdcctl::Lcboost,
4843 Dcdcctl_SPEC,
4844 crate::common::RW,
4845 >::from_register(self, 0)
4846 }
4847
4848 #[doc = "DCDC Fast Startup"]
4849 #[inline(always)]
4850 pub fn fst(
4851 self,
4852 ) -> crate::common::RegisterField<
4853 6,
4854 0x1,
4855 1,
4856 0,
4857 dcdcctl::Fst,
4858 dcdcctl::Fst,
4859 Dcdcctl_SPEC,
4860 crate::common::RW,
4861 > {
4862 crate::common::RegisterField::<
4863 6,
4864 0x1,
4865 1,
4866 0,
4867 dcdcctl::Fst,
4868 dcdcctl::Fst,
4869 Dcdcctl_SPEC,
4870 crate::common::RW,
4871 >::from_register(self, 0)
4872 }
4873
4874 #[doc = "DCDC VREF Generate Disable bit"]
4875 #[inline(always)]
4876 pub fn pd(
4877 self,
4878 ) -> crate::common::RegisterField<
4879 7,
4880 0x1,
4881 1,
4882 0,
4883 dcdcctl::Pd,
4884 dcdcctl::Pd,
4885 Dcdcctl_SPEC,
4886 crate::common::RW,
4887 > {
4888 crate::common::RegisterField::<
4889 7,
4890 0x1,
4891 1,
4892 0,
4893 dcdcctl::Pd,
4894 dcdcctl::Pd,
4895 Dcdcctl_SPEC,
4896 crate::common::RW,
4897 >::from_register(self, 0)
4898 }
4899}
4900impl ::core::default::Default for Dcdcctl {
4901 #[inline(always)]
4902 fn default() -> Dcdcctl {
4903 <crate::RegValueT<Dcdcctl_SPEC> as RegisterValue<_>>::new(192)
4904 }
4905}
4906pub mod dcdcctl {
4907
4908 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4909 pub struct Dcdcon_SPEC;
4910 pub type Dcdcon = crate::EnumBitfieldStruct<u8, Dcdcon_SPEC>;
4911 impl Dcdcon {
4912 #[doc = "LDO is on and DCDC is off"]
4913 pub const _0: Self = Self::new(0);
4914
4915 #[doc = "LDO is off and DCDC is on"]
4916 pub const _1: Self = Self::new(1);
4917 }
4918 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4919 pub struct Ocpen_SPEC;
4920 pub type Ocpen = crate::EnumBitfieldStruct<u8, Ocpen_SPEC>;
4921 impl Ocpen {
4922 #[doc = "DCDC OCP (Over Current Protection) Function disable"]
4923 pub const _0: Self = Self::new(0);
4924
4925 #[doc = "DCDC OCP (Over Current Protection) Function enable"]
4926 pub const _1: Self = Self::new(1);
4927 }
4928 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4929 pub struct Stopza_SPEC;
4930 pub type Stopza = crate::EnumBitfieldStruct<u8, Stopza_SPEC>;
4931 impl Stopza {
4932 #[doc = "DCDC IO buffer power down"]
4933 pub const _0: Self = Self::new(0);
4934
4935 #[doc = "DCDC IO buffer power up"]
4936 pub const _1: Self = Self::new(1);
4937 }
4938 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4939 pub struct Lcboost_SPEC;
4940 pub type Lcboost = crate::EnumBitfieldStruct<u8, Lcboost_SPEC>;
4941 impl Lcboost {
4942 #[doc = "LDO power mode is other than LCBOOST"]
4943 pub const _0: Self = Self::new(0);
4944
4945 #[doc = "LDO power mode is in LCBOOST"]
4946 pub const _1: Self = Self::new(1);
4947 }
4948 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4949 pub struct Fst_SPEC;
4950 pub type Fst = crate::EnumBitfieldStruct<u8, Fst_SPEC>;
4951 impl Fst {
4952 #[doc = "Fast startupBecause it is a circuit-oriented expression, it is hard to understand. Reexamination of expression is necessary."]
4953 pub const _0: Self = Self::new(0);
4954
4955 #[doc = "Not fast startupBecause it is a circuit-oriented expression, it is hard to understand. Reexamination of expression is necessary."]
4956 pub const _1: Self = Self::new(1);
4957 }
4958 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4959 pub struct Pd_SPEC;
4960 pub type Pd = crate::EnumBitfieldStruct<u8, Pd_SPEC>;
4961 impl Pd {
4962 #[doc = "DCDC VREF BIAS output enable"]
4963 pub const _0: Self = Self::new(0);
4964
4965 #[doc = "DCDC VREF BIAS output disable"]
4966 pub const _1: Self = Self::new(1);
4967 }
4968}
4969#[doc(hidden)]
4970#[derive(Copy, Clone, Eq, PartialEq)]
4971pub struct Vccsel_SPEC;
4972impl crate::sealed::RegSpec for Vccsel_SPEC {
4973 type DataType = u8;
4974}
4975
4976#[doc = "Voltage Level Selection Control Register"]
4977pub type Vccsel = crate::RegValueT<Vccsel_SPEC>;
4978
4979impl Vccsel {
4980 #[doc = "DCDC Working Voltage Level Selection"]
4981 #[inline(always)]
4982 pub fn vccsel(
4983 self,
4984 ) -> crate::common::RegisterField<
4985 0,
4986 0x3,
4987 1,
4988 0,
4989 vccsel::Vccsel,
4990 vccsel::Vccsel,
4991 Vccsel_SPEC,
4992 crate::common::RW,
4993 > {
4994 crate::common::RegisterField::<
4995 0,
4996 0x3,
4997 1,
4998 0,
4999 vccsel::Vccsel,
5000 vccsel::Vccsel,
5001 Vccsel_SPEC,
5002 crate::common::RW,
5003 >::from_register(self, 0)
5004 }
5005}
5006impl ::core::default::Default for Vccsel {
5007 #[inline(always)]
5008 fn default() -> Vccsel {
5009 <crate::RegValueT<Vccsel_SPEC> as RegisterValue<_>>::new(0)
5010 }
5011}
5012pub mod vccsel {
5013
5014 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5015 pub struct Vccsel_SPEC;
5016 pub type Vccsel = crate::EnumBitfieldStruct<u8, Vccsel_SPEC>;
5017 impl Vccsel {
5018 #[doc = "2.7 V =< VCC < 3.6 V"]
5019 pub const _00: Self = Self::new(0);
5020
5021 #[doc = "3.6 V =< VCC < 4.5 V"]
5022 pub const _01: Self = Self::new(1);
5023
5024 #[doc = "4.5 V =< VCC ≤ 5.5 V"]
5025 pub const _10: Self = Self::new(2);
5026
5027 #[doc = "2.4 V =< VCC < 2.7 V"]
5028 pub const _11: Self = Self::new(3);
5029 }
5030}
5031#[doc(hidden)]
5032#[derive(Copy, Clone, Eq, PartialEq)]
5033pub struct Sosccr_SPEC;
5034impl crate::sealed::RegSpec for Sosccr_SPEC {
5035 type DataType = u8;
5036}
5037
5038#[doc = "Sub-Clock Oscillator Control Register"]
5039pub type Sosccr = crate::RegValueT<Sosccr_SPEC>;
5040
5041impl Sosccr {
5042 #[doc = "Sub Clock Oscillator Stop"]
5043 #[inline(always)]
5044 pub fn sostp(
5045 self,
5046 ) -> crate::common::RegisterField<
5047 0,
5048 0x1,
5049 1,
5050 0,
5051 sosccr::Sostp,
5052 sosccr::Sostp,
5053 Sosccr_SPEC,
5054 crate::common::RW,
5055 > {
5056 crate::common::RegisterField::<
5057 0,
5058 0x1,
5059 1,
5060 0,
5061 sosccr::Sostp,
5062 sosccr::Sostp,
5063 Sosccr_SPEC,
5064 crate::common::RW,
5065 >::from_register(self, 0)
5066 }
5067}
5068impl ::core::default::Default for Sosccr {
5069 #[inline(always)]
5070 fn default() -> Sosccr {
5071 <crate::RegValueT<Sosccr_SPEC> as RegisterValue<_>>::new(1)
5072 }
5073}
5074pub mod sosccr {
5075
5076 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5077 pub struct Sostp_SPEC;
5078 pub type Sostp = crate::EnumBitfieldStruct<u8, Sostp_SPEC>;
5079 impl Sostp {
5080 #[doc = "Operate the sub-clock oscillator"]
5081 pub const _0: Self = Self::new(0);
5082
5083 #[doc = "Stop the sub-clock oscillator"]
5084 pub const _1: Self = Self::new(1);
5085 }
5086}
5087#[doc(hidden)]
5088#[derive(Copy, Clone, Eq, PartialEq)]
5089pub struct Somcr_SPEC;
5090impl crate::sealed::RegSpec for Somcr_SPEC {
5091 type DataType = u8;
5092}
5093
5094#[doc = "Sub-Clock Oscillator Mode Control Register"]
5095pub type Somcr = crate::RegValueT<Somcr_SPEC>;
5096
5097impl Somcr {
5098 #[doc = "Sub-Clock Oscillator Drive Capability Switching"]
5099 #[inline(always)]
5100 pub fn sodrv(
5101 self,
5102 ) -> crate::common::RegisterField<
5103 0,
5104 0x3,
5105 1,
5106 0,
5107 somcr::Sodrv,
5108 somcr::Sodrv,
5109 Somcr_SPEC,
5110 crate::common::RW,
5111 > {
5112 crate::common::RegisterField::<
5113 0,
5114 0x3,
5115 1,
5116 0,
5117 somcr::Sodrv,
5118 somcr::Sodrv,
5119 Somcr_SPEC,
5120 crate::common::RW,
5121 >::from_register(self, 0)
5122 }
5123}
5124impl ::core::default::Default for Somcr {
5125 #[inline(always)]
5126 fn default() -> Somcr {
5127 <crate::RegValueT<Somcr_SPEC> as RegisterValue<_>>::new(0)
5128 }
5129}
5130pub mod somcr {
5131
5132 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5133 pub struct Sodrv_SPEC;
5134 pub type Sodrv = crate::EnumBitfieldStruct<u8, Sodrv_SPEC>;
5135 impl Sodrv {
5136 #[doc = "Normal Mode"]
5137 pub const _00: Self = Self::new(0);
5138
5139 #[doc = "Low Power Mode 1"]
5140 pub const _01: Self = Self::new(1);
5141
5142 #[doc = "Low Power Mode 2"]
5143 pub const _10: Self = Self::new(2);
5144
5145 #[doc = "Low Power Mode 3"]
5146 pub const _11: Self = Self::new(3);
5147 }
5148}
5149#[doc(hidden)]
5150#[derive(Copy, Clone, Eq, PartialEq)]
5151pub struct Somrg_SPEC;
5152impl crate::sealed::RegSpec for Somrg_SPEC {
5153 type DataType = u8;
5154}
5155
5156#[doc = "Sub-Clock Oscillator Margin Check Register"]
5157pub type Somrg = crate::RegValueT<Somrg_SPEC>;
5158
5159impl Somrg {
5160 #[doc = "Sub Clock Oscillator Margin check Switching"]
5161 #[inline(always)]
5162 pub fn soscmrg(
5163 self,
5164 ) -> crate::common::RegisterField<
5165 0,
5166 0x3,
5167 1,
5168 0,
5169 somrg::Soscmrg,
5170 somrg::Soscmrg,
5171 Somrg_SPEC,
5172 crate::common::RW,
5173 > {
5174 crate::common::RegisterField::<
5175 0,
5176 0x3,
5177 1,
5178 0,
5179 somrg::Soscmrg,
5180 somrg::Soscmrg,
5181 Somrg_SPEC,
5182 crate::common::RW,
5183 >::from_register(self, 0)
5184 }
5185}
5186impl ::core::default::Default for Somrg {
5187 #[inline(always)]
5188 fn default() -> Somrg {
5189 <crate::RegValueT<Somrg_SPEC> as RegisterValue<_>>::new(0)
5190 }
5191}
5192pub mod somrg {
5193
5194 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5195 pub struct Soscmrg_SPEC;
5196 pub type Soscmrg = crate::EnumBitfieldStruct<u8, Soscmrg_SPEC>;
5197 impl Soscmrg {
5198 #[doc = "Normal Current"]
5199 pub const _00: Self = Self::new(0);
5200
5201 #[doc = "Lower Margin check"]
5202 pub const _01: Self = Self::new(1);
5203
5204 #[doc = "Upper Margin check"]
5205 pub const _10: Self = Self::new(2);
5206
5207 #[doc = "Setting prohibited"]
5208 pub const _11: Self = Self::new(3);
5209 }
5210}
5211#[doc(hidden)]
5212#[derive(Copy, Clone, Eq, PartialEq)]
5213pub struct Lococr_SPEC;
5214impl crate::sealed::RegSpec for Lococr_SPEC {
5215 type DataType = u8;
5216}
5217
5218#[doc = "Low-Speed On-Chip Oscillator Control Register"]
5219pub type Lococr = crate::RegValueT<Lococr_SPEC>;
5220
5221impl Lococr {
5222 #[doc = "LOCO Stop"]
5223 #[inline(always)]
5224 pub fn lcstp(
5225 self,
5226 ) -> crate::common::RegisterField<
5227 0,
5228 0x1,
5229 1,
5230 0,
5231 lococr::Lcstp,
5232 lococr::Lcstp,
5233 Lococr_SPEC,
5234 crate::common::RW,
5235 > {
5236 crate::common::RegisterField::<
5237 0,
5238 0x1,
5239 1,
5240 0,
5241 lococr::Lcstp,
5242 lococr::Lcstp,
5243 Lococr_SPEC,
5244 crate::common::RW,
5245 >::from_register(self, 0)
5246 }
5247}
5248impl ::core::default::Default for Lococr {
5249 #[inline(always)]
5250 fn default() -> Lococr {
5251 <crate::RegValueT<Lococr_SPEC> as RegisterValue<_>>::new(0)
5252 }
5253}
5254pub mod lococr {
5255
5256 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5257 pub struct Lcstp_SPEC;
5258 pub type Lcstp = crate::EnumBitfieldStruct<u8, Lcstp_SPEC>;
5259 impl Lcstp {
5260 #[doc = "Operate the LOCO clock"]
5261 pub const _0: Self = Self::new(0);
5262
5263 #[doc = "Stop the LOCO clock"]
5264 pub const _1: Self = Self::new(1);
5265 }
5266}
5267#[doc(hidden)]
5268#[derive(Copy, Clone, Eq, PartialEq)]
5269pub struct Locoutcr_SPEC;
5270impl crate::sealed::RegSpec for Locoutcr_SPEC {
5271 type DataType = u8;
5272}
5273
5274#[doc = "LOCO User Trimming Control Register"]
5275pub type Locoutcr = crate::RegValueT<Locoutcr_SPEC>;
5276
5277impl Locoutcr {
5278 #[doc = "LOCO User Trimming"]
5279 #[inline(always)]
5280 pub fn locoutrm(
5281 self,
5282 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Locoutcr_SPEC, crate::common::RW> {
5283 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Locoutcr_SPEC,crate::common::RW>::from_register(self,0)
5284 }
5285}
5286impl ::core::default::Default for Locoutcr {
5287 #[inline(always)]
5288 fn default() -> Locoutcr {
5289 <crate::RegValueT<Locoutcr_SPEC> as RegisterValue<_>>::new(0)
5290 }
5291}