ra2e3_pac/
pfs.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.20.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:02:40 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Pmn Pin Function Control Register"]
28unsafe impl ::core::marker::Send for super::Pfs {}
29unsafe impl ::core::marker::Sync for super::Pfs {}
30impl super::Pfs {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Port 00%s Pin Function Select Register"]
38    #[inline(always)]
39    pub const fn p00pfs(
40        &self,
41    ) -> &'static crate::common::ClusterRegisterArray<
42        crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW>,
43        3,
44        0x4,
45    > {
46        unsafe {
47            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
48        }
49    }
50    #[inline(always)]
51    pub const fn p000pfs(
52        &self,
53    ) -> &'static crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::P00Pfs_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(0x0usize),
57            )
58        }
59    }
60    #[inline(always)]
61    pub const fn p001pfs(
62        &self,
63    ) -> &'static crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW> {
64        unsafe {
65            crate::common::Reg::<self::P00Pfs_SPEC, crate::common::RW>::from_ptr(
66                self._svd2pac_as_ptr().add(0x4usize),
67            )
68        }
69    }
70    #[inline(always)]
71    pub const fn p002pfs(
72        &self,
73    ) -> &'static crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW> {
74        unsafe {
75            crate::common::Reg::<self::P00Pfs_SPEC, crate::common::RW>::from_ptr(
76                self._svd2pac_as_ptr().add(0x8usize),
77            )
78        }
79    }
80
81    #[doc = "Port 00%s Pin Function Select Register"]
82    #[inline(always)]
83    pub const fn p00pfs_ha(
84        &self,
85    ) -> &'static crate::common::ClusterRegisterArray<
86        crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW>,
87        3,
88        0x4,
89    > {
90        unsafe {
91            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x2usize))
92        }
93    }
94    #[inline(always)]
95    pub const fn p000pfs_ha(
96        &self,
97    ) -> &'static crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW> {
98        unsafe {
99            crate::common::Reg::<self::P00PfsHa_SPEC, crate::common::RW>::from_ptr(
100                self._svd2pac_as_ptr().add(0x2usize),
101            )
102        }
103    }
104    #[inline(always)]
105    pub const fn p001pfs_ha(
106        &self,
107    ) -> &'static crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW> {
108        unsafe {
109            crate::common::Reg::<self::P00PfsHa_SPEC, crate::common::RW>::from_ptr(
110                self._svd2pac_as_ptr().add(0x6usize),
111            )
112        }
113    }
114    #[inline(always)]
115    pub const fn p002pfs_ha(
116        &self,
117    ) -> &'static crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW> {
118        unsafe {
119            crate::common::Reg::<self::P00PfsHa_SPEC, crate::common::RW>::from_ptr(
120                self._svd2pac_as_ptr().add(0xausize),
121            )
122        }
123    }
124
125    #[doc = "Port 00%s Pin Function Select Register"]
126    #[inline(always)]
127    pub const fn p00pfs_by(
128        &self,
129    ) -> &'static crate::common::ClusterRegisterArray<
130        crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW>,
131        3,
132        0x4,
133    > {
134        unsafe {
135            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x3usize))
136        }
137    }
138    #[inline(always)]
139    pub const fn p000pfs_by(
140        &self,
141    ) -> &'static crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW> {
142        unsafe {
143            crate::common::Reg::<self::P00PfsBy_SPEC, crate::common::RW>::from_ptr(
144                self._svd2pac_as_ptr().add(0x3usize),
145            )
146        }
147    }
148    #[inline(always)]
149    pub const fn p001pfs_by(
150        &self,
151    ) -> &'static crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW> {
152        unsafe {
153            crate::common::Reg::<self::P00PfsBy_SPEC, crate::common::RW>::from_ptr(
154                self._svd2pac_as_ptr().add(0x7usize),
155            )
156        }
157    }
158    #[inline(always)]
159    pub const fn p002pfs_by(
160        &self,
161    ) -> &'static crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW> {
162        unsafe {
163            crate::common::Reg::<self::P00PfsBy_SPEC, crate::common::RW>::from_ptr(
164                self._svd2pac_as_ptr().add(0xbusize),
165            )
166        }
167    }
168
169    #[doc = "Port 0%s Pin Function Select Register"]
170    #[inline(always)]
171    pub const fn p0pfs(
172        &self,
173    ) -> &'static crate::common::ClusterRegisterArray<
174        crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW>,
175        6,
176        0x4,
177    > {
178        unsafe {
179            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x28usize))
180        }
181    }
182    #[inline(always)]
183    pub const fn p010pfs(
184        &self,
185    ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
186        unsafe {
187            crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
188                self._svd2pac_as_ptr().add(0x28usize),
189            )
190        }
191    }
192    #[inline(always)]
193    pub const fn p011pfs(
194        &self,
195    ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
196        unsafe {
197            crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
198                self._svd2pac_as_ptr().add(0x2cusize),
199            )
200        }
201    }
202    #[inline(always)]
203    pub const fn p012pfs(
204        &self,
205    ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
206        unsafe {
207            crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
208                self._svd2pac_as_ptr().add(0x30usize),
209            )
210        }
211    }
212    #[inline(always)]
213    pub const fn p013pfs(
214        &self,
215    ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
216        unsafe {
217            crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
218                self._svd2pac_as_ptr().add(0x34usize),
219            )
220        }
221    }
222    #[inline(always)]
223    pub const fn p014pfs(
224        &self,
225    ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
226        unsafe {
227            crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
228                self._svd2pac_as_ptr().add(0x38usize),
229            )
230        }
231    }
232    #[inline(always)]
233    pub const fn p015pfs(
234        &self,
235    ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
236        unsafe {
237            crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
238                self._svd2pac_as_ptr().add(0x3cusize),
239            )
240        }
241    }
242
243    #[doc = "Port 0%s Pin Function Select Register"]
244    #[inline(always)]
245    pub const fn p0pfs_ha(
246        &self,
247    ) -> &'static crate::common::ClusterRegisterArray<
248        crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW>,
249        6,
250        0x4,
251    > {
252        unsafe {
253            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x2ausize))
254        }
255    }
256    #[inline(always)]
257    pub const fn p010pfs_ha(
258        &self,
259    ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
260        unsafe {
261            crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
262                self._svd2pac_as_ptr().add(0x2ausize),
263            )
264        }
265    }
266    #[inline(always)]
267    pub const fn p011pfs_ha(
268        &self,
269    ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
270        unsafe {
271            crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
272                self._svd2pac_as_ptr().add(0x2eusize),
273            )
274        }
275    }
276    #[inline(always)]
277    pub const fn p012pfs_ha(
278        &self,
279    ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
280        unsafe {
281            crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
282                self._svd2pac_as_ptr().add(0x32usize),
283            )
284        }
285    }
286    #[inline(always)]
287    pub const fn p013pfs_ha(
288        &self,
289    ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
290        unsafe {
291            crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
292                self._svd2pac_as_ptr().add(0x36usize),
293            )
294        }
295    }
296    #[inline(always)]
297    pub const fn p014pfs_ha(
298        &self,
299    ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
300        unsafe {
301            crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
302                self._svd2pac_as_ptr().add(0x3ausize),
303            )
304        }
305    }
306    #[inline(always)]
307    pub const fn p015pfs_ha(
308        &self,
309    ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
310        unsafe {
311            crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
312                self._svd2pac_as_ptr().add(0x3eusize),
313            )
314        }
315    }
316
317    #[doc = "Port 0%s Pin Function Select Register"]
318    #[inline(always)]
319    pub const fn p0pfs_by(
320        &self,
321    ) -> &'static crate::common::ClusterRegisterArray<
322        crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW>,
323        6,
324        0x4,
325    > {
326        unsafe {
327            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x2busize))
328        }
329    }
330    #[inline(always)]
331    pub const fn p010pfs_by(
332        &self,
333    ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
334        unsafe {
335            crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
336                self._svd2pac_as_ptr().add(0x2busize),
337            )
338        }
339    }
340    #[inline(always)]
341    pub const fn p011pfs_by(
342        &self,
343    ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
344        unsafe {
345            crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
346                self._svd2pac_as_ptr().add(0x2fusize),
347            )
348        }
349    }
350    #[inline(always)]
351    pub const fn p012pfs_by(
352        &self,
353    ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
354        unsafe {
355            crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
356                self._svd2pac_as_ptr().add(0x33usize),
357            )
358        }
359    }
360    #[inline(always)]
361    pub const fn p013pfs_by(
362        &self,
363    ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
364        unsafe {
365            crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
366                self._svd2pac_as_ptr().add(0x37usize),
367            )
368        }
369    }
370    #[inline(always)]
371    pub const fn p014pfs_by(
372        &self,
373    ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
374        unsafe {
375            crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
376                self._svd2pac_as_ptr().add(0x3busize),
377            )
378        }
379    }
380    #[inline(always)]
381    pub const fn p015pfs_by(
382        &self,
383    ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
384        unsafe {
385            crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
386                self._svd2pac_as_ptr().add(0x3fusize),
387            )
388        }
389    }
390
391    #[doc = "Port 10%s Pin Function Select Register"]
392    #[inline(always)]
393    pub const fn p10pfs(
394        &self,
395    ) -> &'static crate::common::ClusterRegisterArray<
396        crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW>,
397        5,
398        0x4,
399    > {
400        unsafe {
401            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x40usize))
402        }
403    }
404    #[inline(always)]
405    pub const fn p100pfs(
406        &self,
407    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
408        unsafe {
409            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
410                self._svd2pac_as_ptr().add(0x40usize),
411            )
412        }
413    }
414    #[inline(always)]
415    pub const fn p101pfs(
416        &self,
417    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
418        unsafe {
419            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
420                self._svd2pac_as_ptr().add(0x44usize),
421            )
422        }
423    }
424    #[inline(always)]
425    pub const fn p102pfs(
426        &self,
427    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
428        unsafe {
429            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
430                self._svd2pac_as_ptr().add(0x48usize),
431            )
432        }
433    }
434    #[inline(always)]
435    pub const fn p103pfs(
436        &self,
437    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
438        unsafe {
439            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
440                self._svd2pac_as_ptr().add(0x4cusize),
441            )
442        }
443    }
444    #[inline(always)]
445    pub const fn p104pfs(
446        &self,
447    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
448        unsafe {
449            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
450                self._svd2pac_as_ptr().add(0x50usize),
451            )
452        }
453    }
454
455    #[doc = "Port 10%s Pin Function Select Register"]
456    #[inline(always)]
457    pub const fn p10pfs_ha(
458        &self,
459    ) -> &'static crate::common::ClusterRegisterArray<
460        crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW>,
461        5,
462        0x4,
463    > {
464        unsafe {
465            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x42usize))
466        }
467    }
468    #[inline(always)]
469    pub const fn p100pfs_ha(
470        &self,
471    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
472        unsafe {
473            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
474                self._svd2pac_as_ptr().add(0x42usize),
475            )
476        }
477    }
478    #[inline(always)]
479    pub const fn p101pfs_ha(
480        &self,
481    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
482        unsafe {
483            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
484                self._svd2pac_as_ptr().add(0x46usize),
485            )
486        }
487    }
488    #[inline(always)]
489    pub const fn p102pfs_ha(
490        &self,
491    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
492        unsafe {
493            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
494                self._svd2pac_as_ptr().add(0x4ausize),
495            )
496        }
497    }
498    #[inline(always)]
499    pub const fn p103pfs_ha(
500        &self,
501    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
502        unsafe {
503            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
504                self._svd2pac_as_ptr().add(0x4eusize),
505            )
506        }
507    }
508    #[inline(always)]
509    pub const fn p104pfs_ha(
510        &self,
511    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
512        unsafe {
513            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
514                self._svd2pac_as_ptr().add(0x52usize),
515            )
516        }
517    }
518
519    #[doc = "Port 10%s Pin Function Select Register"]
520    #[inline(always)]
521    pub const fn p10pfs_by(
522        &self,
523    ) -> &'static crate::common::ClusterRegisterArray<
524        crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW>,
525        5,
526        0x4,
527    > {
528        unsafe {
529            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x43usize))
530        }
531    }
532    #[inline(always)]
533    pub const fn p100pfs_by(
534        &self,
535    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
536        unsafe {
537            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
538                self._svd2pac_as_ptr().add(0x43usize),
539            )
540        }
541    }
542    #[inline(always)]
543    pub const fn p101pfs_by(
544        &self,
545    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
546        unsafe {
547            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
548                self._svd2pac_as_ptr().add(0x47usize),
549            )
550        }
551    }
552    #[inline(always)]
553    pub const fn p102pfs_by(
554        &self,
555    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
556        unsafe {
557            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
558                self._svd2pac_as_ptr().add(0x4busize),
559            )
560        }
561    }
562    #[inline(always)]
563    pub const fn p103pfs_by(
564        &self,
565    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
566        unsafe {
567            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
568                self._svd2pac_as_ptr().add(0x4fusize),
569            )
570        }
571    }
572    #[inline(always)]
573    pub const fn p104pfs_by(
574        &self,
575    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
576        unsafe {
577            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
578                self._svd2pac_as_ptr().add(0x53usize),
579            )
580        }
581    }
582
583    #[doc = "Port 108 Pin Function Select Register"]
584    #[inline(always)]
585    pub const fn p108pfs(
586        &self,
587    ) -> &'static crate::common::Reg<self::P108Pfs_SPEC, crate::common::RW> {
588        unsafe {
589            crate::common::Reg::<self::P108Pfs_SPEC, crate::common::RW>::from_ptr(
590                self._svd2pac_as_ptr().add(96usize),
591            )
592        }
593    }
594
595    #[doc = "Port 108 Pin Function Select Register"]
596    #[inline(always)]
597    pub const fn p108pfs_ha(
598        &self,
599    ) -> &'static crate::common::Reg<self::P108PfsHa_SPEC, crate::common::RW> {
600        unsafe {
601            crate::common::Reg::<self::P108PfsHa_SPEC, crate::common::RW>::from_ptr(
602                self._svd2pac_as_ptr().add(98usize),
603            )
604        }
605    }
606
607    #[doc = "Port 108 Pin Function Select Register"]
608    #[inline(always)]
609    pub const fn p108pfs_by(
610        &self,
611    ) -> &'static crate::common::Reg<self::P108PfsBy_SPEC, crate::common::RW> {
612        unsafe {
613            crate::common::Reg::<self::P108PfsBy_SPEC, crate::common::RW>::from_ptr(
614                self._svd2pac_as_ptr().add(99usize),
615            )
616        }
617    }
618
619    #[doc = "Port 109 Pin Function Select Register"]
620    #[inline(always)]
621    pub const fn p109pfs(
622        &self,
623    ) -> &'static crate::common::Reg<self::P109Pfs_SPEC, crate::common::RW> {
624        unsafe {
625            crate::common::Reg::<self::P109Pfs_SPEC, crate::common::RW>::from_ptr(
626                self._svd2pac_as_ptr().add(100usize),
627            )
628        }
629    }
630
631    #[doc = "Port 109 Pin Function Select Register"]
632    #[inline(always)]
633    pub const fn p109pfs_ha(
634        &self,
635    ) -> &'static crate::common::Reg<self::P109PfsHa_SPEC, crate::common::RW> {
636        unsafe {
637            crate::common::Reg::<self::P109PfsHa_SPEC, crate::common::RW>::from_ptr(
638                self._svd2pac_as_ptr().add(102usize),
639            )
640        }
641    }
642
643    #[doc = "Port 109 Pin Function Select Register"]
644    #[inline(always)]
645    pub const fn p109pfs_by(
646        &self,
647    ) -> &'static crate::common::Reg<self::P109PfsBy_SPEC, crate::common::RW> {
648        unsafe {
649            crate::common::Reg::<self::P109PfsBy_SPEC, crate::common::RW>::from_ptr(
650                self._svd2pac_as_ptr().add(103usize),
651            )
652        }
653    }
654
655    #[doc = "Port 1%s Pin Function Select Register"]
656    #[inline(always)]
657    pub const fn p1pfs(
658        &self,
659    ) -> &'static crate::common::ClusterRegisterArray<
660        crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW>,
661        3,
662        0x4,
663    > {
664        unsafe {
665            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x68usize))
666        }
667    }
668    #[inline(always)]
669    pub const fn p110pfs(
670        &self,
671    ) -> &'static crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW> {
672        unsafe {
673            crate::common::Reg::<self::P1Pfs_SPEC, crate::common::RW>::from_ptr(
674                self._svd2pac_as_ptr().add(0x68usize),
675            )
676        }
677    }
678    #[inline(always)]
679    pub const fn p111pfs(
680        &self,
681    ) -> &'static crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW> {
682        unsafe {
683            crate::common::Reg::<self::P1Pfs_SPEC, crate::common::RW>::from_ptr(
684                self._svd2pac_as_ptr().add(0x6cusize),
685            )
686        }
687    }
688    #[inline(always)]
689    pub const fn p112pfs(
690        &self,
691    ) -> &'static crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW> {
692        unsafe {
693            crate::common::Reg::<self::P1Pfs_SPEC, crate::common::RW>::from_ptr(
694                self._svd2pac_as_ptr().add(0x70usize),
695            )
696        }
697    }
698
699    #[doc = "Port 1%s Pin Function Select Register"]
700    #[inline(always)]
701    pub const fn p1pfs_ha(
702        &self,
703    ) -> &'static crate::common::ClusterRegisterArray<
704        crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW>,
705        3,
706        0x4,
707    > {
708        unsafe {
709            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x6ausize))
710        }
711    }
712    #[inline(always)]
713    pub const fn p110pfs_ha(
714        &self,
715    ) -> &'static crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW> {
716        unsafe {
717            crate::common::Reg::<self::P1PfsHa_SPEC, crate::common::RW>::from_ptr(
718                self._svd2pac_as_ptr().add(0x6ausize),
719            )
720        }
721    }
722    #[inline(always)]
723    pub const fn p111pfs_ha(
724        &self,
725    ) -> &'static crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW> {
726        unsafe {
727            crate::common::Reg::<self::P1PfsHa_SPEC, crate::common::RW>::from_ptr(
728                self._svd2pac_as_ptr().add(0x6eusize),
729            )
730        }
731    }
732    #[inline(always)]
733    pub const fn p112pfs_ha(
734        &self,
735    ) -> &'static crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW> {
736        unsafe {
737            crate::common::Reg::<self::P1PfsHa_SPEC, crate::common::RW>::from_ptr(
738                self._svd2pac_as_ptr().add(0x72usize),
739            )
740        }
741    }
742
743    #[doc = "Port 1%s Pin Function Select Register"]
744    #[inline(always)]
745    pub const fn p1pfs_by(
746        &self,
747    ) -> &'static crate::common::ClusterRegisterArray<
748        crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW>,
749        3,
750        0x4,
751    > {
752        unsafe {
753            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x6busize))
754        }
755    }
756    #[inline(always)]
757    pub const fn p110pfs_by(
758        &self,
759    ) -> &'static crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW> {
760        unsafe {
761            crate::common::Reg::<self::P1PfsBy_SPEC, crate::common::RW>::from_ptr(
762                self._svd2pac_as_ptr().add(0x6busize),
763            )
764        }
765    }
766    #[inline(always)]
767    pub const fn p111pfs_by(
768        &self,
769    ) -> &'static crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW> {
770        unsafe {
771            crate::common::Reg::<self::P1PfsBy_SPEC, crate::common::RW>::from_ptr(
772                self._svd2pac_as_ptr().add(0x6fusize),
773            )
774        }
775    }
776    #[inline(always)]
777    pub const fn p112pfs_by(
778        &self,
779    ) -> &'static crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW> {
780        unsafe {
781            crate::common::Reg::<self::P1PfsBy_SPEC, crate::common::RW>::from_ptr(
782                self._svd2pac_as_ptr().add(0x73usize),
783            )
784        }
785    }
786
787    #[doc = "Port 200 Pin Function Select Register"]
788    #[inline(always)]
789    pub const fn p200pfs(
790        &self,
791    ) -> &'static crate::common::Reg<self::P200Pfs_SPEC, crate::common::RW> {
792        unsafe {
793            crate::common::Reg::<self::P200Pfs_SPEC, crate::common::RW>::from_ptr(
794                self._svd2pac_as_ptr().add(128usize),
795            )
796        }
797    }
798
799    #[doc = "Port 200 Pin Function Select Register"]
800    #[inline(always)]
801    pub const fn p200pfs_ha(
802        &self,
803    ) -> &'static crate::common::Reg<self::P200PfsHa_SPEC, crate::common::RW> {
804        unsafe {
805            crate::common::Reg::<self::P200PfsHa_SPEC, crate::common::RW>::from_ptr(
806                self._svd2pac_as_ptr().add(130usize),
807            )
808        }
809    }
810
811    #[doc = "Port 200 Pin Function Select Register"]
812    #[inline(always)]
813    pub const fn p200pfs_by(
814        &self,
815    ) -> &'static crate::common::Reg<self::P200PfsBy_SPEC, crate::common::RW> {
816        unsafe {
817            crate::common::Reg::<self::P200PfsBy_SPEC, crate::common::RW>::from_ptr(
818                self._svd2pac_as_ptr().add(131usize),
819            )
820        }
821    }
822
823    #[doc = "Port 201 Pin Function Select Register"]
824    #[inline(always)]
825    pub const fn p201pfs(
826        &self,
827    ) -> &'static crate::common::Reg<self::P201Pfs_SPEC, crate::common::RW> {
828        unsafe {
829            crate::common::Reg::<self::P201Pfs_SPEC, crate::common::RW>::from_ptr(
830                self._svd2pac_as_ptr().add(132usize),
831            )
832        }
833    }
834
835    #[doc = "Port 201 Pin Function Select Register"]
836    #[inline(always)]
837    pub const fn p201pfs_ha(
838        &self,
839    ) -> &'static crate::common::Reg<self::P201PfsHa_SPEC, crate::common::RW> {
840        unsafe {
841            crate::common::Reg::<self::P201PfsHa_SPEC, crate::common::RW>::from_ptr(
842                self._svd2pac_as_ptr().add(134usize),
843            )
844        }
845    }
846
847    #[doc = "Port 201 Pin Function Select Register"]
848    #[inline(always)]
849    pub const fn p201pfs_by(
850        &self,
851    ) -> &'static crate::common::Reg<self::P201PfsBy_SPEC, crate::common::RW> {
852        unsafe {
853            crate::common::Reg::<self::P201PfsBy_SPEC, crate::common::RW>::from_ptr(
854                self._svd2pac_as_ptr().add(135usize),
855            )
856        }
857    }
858
859    #[doc = "Port 20%s Pin Function Select Register"]
860    #[inline(always)]
861    pub const fn p20pfs(
862        &self,
863    ) -> &'static crate::common::ClusterRegisterArray<
864        crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW>,
865        3,
866        0x4,
867    > {
868        unsafe {
869            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x98usize))
870        }
871    }
872    #[inline(always)]
873    pub const fn p206pfs(
874        &self,
875    ) -> &'static crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW> {
876        unsafe {
877            crate::common::Reg::<self::P20Pfs_SPEC, crate::common::RW>::from_ptr(
878                self._svd2pac_as_ptr().add(0x98usize),
879            )
880        }
881    }
882    #[inline(always)]
883    pub const fn p207pfs(
884        &self,
885    ) -> &'static crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW> {
886        unsafe {
887            crate::common::Reg::<self::P20Pfs_SPEC, crate::common::RW>::from_ptr(
888                self._svd2pac_as_ptr().add(0x9cusize),
889            )
890        }
891    }
892    #[inline(always)]
893    pub const fn p208pfs(
894        &self,
895    ) -> &'static crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW> {
896        unsafe {
897            crate::common::Reg::<self::P20Pfs_SPEC, crate::common::RW>::from_ptr(
898                self._svd2pac_as_ptr().add(0xa0usize),
899            )
900        }
901    }
902
903    #[doc = "Port 20%s Pin Function Select Register"]
904    #[inline(always)]
905    pub const fn p20pfs_ha(
906        &self,
907    ) -> &'static crate::common::ClusterRegisterArray<
908        crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW>,
909        3,
910        0x4,
911    > {
912        unsafe {
913            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x9ausize))
914        }
915    }
916    #[inline(always)]
917    pub const fn p206pfs_ha(
918        &self,
919    ) -> &'static crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW> {
920        unsafe {
921            crate::common::Reg::<self::P20PfsHa_SPEC, crate::common::RW>::from_ptr(
922                self._svd2pac_as_ptr().add(0x9ausize),
923            )
924        }
925    }
926    #[inline(always)]
927    pub const fn p207pfs_ha(
928        &self,
929    ) -> &'static crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW> {
930        unsafe {
931            crate::common::Reg::<self::P20PfsHa_SPEC, crate::common::RW>::from_ptr(
932                self._svd2pac_as_ptr().add(0x9eusize),
933            )
934        }
935    }
936    #[inline(always)]
937    pub const fn p208pfs_ha(
938        &self,
939    ) -> &'static crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW> {
940        unsafe {
941            crate::common::Reg::<self::P20PfsHa_SPEC, crate::common::RW>::from_ptr(
942                self._svd2pac_as_ptr().add(0xa2usize),
943            )
944        }
945    }
946
947    #[doc = "Port 20%s Pin Function Select Register"]
948    #[inline(always)]
949    pub const fn p20pfs_by(
950        &self,
951    ) -> &'static crate::common::ClusterRegisterArray<
952        crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW>,
953        3,
954        0x4,
955    > {
956        unsafe {
957            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x9busize))
958        }
959    }
960    #[inline(always)]
961    pub const fn p206pfs_by(
962        &self,
963    ) -> &'static crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW> {
964        unsafe {
965            crate::common::Reg::<self::P20PfsBy_SPEC, crate::common::RW>::from_ptr(
966                self._svd2pac_as_ptr().add(0x9busize),
967            )
968        }
969    }
970    #[inline(always)]
971    pub const fn p207pfs_by(
972        &self,
973    ) -> &'static crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW> {
974        unsafe {
975            crate::common::Reg::<self::P20PfsBy_SPEC, crate::common::RW>::from_ptr(
976                self._svd2pac_as_ptr().add(0x9fusize),
977            )
978        }
979    }
980    #[inline(always)]
981    pub const fn p208pfs_by(
982        &self,
983    ) -> &'static crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW> {
984        unsafe {
985            crate::common::Reg::<self::P20PfsBy_SPEC, crate::common::RW>::from_ptr(
986                self._svd2pac_as_ptr().add(0xa3usize),
987            )
988        }
989    }
990
991    #[doc = "Port 2%s Pin Function Select Register"]
992    #[inline(always)]
993    pub const fn p2pfs(
994        &self,
995    ) -> &'static crate::common::ClusterRegisterArray<
996        crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW>,
997        4,
998        0x4,
999    > {
1000        unsafe {
1001            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xb0usize))
1002        }
1003    }
1004    #[inline(always)]
1005    pub const fn p212pfs(
1006        &self,
1007    ) -> &'static crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW> {
1008        unsafe {
1009            crate::common::Reg::<self::P2Pfs_SPEC, crate::common::RW>::from_ptr(
1010                self._svd2pac_as_ptr().add(0xb0usize),
1011            )
1012        }
1013    }
1014    #[inline(always)]
1015    pub const fn p213pfs(
1016        &self,
1017    ) -> &'static crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW> {
1018        unsafe {
1019            crate::common::Reg::<self::P2Pfs_SPEC, crate::common::RW>::from_ptr(
1020                self._svd2pac_as_ptr().add(0xb4usize),
1021            )
1022        }
1023    }
1024    #[inline(always)]
1025    pub const fn p214pfs(
1026        &self,
1027    ) -> &'static crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW> {
1028        unsafe {
1029            crate::common::Reg::<self::P2Pfs_SPEC, crate::common::RW>::from_ptr(
1030                self._svd2pac_as_ptr().add(0xb8usize),
1031            )
1032        }
1033    }
1034    #[inline(always)]
1035    pub const fn p215pfs(
1036        &self,
1037    ) -> &'static crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW> {
1038        unsafe {
1039            crate::common::Reg::<self::P2Pfs_SPEC, crate::common::RW>::from_ptr(
1040                self._svd2pac_as_ptr().add(0xbcusize),
1041            )
1042        }
1043    }
1044
1045    #[doc = "Port 2%s Pin Function Select Register"]
1046    #[inline(always)]
1047    pub const fn p2pfs_ha(
1048        &self,
1049    ) -> &'static crate::common::ClusterRegisterArray<
1050        crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW>,
1051        4,
1052        0x4,
1053    > {
1054        unsafe {
1055            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xb2usize))
1056        }
1057    }
1058    #[inline(always)]
1059    pub const fn p212pfs_ha(
1060        &self,
1061    ) -> &'static crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW> {
1062        unsafe {
1063            crate::common::Reg::<self::P2PfsHa_SPEC, crate::common::RW>::from_ptr(
1064                self._svd2pac_as_ptr().add(0xb2usize),
1065            )
1066        }
1067    }
1068    #[inline(always)]
1069    pub const fn p213pfs_ha(
1070        &self,
1071    ) -> &'static crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW> {
1072        unsafe {
1073            crate::common::Reg::<self::P2PfsHa_SPEC, crate::common::RW>::from_ptr(
1074                self._svd2pac_as_ptr().add(0xb6usize),
1075            )
1076        }
1077    }
1078    #[inline(always)]
1079    pub const fn p214pfs_ha(
1080        &self,
1081    ) -> &'static crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW> {
1082        unsafe {
1083            crate::common::Reg::<self::P2PfsHa_SPEC, crate::common::RW>::from_ptr(
1084                self._svd2pac_as_ptr().add(0xbausize),
1085            )
1086        }
1087    }
1088    #[inline(always)]
1089    pub const fn p215pfs_ha(
1090        &self,
1091    ) -> &'static crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW> {
1092        unsafe {
1093            crate::common::Reg::<self::P2PfsHa_SPEC, crate::common::RW>::from_ptr(
1094                self._svd2pac_as_ptr().add(0xbeusize),
1095            )
1096        }
1097    }
1098
1099    #[doc = "Port 2%s Pin Function Select Register"]
1100    #[inline(always)]
1101    pub const fn p2pfs_by(
1102        &self,
1103    ) -> &'static crate::common::ClusterRegisterArray<
1104        crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW>,
1105        4,
1106        0x4,
1107    > {
1108        unsafe {
1109            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xb3usize))
1110        }
1111    }
1112    #[inline(always)]
1113    pub const fn p212pfs_by(
1114        &self,
1115    ) -> &'static crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW> {
1116        unsafe {
1117            crate::common::Reg::<self::P2PfsBy_SPEC, crate::common::RW>::from_ptr(
1118                self._svd2pac_as_ptr().add(0xb3usize),
1119            )
1120        }
1121    }
1122    #[inline(always)]
1123    pub const fn p213pfs_by(
1124        &self,
1125    ) -> &'static crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW> {
1126        unsafe {
1127            crate::common::Reg::<self::P2PfsBy_SPEC, crate::common::RW>::from_ptr(
1128                self._svd2pac_as_ptr().add(0xb7usize),
1129            )
1130        }
1131    }
1132    #[inline(always)]
1133    pub const fn p214pfs_by(
1134        &self,
1135    ) -> &'static crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW> {
1136        unsafe {
1137            crate::common::Reg::<self::P2PfsBy_SPEC, crate::common::RW>::from_ptr(
1138                self._svd2pac_as_ptr().add(0xbbusize),
1139            )
1140        }
1141    }
1142    #[inline(always)]
1143    pub const fn p215pfs_by(
1144        &self,
1145    ) -> &'static crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW> {
1146        unsafe {
1147            crate::common::Reg::<self::P2PfsBy_SPEC, crate::common::RW>::from_ptr(
1148                self._svd2pac_as_ptr().add(0xbfusize),
1149            )
1150        }
1151    }
1152
1153    #[doc = "Port 300 Pin Function Select Register"]
1154    #[inline(always)]
1155    pub const fn p300pfs(
1156        &self,
1157    ) -> &'static crate::common::Reg<self::P300Pfs_SPEC, crate::common::RW> {
1158        unsafe {
1159            crate::common::Reg::<self::P300Pfs_SPEC, crate::common::RW>::from_ptr(
1160                self._svd2pac_as_ptr().add(192usize),
1161            )
1162        }
1163    }
1164
1165    #[doc = "Port 300 Pin Function Select Register"]
1166    #[inline(always)]
1167    pub const fn p300pfs_ha(
1168        &self,
1169    ) -> &'static crate::common::Reg<self::P300PfsHa_SPEC, crate::common::RW> {
1170        unsafe {
1171            crate::common::Reg::<self::P300PfsHa_SPEC, crate::common::RW>::from_ptr(
1172                self._svd2pac_as_ptr().add(194usize),
1173            )
1174        }
1175    }
1176
1177    #[doc = "Port 300 Pin Function Select Register"]
1178    #[inline(always)]
1179    pub const fn p300pfs_by(
1180        &self,
1181    ) -> &'static crate::common::Reg<self::P300PfsBy_SPEC, crate::common::RW> {
1182        unsafe {
1183            crate::common::Reg::<self::P300PfsBy_SPEC, crate::common::RW>::from_ptr(
1184                self._svd2pac_as_ptr().add(195usize),
1185            )
1186        }
1187    }
1188
1189    #[doc = "Port 30%s Pin Function Select Register"]
1190    #[inline(always)]
1191    pub const fn p30pfs(
1192        &self,
1193    ) -> &'static crate::common::ClusterRegisterArray<
1194        crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW>,
1195        2,
1196        0x4,
1197    > {
1198        unsafe {
1199            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xc4usize))
1200        }
1201    }
1202    #[inline(always)]
1203    pub const fn p301pfs(
1204        &self,
1205    ) -> &'static crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW> {
1206        unsafe {
1207            crate::common::Reg::<self::P30Pfs_SPEC, crate::common::RW>::from_ptr(
1208                self._svd2pac_as_ptr().add(0xc4usize),
1209            )
1210        }
1211    }
1212    #[inline(always)]
1213    pub const fn p302pfs(
1214        &self,
1215    ) -> &'static crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW> {
1216        unsafe {
1217            crate::common::Reg::<self::P30Pfs_SPEC, crate::common::RW>::from_ptr(
1218                self._svd2pac_as_ptr().add(0xc8usize),
1219            )
1220        }
1221    }
1222
1223    #[doc = "Port 30%s Pin Function Select Register"]
1224    #[inline(always)]
1225    pub const fn p30pfs_ha(
1226        &self,
1227    ) -> &'static crate::common::ClusterRegisterArray<
1228        crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW>,
1229        2,
1230        0x4,
1231    > {
1232        unsafe {
1233            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xc6usize))
1234        }
1235    }
1236    #[inline(always)]
1237    pub const fn p301pfs_ha(
1238        &self,
1239    ) -> &'static crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW> {
1240        unsafe {
1241            crate::common::Reg::<self::P30PfsHa_SPEC, crate::common::RW>::from_ptr(
1242                self._svd2pac_as_ptr().add(0xc6usize),
1243            )
1244        }
1245    }
1246    #[inline(always)]
1247    pub const fn p302pfs_ha(
1248        &self,
1249    ) -> &'static crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW> {
1250        unsafe {
1251            crate::common::Reg::<self::P30PfsHa_SPEC, crate::common::RW>::from_ptr(
1252                self._svd2pac_as_ptr().add(0xcausize),
1253            )
1254        }
1255    }
1256
1257    #[doc = "Port 30%s Pin Function Select Register"]
1258    #[inline(always)]
1259    pub const fn p30pfs_by(
1260        &self,
1261    ) -> &'static crate::common::ClusterRegisterArray<
1262        crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW>,
1263        2,
1264        0x4,
1265    > {
1266        unsafe {
1267            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xc7usize))
1268        }
1269    }
1270    #[inline(always)]
1271    pub const fn p301pfs_by(
1272        &self,
1273    ) -> &'static crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW> {
1274        unsafe {
1275            crate::common::Reg::<self::P30PfsBy_SPEC, crate::common::RW>::from_ptr(
1276                self._svd2pac_as_ptr().add(0xc7usize),
1277            )
1278        }
1279    }
1280    #[inline(always)]
1281    pub const fn p302pfs_by(
1282        &self,
1283    ) -> &'static crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW> {
1284        unsafe {
1285            crate::common::Reg::<self::P30PfsBy_SPEC, crate::common::RW>::from_ptr(
1286                self._svd2pac_as_ptr().add(0xcbusize),
1287            )
1288        }
1289    }
1290
1291    #[doc = "Port 40%s Pin Function Select Register"]
1292    #[inline(always)]
1293    pub const fn p40pfs(
1294        &self,
1295    ) -> &'static crate::common::ClusterRegisterArray<
1296        crate::common::Reg<self::P40Pfs_SPEC, crate::common::RW>,
1297        3,
1298        0x4,
1299    > {
1300        unsafe {
1301            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x11cusize))
1302        }
1303    }
1304    #[inline(always)]
1305    pub const fn p407pfs(
1306        &self,
1307    ) -> &'static crate::common::Reg<self::P40Pfs_SPEC, crate::common::RW> {
1308        unsafe {
1309            crate::common::Reg::<self::P40Pfs_SPEC, crate::common::RW>::from_ptr(
1310                self._svd2pac_as_ptr().add(0x11cusize),
1311            )
1312        }
1313    }
1314    #[inline(always)]
1315    pub const fn p408pfs(
1316        &self,
1317    ) -> &'static crate::common::Reg<self::P40Pfs_SPEC, crate::common::RW> {
1318        unsafe {
1319            crate::common::Reg::<self::P40Pfs_SPEC, crate::common::RW>::from_ptr(
1320                self._svd2pac_as_ptr().add(0x120usize),
1321            )
1322        }
1323    }
1324    #[inline(always)]
1325    pub const fn p409pfs(
1326        &self,
1327    ) -> &'static crate::common::Reg<self::P40Pfs_SPEC, crate::common::RW> {
1328        unsafe {
1329            crate::common::Reg::<self::P40Pfs_SPEC, crate::common::RW>::from_ptr(
1330                self._svd2pac_as_ptr().add(0x124usize),
1331            )
1332        }
1333    }
1334
1335    #[doc = "Port 40%s Pin Function Select Register"]
1336    #[inline(always)]
1337    pub const fn p40pfs_ha(
1338        &self,
1339    ) -> &'static crate::common::ClusterRegisterArray<
1340        crate::common::Reg<self::P40PfsHa_SPEC, crate::common::RW>,
1341        3,
1342        0x4,
1343    > {
1344        unsafe {
1345            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x11eusize))
1346        }
1347    }
1348    #[inline(always)]
1349    pub const fn p407pfs_ha(
1350        &self,
1351    ) -> &'static crate::common::Reg<self::P40PfsHa_SPEC, crate::common::RW> {
1352        unsafe {
1353            crate::common::Reg::<self::P40PfsHa_SPEC, crate::common::RW>::from_ptr(
1354                self._svd2pac_as_ptr().add(0x11eusize),
1355            )
1356        }
1357    }
1358    #[inline(always)]
1359    pub const fn p408pfs_ha(
1360        &self,
1361    ) -> &'static crate::common::Reg<self::P40PfsHa_SPEC, crate::common::RW> {
1362        unsafe {
1363            crate::common::Reg::<self::P40PfsHa_SPEC, crate::common::RW>::from_ptr(
1364                self._svd2pac_as_ptr().add(0x122usize),
1365            )
1366        }
1367    }
1368    #[inline(always)]
1369    pub const fn p409pfs_ha(
1370        &self,
1371    ) -> &'static crate::common::Reg<self::P40PfsHa_SPEC, crate::common::RW> {
1372        unsafe {
1373            crate::common::Reg::<self::P40PfsHa_SPEC, crate::common::RW>::from_ptr(
1374                self._svd2pac_as_ptr().add(0x126usize),
1375            )
1376        }
1377    }
1378
1379    #[doc = "Port 40%s Pin Function Select Register"]
1380    #[inline(always)]
1381    pub const fn p40pfs_by(
1382        &self,
1383    ) -> &'static crate::common::ClusterRegisterArray<
1384        crate::common::Reg<self::P40PfsBy_SPEC, crate::common::RW>,
1385        3,
1386        0x4,
1387    > {
1388        unsafe {
1389            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x11fusize))
1390        }
1391    }
1392    #[inline(always)]
1393    pub const fn p407pfs_by(
1394        &self,
1395    ) -> &'static crate::common::Reg<self::P40PfsBy_SPEC, crate::common::RW> {
1396        unsafe {
1397            crate::common::Reg::<self::P40PfsBy_SPEC, crate::common::RW>::from_ptr(
1398                self._svd2pac_as_ptr().add(0x11fusize),
1399            )
1400        }
1401    }
1402    #[inline(always)]
1403    pub const fn p408pfs_by(
1404        &self,
1405    ) -> &'static crate::common::Reg<self::P40PfsBy_SPEC, crate::common::RW> {
1406        unsafe {
1407            crate::common::Reg::<self::P40PfsBy_SPEC, crate::common::RW>::from_ptr(
1408                self._svd2pac_as_ptr().add(0x123usize),
1409            )
1410        }
1411    }
1412    #[inline(always)]
1413    pub const fn p409pfs_by(
1414        &self,
1415    ) -> &'static crate::common::Reg<self::P40PfsBy_SPEC, crate::common::RW> {
1416        unsafe {
1417            crate::common::Reg::<self::P40PfsBy_SPEC, crate::common::RW>::from_ptr(
1418                self._svd2pac_as_ptr().add(0x127usize),
1419            )
1420        }
1421    }
1422
1423    #[doc = "Port 500 Pin Function Select Register"]
1424    #[inline(always)]
1425    pub const fn p500pfs(
1426        &self,
1427    ) -> &'static crate::common::Reg<self::P500Pfs_SPEC, crate::common::RW> {
1428        unsafe {
1429            crate::common::Reg::<self::P500Pfs_SPEC, crate::common::RW>::from_ptr(
1430                self._svd2pac_as_ptr().add(320usize),
1431            )
1432        }
1433    }
1434
1435    #[doc = "Port 500 Pin Function Select Register"]
1436    #[inline(always)]
1437    pub const fn p500pfs_ha(
1438        &self,
1439    ) -> &'static crate::common::Reg<self::P500PfsHa_SPEC, crate::common::RW> {
1440        unsafe {
1441            crate::common::Reg::<self::P500PfsHa_SPEC, crate::common::RW>::from_ptr(
1442                self._svd2pac_as_ptr().add(322usize),
1443            )
1444        }
1445    }
1446
1447    #[doc = "Port 500 Pin Function Select Register"]
1448    #[inline(always)]
1449    pub const fn p500pfs_by(
1450        &self,
1451    ) -> &'static crate::common::Reg<self::P500PfsBy_SPEC, crate::common::RW> {
1452        unsafe {
1453            crate::common::Reg::<self::P500PfsBy_SPEC, crate::common::RW>::from_ptr(
1454                self._svd2pac_as_ptr().add(323usize),
1455            )
1456        }
1457    }
1458
1459    #[doc = "Port 9%s Pin Function Select Register"]
1460    #[inline(always)]
1461    pub const fn p9pfs(
1462        &self,
1463    ) -> &'static crate::common::ClusterRegisterArray<
1464        crate::common::Reg<self::P9Pfs_SPEC, crate::common::RW>,
1465        3,
1466        0x4,
1467    > {
1468        unsafe {
1469            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x274usize))
1470        }
1471    }
1472    #[inline(always)]
1473    pub const fn p913pfs(
1474        &self,
1475    ) -> &'static crate::common::Reg<self::P9Pfs_SPEC, crate::common::RW> {
1476        unsafe {
1477            crate::common::Reg::<self::P9Pfs_SPEC, crate::common::RW>::from_ptr(
1478                self._svd2pac_as_ptr().add(0x274usize),
1479            )
1480        }
1481    }
1482    #[inline(always)]
1483    pub const fn p914pfs(
1484        &self,
1485    ) -> &'static crate::common::Reg<self::P9Pfs_SPEC, crate::common::RW> {
1486        unsafe {
1487            crate::common::Reg::<self::P9Pfs_SPEC, crate::common::RW>::from_ptr(
1488                self._svd2pac_as_ptr().add(0x278usize),
1489            )
1490        }
1491    }
1492    #[inline(always)]
1493    pub const fn p915pfs(
1494        &self,
1495    ) -> &'static crate::common::Reg<self::P9Pfs_SPEC, crate::common::RW> {
1496        unsafe {
1497            crate::common::Reg::<self::P9Pfs_SPEC, crate::common::RW>::from_ptr(
1498                self._svd2pac_as_ptr().add(0x27cusize),
1499            )
1500        }
1501    }
1502
1503    #[doc = "Port 9%s Pin Function Select Register"]
1504    #[inline(always)]
1505    pub const fn p9pfs_ha(
1506        &self,
1507    ) -> &'static crate::common::ClusterRegisterArray<
1508        crate::common::Reg<self::P9PfsHa_SPEC, crate::common::RW>,
1509        3,
1510        0x4,
1511    > {
1512        unsafe {
1513            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x276usize))
1514        }
1515    }
1516    #[inline(always)]
1517    pub const fn p913pfs_ha(
1518        &self,
1519    ) -> &'static crate::common::Reg<self::P9PfsHa_SPEC, crate::common::RW> {
1520        unsafe {
1521            crate::common::Reg::<self::P9PfsHa_SPEC, crate::common::RW>::from_ptr(
1522                self._svd2pac_as_ptr().add(0x276usize),
1523            )
1524        }
1525    }
1526    #[inline(always)]
1527    pub const fn p914pfs_ha(
1528        &self,
1529    ) -> &'static crate::common::Reg<self::P9PfsHa_SPEC, crate::common::RW> {
1530        unsafe {
1531            crate::common::Reg::<self::P9PfsHa_SPEC, crate::common::RW>::from_ptr(
1532                self._svd2pac_as_ptr().add(0x27ausize),
1533            )
1534        }
1535    }
1536    #[inline(always)]
1537    pub const fn p915pfs_ha(
1538        &self,
1539    ) -> &'static crate::common::Reg<self::P9PfsHa_SPEC, crate::common::RW> {
1540        unsafe {
1541            crate::common::Reg::<self::P9PfsHa_SPEC, crate::common::RW>::from_ptr(
1542                self._svd2pac_as_ptr().add(0x27eusize),
1543            )
1544        }
1545    }
1546
1547    #[doc = "Port 9%s Pin Function Select Register"]
1548    #[inline(always)]
1549    pub const fn p9pfs_by(
1550        &self,
1551    ) -> &'static crate::common::ClusterRegisterArray<
1552        crate::common::Reg<self::P9PfsBy_SPEC, crate::common::RW>,
1553        3,
1554        0x4,
1555    > {
1556        unsafe {
1557            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x277usize))
1558        }
1559    }
1560    #[inline(always)]
1561    pub const fn p913pfs_by(
1562        &self,
1563    ) -> &'static crate::common::Reg<self::P9PfsBy_SPEC, crate::common::RW> {
1564        unsafe {
1565            crate::common::Reg::<self::P9PfsBy_SPEC, crate::common::RW>::from_ptr(
1566                self._svd2pac_as_ptr().add(0x277usize),
1567            )
1568        }
1569    }
1570    #[inline(always)]
1571    pub const fn p914pfs_by(
1572        &self,
1573    ) -> &'static crate::common::Reg<self::P9PfsBy_SPEC, crate::common::RW> {
1574        unsafe {
1575            crate::common::Reg::<self::P9PfsBy_SPEC, crate::common::RW>::from_ptr(
1576                self._svd2pac_as_ptr().add(0x27busize),
1577            )
1578        }
1579    }
1580    #[inline(always)]
1581    pub const fn p915pfs_by(
1582        &self,
1583    ) -> &'static crate::common::Reg<self::P9PfsBy_SPEC, crate::common::RW> {
1584        unsafe {
1585            crate::common::Reg::<self::P9PfsBy_SPEC, crate::common::RW>::from_ptr(
1586                self._svd2pac_as_ptr().add(0x27fusize),
1587            )
1588        }
1589    }
1590
1591    #[doc = "Write-Protect Register"]
1592    #[inline(always)]
1593    pub const fn pwpr(&self) -> &'static crate::common::Reg<self::Pwpr_SPEC, crate::common::RW> {
1594        unsafe {
1595            crate::common::Reg::<self::Pwpr_SPEC, crate::common::RW>::from_ptr(
1596                self._svd2pac_as_ptr().add(1283usize),
1597            )
1598        }
1599    }
1600
1601    #[doc = "Port Read Wait Control Register"]
1602    #[inline(always)]
1603    pub const fn prwcntr(
1604        &self,
1605    ) -> &'static crate::common::Reg<self::Prwcntr_SPEC, crate::common::RW> {
1606        unsafe {
1607            crate::common::Reg::<self::Prwcntr_SPEC, crate::common::RW>::from_ptr(
1608                self._svd2pac_as_ptr().add(1295usize),
1609            )
1610        }
1611    }
1612}
1613#[doc(hidden)]
1614#[derive(Copy, Clone, Eq, PartialEq)]
1615pub struct P00Pfs_SPEC;
1616impl crate::sealed::RegSpec for P00Pfs_SPEC {
1617    type DataType = u32;
1618}
1619
1620#[doc = "Port 00%s Pin Function Select Register"]
1621pub type P00Pfs = crate::RegValueT<P00Pfs_SPEC>;
1622
1623impl P00Pfs {
1624    #[doc = "Port Output Data"]
1625    #[inline(always)]
1626    pub fn podr(
1627        self,
1628    ) -> crate::common::RegisterField<
1629        0,
1630        0x1,
1631        1,
1632        0,
1633        p00pfs::Podr,
1634        p00pfs::Podr,
1635        P00Pfs_SPEC,
1636        crate::common::RW,
1637    > {
1638        crate::common::RegisterField::<
1639            0,
1640            0x1,
1641            1,
1642            0,
1643            p00pfs::Podr,
1644            p00pfs::Podr,
1645            P00Pfs_SPEC,
1646            crate::common::RW,
1647        >::from_register(self, 0)
1648    }
1649
1650    #[doc = "Port State"]
1651    #[inline(always)]
1652    pub fn pidr(
1653        self,
1654    ) -> crate::common::RegisterField<
1655        1,
1656        0x1,
1657        1,
1658        0,
1659        p00pfs::Pidr,
1660        p00pfs::Pidr,
1661        P00Pfs_SPEC,
1662        crate::common::R,
1663    > {
1664        crate::common::RegisterField::<
1665            1,
1666            0x1,
1667            1,
1668            0,
1669            p00pfs::Pidr,
1670            p00pfs::Pidr,
1671            P00Pfs_SPEC,
1672            crate::common::R,
1673        >::from_register(self, 0)
1674    }
1675
1676    #[doc = "Port Direction"]
1677    #[inline(always)]
1678    pub fn pdr(
1679        self,
1680    ) -> crate::common::RegisterField<
1681        2,
1682        0x1,
1683        1,
1684        0,
1685        p00pfs::Pdr,
1686        p00pfs::Pdr,
1687        P00Pfs_SPEC,
1688        crate::common::RW,
1689    > {
1690        crate::common::RegisterField::<
1691            2,
1692            0x1,
1693            1,
1694            0,
1695            p00pfs::Pdr,
1696            p00pfs::Pdr,
1697            P00Pfs_SPEC,
1698            crate::common::RW,
1699        >::from_register(self, 0)
1700    }
1701
1702    #[doc = "Pull-up Control"]
1703    #[inline(always)]
1704    pub fn pcr(
1705        self,
1706    ) -> crate::common::RegisterField<
1707        4,
1708        0x1,
1709        1,
1710        0,
1711        p00pfs::Pcr,
1712        p00pfs::Pcr,
1713        P00Pfs_SPEC,
1714        crate::common::RW,
1715    > {
1716        crate::common::RegisterField::<
1717            4,
1718            0x1,
1719            1,
1720            0,
1721            p00pfs::Pcr,
1722            p00pfs::Pcr,
1723            P00Pfs_SPEC,
1724            crate::common::RW,
1725        >::from_register(self, 0)
1726    }
1727
1728    #[doc = "N-Channel Open-Drain Control"]
1729    #[inline(always)]
1730    pub fn ncodr(
1731        self,
1732    ) -> crate::common::RegisterField<
1733        6,
1734        0x1,
1735        1,
1736        0,
1737        p00pfs::Ncodr,
1738        p00pfs::Ncodr,
1739        P00Pfs_SPEC,
1740        crate::common::RW,
1741    > {
1742        crate::common::RegisterField::<
1743            6,
1744            0x1,
1745            1,
1746            0,
1747            p00pfs::Ncodr,
1748            p00pfs::Ncodr,
1749            P00Pfs_SPEC,
1750            crate::common::RW,
1751        >::from_register(self, 0)
1752    }
1753
1754    #[doc = "IRQ Input Enable"]
1755    #[inline(always)]
1756    pub fn isel(
1757        self,
1758    ) -> crate::common::RegisterField<
1759        14,
1760        0x1,
1761        1,
1762        0,
1763        p00pfs::Isel,
1764        p00pfs::Isel,
1765        P00Pfs_SPEC,
1766        crate::common::RW,
1767    > {
1768        crate::common::RegisterField::<
1769            14,
1770            0x1,
1771            1,
1772            0,
1773            p00pfs::Isel,
1774            p00pfs::Isel,
1775            P00Pfs_SPEC,
1776            crate::common::RW,
1777        >::from_register(self, 0)
1778    }
1779
1780    #[doc = "Analog Input Enable"]
1781    #[inline(always)]
1782    pub fn asel(
1783        self,
1784    ) -> crate::common::RegisterField<
1785        15,
1786        0x1,
1787        1,
1788        0,
1789        p00pfs::Asel,
1790        p00pfs::Asel,
1791        P00Pfs_SPEC,
1792        crate::common::RW,
1793    > {
1794        crate::common::RegisterField::<
1795            15,
1796            0x1,
1797            1,
1798            0,
1799            p00pfs::Asel,
1800            p00pfs::Asel,
1801            P00Pfs_SPEC,
1802            crate::common::RW,
1803        >::from_register(self, 0)
1804    }
1805
1806    #[doc = "Port Mode Control"]
1807    #[inline(always)]
1808    pub fn pmr(
1809        self,
1810    ) -> crate::common::RegisterField<
1811        16,
1812        0x1,
1813        1,
1814        0,
1815        p00pfs::Pmr,
1816        p00pfs::Pmr,
1817        P00Pfs_SPEC,
1818        crate::common::RW,
1819    > {
1820        crate::common::RegisterField::<
1821            16,
1822            0x1,
1823            1,
1824            0,
1825            p00pfs::Pmr,
1826            p00pfs::Pmr,
1827            P00Pfs_SPEC,
1828            crate::common::RW,
1829        >::from_register(self, 0)
1830    }
1831
1832    #[doc = "Peripheral Select"]
1833    #[inline(always)]
1834    pub fn psel(
1835        self,
1836    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P00Pfs_SPEC, crate::common::RW> {
1837        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P00Pfs_SPEC,crate::common::RW>::from_register(self,0)
1838    }
1839}
1840impl ::core::default::Default for P00Pfs {
1841    #[inline(always)]
1842    fn default() -> P00Pfs {
1843        <crate::RegValueT<P00Pfs_SPEC> as RegisterValue<_>>::new(0)
1844    }
1845}
1846pub mod p00pfs {
1847
1848    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1849    pub struct Podr_SPEC;
1850    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
1851    impl Podr {
1852        #[doc = "Output low"]
1853        pub const _0: Self = Self::new(0);
1854
1855        #[doc = "Output high"]
1856        pub const _1: Self = Self::new(1);
1857    }
1858    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1859    pub struct Pidr_SPEC;
1860    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
1861    impl Pidr {
1862        #[doc = "Low level"]
1863        pub const _0: Self = Self::new(0);
1864
1865        #[doc = "High level"]
1866        pub const _1: Self = Self::new(1);
1867    }
1868    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1869    pub struct Pdr_SPEC;
1870    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
1871    impl Pdr {
1872        #[doc = "Input (functions as an input pin)"]
1873        pub const _0: Self = Self::new(0);
1874
1875        #[doc = "Output (functions as an output pin)"]
1876        pub const _1: Self = Self::new(1);
1877    }
1878    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1879    pub struct Pcr_SPEC;
1880    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
1881    impl Pcr {
1882        #[doc = "Disable input pull-up"]
1883        pub const _0: Self = Self::new(0);
1884
1885        #[doc = "Enable input pull-up"]
1886        pub const _1: Self = Self::new(1);
1887    }
1888    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1889    pub struct Ncodr_SPEC;
1890    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
1891    impl Ncodr {
1892        #[doc = "Output CMOS"]
1893        pub const _0: Self = Self::new(0);
1894
1895        #[doc = "Output NMOS open-drain"]
1896        pub const _1: Self = Self::new(1);
1897    }
1898    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1899    pub struct Isel_SPEC;
1900    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
1901    impl Isel {
1902        #[doc = "Do not use as IRQn input pin"]
1903        pub const _0: Self = Self::new(0);
1904
1905        #[doc = "Use as IRQn input pin"]
1906        pub const _1: Self = Self::new(1);
1907    }
1908    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1909    pub struct Asel_SPEC;
1910    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
1911    impl Asel {
1912        #[doc = "Do not use as analog pin"]
1913        pub const _0: Self = Self::new(0);
1914
1915        #[doc = "Use as analog pin"]
1916        pub const _1: Self = Self::new(1);
1917    }
1918    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1919    pub struct Pmr_SPEC;
1920    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
1921    impl Pmr {
1922        #[doc = "Use as general I/O pin"]
1923        pub const _0: Self = Self::new(0);
1924
1925        #[doc = "Use as I/O port for peripheral functions"]
1926        pub const _1: Self = Self::new(1);
1927    }
1928}
1929#[doc(hidden)]
1930#[derive(Copy, Clone, Eq, PartialEq)]
1931pub struct P00PfsHa_SPEC;
1932impl crate::sealed::RegSpec for P00PfsHa_SPEC {
1933    type DataType = u16;
1934}
1935
1936#[doc = "Port 00%s Pin Function Select Register"]
1937pub type P00PfsHa = crate::RegValueT<P00PfsHa_SPEC>;
1938
1939impl P00PfsHa {
1940    #[doc = "Port Output Data"]
1941    #[inline(always)]
1942    pub fn podr(
1943        self,
1944    ) -> crate::common::RegisterField<
1945        0,
1946        0x1,
1947        1,
1948        0,
1949        p00pfs_ha::Podr,
1950        p00pfs_ha::Podr,
1951        P00PfsHa_SPEC,
1952        crate::common::RW,
1953    > {
1954        crate::common::RegisterField::<
1955            0,
1956            0x1,
1957            1,
1958            0,
1959            p00pfs_ha::Podr,
1960            p00pfs_ha::Podr,
1961            P00PfsHa_SPEC,
1962            crate::common::RW,
1963        >::from_register(self, 0)
1964    }
1965
1966    #[doc = "Port State"]
1967    #[inline(always)]
1968    pub fn pidr(
1969        self,
1970    ) -> crate::common::RegisterField<
1971        1,
1972        0x1,
1973        1,
1974        0,
1975        p00pfs_ha::Pidr,
1976        p00pfs_ha::Pidr,
1977        P00PfsHa_SPEC,
1978        crate::common::R,
1979    > {
1980        crate::common::RegisterField::<
1981            1,
1982            0x1,
1983            1,
1984            0,
1985            p00pfs_ha::Pidr,
1986            p00pfs_ha::Pidr,
1987            P00PfsHa_SPEC,
1988            crate::common::R,
1989        >::from_register(self, 0)
1990    }
1991
1992    #[doc = "Port Direction"]
1993    #[inline(always)]
1994    pub fn pdr(
1995        self,
1996    ) -> crate::common::RegisterField<
1997        2,
1998        0x1,
1999        1,
2000        0,
2001        p00pfs_ha::Pdr,
2002        p00pfs_ha::Pdr,
2003        P00PfsHa_SPEC,
2004        crate::common::RW,
2005    > {
2006        crate::common::RegisterField::<
2007            2,
2008            0x1,
2009            1,
2010            0,
2011            p00pfs_ha::Pdr,
2012            p00pfs_ha::Pdr,
2013            P00PfsHa_SPEC,
2014            crate::common::RW,
2015        >::from_register(self, 0)
2016    }
2017
2018    #[doc = "Pull-up Control"]
2019    #[inline(always)]
2020    pub fn pcr(
2021        self,
2022    ) -> crate::common::RegisterField<
2023        4,
2024        0x1,
2025        1,
2026        0,
2027        p00pfs_ha::Pcr,
2028        p00pfs_ha::Pcr,
2029        P00PfsHa_SPEC,
2030        crate::common::RW,
2031    > {
2032        crate::common::RegisterField::<
2033            4,
2034            0x1,
2035            1,
2036            0,
2037            p00pfs_ha::Pcr,
2038            p00pfs_ha::Pcr,
2039            P00PfsHa_SPEC,
2040            crate::common::RW,
2041        >::from_register(self, 0)
2042    }
2043
2044    #[doc = "N-Channel Open-Drain Control"]
2045    #[inline(always)]
2046    pub fn ncodr(
2047        self,
2048    ) -> crate::common::RegisterField<
2049        6,
2050        0x1,
2051        1,
2052        0,
2053        p00pfs_ha::Ncodr,
2054        p00pfs_ha::Ncodr,
2055        P00PfsHa_SPEC,
2056        crate::common::RW,
2057    > {
2058        crate::common::RegisterField::<
2059            6,
2060            0x1,
2061            1,
2062            0,
2063            p00pfs_ha::Ncodr,
2064            p00pfs_ha::Ncodr,
2065            P00PfsHa_SPEC,
2066            crate::common::RW,
2067        >::from_register(self, 0)
2068    }
2069
2070    #[doc = "IRQ Input Enable"]
2071    #[inline(always)]
2072    pub fn isel(
2073        self,
2074    ) -> crate::common::RegisterField<
2075        14,
2076        0x1,
2077        1,
2078        0,
2079        p00pfs_ha::Isel,
2080        p00pfs_ha::Isel,
2081        P00PfsHa_SPEC,
2082        crate::common::RW,
2083    > {
2084        crate::common::RegisterField::<
2085            14,
2086            0x1,
2087            1,
2088            0,
2089            p00pfs_ha::Isel,
2090            p00pfs_ha::Isel,
2091            P00PfsHa_SPEC,
2092            crate::common::RW,
2093        >::from_register(self, 0)
2094    }
2095
2096    #[doc = "Analog Input Enable"]
2097    #[inline(always)]
2098    pub fn asel(
2099        self,
2100    ) -> crate::common::RegisterField<
2101        15,
2102        0x1,
2103        1,
2104        0,
2105        p00pfs_ha::Asel,
2106        p00pfs_ha::Asel,
2107        P00PfsHa_SPEC,
2108        crate::common::RW,
2109    > {
2110        crate::common::RegisterField::<
2111            15,
2112            0x1,
2113            1,
2114            0,
2115            p00pfs_ha::Asel,
2116            p00pfs_ha::Asel,
2117            P00PfsHa_SPEC,
2118            crate::common::RW,
2119        >::from_register(self, 0)
2120    }
2121}
2122impl ::core::default::Default for P00PfsHa {
2123    #[inline(always)]
2124    fn default() -> P00PfsHa {
2125        <crate::RegValueT<P00PfsHa_SPEC> as RegisterValue<_>>::new(0)
2126    }
2127}
2128pub mod p00pfs_ha {
2129
2130    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2131    pub struct Podr_SPEC;
2132    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
2133    impl Podr {
2134        #[doc = "Output low"]
2135        pub const _0: Self = Self::new(0);
2136
2137        #[doc = "Output high"]
2138        pub const _1: Self = Self::new(1);
2139    }
2140    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2141    pub struct Pidr_SPEC;
2142    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
2143    impl Pidr {
2144        #[doc = "Low level"]
2145        pub const _0: Self = Self::new(0);
2146
2147        #[doc = "High level"]
2148        pub const _1: Self = Self::new(1);
2149    }
2150    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2151    pub struct Pdr_SPEC;
2152    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
2153    impl Pdr {
2154        #[doc = "Input (functions as an input pin)"]
2155        pub const _0: Self = Self::new(0);
2156
2157        #[doc = "Output (functions as an output pin)"]
2158        pub const _1: Self = Self::new(1);
2159    }
2160    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2161    pub struct Pcr_SPEC;
2162    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
2163    impl Pcr {
2164        #[doc = "Disable input pull-up"]
2165        pub const _0: Self = Self::new(0);
2166
2167        #[doc = "Enable input pull-up"]
2168        pub const _1: Self = Self::new(1);
2169    }
2170    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2171    pub struct Ncodr_SPEC;
2172    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
2173    impl Ncodr {
2174        #[doc = "Output CMOS"]
2175        pub const _0: Self = Self::new(0);
2176
2177        #[doc = "Output NMOS open-drain"]
2178        pub const _1: Self = Self::new(1);
2179    }
2180    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2181    pub struct Isel_SPEC;
2182    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
2183    impl Isel {
2184        #[doc = "Do not use as IRQn input pin"]
2185        pub const _0: Self = Self::new(0);
2186
2187        #[doc = "Use as IRQn input pin"]
2188        pub const _1: Self = Self::new(1);
2189    }
2190    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2191    pub struct Asel_SPEC;
2192    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
2193    impl Asel {
2194        #[doc = "Do not use as analog pin"]
2195        pub const _0: Self = Self::new(0);
2196
2197        #[doc = "Use as analog pin"]
2198        pub const _1: Self = Self::new(1);
2199    }
2200}
2201#[doc(hidden)]
2202#[derive(Copy, Clone, Eq, PartialEq)]
2203pub struct P00PfsBy_SPEC;
2204impl crate::sealed::RegSpec for P00PfsBy_SPEC {
2205    type DataType = u8;
2206}
2207
2208#[doc = "Port 00%s Pin Function Select Register"]
2209pub type P00PfsBy = crate::RegValueT<P00PfsBy_SPEC>;
2210
2211impl P00PfsBy {
2212    #[doc = "Port Output Data"]
2213    #[inline(always)]
2214    pub fn podr(
2215        self,
2216    ) -> crate::common::RegisterField<
2217        0,
2218        0x1,
2219        1,
2220        0,
2221        p00pfs_by::Podr,
2222        p00pfs_by::Podr,
2223        P00PfsBy_SPEC,
2224        crate::common::RW,
2225    > {
2226        crate::common::RegisterField::<
2227            0,
2228            0x1,
2229            1,
2230            0,
2231            p00pfs_by::Podr,
2232            p00pfs_by::Podr,
2233            P00PfsBy_SPEC,
2234            crate::common::RW,
2235        >::from_register(self, 0)
2236    }
2237
2238    #[doc = "Port State"]
2239    #[inline(always)]
2240    pub fn pidr(
2241        self,
2242    ) -> crate::common::RegisterField<
2243        1,
2244        0x1,
2245        1,
2246        0,
2247        p00pfs_by::Pidr,
2248        p00pfs_by::Pidr,
2249        P00PfsBy_SPEC,
2250        crate::common::R,
2251    > {
2252        crate::common::RegisterField::<
2253            1,
2254            0x1,
2255            1,
2256            0,
2257            p00pfs_by::Pidr,
2258            p00pfs_by::Pidr,
2259            P00PfsBy_SPEC,
2260            crate::common::R,
2261        >::from_register(self, 0)
2262    }
2263
2264    #[doc = "Port Direction"]
2265    #[inline(always)]
2266    pub fn pdr(
2267        self,
2268    ) -> crate::common::RegisterField<
2269        2,
2270        0x1,
2271        1,
2272        0,
2273        p00pfs_by::Pdr,
2274        p00pfs_by::Pdr,
2275        P00PfsBy_SPEC,
2276        crate::common::RW,
2277    > {
2278        crate::common::RegisterField::<
2279            2,
2280            0x1,
2281            1,
2282            0,
2283            p00pfs_by::Pdr,
2284            p00pfs_by::Pdr,
2285            P00PfsBy_SPEC,
2286            crate::common::RW,
2287        >::from_register(self, 0)
2288    }
2289
2290    #[doc = "Pull-up Control"]
2291    #[inline(always)]
2292    pub fn pcr(
2293        self,
2294    ) -> crate::common::RegisterField<
2295        4,
2296        0x1,
2297        1,
2298        0,
2299        p00pfs_by::Pcr,
2300        p00pfs_by::Pcr,
2301        P00PfsBy_SPEC,
2302        crate::common::RW,
2303    > {
2304        crate::common::RegisterField::<
2305            4,
2306            0x1,
2307            1,
2308            0,
2309            p00pfs_by::Pcr,
2310            p00pfs_by::Pcr,
2311            P00PfsBy_SPEC,
2312            crate::common::RW,
2313        >::from_register(self, 0)
2314    }
2315
2316    #[doc = "N-Channel Open-Drain Control"]
2317    #[inline(always)]
2318    pub fn ncodr(
2319        self,
2320    ) -> crate::common::RegisterField<
2321        6,
2322        0x1,
2323        1,
2324        0,
2325        p00pfs_by::Ncodr,
2326        p00pfs_by::Ncodr,
2327        P00PfsBy_SPEC,
2328        crate::common::RW,
2329    > {
2330        crate::common::RegisterField::<
2331            6,
2332            0x1,
2333            1,
2334            0,
2335            p00pfs_by::Ncodr,
2336            p00pfs_by::Ncodr,
2337            P00PfsBy_SPEC,
2338            crate::common::RW,
2339        >::from_register(self, 0)
2340    }
2341}
2342impl ::core::default::Default for P00PfsBy {
2343    #[inline(always)]
2344    fn default() -> P00PfsBy {
2345        <crate::RegValueT<P00PfsBy_SPEC> as RegisterValue<_>>::new(0)
2346    }
2347}
2348pub mod p00pfs_by {
2349
2350    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2351    pub struct Podr_SPEC;
2352    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
2353    impl Podr {
2354        #[doc = "Output low"]
2355        pub const _0: Self = Self::new(0);
2356
2357        #[doc = "Output high"]
2358        pub const _1: Self = Self::new(1);
2359    }
2360    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2361    pub struct Pidr_SPEC;
2362    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
2363    impl Pidr {
2364        #[doc = "Low level"]
2365        pub const _0: Self = Self::new(0);
2366
2367        #[doc = "High level"]
2368        pub const _1: Self = Self::new(1);
2369    }
2370    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2371    pub struct Pdr_SPEC;
2372    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
2373    impl Pdr {
2374        #[doc = "Input (functions as an input pin)"]
2375        pub const _0: Self = Self::new(0);
2376
2377        #[doc = "Output (functions as an output pin)"]
2378        pub const _1: Self = Self::new(1);
2379    }
2380    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2381    pub struct Pcr_SPEC;
2382    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
2383    impl Pcr {
2384        #[doc = "Disable input pull-up"]
2385        pub const _0: Self = Self::new(0);
2386
2387        #[doc = "Enable input pull-up"]
2388        pub const _1: Self = Self::new(1);
2389    }
2390    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2391    pub struct Ncodr_SPEC;
2392    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
2393    impl Ncodr {
2394        #[doc = "Output CMOS"]
2395        pub const _0: Self = Self::new(0);
2396
2397        #[doc = "Output NMOS open-drain"]
2398        pub const _1: Self = Self::new(1);
2399    }
2400}
2401#[doc(hidden)]
2402#[derive(Copy, Clone, Eq, PartialEq)]
2403pub struct P0Pfs_SPEC;
2404impl crate::sealed::RegSpec for P0Pfs_SPEC {
2405    type DataType = u32;
2406}
2407
2408#[doc = "Port 0%s Pin Function Select Register"]
2409pub type P0Pfs = crate::RegValueT<P0Pfs_SPEC>;
2410
2411impl P0Pfs {
2412    #[doc = "Port Output Data"]
2413    #[inline(always)]
2414    pub fn podr(
2415        self,
2416    ) -> crate::common::RegisterField<
2417        0,
2418        0x1,
2419        1,
2420        0,
2421        p0pfs::Podr,
2422        p0pfs::Podr,
2423        P0Pfs_SPEC,
2424        crate::common::RW,
2425    > {
2426        crate::common::RegisterField::<
2427            0,
2428            0x1,
2429            1,
2430            0,
2431            p0pfs::Podr,
2432            p0pfs::Podr,
2433            P0Pfs_SPEC,
2434            crate::common::RW,
2435        >::from_register(self, 0)
2436    }
2437
2438    #[doc = "Port State"]
2439    #[inline(always)]
2440    pub fn pidr(
2441        self,
2442    ) -> crate::common::RegisterField<
2443        1,
2444        0x1,
2445        1,
2446        0,
2447        p0pfs::Pidr,
2448        p0pfs::Pidr,
2449        P0Pfs_SPEC,
2450        crate::common::R,
2451    > {
2452        crate::common::RegisterField::<
2453            1,
2454            0x1,
2455            1,
2456            0,
2457            p0pfs::Pidr,
2458            p0pfs::Pidr,
2459            P0Pfs_SPEC,
2460            crate::common::R,
2461        >::from_register(self, 0)
2462    }
2463
2464    #[doc = "Port Direction"]
2465    #[inline(always)]
2466    pub fn pdr(
2467        self,
2468    ) -> crate::common::RegisterField<
2469        2,
2470        0x1,
2471        1,
2472        0,
2473        p0pfs::Pdr,
2474        p0pfs::Pdr,
2475        P0Pfs_SPEC,
2476        crate::common::RW,
2477    > {
2478        crate::common::RegisterField::<
2479            2,
2480            0x1,
2481            1,
2482            0,
2483            p0pfs::Pdr,
2484            p0pfs::Pdr,
2485            P0Pfs_SPEC,
2486            crate::common::RW,
2487        >::from_register(self, 0)
2488    }
2489
2490    #[doc = "Pull-up Control"]
2491    #[inline(always)]
2492    pub fn pcr(
2493        self,
2494    ) -> crate::common::RegisterField<
2495        4,
2496        0x1,
2497        1,
2498        0,
2499        p0pfs::Pcr,
2500        p0pfs::Pcr,
2501        P0Pfs_SPEC,
2502        crate::common::RW,
2503    > {
2504        crate::common::RegisterField::<
2505            4,
2506            0x1,
2507            1,
2508            0,
2509            p0pfs::Pcr,
2510            p0pfs::Pcr,
2511            P0Pfs_SPEC,
2512            crate::common::RW,
2513        >::from_register(self, 0)
2514    }
2515
2516    #[doc = "N-Channel Open-Drain Control"]
2517    #[inline(always)]
2518    pub fn ncodr(
2519        self,
2520    ) -> crate::common::RegisterField<
2521        6,
2522        0x1,
2523        1,
2524        0,
2525        p0pfs::Ncodr,
2526        p0pfs::Ncodr,
2527        P0Pfs_SPEC,
2528        crate::common::RW,
2529    > {
2530        crate::common::RegisterField::<
2531            6,
2532            0x1,
2533            1,
2534            0,
2535            p0pfs::Ncodr,
2536            p0pfs::Ncodr,
2537            P0Pfs_SPEC,
2538            crate::common::RW,
2539        >::from_register(self, 0)
2540    }
2541
2542    #[doc = "IRQ Input Enable"]
2543    #[inline(always)]
2544    pub fn isel(
2545        self,
2546    ) -> crate::common::RegisterField<
2547        14,
2548        0x1,
2549        1,
2550        0,
2551        p0pfs::Isel,
2552        p0pfs::Isel,
2553        P0Pfs_SPEC,
2554        crate::common::RW,
2555    > {
2556        crate::common::RegisterField::<
2557            14,
2558            0x1,
2559            1,
2560            0,
2561            p0pfs::Isel,
2562            p0pfs::Isel,
2563            P0Pfs_SPEC,
2564            crate::common::RW,
2565        >::from_register(self, 0)
2566    }
2567
2568    #[doc = "Analog Input Enable"]
2569    #[inline(always)]
2570    pub fn asel(
2571        self,
2572    ) -> crate::common::RegisterField<
2573        15,
2574        0x1,
2575        1,
2576        0,
2577        p0pfs::Asel,
2578        p0pfs::Asel,
2579        P0Pfs_SPEC,
2580        crate::common::RW,
2581    > {
2582        crate::common::RegisterField::<
2583            15,
2584            0x1,
2585            1,
2586            0,
2587            p0pfs::Asel,
2588            p0pfs::Asel,
2589            P0Pfs_SPEC,
2590            crate::common::RW,
2591        >::from_register(self, 0)
2592    }
2593
2594    #[doc = "Port Mode Control"]
2595    #[inline(always)]
2596    pub fn pmr(
2597        self,
2598    ) -> crate::common::RegisterField<
2599        16,
2600        0x1,
2601        1,
2602        0,
2603        p0pfs::Pmr,
2604        p0pfs::Pmr,
2605        P0Pfs_SPEC,
2606        crate::common::RW,
2607    > {
2608        crate::common::RegisterField::<
2609            16,
2610            0x1,
2611            1,
2612            0,
2613            p0pfs::Pmr,
2614            p0pfs::Pmr,
2615            P0Pfs_SPEC,
2616            crate::common::RW,
2617        >::from_register(self, 0)
2618    }
2619
2620    #[doc = "Peripheral Select"]
2621    #[inline(always)]
2622    pub fn psel(
2623        self,
2624    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P0Pfs_SPEC, crate::common::RW> {
2625        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P0Pfs_SPEC,crate::common::RW>::from_register(self,0)
2626    }
2627}
2628impl ::core::default::Default for P0Pfs {
2629    #[inline(always)]
2630    fn default() -> P0Pfs {
2631        <crate::RegValueT<P0Pfs_SPEC> as RegisterValue<_>>::new(0)
2632    }
2633}
2634pub mod p0pfs {
2635
2636    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2637    pub struct Podr_SPEC;
2638    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
2639    impl Podr {
2640        #[doc = "Output low"]
2641        pub const _0: Self = Self::new(0);
2642
2643        #[doc = "Output high"]
2644        pub const _1: Self = Self::new(1);
2645    }
2646    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2647    pub struct Pidr_SPEC;
2648    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
2649    impl Pidr {
2650        #[doc = "Low level"]
2651        pub const _0: Self = Self::new(0);
2652
2653        #[doc = "High level"]
2654        pub const _1: Self = Self::new(1);
2655    }
2656    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2657    pub struct Pdr_SPEC;
2658    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
2659    impl Pdr {
2660        #[doc = "Input (functions as an input pin)"]
2661        pub const _0: Self = Self::new(0);
2662
2663        #[doc = "Output (functions as an output pin)"]
2664        pub const _1: Self = Self::new(1);
2665    }
2666    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2667    pub struct Pcr_SPEC;
2668    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
2669    impl Pcr {
2670        #[doc = "Disable input pull-up"]
2671        pub const _0: Self = Self::new(0);
2672
2673        #[doc = "Enable input pull-up"]
2674        pub const _1: Self = Self::new(1);
2675    }
2676    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2677    pub struct Ncodr_SPEC;
2678    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
2679    impl Ncodr {
2680        #[doc = "Output CMOS"]
2681        pub const _0: Self = Self::new(0);
2682
2683        #[doc = "Output NMOS open-drain"]
2684        pub const _1: Self = Self::new(1);
2685    }
2686    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2687    pub struct Isel_SPEC;
2688    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
2689    impl Isel {
2690        #[doc = "Do not use as IRQn input pin"]
2691        pub const _0: Self = Self::new(0);
2692
2693        #[doc = "Use as IRQn input pin"]
2694        pub const _1: Self = Self::new(1);
2695    }
2696    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2697    pub struct Asel_SPEC;
2698    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
2699    impl Asel {
2700        #[doc = "Do not use as analog pin"]
2701        pub const _0: Self = Self::new(0);
2702
2703        #[doc = "Use as analog pin"]
2704        pub const _1: Self = Self::new(1);
2705    }
2706    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2707    pub struct Pmr_SPEC;
2708    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
2709    impl Pmr {
2710        #[doc = "Use as general I/O pin"]
2711        pub const _0: Self = Self::new(0);
2712
2713        #[doc = "Use as I/O port for peripheral functions"]
2714        pub const _1: Self = Self::new(1);
2715    }
2716}
2717#[doc(hidden)]
2718#[derive(Copy, Clone, Eq, PartialEq)]
2719pub struct P0PfsHa_SPEC;
2720impl crate::sealed::RegSpec for P0PfsHa_SPEC {
2721    type DataType = u16;
2722}
2723
2724#[doc = "Port 0%s Pin Function Select Register"]
2725pub type P0PfsHa = crate::RegValueT<P0PfsHa_SPEC>;
2726
2727impl P0PfsHa {
2728    #[doc = "Port Output Data"]
2729    #[inline(always)]
2730    pub fn podr(
2731        self,
2732    ) -> crate::common::RegisterField<
2733        0,
2734        0x1,
2735        1,
2736        0,
2737        p0pfs_ha::Podr,
2738        p0pfs_ha::Podr,
2739        P0PfsHa_SPEC,
2740        crate::common::RW,
2741    > {
2742        crate::common::RegisterField::<
2743            0,
2744            0x1,
2745            1,
2746            0,
2747            p0pfs_ha::Podr,
2748            p0pfs_ha::Podr,
2749            P0PfsHa_SPEC,
2750            crate::common::RW,
2751        >::from_register(self, 0)
2752    }
2753
2754    #[doc = "Port State"]
2755    #[inline(always)]
2756    pub fn pidr(
2757        self,
2758    ) -> crate::common::RegisterField<
2759        1,
2760        0x1,
2761        1,
2762        0,
2763        p0pfs_ha::Pidr,
2764        p0pfs_ha::Pidr,
2765        P0PfsHa_SPEC,
2766        crate::common::R,
2767    > {
2768        crate::common::RegisterField::<
2769            1,
2770            0x1,
2771            1,
2772            0,
2773            p0pfs_ha::Pidr,
2774            p0pfs_ha::Pidr,
2775            P0PfsHa_SPEC,
2776            crate::common::R,
2777        >::from_register(self, 0)
2778    }
2779
2780    #[doc = "Port Direction"]
2781    #[inline(always)]
2782    pub fn pdr(
2783        self,
2784    ) -> crate::common::RegisterField<
2785        2,
2786        0x1,
2787        1,
2788        0,
2789        p0pfs_ha::Pdr,
2790        p0pfs_ha::Pdr,
2791        P0PfsHa_SPEC,
2792        crate::common::RW,
2793    > {
2794        crate::common::RegisterField::<
2795            2,
2796            0x1,
2797            1,
2798            0,
2799            p0pfs_ha::Pdr,
2800            p0pfs_ha::Pdr,
2801            P0PfsHa_SPEC,
2802            crate::common::RW,
2803        >::from_register(self, 0)
2804    }
2805
2806    #[doc = "Pull-up Control"]
2807    #[inline(always)]
2808    pub fn pcr(
2809        self,
2810    ) -> crate::common::RegisterField<
2811        4,
2812        0x1,
2813        1,
2814        0,
2815        p0pfs_ha::Pcr,
2816        p0pfs_ha::Pcr,
2817        P0PfsHa_SPEC,
2818        crate::common::RW,
2819    > {
2820        crate::common::RegisterField::<
2821            4,
2822            0x1,
2823            1,
2824            0,
2825            p0pfs_ha::Pcr,
2826            p0pfs_ha::Pcr,
2827            P0PfsHa_SPEC,
2828            crate::common::RW,
2829        >::from_register(self, 0)
2830    }
2831
2832    #[doc = "N-Channel Open-Drain Control"]
2833    #[inline(always)]
2834    pub fn ncodr(
2835        self,
2836    ) -> crate::common::RegisterField<
2837        6,
2838        0x1,
2839        1,
2840        0,
2841        p0pfs_ha::Ncodr,
2842        p0pfs_ha::Ncodr,
2843        P0PfsHa_SPEC,
2844        crate::common::RW,
2845    > {
2846        crate::common::RegisterField::<
2847            6,
2848            0x1,
2849            1,
2850            0,
2851            p0pfs_ha::Ncodr,
2852            p0pfs_ha::Ncodr,
2853            P0PfsHa_SPEC,
2854            crate::common::RW,
2855        >::from_register(self, 0)
2856    }
2857
2858    #[doc = "IRQ Input Enable"]
2859    #[inline(always)]
2860    pub fn isel(
2861        self,
2862    ) -> crate::common::RegisterField<
2863        14,
2864        0x1,
2865        1,
2866        0,
2867        p0pfs_ha::Isel,
2868        p0pfs_ha::Isel,
2869        P0PfsHa_SPEC,
2870        crate::common::RW,
2871    > {
2872        crate::common::RegisterField::<
2873            14,
2874            0x1,
2875            1,
2876            0,
2877            p0pfs_ha::Isel,
2878            p0pfs_ha::Isel,
2879            P0PfsHa_SPEC,
2880            crate::common::RW,
2881        >::from_register(self, 0)
2882    }
2883
2884    #[doc = "Analog Input Enable"]
2885    #[inline(always)]
2886    pub fn asel(
2887        self,
2888    ) -> crate::common::RegisterField<
2889        15,
2890        0x1,
2891        1,
2892        0,
2893        p0pfs_ha::Asel,
2894        p0pfs_ha::Asel,
2895        P0PfsHa_SPEC,
2896        crate::common::RW,
2897    > {
2898        crate::common::RegisterField::<
2899            15,
2900            0x1,
2901            1,
2902            0,
2903            p0pfs_ha::Asel,
2904            p0pfs_ha::Asel,
2905            P0PfsHa_SPEC,
2906            crate::common::RW,
2907        >::from_register(self, 0)
2908    }
2909}
2910impl ::core::default::Default for P0PfsHa {
2911    #[inline(always)]
2912    fn default() -> P0PfsHa {
2913        <crate::RegValueT<P0PfsHa_SPEC> as RegisterValue<_>>::new(0)
2914    }
2915}
2916pub mod p0pfs_ha {
2917
2918    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2919    pub struct Podr_SPEC;
2920    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
2921    impl Podr {
2922        #[doc = "Output low"]
2923        pub const _0: Self = Self::new(0);
2924
2925        #[doc = "Output high"]
2926        pub const _1: Self = Self::new(1);
2927    }
2928    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2929    pub struct Pidr_SPEC;
2930    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
2931    impl Pidr {
2932        #[doc = "Low level"]
2933        pub const _0: Self = Self::new(0);
2934
2935        #[doc = "High level"]
2936        pub const _1: Self = Self::new(1);
2937    }
2938    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2939    pub struct Pdr_SPEC;
2940    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
2941    impl Pdr {
2942        #[doc = "Input (functions as an input pin)"]
2943        pub const _0: Self = Self::new(0);
2944
2945        #[doc = "Output (functions as an output pin)"]
2946        pub const _1: Self = Self::new(1);
2947    }
2948    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2949    pub struct Pcr_SPEC;
2950    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
2951    impl Pcr {
2952        #[doc = "Disable input pull-up"]
2953        pub const _0: Self = Self::new(0);
2954
2955        #[doc = "Enable input pull-up"]
2956        pub const _1: Self = Self::new(1);
2957    }
2958    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2959    pub struct Ncodr_SPEC;
2960    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
2961    impl Ncodr {
2962        #[doc = "Output CMOS"]
2963        pub const _0: Self = Self::new(0);
2964
2965        #[doc = "Output NMOS open-drain"]
2966        pub const _1: Self = Self::new(1);
2967    }
2968    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2969    pub struct Isel_SPEC;
2970    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
2971    impl Isel {
2972        #[doc = "Do not use as IRQn input pin"]
2973        pub const _0: Self = Self::new(0);
2974
2975        #[doc = "Use as IRQn input pin"]
2976        pub const _1: Self = Self::new(1);
2977    }
2978    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2979    pub struct Asel_SPEC;
2980    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
2981    impl Asel {
2982        #[doc = "Do not use as analog pin"]
2983        pub const _0: Self = Self::new(0);
2984
2985        #[doc = "Use as analog pin"]
2986        pub const _1: Self = Self::new(1);
2987    }
2988}
2989#[doc(hidden)]
2990#[derive(Copy, Clone, Eq, PartialEq)]
2991pub struct P0PfsBy_SPEC;
2992impl crate::sealed::RegSpec for P0PfsBy_SPEC {
2993    type DataType = u8;
2994}
2995
2996#[doc = "Port 0%s Pin Function Select Register"]
2997pub type P0PfsBy = crate::RegValueT<P0PfsBy_SPEC>;
2998
2999impl P0PfsBy {
3000    #[doc = "Port Output Data"]
3001    #[inline(always)]
3002    pub fn podr(
3003        self,
3004    ) -> crate::common::RegisterField<
3005        0,
3006        0x1,
3007        1,
3008        0,
3009        p0pfs_by::Podr,
3010        p0pfs_by::Podr,
3011        P0PfsBy_SPEC,
3012        crate::common::RW,
3013    > {
3014        crate::common::RegisterField::<
3015            0,
3016            0x1,
3017            1,
3018            0,
3019            p0pfs_by::Podr,
3020            p0pfs_by::Podr,
3021            P0PfsBy_SPEC,
3022            crate::common::RW,
3023        >::from_register(self, 0)
3024    }
3025
3026    #[doc = "Port State"]
3027    #[inline(always)]
3028    pub fn pidr(
3029        self,
3030    ) -> crate::common::RegisterField<
3031        1,
3032        0x1,
3033        1,
3034        0,
3035        p0pfs_by::Pidr,
3036        p0pfs_by::Pidr,
3037        P0PfsBy_SPEC,
3038        crate::common::R,
3039    > {
3040        crate::common::RegisterField::<
3041            1,
3042            0x1,
3043            1,
3044            0,
3045            p0pfs_by::Pidr,
3046            p0pfs_by::Pidr,
3047            P0PfsBy_SPEC,
3048            crate::common::R,
3049        >::from_register(self, 0)
3050    }
3051
3052    #[doc = "Port Direction"]
3053    #[inline(always)]
3054    pub fn pdr(
3055        self,
3056    ) -> crate::common::RegisterField<
3057        2,
3058        0x1,
3059        1,
3060        0,
3061        p0pfs_by::Pdr,
3062        p0pfs_by::Pdr,
3063        P0PfsBy_SPEC,
3064        crate::common::RW,
3065    > {
3066        crate::common::RegisterField::<
3067            2,
3068            0x1,
3069            1,
3070            0,
3071            p0pfs_by::Pdr,
3072            p0pfs_by::Pdr,
3073            P0PfsBy_SPEC,
3074            crate::common::RW,
3075        >::from_register(self, 0)
3076    }
3077
3078    #[doc = "Pull-up Control"]
3079    #[inline(always)]
3080    pub fn pcr(
3081        self,
3082    ) -> crate::common::RegisterField<
3083        4,
3084        0x1,
3085        1,
3086        0,
3087        p0pfs_by::Pcr,
3088        p0pfs_by::Pcr,
3089        P0PfsBy_SPEC,
3090        crate::common::RW,
3091    > {
3092        crate::common::RegisterField::<
3093            4,
3094            0x1,
3095            1,
3096            0,
3097            p0pfs_by::Pcr,
3098            p0pfs_by::Pcr,
3099            P0PfsBy_SPEC,
3100            crate::common::RW,
3101        >::from_register(self, 0)
3102    }
3103
3104    #[doc = "N-Channel Open-Drain Control"]
3105    #[inline(always)]
3106    pub fn ncodr(
3107        self,
3108    ) -> crate::common::RegisterField<
3109        6,
3110        0x1,
3111        1,
3112        0,
3113        p0pfs_by::Ncodr,
3114        p0pfs_by::Ncodr,
3115        P0PfsBy_SPEC,
3116        crate::common::RW,
3117    > {
3118        crate::common::RegisterField::<
3119            6,
3120            0x1,
3121            1,
3122            0,
3123            p0pfs_by::Ncodr,
3124            p0pfs_by::Ncodr,
3125            P0PfsBy_SPEC,
3126            crate::common::RW,
3127        >::from_register(self, 0)
3128    }
3129}
3130impl ::core::default::Default for P0PfsBy {
3131    #[inline(always)]
3132    fn default() -> P0PfsBy {
3133        <crate::RegValueT<P0PfsBy_SPEC> as RegisterValue<_>>::new(0)
3134    }
3135}
3136pub mod p0pfs_by {
3137
3138    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3139    pub struct Podr_SPEC;
3140    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
3141    impl Podr {
3142        #[doc = "Output low"]
3143        pub const _0: Self = Self::new(0);
3144
3145        #[doc = "Output high"]
3146        pub const _1: Self = Self::new(1);
3147    }
3148    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3149    pub struct Pidr_SPEC;
3150    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
3151    impl Pidr {
3152        #[doc = "Low level"]
3153        pub const _0: Self = Self::new(0);
3154
3155        #[doc = "High level"]
3156        pub const _1: Self = Self::new(1);
3157    }
3158    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3159    pub struct Pdr_SPEC;
3160    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
3161    impl Pdr {
3162        #[doc = "Input (functions as an input pin)"]
3163        pub const _0: Self = Self::new(0);
3164
3165        #[doc = "Output (functions as an output pin)"]
3166        pub const _1: Self = Self::new(1);
3167    }
3168    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3169    pub struct Pcr_SPEC;
3170    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
3171    impl Pcr {
3172        #[doc = "Disable input pull-up"]
3173        pub const _0: Self = Self::new(0);
3174
3175        #[doc = "Enable input pull-up"]
3176        pub const _1: Self = Self::new(1);
3177    }
3178    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3179    pub struct Ncodr_SPEC;
3180    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
3181    impl Ncodr {
3182        #[doc = "Output CMOS"]
3183        pub const _0: Self = Self::new(0);
3184
3185        #[doc = "Output NMOS open-drain"]
3186        pub const _1: Self = Self::new(1);
3187    }
3188}
3189#[doc(hidden)]
3190#[derive(Copy, Clone, Eq, PartialEq)]
3191pub struct P10Pfs_SPEC;
3192impl crate::sealed::RegSpec for P10Pfs_SPEC {
3193    type DataType = u32;
3194}
3195
3196#[doc = "Port 10%s Pin Function Select Register"]
3197pub type P10Pfs = crate::RegValueT<P10Pfs_SPEC>;
3198
3199impl P10Pfs {
3200    #[doc = "Port Output Data"]
3201    #[inline(always)]
3202    pub fn podr(
3203        self,
3204    ) -> crate::common::RegisterField<
3205        0,
3206        0x1,
3207        1,
3208        0,
3209        p10pfs::Podr,
3210        p10pfs::Podr,
3211        P10Pfs_SPEC,
3212        crate::common::RW,
3213    > {
3214        crate::common::RegisterField::<
3215            0,
3216            0x1,
3217            1,
3218            0,
3219            p10pfs::Podr,
3220            p10pfs::Podr,
3221            P10Pfs_SPEC,
3222            crate::common::RW,
3223        >::from_register(self, 0)
3224    }
3225
3226    #[doc = "Port State"]
3227    #[inline(always)]
3228    pub fn pidr(
3229        self,
3230    ) -> crate::common::RegisterField<
3231        1,
3232        0x1,
3233        1,
3234        0,
3235        p10pfs::Pidr,
3236        p10pfs::Pidr,
3237        P10Pfs_SPEC,
3238        crate::common::R,
3239    > {
3240        crate::common::RegisterField::<
3241            1,
3242            0x1,
3243            1,
3244            0,
3245            p10pfs::Pidr,
3246            p10pfs::Pidr,
3247            P10Pfs_SPEC,
3248            crate::common::R,
3249        >::from_register(self, 0)
3250    }
3251
3252    #[doc = "Port Direction"]
3253    #[inline(always)]
3254    pub fn pdr(
3255        self,
3256    ) -> crate::common::RegisterField<
3257        2,
3258        0x1,
3259        1,
3260        0,
3261        p10pfs::Pdr,
3262        p10pfs::Pdr,
3263        P10Pfs_SPEC,
3264        crate::common::RW,
3265    > {
3266        crate::common::RegisterField::<
3267            2,
3268            0x1,
3269            1,
3270            0,
3271            p10pfs::Pdr,
3272            p10pfs::Pdr,
3273            P10Pfs_SPEC,
3274            crate::common::RW,
3275        >::from_register(self, 0)
3276    }
3277
3278    #[doc = "Pull-up Control"]
3279    #[inline(always)]
3280    pub fn pcr(
3281        self,
3282    ) -> crate::common::RegisterField<
3283        4,
3284        0x1,
3285        1,
3286        0,
3287        p10pfs::Pcr,
3288        p10pfs::Pcr,
3289        P10Pfs_SPEC,
3290        crate::common::RW,
3291    > {
3292        crate::common::RegisterField::<
3293            4,
3294            0x1,
3295            1,
3296            0,
3297            p10pfs::Pcr,
3298            p10pfs::Pcr,
3299            P10Pfs_SPEC,
3300            crate::common::RW,
3301        >::from_register(self, 0)
3302    }
3303
3304    #[doc = "N-Channel Open-Drain Control"]
3305    #[inline(always)]
3306    pub fn ncodr(
3307        self,
3308    ) -> crate::common::RegisterField<
3309        6,
3310        0x1,
3311        1,
3312        0,
3313        p10pfs::Ncodr,
3314        p10pfs::Ncodr,
3315        P10Pfs_SPEC,
3316        crate::common::RW,
3317    > {
3318        crate::common::RegisterField::<
3319            6,
3320            0x1,
3321            1,
3322            0,
3323            p10pfs::Ncodr,
3324            p10pfs::Ncodr,
3325            P10Pfs_SPEC,
3326            crate::common::RW,
3327        >::from_register(self, 0)
3328    }
3329
3330    #[doc = "Event on Falling/Event on Rising"]
3331    #[inline(always)]
3332    pub fn eofr(
3333        self,
3334    ) -> crate::common::RegisterField<
3335        12,
3336        0x3,
3337        1,
3338        0,
3339        p10pfs::Eofr,
3340        p10pfs::Eofr,
3341        P10Pfs_SPEC,
3342        crate::common::RW,
3343    > {
3344        crate::common::RegisterField::<
3345            12,
3346            0x3,
3347            1,
3348            0,
3349            p10pfs::Eofr,
3350            p10pfs::Eofr,
3351            P10Pfs_SPEC,
3352            crate::common::RW,
3353        >::from_register(self, 0)
3354    }
3355
3356    #[doc = "IRQ Input Enable"]
3357    #[inline(always)]
3358    pub fn isel(
3359        self,
3360    ) -> crate::common::RegisterField<
3361        14,
3362        0x1,
3363        1,
3364        0,
3365        p10pfs::Isel,
3366        p10pfs::Isel,
3367        P10Pfs_SPEC,
3368        crate::common::RW,
3369    > {
3370        crate::common::RegisterField::<
3371            14,
3372            0x1,
3373            1,
3374            0,
3375            p10pfs::Isel,
3376            p10pfs::Isel,
3377            P10Pfs_SPEC,
3378            crate::common::RW,
3379        >::from_register(self, 0)
3380    }
3381
3382    #[doc = "Analog Input Enable"]
3383    #[inline(always)]
3384    pub fn asel(
3385        self,
3386    ) -> crate::common::RegisterField<
3387        15,
3388        0x1,
3389        1,
3390        0,
3391        p10pfs::Asel,
3392        p10pfs::Asel,
3393        P10Pfs_SPEC,
3394        crate::common::RW,
3395    > {
3396        crate::common::RegisterField::<
3397            15,
3398            0x1,
3399            1,
3400            0,
3401            p10pfs::Asel,
3402            p10pfs::Asel,
3403            P10Pfs_SPEC,
3404            crate::common::RW,
3405        >::from_register(self, 0)
3406    }
3407
3408    #[doc = "Port Mode Control"]
3409    #[inline(always)]
3410    pub fn pmr(
3411        self,
3412    ) -> crate::common::RegisterField<
3413        16,
3414        0x1,
3415        1,
3416        0,
3417        p10pfs::Pmr,
3418        p10pfs::Pmr,
3419        P10Pfs_SPEC,
3420        crate::common::RW,
3421    > {
3422        crate::common::RegisterField::<
3423            16,
3424            0x1,
3425            1,
3426            0,
3427            p10pfs::Pmr,
3428            p10pfs::Pmr,
3429            P10Pfs_SPEC,
3430            crate::common::RW,
3431        >::from_register(self, 0)
3432    }
3433
3434    #[doc = "Peripheral Select"]
3435    #[inline(always)]
3436    pub fn psel(
3437        self,
3438    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P10Pfs_SPEC, crate::common::RW> {
3439        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P10Pfs_SPEC,crate::common::RW>::from_register(self,0)
3440    }
3441}
3442impl ::core::default::Default for P10Pfs {
3443    #[inline(always)]
3444    fn default() -> P10Pfs {
3445        <crate::RegValueT<P10Pfs_SPEC> as RegisterValue<_>>::new(0)
3446    }
3447}
3448pub mod p10pfs {
3449
3450    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3451    pub struct Podr_SPEC;
3452    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
3453    impl Podr {
3454        #[doc = "Output low"]
3455        pub const _0: Self = Self::new(0);
3456
3457        #[doc = "Output high"]
3458        pub const _1: Self = Self::new(1);
3459    }
3460    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3461    pub struct Pidr_SPEC;
3462    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
3463    impl Pidr {
3464        #[doc = "Low level"]
3465        pub const _0: Self = Self::new(0);
3466
3467        #[doc = "High level"]
3468        pub const _1: Self = Self::new(1);
3469    }
3470    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3471    pub struct Pdr_SPEC;
3472    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
3473    impl Pdr {
3474        #[doc = "Input (functions as an input pin)"]
3475        pub const _0: Self = Self::new(0);
3476
3477        #[doc = "Output (functions as an output pin)"]
3478        pub const _1: Self = Self::new(1);
3479    }
3480    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3481    pub struct Pcr_SPEC;
3482    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
3483    impl Pcr {
3484        #[doc = "Disable input pull-up"]
3485        pub const _0: Self = Self::new(0);
3486
3487        #[doc = "Enable input pull-up"]
3488        pub const _1: Self = Self::new(1);
3489    }
3490    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3491    pub struct Ncodr_SPEC;
3492    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
3493    impl Ncodr {
3494        #[doc = "Output CMOS"]
3495        pub const _0: Self = Self::new(0);
3496
3497        #[doc = "Output NMOS open-drain"]
3498        pub const _1: Self = Self::new(1);
3499    }
3500    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3501    pub struct Eofr_SPEC;
3502    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
3503    impl Eofr {
3504        #[doc = "Don\'t care"]
3505        pub const _00: Self = Self::new(0);
3506
3507        #[doc = "Detect rising edge"]
3508        pub const _01: Self = Self::new(1);
3509
3510        #[doc = "Detect falling edge"]
3511        pub const _10: Self = Self::new(2);
3512
3513        #[doc = "Detect both edges"]
3514        pub const _11: Self = Self::new(3);
3515    }
3516    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3517    pub struct Isel_SPEC;
3518    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
3519    impl Isel {
3520        #[doc = "Do not use as IRQn input pin"]
3521        pub const _0: Self = Self::new(0);
3522
3523        #[doc = "Use as IRQn input pin"]
3524        pub const _1: Self = Self::new(1);
3525    }
3526    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3527    pub struct Asel_SPEC;
3528    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
3529    impl Asel {
3530        #[doc = "Do not use as analog pin"]
3531        pub const _0: Self = Self::new(0);
3532
3533        #[doc = "Use as analog pin"]
3534        pub const _1: Self = Self::new(1);
3535    }
3536    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3537    pub struct Pmr_SPEC;
3538    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
3539    impl Pmr {
3540        #[doc = "Use as general I/O pin"]
3541        pub const _0: Self = Self::new(0);
3542
3543        #[doc = "Use as I/O port for peripheral functions"]
3544        pub const _1: Self = Self::new(1);
3545    }
3546}
3547#[doc(hidden)]
3548#[derive(Copy, Clone, Eq, PartialEq)]
3549pub struct P10PfsHa_SPEC;
3550impl crate::sealed::RegSpec for P10PfsHa_SPEC {
3551    type DataType = u16;
3552}
3553
3554#[doc = "Port 10%s Pin Function Select Register"]
3555pub type P10PfsHa = crate::RegValueT<P10PfsHa_SPEC>;
3556
3557impl P10PfsHa {
3558    #[doc = "Port Output Data"]
3559    #[inline(always)]
3560    pub fn podr(
3561        self,
3562    ) -> crate::common::RegisterField<
3563        0,
3564        0x1,
3565        1,
3566        0,
3567        p10pfs_ha::Podr,
3568        p10pfs_ha::Podr,
3569        P10PfsHa_SPEC,
3570        crate::common::RW,
3571    > {
3572        crate::common::RegisterField::<
3573            0,
3574            0x1,
3575            1,
3576            0,
3577            p10pfs_ha::Podr,
3578            p10pfs_ha::Podr,
3579            P10PfsHa_SPEC,
3580            crate::common::RW,
3581        >::from_register(self, 0)
3582    }
3583
3584    #[doc = "Port State"]
3585    #[inline(always)]
3586    pub fn pidr(
3587        self,
3588    ) -> crate::common::RegisterField<
3589        1,
3590        0x1,
3591        1,
3592        0,
3593        p10pfs_ha::Pidr,
3594        p10pfs_ha::Pidr,
3595        P10PfsHa_SPEC,
3596        crate::common::R,
3597    > {
3598        crate::common::RegisterField::<
3599            1,
3600            0x1,
3601            1,
3602            0,
3603            p10pfs_ha::Pidr,
3604            p10pfs_ha::Pidr,
3605            P10PfsHa_SPEC,
3606            crate::common::R,
3607        >::from_register(self, 0)
3608    }
3609
3610    #[doc = "Port Direction"]
3611    #[inline(always)]
3612    pub fn pdr(
3613        self,
3614    ) -> crate::common::RegisterField<
3615        2,
3616        0x1,
3617        1,
3618        0,
3619        p10pfs_ha::Pdr,
3620        p10pfs_ha::Pdr,
3621        P10PfsHa_SPEC,
3622        crate::common::RW,
3623    > {
3624        crate::common::RegisterField::<
3625            2,
3626            0x1,
3627            1,
3628            0,
3629            p10pfs_ha::Pdr,
3630            p10pfs_ha::Pdr,
3631            P10PfsHa_SPEC,
3632            crate::common::RW,
3633        >::from_register(self, 0)
3634    }
3635
3636    #[doc = "Pull-up Control"]
3637    #[inline(always)]
3638    pub fn pcr(
3639        self,
3640    ) -> crate::common::RegisterField<
3641        4,
3642        0x1,
3643        1,
3644        0,
3645        p10pfs_ha::Pcr,
3646        p10pfs_ha::Pcr,
3647        P10PfsHa_SPEC,
3648        crate::common::RW,
3649    > {
3650        crate::common::RegisterField::<
3651            4,
3652            0x1,
3653            1,
3654            0,
3655            p10pfs_ha::Pcr,
3656            p10pfs_ha::Pcr,
3657            P10PfsHa_SPEC,
3658            crate::common::RW,
3659        >::from_register(self, 0)
3660    }
3661
3662    #[doc = "N-Channel Open-Drain Control"]
3663    #[inline(always)]
3664    pub fn ncodr(
3665        self,
3666    ) -> crate::common::RegisterField<
3667        6,
3668        0x1,
3669        1,
3670        0,
3671        p10pfs_ha::Ncodr,
3672        p10pfs_ha::Ncodr,
3673        P10PfsHa_SPEC,
3674        crate::common::RW,
3675    > {
3676        crate::common::RegisterField::<
3677            6,
3678            0x1,
3679            1,
3680            0,
3681            p10pfs_ha::Ncodr,
3682            p10pfs_ha::Ncodr,
3683            P10PfsHa_SPEC,
3684            crate::common::RW,
3685        >::from_register(self, 0)
3686    }
3687
3688    #[doc = "Event on Falling/Event on Rising"]
3689    #[inline(always)]
3690    pub fn eofr(
3691        self,
3692    ) -> crate::common::RegisterField<
3693        12,
3694        0x3,
3695        1,
3696        0,
3697        p10pfs_ha::Eofr,
3698        p10pfs_ha::Eofr,
3699        P10PfsHa_SPEC,
3700        crate::common::RW,
3701    > {
3702        crate::common::RegisterField::<
3703            12,
3704            0x3,
3705            1,
3706            0,
3707            p10pfs_ha::Eofr,
3708            p10pfs_ha::Eofr,
3709            P10PfsHa_SPEC,
3710            crate::common::RW,
3711        >::from_register(self, 0)
3712    }
3713
3714    #[doc = "IRQ Input Enable"]
3715    #[inline(always)]
3716    pub fn isel(
3717        self,
3718    ) -> crate::common::RegisterField<
3719        14,
3720        0x1,
3721        1,
3722        0,
3723        p10pfs_ha::Isel,
3724        p10pfs_ha::Isel,
3725        P10PfsHa_SPEC,
3726        crate::common::RW,
3727    > {
3728        crate::common::RegisterField::<
3729            14,
3730            0x1,
3731            1,
3732            0,
3733            p10pfs_ha::Isel,
3734            p10pfs_ha::Isel,
3735            P10PfsHa_SPEC,
3736            crate::common::RW,
3737        >::from_register(self, 0)
3738    }
3739
3740    #[doc = "Analog Input Enable"]
3741    #[inline(always)]
3742    pub fn asel(
3743        self,
3744    ) -> crate::common::RegisterField<
3745        15,
3746        0x1,
3747        1,
3748        0,
3749        p10pfs_ha::Asel,
3750        p10pfs_ha::Asel,
3751        P10PfsHa_SPEC,
3752        crate::common::RW,
3753    > {
3754        crate::common::RegisterField::<
3755            15,
3756            0x1,
3757            1,
3758            0,
3759            p10pfs_ha::Asel,
3760            p10pfs_ha::Asel,
3761            P10PfsHa_SPEC,
3762            crate::common::RW,
3763        >::from_register(self, 0)
3764    }
3765}
3766impl ::core::default::Default for P10PfsHa {
3767    #[inline(always)]
3768    fn default() -> P10PfsHa {
3769        <crate::RegValueT<P10PfsHa_SPEC> as RegisterValue<_>>::new(0)
3770    }
3771}
3772pub mod p10pfs_ha {
3773
3774    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3775    pub struct Podr_SPEC;
3776    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
3777    impl Podr {
3778        #[doc = "Output low"]
3779        pub const _0: Self = Self::new(0);
3780
3781        #[doc = "Output high"]
3782        pub const _1: Self = Self::new(1);
3783    }
3784    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3785    pub struct Pidr_SPEC;
3786    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
3787    impl Pidr {
3788        #[doc = "Low level"]
3789        pub const _0: Self = Self::new(0);
3790
3791        #[doc = "High level"]
3792        pub const _1: Self = Self::new(1);
3793    }
3794    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3795    pub struct Pdr_SPEC;
3796    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
3797    impl Pdr {
3798        #[doc = "Input (functions as an input pin)"]
3799        pub const _0: Self = Self::new(0);
3800
3801        #[doc = "Output (functions as an output pin)"]
3802        pub const _1: Self = Self::new(1);
3803    }
3804    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3805    pub struct Pcr_SPEC;
3806    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
3807    impl Pcr {
3808        #[doc = "Disable input pull-up"]
3809        pub const _0: Self = Self::new(0);
3810
3811        #[doc = "Enable input pull-up"]
3812        pub const _1: Self = Self::new(1);
3813    }
3814    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3815    pub struct Ncodr_SPEC;
3816    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
3817    impl Ncodr {
3818        #[doc = "Output CMOS"]
3819        pub const _0: Self = Self::new(0);
3820
3821        #[doc = "Output NMOS open-drain"]
3822        pub const _1: Self = Self::new(1);
3823    }
3824    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3825    pub struct Eofr_SPEC;
3826    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
3827    impl Eofr {
3828        #[doc = "Don\'t care"]
3829        pub const _00: Self = Self::new(0);
3830
3831        #[doc = "Detect rising edge"]
3832        pub const _01: Self = Self::new(1);
3833
3834        #[doc = "Detect falling edge"]
3835        pub const _10: Self = Self::new(2);
3836
3837        #[doc = "Detect both edges"]
3838        pub const _11: Self = Self::new(3);
3839    }
3840    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3841    pub struct Isel_SPEC;
3842    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
3843    impl Isel {
3844        #[doc = "Do not use as IRQn input pin"]
3845        pub const _0: Self = Self::new(0);
3846
3847        #[doc = "Use as IRQn input pin"]
3848        pub const _1: Self = Self::new(1);
3849    }
3850    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3851    pub struct Asel_SPEC;
3852    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
3853    impl Asel {
3854        #[doc = "Do not use as analog pin"]
3855        pub const _0: Self = Self::new(0);
3856
3857        #[doc = "Use as analog pin"]
3858        pub const _1: Self = Self::new(1);
3859    }
3860}
3861#[doc(hidden)]
3862#[derive(Copy, Clone, Eq, PartialEq)]
3863pub struct P10PfsBy_SPEC;
3864impl crate::sealed::RegSpec for P10PfsBy_SPEC {
3865    type DataType = u8;
3866}
3867
3868#[doc = "Port 10%s Pin Function Select Register"]
3869pub type P10PfsBy = crate::RegValueT<P10PfsBy_SPEC>;
3870
3871impl P10PfsBy {
3872    #[doc = "Port Output Data"]
3873    #[inline(always)]
3874    pub fn podr(
3875        self,
3876    ) -> crate::common::RegisterField<
3877        0,
3878        0x1,
3879        1,
3880        0,
3881        p10pfs_by::Podr,
3882        p10pfs_by::Podr,
3883        P10PfsBy_SPEC,
3884        crate::common::RW,
3885    > {
3886        crate::common::RegisterField::<
3887            0,
3888            0x1,
3889            1,
3890            0,
3891            p10pfs_by::Podr,
3892            p10pfs_by::Podr,
3893            P10PfsBy_SPEC,
3894            crate::common::RW,
3895        >::from_register(self, 0)
3896    }
3897
3898    #[doc = "Port State"]
3899    #[inline(always)]
3900    pub fn pidr(
3901        self,
3902    ) -> crate::common::RegisterField<
3903        1,
3904        0x1,
3905        1,
3906        0,
3907        p10pfs_by::Pidr,
3908        p10pfs_by::Pidr,
3909        P10PfsBy_SPEC,
3910        crate::common::R,
3911    > {
3912        crate::common::RegisterField::<
3913            1,
3914            0x1,
3915            1,
3916            0,
3917            p10pfs_by::Pidr,
3918            p10pfs_by::Pidr,
3919            P10PfsBy_SPEC,
3920            crate::common::R,
3921        >::from_register(self, 0)
3922    }
3923
3924    #[doc = "Port Direction"]
3925    #[inline(always)]
3926    pub fn pdr(
3927        self,
3928    ) -> crate::common::RegisterField<
3929        2,
3930        0x1,
3931        1,
3932        0,
3933        p10pfs_by::Pdr,
3934        p10pfs_by::Pdr,
3935        P10PfsBy_SPEC,
3936        crate::common::RW,
3937    > {
3938        crate::common::RegisterField::<
3939            2,
3940            0x1,
3941            1,
3942            0,
3943            p10pfs_by::Pdr,
3944            p10pfs_by::Pdr,
3945            P10PfsBy_SPEC,
3946            crate::common::RW,
3947        >::from_register(self, 0)
3948    }
3949
3950    #[doc = "Pull-up Control"]
3951    #[inline(always)]
3952    pub fn pcr(
3953        self,
3954    ) -> crate::common::RegisterField<
3955        4,
3956        0x1,
3957        1,
3958        0,
3959        p10pfs_by::Pcr,
3960        p10pfs_by::Pcr,
3961        P10PfsBy_SPEC,
3962        crate::common::RW,
3963    > {
3964        crate::common::RegisterField::<
3965            4,
3966            0x1,
3967            1,
3968            0,
3969            p10pfs_by::Pcr,
3970            p10pfs_by::Pcr,
3971            P10PfsBy_SPEC,
3972            crate::common::RW,
3973        >::from_register(self, 0)
3974    }
3975
3976    #[doc = "N-Channel Open-Drain Control"]
3977    #[inline(always)]
3978    pub fn ncodr(
3979        self,
3980    ) -> crate::common::RegisterField<
3981        6,
3982        0x1,
3983        1,
3984        0,
3985        p10pfs_by::Ncodr,
3986        p10pfs_by::Ncodr,
3987        P10PfsBy_SPEC,
3988        crate::common::RW,
3989    > {
3990        crate::common::RegisterField::<
3991            6,
3992            0x1,
3993            1,
3994            0,
3995            p10pfs_by::Ncodr,
3996            p10pfs_by::Ncodr,
3997            P10PfsBy_SPEC,
3998            crate::common::RW,
3999        >::from_register(self, 0)
4000    }
4001}
4002impl ::core::default::Default for P10PfsBy {
4003    #[inline(always)]
4004    fn default() -> P10PfsBy {
4005        <crate::RegValueT<P10PfsBy_SPEC> as RegisterValue<_>>::new(0)
4006    }
4007}
4008pub mod p10pfs_by {
4009
4010    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4011    pub struct Podr_SPEC;
4012    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
4013    impl Podr {
4014        #[doc = "Output low"]
4015        pub const _0: Self = Self::new(0);
4016
4017        #[doc = "Output high"]
4018        pub const _1: Self = Self::new(1);
4019    }
4020    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4021    pub struct Pidr_SPEC;
4022    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
4023    impl Pidr {
4024        #[doc = "Low level"]
4025        pub const _0: Self = Self::new(0);
4026
4027        #[doc = "High level"]
4028        pub const _1: Self = Self::new(1);
4029    }
4030    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4031    pub struct Pdr_SPEC;
4032    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
4033    impl Pdr {
4034        #[doc = "Input (functions as an input pin)"]
4035        pub const _0: Self = Self::new(0);
4036
4037        #[doc = "Output (functions as an output pin)"]
4038        pub const _1: Self = Self::new(1);
4039    }
4040    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4041    pub struct Pcr_SPEC;
4042    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
4043    impl Pcr {
4044        #[doc = "Disable input pull-up"]
4045        pub const _0: Self = Self::new(0);
4046
4047        #[doc = "Enable input pull-up"]
4048        pub const _1: Self = Self::new(1);
4049    }
4050    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4051    pub struct Ncodr_SPEC;
4052    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
4053    impl Ncodr {
4054        #[doc = "Output CMOS"]
4055        pub const _0: Self = Self::new(0);
4056
4057        #[doc = "Output NMOS open-drain"]
4058        pub const _1: Self = Self::new(1);
4059    }
4060}
4061#[doc(hidden)]
4062#[derive(Copy, Clone, Eq, PartialEq)]
4063pub struct P108Pfs_SPEC;
4064impl crate::sealed::RegSpec for P108Pfs_SPEC {
4065    type DataType = u32;
4066}
4067
4068#[doc = "Port 108 Pin Function Select Register"]
4069pub type P108Pfs = crate::RegValueT<P108Pfs_SPEC>;
4070
4071impl P108Pfs {
4072    #[doc = "Port Output Data"]
4073    #[inline(always)]
4074    pub fn podr(
4075        self,
4076    ) -> crate::common::RegisterField<
4077        0,
4078        0x1,
4079        1,
4080        0,
4081        p108pfs::Podr,
4082        p108pfs::Podr,
4083        P108Pfs_SPEC,
4084        crate::common::RW,
4085    > {
4086        crate::common::RegisterField::<
4087            0,
4088            0x1,
4089            1,
4090            0,
4091            p108pfs::Podr,
4092            p108pfs::Podr,
4093            P108Pfs_SPEC,
4094            crate::common::RW,
4095        >::from_register(self, 0)
4096    }
4097
4098    #[doc = "Port State"]
4099    #[inline(always)]
4100    pub fn pidr(
4101        self,
4102    ) -> crate::common::RegisterField<
4103        1,
4104        0x1,
4105        1,
4106        0,
4107        p108pfs::Pidr,
4108        p108pfs::Pidr,
4109        P108Pfs_SPEC,
4110        crate::common::R,
4111    > {
4112        crate::common::RegisterField::<
4113            1,
4114            0x1,
4115            1,
4116            0,
4117            p108pfs::Pidr,
4118            p108pfs::Pidr,
4119            P108Pfs_SPEC,
4120            crate::common::R,
4121        >::from_register(self, 0)
4122    }
4123
4124    #[doc = "Port Direction"]
4125    #[inline(always)]
4126    pub fn pdr(
4127        self,
4128    ) -> crate::common::RegisterField<
4129        2,
4130        0x1,
4131        1,
4132        0,
4133        p108pfs::Pdr,
4134        p108pfs::Pdr,
4135        P108Pfs_SPEC,
4136        crate::common::RW,
4137    > {
4138        crate::common::RegisterField::<
4139            2,
4140            0x1,
4141            1,
4142            0,
4143            p108pfs::Pdr,
4144            p108pfs::Pdr,
4145            P108Pfs_SPEC,
4146            crate::common::RW,
4147        >::from_register(self, 0)
4148    }
4149
4150    #[doc = "Pull-up Control"]
4151    #[inline(always)]
4152    pub fn pcr(
4153        self,
4154    ) -> crate::common::RegisterField<
4155        4,
4156        0x1,
4157        1,
4158        0,
4159        p108pfs::Pcr,
4160        p108pfs::Pcr,
4161        P108Pfs_SPEC,
4162        crate::common::RW,
4163    > {
4164        crate::common::RegisterField::<
4165            4,
4166            0x1,
4167            1,
4168            0,
4169            p108pfs::Pcr,
4170            p108pfs::Pcr,
4171            P108Pfs_SPEC,
4172            crate::common::RW,
4173        >::from_register(self, 0)
4174    }
4175
4176    #[doc = "N-Channel Open-Drain Control"]
4177    #[inline(always)]
4178    pub fn ncodr(
4179        self,
4180    ) -> crate::common::RegisterField<
4181        6,
4182        0x1,
4183        1,
4184        0,
4185        p108pfs::Ncodr,
4186        p108pfs::Ncodr,
4187        P108Pfs_SPEC,
4188        crate::common::RW,
4189    > {
4190        crate::common::RegisterField::<
4191            6,
4192            0x1,
4193            1,
4194            0,
4195            p108pfs::Ncodr,
4196            p108pfs::Ncodr,
4197            P108Pfs_SPEC,
4198            crate::common::RW,
4199        >::from_register(self, 0)
4200    }
4201
4202    #[doc = "Event on Falling/Event on Rising"]
4203    #[inline(always)]
4204    pub fn eofr(
4205        self,
4206    ) -> crate::common::RegisterField<
4207        12,
4208        0x3,
4209        1,
4210        0,
4211        p108pfs::Eofr,
4212        p108pfs::Eofr,
4213        P108Pfs_SPEC,
4214        crate::common::RW,
4215    > {
4216        crate::common::RegisterField::<
4217            12,
4218            0x3,
4219            1,
4220            0,
4221            p108pfs::Eofr,
4222            p108pfs::Eofr,
4223            P108Pfs_SPEC,
4224            crate::common::RW,
4225        >::from_register(self, 0)
4226    }
4227
4228    #[doc = "IRQ Input Enable"]
4229    #[inline(always)]
4230    pub fn isel(
4231        self,
4232    ) -> crate::common::RegisterField<
4233        14,
4234        0x1,
4235        1,
4236        0,
4237        p108pfs::Isel,
4238        p108pfs::Isel,
4239        P108Pfs_SPEC,
4240        crate::common::RW,
4241    > {
4242        crate::common::RegisterField::<
4243            14,
4244            0x1,
4245            1,
4246            0,
4247            p108pfs::Isel,
4248            p108pfs::Isel,
4249            P108Pfs_SPEC,
4250            crate::common::RW,
4251        >::from_register(self, 0)
4252    }
4253
4254    #[doc = "Analog Input Enable"]
4255    #[inline(always)]
4256    pub fn asel(
4257        self,
4258    ) -> crate::common::RegisterField<
4259        15,
4260        0x1,
4261        1,
4262        0,
4263        p108pfs::Asel,
4264        p108pfs::Asel,
4265        P108Pfs_SPEC,
4266        crate::common::RW,
4267    > {
4268        crate::common::RegisterField::<
4269            15,
4270            0x1,
4271            1,
4272            0,
4273            p108pfs::Asel,
4274            p108pfs::Asel,
4275            P108Pfs_SPEC,
4276            crate::common::RW,
4277        >::from_register(self, 0)
4278    }
4279
4280    #[doc = "Port Mode Control"]
4281    #[inline(always)]
4282    pub fn pmr(
4283        self,
4284    ) -> crate::common::RegisterField<
4285        16,
4286        0x1,
4287        1,
4288        0,
4289        p108pfs::Pmr,
4290        p108pfs::Pmr,
4291        P108Pfs_SPEC,
4292        crate::common::RW,
4293    > {
4294        crate::common::RegisterField::<
4295            16,
4296            0x1,
4297            1,
4298            0,
4299            p108pfs::Pmr,
4300            p108pfs::Pmr,
4301            P108Pfs_SPEC,
4302            crate::common::RW,
4303        >::from_register(self, 0)
4304    }
4305
4306    #[doc = "Peripheral Select"]
4307    #[inline(always)]
4308    pub fn psel(
4309        self,
4310    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P108Pfs_SPEC, crate::common::RW> {
4311        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P108Pfs_SPEC,crate::common::RW>::from_register(self,0)
4312    }
4313}
4314impl ::core::default::Default for P108Pfs {
4315    #[inline(always)]
4316    fn default() -> P108Pfs {
4317        <crate::RegValueT<P108Pfs_SPEC> as RegisterValue<_>>::new(65552)
4318    }
4319}
4320pub mod p108pfs {
4321
4322    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4323    pub struct Podr_SPEC;
4324    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
4325    impl Podr {
4326        #[doc = "Output low"]
4327        pub const _0: Self = Self::new(0);
4328
4329        #[doc = "Output high"]
4330        pub const _1: Self = Self::new(1);
4331    }
4332    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4333    pub struct Pidr_SPEC;
4334    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
4335    impl Pidr {
4336        #[doc = "Low level"]
4337        pub const _0: Self = Self::new(0);
4338
4339        #[doc = "High level"]
4340        pub const _1: Self = Self::new(1);
4341    }
4342    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4343    pub struct Pdr_SPEC;
4344    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
4345    impl Pdr {
4346        #[doc = "Input (functions as an input pin)"]
4347        pub const _0: Self = Self::new(0);
4348
4349        #[doc = "Output (functions as an output pin)"]
4350        pub const _1: Self = Self::new(1);
4351    }
4352    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4353    pub struct Pcr_SPEC;
4354    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
4355    impl Pcr {
4356        #[doc = "Disable input pull-up"]
4357        pub const _0: Self = Self::new(0);
4358
4359        #[doc = "Enable input pull-up"]
4360        pub const _1: Self = Self::new(1);
4361    }
4362    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4363    pub struct Ncodr_SPEC;
4364    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
4365    impl Ncodr {
4366        #[doc = "Output CMOS"]
4367        pub const _0: Self = Self::new(0);
4368
4369        #[doc = "Output NMOS open-drain"]
4370        pub const _1: Self = Self::new(1);
4371    }
4372    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4373    pub struct Eofr_SPEC;
4374    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
4375    impl Eofr {
4376        #[doc = "Don\'t care"]
4377        pub const _00: Self = Self::new(0);
4378
4379        #[doc = "Detect rising edge"]
4380        pub const _01: Self = Self::new(1);
4381
4382        #[doc = "Detect falling edge"]
4383        pub const _10: Self = Self::new(2);
4384
4385        #[doc = "Detect both edges"]
4386        pub const _11: Self = Self::new(3);
4387    }
4388    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4389    pub struct Isel_SPEC;
4390    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
4391    impl Isel {
4392        #[doc = "Do not use as IRQn input pin"]
4393        pub const _0: Self = Self::new(0);
4394
4395        #[doc = "Use as IRQn input pin"]
4396        pub const _1: Self = Self::new(1);
4397    }
4398    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4399    pub struct Asel_SPEC;
4400    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
4401    impl Asel {
4402        #[doc = "Do not use as analog pin"]
4403        pub const _0: Self = Self::new(0);
4404
4405        #[doc = "Use as analog pin"]
4406        pub const _1: Self = Self::new(1);
4407    }
4408    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4409    pub struct Pmr_SPEC;
4410    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
4411    impl Pmr {
4412        #[doc = "Use as general I/O pin"]
4413        pub const _0: Self = Self::new(0);
4414
4415        #[doc = "Use as I/O port for peripheral functions"]
4416        pub const _1: Self = Self::new(1);
4417    }
4418}
4419#[doc(hidden)]
4420#[derive(Copy, Clone, Eq, PartialEq)]
4421pub struct P108PfsHa_SPEC;
4422impl crate::sealed::RegSpec for P108PfsHa_SPEC {
4423    type DataType = u16;
4424}
4425
4426#[doc = "Port 108 Pin Function Select Register"]
4427pub type P108PfsHa = crate::RegValueT<P108PfsHa_SPEC>;
4428
4429impl P108PfsHa {
4430    #[doc = "Port Output Data"]
4431    #[inline(always)]
4432    pub fn podr(
4433        self,
4434    ) -> crate::common::RegisterField<
4435        0,
4436        0x1,
4437        1,
4438        0,
4439        p108pfs_ha::Podr,
4440        p108pfs_ha::Podr,
4441        P108PfsHa_SPEC,
4442        crate::common::RW,
4443    > {
4444        crate::common::RegisterField::<
4445            0,
4446            0x1,
4447            1,
4448            0,
4449            p108pfs_ha::Podr,
4450            p108pfs_ha::Podr,
4451            P108PfsHa_SPEC,
4452            crate::common::RW,
4453        >::from_register(self, 0)
4454    }
4455
4456    #[doc = "Port State"]
4457    #[inline(always)]
4458    pub fn pidr(
4459        self,
4460    ) -> crate::common::RegisterField<
4461        1,
4462        0x1,
4463        1,
4464        0,
4465        p108pfs_ha::Pidr,
4466        p108pfs_ha::Pidr,
4467        P108PfsHa_SPEC,
4468        crate::common::R,
4469    > {
4470        crate::common::RegisterField::<
4471            1,
4472            0x1,
4473            1,
4474            0,
4475            p108pfs_ha::Pidr,
4476            p108pfs_ha::Pidr,
4477            P108PfsHa_SPEC,
4478            crate::common::R,
4479        >::from_register(self, 0)
4480    }
4481
4482    #[doc = "Port Direction"]
4483    #[inline(always)]
4484    pub fn pdr(
4485        self,
4486    ) -> crate::common::RegisterField<
4487        2,
4488        0x1,
4489        1,
4490        0,
4491        p108pfs_ha::Pdr,
4492        p108pfs_ha::Pdr,
4493        P108PfsHa_SPEC,
4494        crate::common::RW,
4495    > {
4496        crate::common::RegisterField::<
4497            2,
4498            0x1,
4499            1,
4500            0,
4501            p108pfs_ha::Pdr,
4502            p108pfs_ha::Pdr,
4503            P108PfsHa_SPEC,
4504            crate::common::RW,
4505        >::from_register(self, 0)
4506    }
4507
4508    #[doc = "Pull-up Control"]
4509    #[inline(always)]
4510    pub fn pcr(
4511        self,
4512    ) -> crate::common::RegisterField<
4513        4,
4514        0x1,
4515        1,
4516        0,
4517        p108pfs_ha::Pcr,
4518        p108pfs_ha::Pcr,
4519        P108PfsHa_SPEC,
4520        crate::common::RW,
4521    > {
4522        crate::common::RegisterField::<
4523            4,
4524            0x1,
4525            1,
4526            0,
4527            p108pfs_ha::Pcr,
4528            p108pfs_ha::Pcr,
4529            P108PfsHa_SPEC,
4530            crate::common::RW,
4531        >::from_register(self, 0)
4532    }
4533
4534    #[doc = "N-Channel Open-Drain Control"]
4535    #[inline(always)]
4536    pub fn ncodr(
4537        self,
4538    ) -> crate::common::RegisterField<
4539        6,
4540        0x1,
4541        1,
4542        0,
4543        p108pfs_ha::Ncodr,
4544        p108pfs_ha::Ncodr,
4545        P108PfsHa_SPEC,
4546        crate::common::RW,
4547    > {
4548        crate::common::RegisterField::<
4549            6,
4550            0x1,
4551            1,
4552            0,
4553            p108pfs_ha::Ncodr,
4554            p108pfs_ha::Ncodr,
4555            P108PfsHa_SPEC,
4556            crate::common::RW,
4557        >::from_register(self, 0)
4558    }
4559
4560    #[doc = "Event on Falling/Event on Rising"]
4561    #[inline(always)]
4562    pub fn eofr(
4563        self,
4564    ) -> crate::common::RegisterField<
4565        12,
4566        0x3,
4567        1,
4568        0,
4569        p108pfs_ha::Eofr,
4570        p108pfs_ha::Eofr,
4571        P108PfsHa_SPEC,
4572        crate::common::RW,
4573    > {
4574        crate::common::RegisterField::<
4575            12,
4576            0x3,
4577            1,
4578            0,
4579            p108pfs_ha::Eofr,
4580            p108pfs_ha::Eofr,
4581            P108PfsHa_SPEC,
4582            crate::common::RW,
4583        >::from_register(self, 0)
4584    }
4585
4586    #[doc = "IRQ Input Enable"]
4587    #[inline(always)]
4588    pub fn isel(
4589        self,
4590    ) -> crate::common::RegisterField<
4591        14,
4592        0x1,
4593        1,
4594        0,
4595        p108pfs_ha::Isel,
4596        p108pfs_ha::Isel,
4597        P108PfsHa_SPEC,
4598        crate::common::RW,
4599    > {
4600        crate::common::RegisterField::<
4601            14,
4602            0x1,
4603            1,
4604            0,
4605            p108pfs_ha::Isel,
4606            p108pfs_ha::Isel,
4607            P108PfsHa_SPEC,
4608            crate::common::RW,
4609        >::from_register(self, 0)
4610    }
4611
4612    #[doc = "Analog Input Enable"]
4613    #[inline(always)]
4614    pub fn asel(
4615        self,
4616    ) -> crate::common::RegisterField<
4617        15,
4618        0x1,
4619        1,
4620        0,
4621        p108pfs_ha::Asel,
4622        p108pfs_ha::Asel,
4623        P108PfsHa_SPEC,
4624        crate::common::RW,
4625    > {
4626        crate::common::RegisterField::<
4627            15,
4628            0x1,
4629            1,
4630            0,
4631            p108pfs_ha::Asel,
4632            p108pfs_ha::Asel,
4633            P108PfsHa_SPEC,
4634            crate::common::RW,
4635        >::from_register(self, 0)
4636    }
4637}
4638impl ::core::default::Default for P108PfsHa {
4639    #[inline(always)]
4640    fn default() -> P108PfsHa {
4641        <crate::RegValueT<P108PfsHa_SPEC> as RegisterValue<_>>::new(16)
4642    }
4643}
4644pub mod p108pfs_ha {
4645
4646    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4647    pub struct Podr_SPEC;
4648    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
4649    impl Podr {
4650        #[doc = "Output low"]
4651        pub const _0: Self = Self::new(0);
4652
4653        #[doc = "Output high"]
4654        pub const _1: Self = Self::new(1);
4655    }
4656    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4657    pub struct Pidr_SPEC;
4658    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
4659    impl Pidr {
4660        #[doc = "Low level"]
4661        pub const _0: Self = Self::new(0);
4662
4663        #[doc = "High level"]
4664        pub const _1: Self = Self::new(1);
4665    }
4666    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4667    pub struct Pdr_SPEC;
4668    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
4669    impl Pdr {
4670        #[doc = "Input (functions as an input pin)"]
4671        pub const _0: Self = Self::new(0);
4672
4673        #[doc = "Output (functions as an output pin)"]
4674        pub const _1: Self = Self::new(1);
4675    }
4676    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4677    pub struct Pcr_SPEC;
4678    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
4679    impl Pcr {
4680        #[doc = "Disable input pull-up"]
4681        pub const _0: Self = Self::new(0);
4682
4683        #[doc = "Enable input pull-up"]
4684        pub const _1: Self = Self::new(1);
4685    }
4686    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4687    pub struct Ncodr_SPEC;
4688    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
4689    impl Ncodr {
4690        #[doc = "Output CMOS"]
4691        pub const _0: Self = Self::new(0);
4692
4693        #[doc = "Output NMOS open-drain"]
4694        pub const _1: Self = Self::new(1);
4695    }
4696    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4697    pub struct Eofr_SPEC;
4698    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
4699    impl Eofr {
4700        #[doc = "Don\'t care"]
4701        pub const _00: Self = Self::new(0);
4702
4703        #[doc = "Detect rising edge"]
4704        pub const _01: Self = Self::new(1);
4705
4706        #[doc = "Detect falling edge"]
4707        pub const _10: Self = Self::new(2);
4708
4709        #[doc = "Detect both edges"]
4710        pub const _11: Self = Self::new(3);
4711    }
4712    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4713    pub struct Isel_SPEC;
4714    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
4715    impl Isel {
4716        #[doc = "Do not use as IRQn input pin"]
4717        pub const _0: Self = Self::new(0);
4718
4719        #[doc = "Use as IRQn input pin"]
4720        pub const _1: Self = Self::new(1);
4721    }
4722    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4723    pub struct Asel_SPEC;
4724    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
4725    impl Asel {
4726        #[doc = "Do not use as analog pin"]
4727        pub const _0: Self = Self::new(0);
4728
4729        #[doc = "Use as analog pin"]
4730        pub const _1: Self = Self::new(1);
4731    }
4732}
4733#[doc(hidden)]
4734#[derive(Copy, Clone, Eq, PartialEq)]
4735pub struct P108PfsBy_SPEC;
4736impl crate::sealed::RegSpec for P108PfsBy_SPEC {
4737    type DataType = u8;
4738}
4739
4740#[doc = "Port 108 Pin Function Select Register"]
4741pub type P108PfsBy = crate::RegValueT<P108PfsBy_SPEC>;
4742
4743impl P108PfsBy {
4744    #[doc = "Port Output Data"]
4745    #[inline(always)]
4746    pub fn podr(
4747        self,
4748    ) -> crate::common::RegisterField<
4749        0,
4750        0x1,
4751        1,
4752        0,
4753        p108pfs_by::Podr,
4754        p108pfs_by::Podr,
4755        P108PfsBy_SPEC,
4756        crate::common::RW,
4757    > {
4758        crate::common::RegisterField::<
4759            0,
4760            0x1,
4761            1,
4762            0,
4763            p108pfs_by::Podr,
4764            p108pfs_by::Podr,
4765            P108PfsBy_SPEC,
4766            crate::common::RW,
4767        >::from_register(self, 0)
4768    }
4769
4770    #[doc = "Port State"]
4771    #[inline(always)]
4772    pub fn pidr(
4773        self,
4774    ) -> crate::common::RegisterField<
4775        1,
4776        0x1,
4777        1,
4778        0,
4779        p108pfs_by::Pidr,
4780        p108pfs_by::Pidr,
4781        P108PfsBy_SPEC,
4782        crate::common::R,
4783    > {
4784        crate::common::RegisterField::<
4785            1,
4786            0x1,
4787            1,
4788            0,
4789            p108pfs_by::Pidr,
4790            p108pfs_by::Pidr,
4791            P108PfsBy_SPEC,
4792            crate::common::R,
4793        >::from_register(self, 0)
4794    }
4795
4796    #[doc = "Port Direction"]
4797    #[inline(always)]
4798    pub fn pdr(
4799        self,
4800    ) -> crate::common::RegisterField<
4801        2,
4802        0x1,
4803        1,
4804        0,
4805        p108pfs_by::Pdr,
4806        p108pfs_by::Pdr,
4807        P108PfsBy_SPEC,
4808        crate::common::RW,
4809    > {
4810        crate::common::RegisterField::<
4811            2,
4812            0x1,
4813            1,
4814            0,
4815            p108pfs_by::Pdr,
4816            p108pfs_by::Pdr,
4817            P108PfsBy_SPEC,
4818            crate::common::RW,
4819        >::from_register(self, 0)
4820    }
4821
4822    #[doc = "Pull-up Control"]
4823    #[inline(always)]
4824    pub fn pcr(
4825        self,
4826    ) -> crate::common::RegisterField<
4827        4,
4828        0x1,
4829        1,
4830        0,
4831        p108pfs_by::Pcr,
4832        p108pfs_by::Pcr,
4833        P108PfsBy_SPEC,
4834        crate::common::RW,
4835    > {
4836        crate::common::RegisterField::<
4837            4,
4838            0x1,
4839            1,
4840            0,
4841            p108pfs_by::Pcr,
4842            p108pfs_by::Pcr,
4843            P108PfsBy_SPEC,
4844            crate::common::RW,
4845        >::from_register(self, 0)
4846    }
4847
4848    #[doc = "N-Channel Open-Drain Control"]
4849    #[inline(always)]
4850    pub fn ncodr(
4851        self,
4852    ) -> crate::common::RegisterField<
4853        6,
4854        0x1,
4855        1,
4856        0,
4857        p108pfs_by::Ncodr,
4858        p108pfs_by::Ncodr,
4859        P108PfsBy_SPEC,
4860        crate::common::RW,
4861    > {
4862        crate::common::RegisterField::<
4863            6,
4864            0x1,
4865            1,
4866            0,
4867            p108pfs_by::Ncodr,
4868            p108pfs_by::Ncodr,
4869            P108PfsBy_SPEC,
4870            crate::common::RW,
4871        >::from_register(self, 0)
4872    }
4873}
4874impl ::core::default::Default for P108PfsBy {
4875    #[inline(always)]
4876    fn default() -> P108PfsBy {
4877        <crate::RegValueT<P108PfsBy_SPEC> as RegisterValue<_>>::new(16)
4878    }
4879}
4880pub mod p108pfs_by {
4881
4882    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4883    pub struct Podr_SPEC;
4884    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
4885    impl Podr {
4886        #[doc = "Output low"]
4887        pub const _0: Self = Self::new(0);
4888
4889        #[doc = "Output high"]
4890        pub const _1: Self = Self::new(1);
4891    }
4892    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4893    pub struct Pidr_SPEC;
4894    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
4895    impl Pidr {
4896        #[doc = "Low level"]
4897        pub const _0: Self = Self::new(0);
4898
4899        #[doc = "High level"]
4900        pub const _1: Self = Self::new(1);
4901    }
4902    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4903    pub struct Pdr_SPEC;
4904    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
4905    impl Pdr {
4906        #[doc = "Input (functions as an input pin)"]
4907        pub const _0: Self = Self::new(0);
4908
4909        #[doc = "Output (functions as an output pin)"]
4910        pub const _1: Self = Self::new(1);
4911    }
4912    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4913    pub struct Pcr_SPEC;
4914    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
4915    impl Pcr {
4916        #[doc = "Disable input pull-up"]
4917        pub const _0: Self = Self::new(0);
4918
4919        #[doc = "Enable input pull-up"]
4920        pub const _1: Self = Self::new(1);
4921    }
4922    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4923    pub struct Ncodr_SPEC;
4924    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
4925    impl Ncodr {
4926        #[doc = "Output CMOS"]
4927        pub const _0: Self = Self::new(0);
4928
4929        #[doc = "Output NMOS open-drain"]
4930        pub const _1: Self = Self::new(1);
4931    }
4932}
4933#[doc(hidden)]
4934#[derive(Copy, Clone, Eq, PartialEq)]
4935pub struct P109Pfs_SPEC;
4936impl crate::sealed::RegSpec for P109Pfs_SPEC {
4937    type DataType = u32;
4938}
4939
4940#[doc = "Port 109 Pin Function Select Register"]
4941pub type P109Pfs = crate::RegValueT<P109Pfs_SPEC>;
4942
4943impl P109Pfs {
4944    #[doc = "Port Output Data"]
4945    #[inline(always)]
4946    pub fn podr(
4947        self,
4948    ) -> crate::common::RegisterField<
4949        0,
4950        0x1,
4951        1,
4952        0,
4953        p109pfs::Podr,
4954        p109pfs::Podr,
4955        P109Pfs_SPEC,
4956        crate::common::RW,
4957    > {
4958        crate::common::RegisterField::<
4959            0,
4960            0x1,
4961            1,
4962            0,
4963            p109pfs::Podr,
4964            p109pfs::Podr,
4965            P109Pfs_SPEC,
4966            crate::common::RW,
4967        >::from_register(self, 0)
4968    }
4969
4970    #[doc = "Port State"]
4971    #[inline(always)]
4972    pub fn pidr(
4973        self,
4974    ) -> crate::common::RegisterField<
4975        1,
4976        0x1,
4977        1,
4978        0,
4979        p109pfs::Pidr,
4980        p109pfs::Pidr,
4981        P109Pfs_SPEC,
4982        crate::common::R,
4983    > {
4984        crate::common::RegisterField::<
4985            1,
4986            0x1,
4987            1,
4988            0,
4989            p109pfs::Pidr,
4990            p109pfs::Pidr,
4991            P109Pfs_SPEC,
4992            crate::common::R,
4993        >::from_register(self, 0)
4994    }
4995
4996    #[doc = "Port Direction"]
4997    #[inline(always)]
4998    pub fn pdr(
4999        self,
5000    ) -> crate::common::RegisterField<
5001        2,
5002        0x1,
5003        1,
5004        0,
5005        p109pfs::Pdr,
5006        p109pfs::Pdr,
5007        P109Pfs_SPEC,
5008        crate::common::RW,
5009    > {
5010        crate::common::RegisterField::<
5011            2,
5012            0x1,
5013            1,
5014            0,
5015            p109pfs::Pdr,
5016            p109pfs::Pdr,
5017            P109Pfs_SPEC,
5018            crate::common::RW,
5019        >::from_register(self, 0)
5020    }
5021
5022    #[doc = "Pull-up Control"]
5023    #[inline(always)]
5024    pub fn pcr(
5025        self,
5026    ) -> crate::common::RegisterField<
5027        4,
5028        0x1,
5029        1,
5030        0,
5031        p109pfs::Pcr,
5032        p109pfs::Pcr,
5033        P109Pfs_SPEC,
5034        crate::common::RW,
5035    > {
5036        crate::common::RegisterField::<
5037            4,
5038            0x1,
5039            1,
5040            0,
5041            p109pfs::Pcr,
5042            p109pfs::Pcr,
5043            P109Pfs_SPEC,
5044            crate::common::RW,
5045        >::from_register(self, 0)
5046    }
5047
5048    #[doc = "N-Channel Open-Drain Control"]
5049    #[inline(always)]
5050    pub fn ncodr(
5051        self,
5052    ) -> crate::common::RegisterField<
5053        6,
5054        0x1,
5055        1,
5056        0,
5057        p109pfs::Ncodr,
5058        p109pfs::Ncodr,
5059        P109Pfs_SPEC,
5060        crate::common::RW,
5061    > {
5062        crate::common::RegisterField::<
5063            6,
5064            0x1,
5065            1,
5066            0,
5067            p109pfs::Ncodr,
5068            p109pfs::Ncodr,
5069            P109Pfs_SPEC,
5070            crate::common::RW,
5071        >::from_register(self, 0)
5072    }
5073
5074    #[doc = "Event on Falling/Event on Rising"]
5075    #[inline(always)]
5076    pub fn eofr(
5077        self,
5078    ) -> crate::common::RegisterField<
5079        12,
5080        0x3,
5081        1,
5082        0,
5083        p109pfs::Eofr,
5084        p109pfs::Eofr,
5085        P109Pfs_SPEC,
5086        crate::common::RW,
5087    > {
5088        crate::common::RegisterField::<
5089            12,
5090            0x3,
5091            1,
5092            0,
5093            p109pfs::Eofr,
5094            p109pfs::Eofr,
5095            P109Pfs_SPEC,
5096            crate::common::RW,
5097        >::from_register(self, 0)
5098    }
5099
5100    #[doc = "IRQ Input Enable"]
5101    #[inline(always)]
5102    pub fn isel(
5103        self,
5104    ) -> crate::common::RegisterField<
5105        14,
5106        0x1,
5107        1,
5108        0,
5109        p109pfs::Isel,
5110        p109pfs::Isel,
5111        P109Pfs_SPEC,
5112        crate::common::RW,
5113    > {
5114        crate::common::RegisterField::<
5115            14,
5116            0x1,
5117            1,
5118            0,
5119            p109pfs::Isel,
5120            p109pfs::Isel,
5121            P109Pfs_SPEC,
5122            crate::common::RW,
5123        >::from_register(self, 0)
5124    }
5125
5126    #[doc = "Analog Input Enable"]
5127    #[inline(always)]
5128    pub fn asel(
5129        self,
5130    ) -> crate::common::RegisterField<
5131        15,
5132        0x1,
5133        1,
5134        0,
5135        p109pfs::Asel,
5136        p109pfs::Asel,
5137        P109Pfs_SPEC,
5138        crate::common::RW,
5139    > {
5140        crate::common::RegisterField::<
5141            15,
5142            0x1,
5143            1,
5144            0,
5145            p109pfs::Asel,
5146            p109pfs::Asel,
5147            P109Pfs_SPEC,
5148            crate::common::RW,
5149        >::from_register(self, 0)
5150    }
5151
5152    #[doc = "Port Mode Control"]
5153    #[inline(always)]
5154    pub fn pmr(
5155        self,
5156    ) -> crate::common::RegisterField<
5157        16,
5158        0x1,
5159        1,
5160        0,
5161        p109pfs::Pmr,
5162        p109pfs::Pmr,
5163        P109Pfs_SPEC,
5164        crate::common::RW,
5165    > {
5166        crate::common::RegisterField::<
5167            16,
5168            0x1,
5169            1,
5170            0,
5171            p109pfs::Pmr,
5172            p109pfs::Pmr,
5173            P109Pfs_SPEC,
5174            crate::common::RW,
5175        >::from_register(self, 0)
5176    }
5177
5178    #[doc = "Peripheral Select"]
5179    #[inline(always)]
5180    pub fn psel(
5181        self,
5182    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P109Pfs_SPEC, crate::common::RW> {
5183        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P109Pfs_SPEC,crate::common::RW>::from_register(self,0)
5184    }
5185}
5186impl ::core::default::Default for P109Pfs {
5187    #[inline(always)]
5188    fn default() -> P109Pfs {
5189        <crate::RegValueT<P109Pfs_SPEC> as RegisterValue<_>>::new(0)
5190    }
5191}
5192pub mod p109pfs {
5193
5194    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5195    pub struct Podr_SPEC;
5196    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
5197    impl Podr {
5198        #[doc = "Output low"]
5199        pub const _0: Self = Self::new(0);
5200
5201        #[doc = "Output high"]
5202        pub const _1: Self = Self::new(1);
5203    }
5204    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5205    pub struct Pidr_SPEC;
5206    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
5207    impl Pidr {
5208        #[doc = "Low level"]
5209        pub const _0: Self = Self::new(0);
5210
5211        #[doc = "High level"]
5212        pub const _1: Self = Self::new(1);
5213    }
5214    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5215    pub struct Pdr_SPEC;
5216    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
5217    impl Pdr {
5218        #[doc = "Input (functions as an input pin)"]
5219        pub const _0: Self = Self::new(0);
5220
5221        #[doc = "Output (functions as an output pin)"]
5222        pub const _1: Self = Self::new(1);
5223    }
5224    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5225    pub struct Pcr_SPEC;
5226    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
5227    impl Pcr {
5228        #[doc = "Disable input pull-up"]
5229        pub const _0: Self = Self::new(0);
5230
5231        #[doc = "Enable input pull-up"]
5232        pub const _1: Self = Self::new(1);
5233    }
5234    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5235    pub struct Ncodr_SPEC;
5236    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
5237    impl Ncodr {
5238        #[doc = "Output CMOS"]
5239        pub const _0: Self = Self::new(0);
5240
5241        #[doc = "Output NMOS open-drain"]
5242        pub const _1: Self = Self::new(1);
5243    }
5244    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5245    pub struct Eofr_SPEC;
5246    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
5247    impl Eofr {
5248        #[doc = "Don\'t care"]
5249        pub const _00: Self = Self::new(0);
5250
5251        #[doc = "Detect rising edge"]
5252        pub const _01: Self = Self::new(1);
5253
5254        #[doc = "Detect falling edge"]
5255        pub const _10: Self = Self::new(2);
5256
5257        #[doc = "Detect both edges"]
5258        pub const _11: Self = Self::new(3);
5259    }
5260    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5261    pub struct Isel_SPEC;
5262    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
5263    impl Isel {
5264        #[doc = "Do not use as IRQn input pin"]
5265        pub const _0: Self = Self::new(0);
5266
5267        #[doc = "Use as IRQn input pin"]
5268        pub const _1: Self = Self::new(1);
5269    }
5270    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5271    pub struct Asel_SPEC;
5272    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
5273    impl Asel {
5274        #[doc = "Do not use as analog pin"]
5275        pub const _0: Self = Self::new(0);
5276
5277        #[doc = "Use as analog pin"]
5278        pub const _1: Self = Self::new(1);
5279    }
5280    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5281    pub struct Pmr_SPEC;
5282    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
5283    impl Pmr {
5284        #[doc = "Use as general I/O pin"]
5285        pub const _0: Self = Self::new(0);
5286
5287        #[doc = "Use as I/O port for peripheral functions"]
5288        pub const _1: Self = Self::new(1);
5289    }
5290}
5291#[doc(hidden)]
5292#[derive(Copy, Clone, Eq, PartialEq)]
5293pub struct P109PfsHa_SPEC;
5294impl crate::sealed::RegSpec for P109PfsHa_SPEC {
5295    type DataType = u16;
5296}
5297
5298#[doc = "Port 109 Pin Function Select Register"]
5299pub type P109PfsHa = crate::RegValueT<P109PfsHa_SPEC>;
5300
5301impl P109PfsHa {
5302    #[doc = "Port Output Data"]
5303    #[inline(always)]
5304    pub fn podr(
5305        self,
5306    ) -> crate::common::RegisterField<
5307        0,
5308        0x1,
5309        1,
5310        0,
5311        p109pfs_ha::Podr,
5312        p109pfs_ha::Podr,
5313        P109PfsHa_SPEC,
5314        crate::common::RW,
5315    > {
5316        crate::common::RegisterField::<
5317            0,
5318            0x1,
5319            1,
5320            0,
5321            p109pfs_ha::Podr,
5322            p109pfs_ha::Podr,
5323            P109PfsHa_SPEC,
5324            crate::common::RW,
5325        >::from_register(self, 0)
5326    }
5327
5328    #[doc = "Port State"]
5329    #[inline(always)]
5330    pub fn pidr(
5331        self,
5332    ) -> crate::common::RegisterField<
5333        1,
5334        0x1,
5335        1,
5336        0,
5337        p109pfs_ha::Pidr,
5338        p109pfs_ha::Pidr,
5339        P109PfsHa_SPEC,
5340        crate::common::R,
5341    > {
5342        crate::common::RegisterField::<
5343            1,
5344            0x1,
5345            1,
5346            0,
5347            p109pfs_ha::Pidr,
5348            p109pfs_ha::Pidr,
5349            P109PfsHa_SPEC,
5350            crate::common::R,
5351        >::from_register(self, 0)
5352    }
5353
5354    #[doc = "Port Direction"]
5355    #[inline(always)]
5356    pub fn pdr(
5357        self,
5358    ) -> crate::common::RegisterField<
5359        2,
5360        0x1,
5361        1,
5362        0,
5363        p109pfs_ha::Pdr,
5364        p109pfs_ha::Pdr,
5365        P109PfsHa_SPEC,
5366        crate::common::RW,
5367    > {
5368        crate::common::RegisterField::<
5369            2,
5370            0x1,
5371            1,
5372            0,
5373            p109pfs_ha::Pdr,
5374            p109pfs_ha::Pdr,
5375            P109PfsHa_SPEC,
5376            crate::common::RW,
5377        >::from_register(self, 0)
5378    }
5379
5380    #[doc = "Pull-up Control"]
5381    #[inline(always)]
5382    pub fn pcr(
5383        self,
5384    ) -> crate::common::RegisterField<
5385        4,
5386        0x1,
5387        1,
5388        0,
5389        p109pfs_ha::Pcr,
5390        p109pfs_ha::Pcr,
5391        P109PfsHa_SPEC,
5392        crate::common::RW,
5393    > {
5394        crate::common::RegisterField::<
5395            4,
5396            0x1,
5397            1,
5398            0,
5399            p109pfs_ha::Pcr,
5400            p109pfs_ha::Pcr,
5401            P109PfsHa_SPEC,
5402            crate::common::RW,
5403        >::from_register(self, 0)
5404    }
5405
5406    #[doc = "N-Channel Open-Drain Control"]
5407    #[inline(always)]
5408    pub fn ncodr(
5409        self,
5410    ) -> crate::common::RegisterField<
5411        6,
5412        0x1,
5413        1,
5414        0,
5415        p109pfs_ha::Ncodr,
5416        p109pfs_ha::Ncodr,
5417        P109PfsHa_SPEC,
5418        crate::common::RW,
5419    > {
5420        crate::common::RegisterField::<
5421            6,
5422            0x1,
5423            1,
5424            0,
5425            p109pfs_ha::Ncodr,
5426            p109pfs_ha::Ncodr,
5427            P109PfsHa_SPEC,
5428            crate::common::RW,
5429        >::from_register(self, 0)
5430    }
5431
5432    #[doc = "Event on Falling/Event on Rising"]
5433    #[inline(always)]
5434    pub fn eofr(
5435        self,
5436    ) -> crate::common::RegisterField<
5437        12,
5438        0x3,
5439        1,
5440        0,
5441        p109pfs_ha::Eofr,
5442        p109pfs_ha::Eofr,
5443        P109PfsHa_SPEC,
5444        crate::common::RW,
5445    > {
5446        crate::common::RegisterField::<
5447            12,
5448            0x3,
5449            1,
5450            0,
5451            p109pfs_ha::Eofr,
5452            p109pfs_ha::Eofr,
5453            P109PfsHa_SPEC,
5454            crate::common::RW,
5455        >::from_register(self, 0)
5456    }
5457
5458    #[doc = "IRQ Input Enable"]
5459    #[inline(always)]
5460    pub fn isel(
5461        self,
5462    ) -> crate::common::RegisterField<
5463        14,
5464        0x1,
5465        1,
5466        0,
5467        p109pfs_ha::Isel,
5468        p109pfs_ha::Isel,
5469        P109PfsHa_SPEC,
5470        crate::common::RW,
5471    > {
5472        crate::common::RegisterField::<
5473            14,
5474            0x1,
5475            1,
5476            0,
5477            p109pfs_ha::Isel,
5478            p109pfs_ha::Isel,
5479            P109PfsHa_SPEC,
5480            crate::common::RW,
5481        >::from_register(self, 0)
5482    }
5483
5484    #[doc = "Analog Input Enable"]
5485    #[inline(always)]
5486    pub fn asel(
5487        self,
5488    ) -> crate::common::RegisterField<
5489        15,
5490        0x1,
5491        1,
5492        0,
5493        p109pfs_ha::Asel,
5494        p109pfs_ha::Asel,
5495        P109PfsHa_SPEC,
5496        crate::common::RW,
5497    > {
5498        crate::common::RegisterField::<
5499            15,
5500            0x1,
5501            1,
5502            0,
5503            p109pfs_ha::Asel,
5504            p109pfs_ha::Asel,
5505            P109PfsHa_SPEC,
5506            crate::common::RW,
5507        >::from_register(self, 0)
5508    }
5509}
5510impl ::core::default::Default for P109PfsHa {
5511    #[inline(always)]
5512    fn default() -> P109PfsHa {
5513        <crate::RegValueT<P109PfsHa_SPEC> as RegisterValue<_>>::new(0)
5514    }
5515}
5516pub mod p109pfs_ha {
5517
5518    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5519    pub struct Podr_SPEC;
5520    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
5521    impl Podr {
5522        #[doc = "Output low"]
5523        pub const _0: Self = Self::new(0);
5524
5525        #[doc = "Output high"]
5526        pub const _1: Self = Self::new(1);
5527    }
5528    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5529    pub struct Pidr_SPEC;
5530    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
5531    impl Pidr {
5532        #[doc = "Low level"]
5533        pub const _0: Self = Self::new(0);
5534
5535        #[doc = "High level"]
5536        pub const _1: Self = Self::new(1);
5537    }
5538    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5539    pub struct Pdr_SPEC;
5540    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
5541    impl Pdr {
5542        #[doc = "Input (functions as an input pin)"]
5543        pub const _0: Self = Self::new(0);
5544
5545        #[doc = "Output (functions as an output pin)"]
5546        pub const _1: Self = Self::new(1);
5547    }
5548    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5549    pub struct Pcr_SPEC;
5550    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
5551    impl Pcr {
5552        #[doc = "Disable input pull-up"]
5553        pub const _0: Self = Self::new(0);
5554
5555        #[doc = "Enable input pull-up"]
5556        pub const _1: Self = Self::new(1);
5557    }
5558    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5559    pub struct Ncodr_SPEC;
5560    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
5561    impl Ncodr {
5562        #[doc = "Output CMOS"]
5563        pub const _0: Self = Self::new(0);
5564
5565        #[doc = "Output NMOS open-drain"]
5566        pub const _1: Self = Self::new(1);
5567    }
5568    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5569    pub struct Eofr_SPEC;
5570    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
5571    impl Eofr {
5572        #[doc = "Don\'t care"]
5573        pub const _00: Self = Self::new(0);
5574
5575        #[doc = "Detect rising edge"]
5576        pub const _01: Self = Self::new(1);
5577
5578        #[doc = "Detect falling edge"]
5579        pub const _10: Self = Self::new(2);
5580
5581        #[doc = "Detect both edges"]
5582        pub const _11: Self = Self::new(3);
5583    }
5584    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5585    pub struct Isel_SPEC;
5586    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
5587    impl Isel {
5588        #[doc = "Do not use as IRQn input pin"]
5589        pub const _0: Self = Self::new(0);
5590
5591        #[doc = "Use as IRQn input pin"]
5592        pub const _1: Self = Self::new(1);
5593    }
5594    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5595    pub struct Asel_SPEC;
5596    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
5597    impl Asel {
5598        #[doc = "Do not use as analog pin"]
5599        pub const _0: Self = Self::new(0);
5600
5601        #[doc = "Use as analog pin"]
5602        pub const _1: Self = Self::new(1);
5603    }
5604}
5605#[doc(hidden)]
5606#[derive(Copy, Clone, Eq, PartialEq)]
5607pub struct P109PfsBy_SPEC;
5608impl crate::sealed::RegSpec for P109PfsBy_SPEC {
5609    type DataType = u8;
5610}
5611
5612#[doc = "Port 109 Pin Function Select Register"]
5613pub type P109PfsBy = crate::RegValueT<P109PfsBy_SPEC>;
5614
5615impl P109PfsBy {
5616    #[doc = "Port Output Data"]
5617    #[inline(always)]
5618    pub fn podr(
5619        self,
5620    ) -> crate::common::RegisterField<
5621        0,
5622        0x1,
5623        1,
5624        0,
5625        p109pfs_by::Podr,
5626        p109pfs_by::Podr,
5627        P109PfsBy_SPEC,
5628        crate::common::RW,
5629    > {
5630        crate::common::RegisterField::<
5631            0,
5632            0x1,
5633            1,
5634            0,
5635            p109pfs_by::Podr,
5636            p109pfs_by::Podr,
5637            P109PfsBy_SPEC,
5638            crate::common::RW,
5639        >::from_register(self, 0)
5640    }
5641
5642    #[doc = "Port State"]
5643    #[inline(always)]
5644    pub fn pidr(
5645        self,
5646    ) -> crate::common::RegisterField<
5647        1,
5648        0x1,
5649        1,
5650        0,
5651        p109pfs_by::Pidr,
5652        p109pfs_by::Pidr,
5653        P109PfsBy_SPEC,
5654        crate::common::R,
5655    > {
5656        crate::common::RegisterField::<
5657            1,
5658            0x1,
5659            1,
5660            0,
5661            p109pfs_by::Pidr,
5662            p109pfs_by::Pidr,
5663            P109PfsBy_SPEC,
5664            crate::common::R,
5665        >::from_register(self, 0)
5666    }
5667
5668    #[doc = "Port Direction"]
5669    #[inline(always)]
5670    pub fn pdr(
5671        self,
5672    ) -> crate::common::RegisterField<
5673        2,
5674        0x1,
5675        1,
5676        0,
5677        p109pfs_by::Pdr,
5678        p109pfs_by::Pdr,
5679        P109PfsBy_SPEC,
5680        crate::common::RW,
5681    > {
5682        crate::common::RegisterField::<
5683            2,
5684            0x1,
5685            1,
5686            0,
5687            p109pfs_by::Pdr,
5688            p109pfs_by::Pdr,
5689            P109PfsBy_SPEC,
5690            crate::common::RW,
5691        >::from_register(self, 0)
5692    }
5693
5694    #[doc = "Pull-up Control"]
5695    #[inline(always)]
5696    pub fn pcr(
5697        self,
5698    ) -> crate::common::RegisterField<
5699        4,
5700        0x1,
5701        1,
5702        0,
5703        p109pfs_by::Pcr,
5704        p109pfs_by::Pcr,
5705        P109PfsBy_SPEC,
5706        crate::common::RW,
5707    > {
5708        crate::common::RegisterField::<
5709            4,
5710            0x1,
5711            1,
5712            0,
5713            p109pfs_by::Pcr,
5714            p109pfs_by::Pcr,
5715            P109PfsBy_SPEC,
5716            crate::common::RW,
5717        >::from_register(self, 0)
5718    }
5719
5720    #[doc = "N-Channel Open-Drain Control"]
5721    #[inline(always)]
5722    pub fn ncodr(
5723        self,
5724    ) -> crate::common::RegisterField<
5725        6,
5726        0x1,
5727        1,
5728        0,
5729        p109pfs_by::Ncodr,
5730        p109pfs_by::Ncodr,
5731        P109PfsBy_SPEC,
5732        crate::common::RW,
5733    > {
5734        crate::common::RegisterField::<
5735            6,
5736            0x1,
5737            1,
5738            0,
5739            p109pfs_by::Ncodr,
5740            p109pfs_by::Ncodr,
5741            P109PfsBy_SPEC,
5742            crate::common::RW,
5743        >::from_register(self, 0)
5744    }
5745}
5746impl ::core::default::Default for P109PfsBy {
5747    #[inline(always)]
5748    fn default() -> P109PfsBy {
5749        <crate::RegValueT<P109PfsBy_SPEC> as RegisterValue<_>>::new(0)
5750    }
5751}
5752pub mod p109pfs_by {
5753
5754    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5755    pub struct Podr_SPEC;
5756    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
5757    impl Podr {
5758        #[doc = "Output low"]
5759        pub const _0: Self = Self::new(0);
5760
5761        #[doc = "Output high"]
5762        pub const _1: Self = Self::new(1);
5763    }
5764    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5765    pub struct Pidr_SPEC;
5766    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
5767    impl Pidr {
5768        #[doc = "Low level"]
5769        pub const _0: Self = Self::new(0);
5770
5771        #[doc = "High level"]
5772        pub const _1: Self = Self::new(1);
5773    }
5774    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5775    pub struct Pdr_SPEC;
5776    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
5777    impl Pdr {
5778        #[doc = "Input (functions as an input pin)"]
5779        pub const _0: Self = Self::new(0);
5780
5781        #[doc = "Output (functions as an output pin)"]
5782        pub const _1: Self = Self::new(1);
5783    }
5784    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5785    pub struct Pcr_SPEC;
5786    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
5787    impl Pcr {
5788        #[doc = "Disable input pull-up"]
5789        pub const _0: Self = Self::new(0);
5790
5791        #[doc = "Enable input pull-up"]
5792        pub const _1: Self = Self::new(1);
5793    }
5794    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5795    pub struct Ncodr_SPEC;
5796    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
5797    impl Ncodr {
5798        #[doc = "Output CMOS"]
5799        pub const _0: Self = Self::new(0);
5800
5801        #[doc = "Output NMOS open-drain"]
5802        pub const _1: Self = Self::new(1);
5803    }
5804}
5805#[doc(hidden)]
5806#[derive(Copy, Clone, Eq, PartialEq)]
5807pub struct P1Pfs_SPEC;
5808impl crate::sealed::RegSpec for P1Pfs_SPEC {
5809    type DataType = u32;
5810}
5811
5812#[doc = "Port 1%s Pin Function Select Register"]
5813pub type P1Pfs = crate::RegValueT<P1Pfs_SPEC>;
5814
5815impl P1Pfs {
5816    #[doc = "Port Output Data"]
5817    #[inline(always)]
5818    pub fn podr(
5819        self,
5820    ) -> crate::common::RegisterField<
5821        0,
5822        0x1,
5823        1,
5824        0,
5825        p1pfs::Podr,
5826        p1pfs::Podr,
5827        P1Pfs_SPEC,
5828        crate::common::RW,
5829    > {
5830        crate::common::RegisterField::<
5831            0,
5832            0x1,
5833            1,
5834            0,
5835            p1pfs::Podr,
5836            p1pfs::Podr,
5837            P1Pfs_SPEC,
5838            crate::common::RW,
5839        >::from_register(self, 0)
5840    }
5841
5842    #[doc = "Port State"]
5843    #[inline(always)]
5844    pub fn pidr(
5845        self,
5846    ) -> crate::common::RegisterField<
5847        1,
5848        0x1,
5849        1,
5850        0,
5851        p1pfs::Pidr,
5852        p1pfs::Pidr,
5853        P1Pfs_SPEC,
5854        crate::common::R,
5855    > {
5856        crate::common::RegisterField::<
5857            1,
5858            0x1,
5859            1,
5860            0,
5861            p1pfs::Pidr,
5862            p1pfs::Pidr,
5863            P1Pfs_SPEC,
5864            crate::common::R,
5865        >::from_register(self, 0)
5866    }
5867
5868    #[doc = "Port Direction"]
5869    #[inline(always)]
5870    pub fn pdr(
5871        self,
5872    ) -> crate::common::RegisterField<
5873        2,
5874        0x1,
5875        1,
5876        0,
5877        p1pfs::Pdr,
5878        p1pfs::Pdr,
5879        P1Pfs_SPEC,
5880        crate::common::RW,
5881    > {
5882        crate::common::RegisterField::<
5883            2,
5884            0x1,
5885            1,
5886            0,
5887            p1pfs::Pdr,
5888            p1pfs::Pdr,
5889            P1Pfs_SPEC,
5890            crate::common::RW,
5891        >::from_register(self, 0)
5892    }
5893
5894    #[doc = "Pull-up Control"]
5895    #[inline(always)]
5896    pub fn pcr(
5897        self,
5898    ) -> crate::common::RegisterField<
5899        4,
5900        0x1,
5901        1,
5902        0,
5903        p1pfs::Pcr,
5904        p1pfs::Pcr,
5905        P1Pfs_SPEC,
5906        crate::common::RW,
5907    > {
5908        crate::common::RegisterField::<
5909            4,
5910            0x1,
5911            1,
5912            0,
5913            p1pfs::Pcr,
5914            p1pfs::Pcr,
5915            P1Pfs_SPEC,
5916            crate::common::RW,
5917        >::from_register(self, 0)
5918    }
5919
5920    #[doc = "N-Channel Open-Drain Control"]
5921    #[inline(always)]
5922    pub fn ncodr(
5923        self,
5924    ) -> crate::common::RegisterField<
5925        6,
5926        0x1,
5927        1,
5928        0,
5929        p1pfs::Ncodr,
5930        p1pfs::Ncodr,
5931        P1Pfs_SPEC,
5932        crate::common::RW,
5933    > {
5934        crate::common::RegisterField::<
5935            6,
5936            0x1,
5937            1,
5938            0,
5939            p1pfs::Ncodr,
5940            p1pfs::Ncodr,
5941            P1Pfs_SPEC,
5942            crate::common::RW,
5943        >::from_register(self, 0)
5944    }
5945
5946    #[doc = "Event on Falling/Event on Rising"]
5947    #[inline(always)]
5948    pub fn eofr(
5949        self,
5950    ) -> crate::common::RegisterField<
5951        12,
5952        0x3,
5953        1,
5954        0,
5955        p1pfs::Eofr,
5956        p1pfs::Eofr,
5957        P1Pfs_SPEC,
5958        crate::common::RW,
5959    > {
5960        crate::common::RegisterField::<
5961            12,
5962            0x3,
5963            1,
5964            0,
5965            p1pfs::Eofr,
5966            p1pfs::Eofr,
5967            P1Pfs_SPEC,
5968            crate::common::RW,
5969        >::from_register(self, 0)
5970    }
5971
5972    #[doc = "IRQ Input Enable"]
5973    #[inline(always)]
5974    pub fn isel(
5975        self,
5976    ) -> crate::common::RegisterField<
5977        14,
5978        0x1,
5979        1,
5980        0,
5981        p1pfs::Isel,
5982        p1pfs::Isel,
5983        P1Pfs_SPEC,
5984        crate::common::RW,
5985    > {
5986        crate::common::RegisterField::<
5987            14,
5988            0x1,
5989            1,
5990            0,
5991            p1pfs::Isel,
5992            p1pfs::Isel,
5993            P1Pfs_SPEC,
5994            crate::common::RW,
5995        >::from_register(self, 0)
5996    }
5997
5998    #[doc = "Analog Input Enable"]
5999    #[inline(always)]
6000    pub fn asel(
6001        self,
6002    ) -> crate::common::RegisterField<
6003        15,
6004        0x1,
6005        1,
6006        0,
6007        p1pfs::Asel,
6008        p1pfs::Asel,
6009        P1Pfs_SPEC,
6010        crate::common::RW,
6011    > {
6012        crate::common::RegisterField::<
6013            15,
6014            0x1,
6015            1,
6016            0,
6017            p1pfs::Asel,
6018            p1pfs::Asel,
6019            P1Pfs_SPEC,
6020            crate::common::RW,
6021        >::from_register(self, 0)
6022    }
6023
6024    #[doc = "Port Mode Control"]
6025    #[inline(always)]
6026    pub fn pmr(
6027        self,
6028    ) -> crate::common::RegisterField<
6029        16,
6030        0x1,
6031        1,
6032        0,
6033        p1pfs::Pmr,
6034        p1pfs::Pmr,
6035        P1Pfs_SPEC,
6036        crate::common::RW,
6037    > {
6038        crate::common::RegisterField::<
6039            16,
6040            0x1,
6041            1,
6042            0,
6043            p1pfs::Pmr,
6044            p1pfs::Pmr,
6045            P1Pfs_SPEC,
6046            crate::common::RW,
6047        >::from_register(self, 0)
6048    }
6049
6050    #[doc = "Peripheral Select"]
6051    #[inline(always)]
6052    pub fn psel(
6053        self,
6054    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P1Pfs_SPEC, crate::common::RW> {
6055        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P1Pfs_SPEC,crate::common::RW>::from_register(self,0)
6056    }
6057}
6058impl ::core::default::Default for P1Pfs {
6059    #[inline(always)]
6060    fn default() -> P1Pfs {
6061        <crate::RegValueT<P1Pfs_SPEC> as RegisterValue<_>>::new(0)
6062    }
6063}
6064pub mod p1pfs {
6065
6066    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6067    pub struct Podr_SPEC;
6068    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
6069    impl Podr {
6070        #[doc = "Output low"]
6071        pub const _0: Self = Self::new(0);
6072
6073        #[doc = "Output high"]
6074        pub const _1: Self = Self::new(1);
6075    }
6076    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6077    pub struct Pidr_SPEC;
6078    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
6079    impl Pidr {
6080        #[doc = "Low level"]
6081        pub const _0: Self = Self::new(0);
6082
6083        #[doc = "High level"]
6084        pub const _1: Self = Self::new(1);
6085    }
6086    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6087    pub struct Pdr_SPEC;
6088    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
6089    impl Pdr {
6090        #[doc = "Input (functions as an input pin)"]
6091        pub const _0: Self = Self::new(0);
6092
6093        #[doc = "Output (functions as an output pin)"]
6094        pub const _1: Self = Self::new(1);
6095    }
6096    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6097    pub struct Pcr_SPEC;
6098    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
6099    impl Pcr {
6100        #[doc = "Disable input pull-up"]
6101        pub const _0: Self = Self::new(0);
6102
6103        #[doc = "Enable input pull-up"]
6104        pub const _1: Self = Self::new(1);
6105    }
6106    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6107    pub struct Ncodr_SPEC;
6108    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
6109    impl Ncodr {
6110        #[doc = "Output CMOS"]
6111        pub const _0: Self = Self::new(0);
6112
6113        #[doc = "Output NMOS open-drain"]
6114        pub const _1: Self = Self::new(1);
6115    }
6116    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6117    pub struct Eofr_SPEC;
6118    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
6119    impl Eofr {
6120        #[doc = "Don\'t care"]
6121        pub const _00: Self = Self::new(0);
6122
6123        #[doc = "Detect rising edge"]
6124        pub const _01: Self = Self::new(1);
6125
6126        #[doc = "Detect falling edge"]
6127        pub const _10: Self = Self::new(2);
6128
6129        #[doc = "Detect both edges"]
6130        pub const _11: Self = Self::new(3);
6131    }
6132    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6133    pub struct Isel_SPEC;
6134    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
6135    impl Isel {
6136        #[doc = "Do not use as IRQn input pin"]
6137        pub const _0: Self = Self::new(0);
6138
6139        #[doc = "Use as IRQn input pin"]
6140        pub const _1: Self = Self::new(1);
6141    }
6142    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6143    pub struct Asel_SPEC;
6144    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
6145    impl Asel {
6146        #[doc = "Do not use as analog pin"]
6147        pub const _0: Self = Self::new(0);
6148
6149        #[doc = "Use as analog pin"]
6150        pub const _1: Self = Self::new(1);
6151    }
6152    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6153    pub struct Pmr_SPEC;
6154    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
6155    impl Pmr {
6156        #[doc = "Use as general I/O pin"]
6157        pub const _0: Self = Self::new(0);
6158
6159        #[doc = "Use as I/O port for peripheral functions"]
6160        pub const _1: Self = Self::new(1);
6161    }
6162}
6163#[doc(hidden)]
6164#[derive(Copy, Clone, Eq, PartialEq)]
6165pub struct P1PfsHa_SPEC;
6166impl crate::sealed::RegSpec for P1PfsHa_SPEC {
6167    type DataType = u16;
6168}
6169
6170#[doc = "Port 1%s Pin Function Select Register"]
6171pub type P1PfsHa = crate::RegValueT<P1PfsHa_SPEC>;
6172
6173impl P1PfsHa {
6174    #[doc = "Port Output Data"]
6175    #[inline(always)]
6176    pub fn podr(
6177        self,
6178    ) -> crate::common::RegisterField<
6179        0,
6180        0x1,
6181        1,
6182        0,
6183        p1pfs_ha::Podr,
6184        p1pfs_ha::Podr,
6185        P1PfsHa_SPEC,
6186        crate::common::RW,
6187    > {
6188        crate::common::RegisterField::<
6189            0,
6190            0x1,
6191            1,
6192            0,
6193            p1pfs_ha::Podr,
6194            p1pfs_ha::Podr,
6195            P1PfsHa_SPEC,
6196            crate::common::RW,
6197        >::from_register(self, 0)
6198    }
6199
6200    #[doc = "Port State"]
6201    #[inline(always)]
6202    pub fn pidr(
6203        self,
6204    ) -> crate::common::RegisterField<
6205        1,
6206        0x1,
6207        1,
6208        0,
6209        p1pfs_ha::Pidr,
6210        p1pfs_ha::Pidr,
6211        P1PfsHa_SPEC,
6212        crate::common::R,
6213    > {
6214        crate::common::RegisterField::<
6215            1,
6216            0x1,
6217            1,
6218            0,
6219            p1pfs_ha::Pidr,
6220            p1pfs_ha::Pidr,
6221            P1PfsHa_SPEC,
6222            crate::common::R,
6223        >::from_register(self, 0)
6224    }
6225
6226    #[doc = "Port Direction"]
6227    #[inline(always)]
6228    pub fn pdr(
6229        self,
6230    ) -> crate::common::RegisterField<
6231        2,
6232        0x1,
6233        1,
6234        0,
6235        p1pfs_ha::Pdr,
6236        p1pfs_ha::Pdr,
6237        P1PfsHa_SPEC,
6238        crate::common::RW,
6239    > {
6240        crate::common::RegisterField::<
6241            2,
6242            0x1,
6243            1,
6244            0,
6245            p1pfs_ha::Pdr,
6246            p1pfs_ha::Pdr,
6247            P1PfsHa_SPEC,
6248            crate::common::RW,
6249        >::from_register(self, 0)
6250    }
6251
6252    #[doc = "Pull-up Control"]
6253    #[inline(always)]
6254    pub fn pcr(
6255        self,
6256    ) -> crate::common::RegisterField<
6257        4,
6258        0x1,
6259        1,
6260        0,
6261        p1pfs_ha::Pcr,
6262        p1pfs_ha::Pcr,
6263        P1PfsHa_SPEC,
6264        crate::common::RW,
6265    > {
6266        crate::common::RegisterField::<
6267            4,
6268            0x1,
6269            1,
6270            0,
6271            p1pfs_ha::Pcr,
6272            p1pfs_ha::Pcr,
6273            P1PfsHa_SPEC,
6274            crate::common::RW,
6275        >::from_register(self, 0)
6276    }
6277
6278    #[doc = "N-Channel Open-Drain Control"]
6279    #[inline(always)]
6280    pub fn ncodr(
6281        self,
6282    ) -> crate::common::RegisterField<
6283        6,
6284        0x1,
6285        1,
6286        0,
6287        p1pfs_ha::Ncodr,
6288        p1pfs_ha::Ncodr,
6289        P1PfsHa_SPEC,
6290        crate::common::RW,
6291    > {
6292        crate::common::RegisterField::<
6293            6,
6294            0x1,
6295            1,
6296            0,
6297            p1pfs_ha::Ncodr,
6298            p1pfs_ha::Ncodr,
6299            P1PfsHa_SPEC,
6300            crate::common::RW,
6301        >::from_register(self, 0)
6302    }
6303
6304    #[doc = "Event on Falling/Event on Rising"]
6305    #[inline(always)]
6306    pub fn eofr(
6307        self,
6308    ) -> crate::common::RegisterField<
6309        12,
6310        0x3,
6311        1,
6312        0,
6313        p1pfs_ha::Eofr,
6314        p1pfs_ha::Eofr,
6315        P1PfsHa_SPEC,
6316        crate::common::RW,
6317    > {
6318        crate::common::RegisterField::<
6319            12,
6320            0x3,
6321            1,
6322            0,
6323            p1pfs_ha::Eofr,
6324            p1pfs_ha::Eofr,
6325            P1PfsHa_SPEC,
6326            crate::common::RW,
6327        >::from_register(self, 0)
6328    }
6329
6330    #[doc = "IRQ Input Enable"]
6331    #[inline(always)]
6332    pub fn isel(
6333        self,
6334    ) -> crate::common::RegisterField<
6335        14,
6336        0x1,
6337        1,
6338        0,
6339        p1pfs_ha::Isel,
6340        p1pfs_ha::Isel,
6341        P1PfsHa_SPEC,
6342        crate::common::RW,
6343    > {
6344        crate::common::RegisterField::<
6345            14,
6346            0x1,
6347            1,
6348            0,
6349            p1pfs_ha::Isel,
6350            p1pfs_ha::Isel,
6351            P1PfsHa_SPEC,
6352            crate::common::RW,
6353        >::from_register(self, 0)
6354    }
6355
6356    #[doc = "Analog Input Enable"]
6357    #[inline(always)]
6358    pub fn asel(
6359        self,
6360    ) -> crate::common::RegisterField<
6361        15,
6362        0x1,
6363        1,
6364        0,
6365        p1pfs_ha::Asel,
6366        p1pfs_ha::Asel,
6367        P1PfsHa_SPEC,
6368        crate::common::RW,
6369    > {
6370        crate::common::RegisterField::<
6371            15,
6372            0x1,
6373            1,
6374            0,
6375            p1pfs_ha::Asel,
6376            p1pfs_ha::Asel,
6377            P1PfsHa_SPEC,
6378            crate::common::RW,
6379        >::from_register(self, 0)
6380    }
6381}
6382impl ::core::default::Default for P1PfsHa {
6383    #[inline(always)]
6384    fn default() -> P1PfsHa {
6385        <crate::RegValueT<P1PfsHa_SPEC> as RegisterValue<_>>::new(0)
6386    }
6387}
6388pub mod p1pfs_ha {
6389
6390    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6391    pub struct Podr_SPEC;
6392    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
6393    impl Podr {
6394        #[doc = "Output low"]
6395        pub const _0: Self = Self::new(0);
6396
6397        #[doc = "Output high"]
6398        pub const _1: Self = Self::new(1);
6399    }
6400    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6401    pub struct Pidr_SPEC;
6402    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
6403    impl Pidr {
6404        #[doc = "Low level"]
6405        pub const _0: Self = Self::new(0);
6406
6407        #[doc = "High level"]
6408        pub const _1: Self = Self::new(1);
6409    }
6410    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6411    pub struct Pdr_SPEC;
6412    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
6413    impl Pdr {
6414        #[doc = "Input (functions as an input pin)"]
6415        pub const _0: Self = Self::new(0);
6416
6417        #[doc = "Output (functions as an output pin)"]
6418        pub const _1: Self = Self::new(1);
6419    }
6420    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6421    pub struct Pcr_SPEC;
6422    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
6423    impl Pcr {
6424        #[doc = "Disable input pull-up"]
6425        pub const _0: Self = Self::new(0);
6426
6427        #[doc = "Enable input pull-up"]
6428        pub const _1: Self = Self::new(1);
6429    }
6430    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6431    pub struct Ncodr_SPEC;
6432    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
6433    impl Ncodr {
6434        #[doc = "Output CMOS"]
6435        pub const _0: Self = Self::new(0);
6436
6437        #[doc = "Output NMOS open-drain"]
6438        pub const _1: Self = Self::new(1);
6439    }
6440    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6441    pub struct Eofr_SPEC;
6442    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
6443    impl Eofr {
6444        #[doc = "Don\'t care"]
6445        pub const _00: Self = Self::new(0);
6446
6447        #[doc = "Detect rising edge"]
6448        pub const _01: Self = Self::new(1);
6449
6450        #[doc = "Detect falling edge"]
6451        pub const _10: Self = Self::new(2);
6452
6453        #[doc = "Detect both edges"]
6454        pub const _11: Self = Self::new(3);
6455    }
6456    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6457    pub struct Isel_SPEC;
6458    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
6459    impl Isel {
6460        #[doc = "Do not use as IRQn input pin"]
6461        pub const _0: Self = Self::new(0);
6462
6463        #[doc = "Use as IRQn input pin"]
6464        pub const _1: Self = Self::new(1);
6465    }
6466    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6467    pub struct Asel_SPEC;
6468    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
6469    impl Asel {
6470        #[doc = "Do not use as analog pin"]
6471        pub const _0: Self = Self::new(0);
6472
6473        #[doc = "Use as analog pin"]
6474        pub const _1: Self = Self::new(1);
6475    }
6476}
6477#[doc(hidden)]
6478#[derive(Copy, Clone, Eq, PartialEq)]
6479pub struct P1PfsBy_SPEC;
6480impl crate::sealed::RegSpec for P1PfsBy_SPEC {
6481    type DataType = u8;
6482}
6483
6484#[doc = "Port 1%s Pin Function Select Register"]
6485pub type P1PfsBy = crate::RegValueT<P1PfsBy_SPEC>;
6486
6487impl P1PfsBy {
6488    #[doc = "Port Output Data"]
6489    #[inline(always)]
6490    pub fn podr(
6491        self,
6492    ) -> crate::common::RegisterField<
6493        0,
6494        0x1,
6495        1,
6496        0,
6497        p1pfs_by::Podr,
6498        p1pfs_by::Podr,
6499        P1PfsBy_SPEC,
6500        crate::common::RW,
6501    > {
6502        crate::common::RegisterField::<
6503            0,
6504            0x1,
6505            1,
6506            0,
6507            p1pfs_by::Podr,
6508            p1pfs_by::Podr,
6509            P1PfsBy_SPEC,
6510            crate::common::RW,
6511        >::from_register(self, 0)
6512    }
6513
6514    #[doc = "Port State"]
6515    #[inline(always)]
6516    pub fn pidr(
6517        self,
6518    ) -> crate::common::RegisterField<
6519        1,
6520        0x1,
6521        1,
6522        0,
6523        p1pfs_by::Pidr,
6524        p1pfs_by::Pidr,
6525        P1PfsBy_SPEC,
6526        crate::common::R,
6527    > {
6528        crate::common::RegisterField::<
6529            1,
6530            0x1,
6531            1,
6532            0,
6533            p1pfs_by::Pidr,
6534            p1pfs_by::Pidr,
6535            P1PfsBy_SPEC,
6536            crate::common::R,
6537        >::from_register(self, 0)
6538    }
6539
6540    #[doc = "Port Direction"]
6541    #[inline(always)]
6542    pub fn pdr(
6543        self,
6544    ) -> crate::common::RegisterField<
6545        2,
6546        0x1,
6547        1,
6548        0,
6549        p1pfs_by::Pdr,
6550        p1pfs_by::Pdr,
6551        P1PfsBy_SPEC,
6552        crate::common::RW,
6553    > {
6554        crate::common::RegisterField::<
6555            2,
6556            0x1,
6557            1,
6558            0,
6559            p1pfs_by::Pdr,
6560            p1pfs_by::Pdr,
6561            P1PfsBy_SPEC,
6562            crate::common::RW,
6563        >::from_register(self, 0)
6564    }
6565
6566    #[doc = "Pull-up Control"]
6567    #[inline(always)]
6568    pub fn pcr(
6569        self,
6570    ) -> crate::common::RegisterField<
6571        4,
6572        0x1,
6573        1,
6574        0,
6575        p1pfs_by::Pcr,
6576        p1pfs_by::Pcr,
6577        P1PfsBy_SPEC,
6578        crate::common::RW,
6579    > {
6580        crate::common::RegisterField::<
6581            4,
6582            0x1,
6583            1,
6584            0,
6585            p1pfs_by::Pcr,
6586            p1pfs_by::Pcr,
6587            P1PfsBy_SPEC,
6588            crate::common::RW,
6589        >::from_register(self, 0)
6590    }
6591
6592    #[doc = "N-Channel Open-Drain Control"]
6593    #[inline(always)]
6594    pub fn ncodr(
6595        self,
6596    ) -> crate::common::RegisterField<
6597        6,
6598        0x1,
6599        1,
6600        0,
6601        p1pfs_by::Ncodr,
6602        p1pfs_by::Ncodr,
6603        P1PfsBy_SPEC,
6604        crate::common::RW,
6605    > {
6606        crate::common::RegisterField::<
6607            6,
6608            0x1,
6609            1,
6610            0,
6611            p1pfs_by::Ncodr,
6612            p1pfs_by::Ncodr,
6613            P1PfsBy_SPEC,
6614            crate::common::RW,
6615        >::from_register(self, 0)
6616    }
6617}
6618impl ::core::default::Default for P1PfsBy {
6619    #[inline(always)]
6620    fn default() -> P1PfsBy {
6621        <crate::RegValueT<P1PfsBy_SPEC> as RegisterValue<_>>::new(0)
6622    }
6623}
6624pub mod p1pfs_by {
6625
6626    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6627    pub struct Podr_SPEC;
6628    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
6629    impl Podr {
6630        #[doc = "Output low"]
6631        pub const _0: Self = Self::new(0);
6632
6633        #[doc = "Output high"]
6634        pub const _1: Self = Self::new(1);
6635    }
6636    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6637    pub struct Pidr_SPEC;
6638    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
6639    impl Pidr {
6640        #[doc = "Low level"]
6641        pub const _0: Self = Self::new(0);
6642
6643        #[doc = "High level"]
6644        pub const _1: Self = Self::new(1);
6645    }
6646    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6647    pub struct Pdr_SPEC;
6648    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
6649    impl Pdr {
6650        #[doc = "Input (functions as an input pin)"]
6651        pub const _0: Self = Self::new(0);
6652
6653        #[doc = "Output (functions as an output pin)"]
6654        pub const _1: Self = Self::new(1);
6655    }
6656    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6657    pub struct Pcr_SPEC;
6658    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
6659    impl Pcr {
6660        #[doc = "Disable input pull-up"]
6661        pub const _0: Self = Self::new(0);
6662
6663        #[doc = "Enable input pull-up"]
6664        pub const _1: Self = Self::new(1);
6665    }
6666    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6667    pub struct Ncodr_SPEC;
6668    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
6669    impl Ncodr {
6670        #[doc = "Output CMOS"]
6671        pub const _0: Self = Self::new(0);
6672
6673        #[doc = "Output NMOS open-drain"]
6674        pub const _1: Self = Self::new(1);
6675    }
6676}
6677#[doc(hidden)]
6678#[derive(Copy, Clone, Eq, PartialEq)]
6679pub struct P200Pfs_SPEC;
6680impl crate::sealed::RegSpec for P200Pfs_SPEC {
6681    type DataType = u32;
6682}
6683
6684#[doc = "Port 200 Pin Function Select Register"]
6685pub type P200Pfs = crate::RegValueT<P200Pfs_SPEC>;
6686
6687impl P200Pfs {
6688    #[doc = "Port Output Data"]
6689    #[inline(always)]
6690    pub fn podr(
6691        self,
6692    ) -> crate::common::RegisterField<
6693        0,
6694        0x1,
6695        1,
6696        0,
6697        p200pfs::Podr,
6698        p200pfs::Podr,
6699        P200Pfs_SPEC,
6700        crate::common::RW,
6701    > {
6702        crate::common::RegisterField::<
6703            0,
6704            0x1,
6705            1,
6706            0,
6707            p200pfs::Podr,
6708            p200pfs::Podr,
6709            P200Pfs_SPEC,
6710            crate::common::RW,
6711        >::from_register(self, 0)
6712    }
6713
6714    #[doc = "Port State"]
6715    #[inline(always)]
6716    pub fn pidr(
6717        self,
6718    ) -> crate::common::RegisterField<
6719        1,
6720        0x1,
6721        1,
6722        0,
6723        p200pfs::Pidr,
6724        p200pfs::Pidr,
6725        P200Pfs_SPEC,
6726        crate::common::R,
6727    > {
6728        crate::common::RegisterField::<
6729            1,
6730            0x1,
6731            1,
6732            0,
6733            p200pfs::Pidr,
6734            p200pfs::Pidr,
6735            P200Pfs_SPEC,
6736            crate::common::R,
6737        >::from_register(self, 0)
6738    }
6739
6740    #[doc = "Port Direction"]
6741    #[inline(always)]
6742    pub fn pdr(
6743        self,
6744    ) -> crate::common::RegisterField<
6745        2,
6746        0x1,
6747        1,
6748        0,
6749        p200pfs::Pdr,
6750        p200pfs::Pdr,
6751        P200Pfs_SPEC,
6752        crate::common::RW,
6753    > {
6754        crate::common::RegisterField::<
6755            2,
6756            0x1,
6757            1,
6758            0,
6759            p200pfs::Pdr,
6760            p200pfs::Pdr,
6761            P200Pfs_SPEC,
6762            crate::common::RW,
6763        >::from_register(self, 0)
6764    }
6765
6766    #[doc = "Pull-up Control"]
6767    #[inline(always)]
6768    pub fn pcr(
6769        self,
6770    ) -> crate::common::RegisterField<
6771        4,
6772        0x1,
6773        1,
6774        0,
6775        p200pfs::Pcr,
6776        p200pfs::Pcr,
6777        P200Pfs_SPEC,
6778        crate::common::RW,
6779    > {
6780        crate::common::RegisterField::<
6781            4,
6782            0x1,
6783            1,
6784            0,
6785            p200pfs::Pcr,
6786            p200pfs::Pcr,
6787            P200Pfs_SPEC,
6788            crate::common::RW,
6789        >::from_register(self, 0)
6790    }
6791
6792    #[doc = "N-Channel Open-Drain Control"]
6793    #[inline(always)]
6794    pub fn ncodr(
6795        self,
6796    ) -> crate::common::RegisterField<
6797        6,
6798        0x1,
6799        1,
6800        0,
6801        p200pfs::Ncodr,
6802        p200pfs::Ncodr,
6803        P200Pfs_SPEC,
6804        crate::common::RW,
6805    > {
6806        crate::common::RegisterField::<
6807            6,
6808            0x1,
6809            1,
6810            0,
6811            p200pfs::Ncodr,
6812            p200pfs::Ncodr,
6813            P200Pfs_SPEC,
6814            crate::common::RW,
6815        >::from_register(self, 0)
6816    }
6817
6818    #[doc = "Event on Falling/Event on Rising"]
6819    #[inline(always)]
6820    pub fn eofr(
6821        self,
6822    ) -> crate::common::RegisterField<
6823        12,
6824        0x3,
6825        1,
6826        0,
6827        p200pfs::Eofr,
6828        p200pfs::Eofr,
6829        P200Pfs_SPEC,
6830        crate::common::RW,
6831    > {
6832        crate::common::RegisterField::<
6833            12,
6834            0x3,
6835            1,
6836            0,
6837            p200pfs::Eofr,
6838            p200pfs::Eofr,
6839            P200Pfs_SPEC,
6840            crate::common::RW,
6841        >::from_register(self, 0)
6842    }
6843
6844    #[doc = "IRQ Input Enable"]
6845    #[inline(always)]
6846    pub fn isel(
6847        self,
6848    ) -> crate::common::RegisterField<
6849        14,
6850        0x1,
6851        1,
6852        0,
6853        p200pfs::Isel,
6854        p200pfs::Isel,
6855        P200Pfs_SPEC,
6856        crate::common::RW,
6857    > {
6858        crate::common::RegisterField::<
6859            14,
6860            0x1,
6861            1,
6862            0,
6863            p200pfs::Isel,
6864            p200pfs::Isel,
6865            P200Pfs_SPEC,
6866            crate::common::RW,
6867        >::from_register(self, 0)
6868    }
6869
6870    #[doc = "Analog Input Enable"]
6871    #[inline(always)]
6872    pub fn asel(
6873        self,
6874    ) -> crate::common::RegisterField<
6875        15,
6876        0x1,
6877        1,
6878        0,
6879        p200pfs::Asel,
6880        p200pfs::Asel,
6881        P200Pfs_SPEC,
6882        crate::common::RW,
6883    > {
6884        crate::common::RegisterField::<
6885            15,
6886            0x1,
6887            1,
6888            0,
6889            p200pfs::Asel,
6890            p200pfs::Asel,
6891            P200Pfs_SPEC,
6892            crate::common::RW,
6893        >::from_register(self, 0)
6894    }
6895
6896    #[doc = "Port Mode Control"]
6897    #[inline(always)]
6898    pub fn pmr(
6899        self,
6900    ) -> crate::common::RegisterField<
6901        16,
6902        0x1,
6903        1,
6904        0,
6905        p200pfs::Pmr,
6906        p200pfs::Pmr,
6907        P200Pfs_SPEC,
6908        crate::common::RW,
6909    > {
6910        crate::common::RegisterField::<
6911            16,
6912            0x1,
6913            1,
6914            0,
6915            p200pfs::Pmr,
6916            p200pfs::Pmr,
6917            P200Pfs_SPEC,
6918            crate::common::RW,
6919        >::from_register(self, 0)
6920    }
6921
6922    #[doc = "Peripheral Select"]
6923    #[inline(always)]
6924    pub fn psel(
6925        self,
6926    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P200Pfs_SPEC, crate::common::RW> {
6927        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P200Pfs_SPEC,crate::common::RW>::from_register(self,0)
6928    }
6929}
6930impl ::core::default::Default for P200Pfs {
6931    #[inline(always)]
6932    fn default() -> P200Pfs {
6933        <crate::RegValueT<P200Pfs_SPEC> as RegisterValue<_>>::new(0)
6934    }
6935}
6936pub mod p200pfs {
6937
6938    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6939    pub struct Podr_SPEC;
6940    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
6941    impl Podr {
6942        #[doc = "Output low"]
6943        pub const _0: Self = Self::new(0);
6944
6945        #[doc = "Output high"]
6946        pub const _1: Self = Self::new(1);
6947    }
6948    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6949    pub struct Pidr_SPEC;
6950    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
6951    impl Pidr {
6952        #[doc = "Low level"]
6953        pub const _0: Self = Self::new(0);
6954
6955        #[doc = "High level"]
6956        pub const _1: Self = Self::new(1);
6957    }
6958    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6959    pub struct Pdr_SPEC;
6960    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
6961    impl Pdr {
6962        #[doc = "Input (functions as an input pin)"]
6963        pub const _0: Self = Self::new(0);
6964
6965        #[doc = "Output (functions as an output pin)"]
6966        pub const _1: Self = Self::new(1);
6967    }
6968    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6969    pub struct Pcr_SPEC;
6970    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
6971    impl Pcr {
6972        #[doc = "Disable input pull-up"]
6973        pub const _0: Self = Self::new(0);
6974
6975        #[doc = "Enable input pull-up"]
6976        pub const _1: Self = Self::new(1);
6977    }
6978    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6979    pub struct Ncodr_SPEC;
6980    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
6981    impl Ncodr {
6982        #[doc = "Output CMOS"]
6983        pub const _0: Self = Self::new(0);
6984
6985        #[doc = "Output NMOS open-drain"]
6986        pub const _1: Self = Self::new(1);
6987    }
6988    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6989    pub struct Eofr_SPEC;
6990    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
6991    impl Eofr {
6992        #[doc = "Don\'t care"]
6993        pub const _00: Self = Self::new(0);
6994
6995        #[doc = "Detect rising edge"]
6996        pub const _01: Self = Self::new(1);
6997
6998        #[doc = "Detect falling edge"]
6999        pub const _10: Self = Self::new(2);
7000
7001        #[doc = "Detect both edges"]
7002        pub const _11: Self = Self::new(3);
7003    }
7004    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7005    pub struct Isel_SPEC;
7006    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
7007    impl Isel {
7008        #[doc = "Do not use as IRQn input pin"]
7009        pub const _0: Self = Self::new(0);
7010
7011        #[doc = "Use as IRQn input pin"]
7012        pub const _1: Self = Self::new(1);
7013    }
7014    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7015    pub struct Asel_SPEC;
7016    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
7017    impl Asel {
7018        #[doc = "Do not use as analog pin"]
7019        pub const _0: Self = Self::new(0);
7020
7021        #[doc = "Use as analog pin"]
7022        pub const _1: Self = Self::new(1);
7023    }
7024    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7025    pub struct Pmr_SPEC;
7026    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
7027    impl Pmr {
7028        #[doc = "Use as general I/O pin"]
7029        pub const _0: Self = Self::new(0);
7030
7031        #[doc = "Use as I/O port for peripheral functions"]
7032        pub const _1: Self = Self::new(1);
7033    }
7034}
7035#[doc(hidden)]
7036#[derive(Copy, Clone, Eq, PartialEq)]
7037pub struct P200PfsHa_SPEC;
7038impl crate::sealed::RegSpec for P200PfsHa_SPEC {
7039    type DataType = u16;
7040}
7041
7042#[doc = "Port 200 Pin Function Select Register"]
7043pub type P200PfsHa = crate::RegValueT<P200PfsHa_SPEC>;
7044
7045impl P200PfsHa {
7046    #[doc = "Port Output Data"]
7047    #[inline(always)]
7048    pub fn podr(
7049        self,
7050    ) -> crate::common::RegisterField<
7051        0,
7052        0x1,
7053        1,
7054        0,
7055        p200pfs_ha::Podr,
7056        p200pfs_ha::Podr,
7057        P200PfsHa_SPEC,
7058        crate::common::RW,
7059    > {
7060        crate::common::RegisterField::<
7061            0,
7062            0x1,
7063            1,
7064            0,
7065            p200pfs_ha::Podr,
7066            p200pfs_ha::Podr,
7067            P200PfsHa_SPEC,
7068            crate::common::RW,
7069        >::from_register(self, 0)
7070    }
7071
7072    #[doc = "Port State"]
7073    #[inline(always)]
7074    pub fn pidr(
7075        self,
7076    ) -> crate::common::RegisterField<
7077        1,
7078        0x1,
7079        1,
7080        0,
7081        p200pfs_ha::Pidr,
7082        p200pfs_ha::Pidr,
7083        P200PfsHa_SPEC,
7084        crate::common::R,
7085    > {
7086        crate::common::RegisterField::<
7087            1,
7088            0x1,
7089            1,
7090            0,
7091            p200pfs_ha::Pidr,
7092            p200pfs_ha::Pidr,
7093            P200PfsHa_SPEC,
7094            crate::common::R,
7095        >::from_register(self, 0)
7096    }
7097
7098    #[doc = "Port Direction"]
7099    #[inline(always)]
7100    pub fn pdr(
7101        self,
7102    ) -> crate::common::RegisterField<
7103        2,
7104        0x1,
7105        1,
7106        0,
7107        p200pfs_ha::Pdr,
7108        p200pfs_ha::Pdr,
7109        P200PfsHa_SPEC,
7110        crate::common::RW,
7111    > {
7112        crate::common::RegisterField::<
7113            2,
7114            0x1,
7115            1,
7116            0,
7117            p200pfs_ha::Pdr,
7118            p200pfs_ha::Pdr,
7119            P200PfsHa_SPEC,
7120            crate::common::RW,
7121        >::from_register(self, 0)
7122    }
7123
7124    #[doc = "Pull-up Control"]
7125    #[inline(always)]
7126    pub fn pcr(
7127        self,
7128    ) -> crate::common::RegisterField<
7129        4,
7130        0x1,
7131        1,
7132        0,
7133        p200pfs_ha::Pcr,
7134        p200pfs_ha::Pcr,
7135        P200PfsHa_SPEC,
7136        crate::common::RW,
7137    > {
7138        crate::common::RegisterField::<
7139            4,
7140            0x1,
7141            1,
7142            0,
7143            p200pfs_ha::Pcr,
7144            p200pfs_ha::Pcr,
7145            P200PfsHa_SPEC,
7146            crate::common::RW,
7147        >::from_register(self, 0)
7148    }
7149
7150    #[doc = "N-Channel Open-Drain Control"]
7151    #[inline(always)]
7152    pub fn ncodr(
7153        self,
7154    ) -> crate::common::RegisterField<
7155        6,
7156        0x1,
7157        1,
7158        0,
7159        p200pfs_ha::Ncodr,
7160        p200pfs_ha::Ncodr,
7161        P200PfsHa_SPEC,
7162        crate::common::RW,
7163    > {
7164        crate::common::RegisterField::<
7165            6,
7166            0x1,
7167            1,
7168            0,
7169            p200pfs_ha::Ncodr,
7170            p200pfs_ha::Ncodr,
7171            P200PfsHa_SPEC,
7172            crate::common::RW,
7173        >::from_register(self, 0)
7174    }
7175
7176    #[doc = "Event on Falling/Event on Rising"]
7177    #[inline(always)]
7178    pub fn eofr(
7179        self,
7180    ) -> crate::common::RegisterField<
7181        12,
7182        0x3,
7183        1,
7184        0,
7185        p200pfs_ha::Eofr,
7186        p200pfs_ha::Eofr,
7187        P200PfsHa_SPEC,
7188        crate::common::RW,
7189    > {
7190        crate::common::RegisterField::<
7191            12,
7192            0x3,
7193            1,
7194            0,
7195            p200pfs_ha::Eofr,
7196            p200pfs_ha::Eofr,
7197            P200PfsHa_SPEC,
7198            crate::common::RW,
7199        >::from_register(self, 0)
7200    }
7201
7202    #[doc = "IRQ Input Enable"]
7203    #[inline(always)]
7204    pub fn isel(
7205        self,
7206    ) -> crate::common::RegisterField<
7207        14,
7208        0x1,
7209        1,
7210        0,
7211        p200pfs_ha::Isel,
7212        p200pfs_ha::Isel,
7213        P200PfsHa_SPEC,
7214        crate::common::RW,
7215    > {
7216        crate::common::RegisterField::<
7217            14,
7218            0x1,
7219            1,
7220            0,
7221            p200pfs_ha::Isel,
7222            p200pfs_ha::Isel,
7223            P200PfsHa_SPEC,
7224            crate::common::RW,
7225        >::from_register(self, 0)
7226    }
7227
7228    #[doc = "Analog Input Enable"]
7229    #[inline(always)]
7230    pub fn asel(
7231        self,
7232    ) -> crate::common::RegisterField<
7233        15,
7234        0x1,
7235        1,
7236        0,
7237        p200pfs_ha::Asel,
7238        p200pfs_ha::Asel,
7239        P200PfsHa_SPEC,
7240        crate::common::RW,
7241    > {
7242        crate::common::RegisterField::<
7243            15,
7244            0x1,
7245            1,
7246            0,
7247            p200pfs_ha::Asel,
7248            p200pfs_ha::Asel,
7249            P200PfsHa_SPEC,
7250            crate::common::RW,
7251        >::from_register(self, 0)
7252    }
7253}
7254impl ::core::default::Default for P200PfsHa {
7255    #[inline(always)]
7256    fn default() -> P200PfsHa {
7257        <crate::RegValueT<P200PfsHa_SPEC> as RegisterValue<_>>::new(0)
7258    }
7259}
7260pub mod p200pfs_ha {
7261
7262    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7263    pub struct Podr_SPEC;
7264    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
7265    impl Podr {
7266        #[doc = "Output low"]
7267        pub const _0: Self = Self::new(0);
7268
7269        #[doc = "Output high"]
7270        pub const _1: Self = Self::new(1);
7271    }
7272    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7273    pub struct Pidr_SPEC;
7274    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
7275    impl Pidr {
7276        #[doc = "Low level"]
7277        pub const _0: Self = Self::new(0);
7278
7279        #[doc = "High level"]
7280        pub const _1: Self = Self::new(1);
7281    }
7282    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7283    pub struct Pdr_SPEC;
7284    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
7285    impl Pdr {
7286        #[doc = "Input (functions as an input pin)"]
7287        pub const _0: Self = Self::new(0);
7288
7289        #[doc = "Output (functions as an output pin)"]
7290        pub const _1: Self = Self::new(1);
7291    }
7292    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7293    pub struct Pcr_SPEC;
7294    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
7295    impl Pcr {
7296        #[doc = "Disable input pull-up"]
7297        pub const _0: Self = Self::new(0);
7298
7299        #[doc = "Enable input pull-up"]
7300        pub const _1: Self = Self::new(1);
7301    }
7302    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7303    pub struct Ncodr_SPEC;
7304    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
7305    impl Ncodr {
7306        #[doc = "Output CMOS"]
7307        pub const _0: Self = Self::new(0);
7308
7309        #[doc = "Output NMOS open-drain"]
7310        pub const _1: Self = Self::new(1);
7311    }
7312    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7313    pub struct Eofr_SPEC;
7314    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
7315    impl Eofr {
7316        #[doc = "Don\'t care"]
7317        pub const _00: Self = Self::new(0);
7318
7319        #[doc = "Detect rising edge"]
7320        pub const _01: Self = Self::new(1);
7321
7322        #[doc = "Detect falling edge"]
7323        pub const _10: Self = Self::new(2);
7324
7325        #[doc = "Detect both edges"]
7326        pub const _11: Self = Self::new(3);
7327    }
7328    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7329    pub struct Isel_SPEC;
7330    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
7331    impl Isel {
7332        #[doc = "Do not use as IRQn input pin"]
7333        pub const _0: Self = Self::new(0);
7334
7335        #[doc = "Use as IRQn input pin"]
7336        pub const _1: Self = Self::new(1);
7337    }
7338    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7339    pub struct Asel_SPEC;
7340    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
7341    impl Asel {
7342        #[doc = "Do not use as analog pin"]
7343        pub const _0: Self = Self::new(0);
7344
7345        #[doc = "Use as analog pin"]
7346        pub const _1: Self = Self::new(1);
7347    }
7348}
7349#[doc(hidden)]
7350#[derive(Copy, Clone, Eq, PartialEq)]
7351pub struct P200PfsBy_SPEC;
7352impl crate::sealed::RegSpec for P200PfsBy_SPEC {
7353    type DataType = u8;
7354}
7355
7356#[doc = "Port 200 Pin Function Select Register"]
7357pub type P200PfsBy = crate::RegValueT<P200PfsBy_SPEC>;
7358
7359impl P200PfsBy {
7360    #[doc = "Port Output Data"]
7361    #[inline(always)]
7362    pub fn podr(
7363        self,
7364    ) -> crate::common::RegisterField<
7365        0,
7366        0x1,
7367        1,
7368        0,
7369        p200pfs_by::Podr,
7370        p200pfs_by::Podr,
7371        P200PfsBy_SPEC,
7372        crate::common::RW,
7373    > {
7374        crate::common::RegisterField::<
7375            0,
7376            0x1,
7377            1,
7378            0,
7379            p200pfs_by::Podr,
7380            p200pfs_by::Podr,
7381            P200PfsBy_SPEC,
7382            crate::common::RW,
7383        >::from_register(self, 0)
7384    }
7385
7386    #[doc = "Port State"]
7387    #[inline(always)]
7388    pub fn pidr(
7389        self,
7390    ) -> crate::common::RegisterField<
7391        1,
7392        0x1,
7393        1,
7394        0,
7395        p200pfs_by::Pidr,
7396        p200pfs_by::Pidr,
7397        P200PfsBy_SPEC,
7398        crate::common::R,
7399    > {
7400        crate::common::RegisterField::<
7401            1,
7402            0x1,
7403            1,
7404            0,
7405            p200pfs_by::Pidr,
7406            p200pfs_by::Pidr,
7407            P200PfsBy_SPEC,
7408            crate::common::R,
7409        >::from_register(self, 0)
7410    }
7411
7412    #[doc = "Port Direction"]
7413    #[inline(always)]
7414    pub fn pdr(
7415        self,
7416    ) -> crate::common::RegisterField<
7417        2,
7418        0x1,
7419        1,
7420        0,
7421        p200pfs_by::Pdr,
7422        p200pfs_by::Pdr,
7423        P200PfsBy_SPEC,
7424        crate::common::RW,
7425    > {
7426        crate::common::RegisterField::<
7427            2,
7428            0x1,
7429            1,
7430            0,
7431            p200pfs_by::Pdr,
7432            p200pfs_by::Pdr,
7433            P200PfsBy_SPEC,
7434            crate::common::RW,
7435        >::from_register(self, 0)
7436    }
7437
7438    #[doc = "Pull-up Control"]
7439    #[inline(always)]
7440    pub fn pcr(
7441        self,
7442    ) -> crate::common::RegisterField<
7443        4,
7444        0x1,
7445        1,
7446        0,
7447        p200pfs_by::Pcr,
7448        p200pfs_by::Pcr,
7449        P200PfsBy_SPEC,
7450        crate::common::RW,
7451    > {
7452        crate::common::RegisterField::<
7453            4,
7454            0x1,
7455            1,
7456            0,
7457            p200pfs_by::Pcr,
7458            p200pfs_by::Pcr,
7459            P200PfsBy_SPEC,
7460            crate::common::RW,
7461        >::from_register(self, 0)
7462    }
7463
7464    #[doc = "N-Channel Open-Drain Control"]
7465    #[inline(always)]
7466    pub fn ncodr(
7467        self,
7468    ) -> crate::common::RegisterField<
7469        6,
7470        0x1,
7471        1,
7472        0,
7473        p200pfs_by::Ncodr,
7474        p200pfs_by::Ncodr,
7475        P200PfsBy_SPEC,
7476        crate::common::RW,
7477    > {
7478        crate::common::RegisterField::<
7479            6,
7480            0x1,
7481            1,
7482            0,
7483            p200pfs_by::Ncodr,
7484            p200pfs_by::Ncodr,
7485            P200PfsBy_SPEC,
7486            crate::common::RW,
7487        >::from_register(self, 0)
7488    }
7489}
7490impl ::core::default::Default for P200PfsBy {
7491    #[inline(always)]
7492    fn default() -> P200PfsBy {
7493        <crate::RegValueT<P200PfsBy_SPEC> as RegisterValue<_>>::new(0)
7494    }
7495}
7496pub mod p200pfs_by {
7497
7498    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7499    pub struct Podr_SPEC;
7500    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
7501    impl Podr {
7502        #[doc = "Output low"]
7503        pub const _0: Self = Self::new(0);
7504
7505        #[doc = "Output high"]
7506        pub const _1: Self = Self::new(1);
7507    }
7508    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7509    pub struct Pidr_SPEC;
7510    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
7511    impl Pidr {
7512        #[doc = "Low level"]
7513        pub const _0: Self = Self::new(0);
7514
7515        #[doc = "High level"]
7516        pub const _1: Self = Self::new(1);
7517    }
7518    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7519    pub struct Pdr_SPEC;
7520    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
7521    impl Pdr {
7522        #[doc = "Input (functions as an input pin)"]
7523        pub const _0: Self = Self::new(0);
7524
7525        #[doc = "Output (functions as an output pin)"]
7526        pub const _1: Self = Self::new(1);
7527    }
7528    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7529    pub struct Pcr_SPEC;
7530    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
7531    impl Pcr {
7532        #[doc = "Disable input pull-up"]
7533        pub const _0: Self = Self::new(0);
7534
7535        #[doc = "Enable input pull-up"]
7536        pub const _1: Self = Self::new(1);
7537    }
7538    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7539    pub struct Ncodr_SPEC;
7540    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
7541    impl Ncodr {
7542        #[doc = "Output CMOS"]
7543        pub const _0: Self = Self::new(0);
7544
7545        #[doc = "Output NMOS open-drain"]
7546        pub const _1: Self = Self::new(1);
7547    }
7548}
7549#[doc(hidden)]
7550#[derive(Copy, Clone, Eq, PartialEq)]
7551pub struct P201Pfs_SPEC;
7552impl crate::sealed::RegSpec for P201Pfs_SPEC {
7553    type DataType = u32;
7554}
7555
7556#[doc = "Port 201 Pin Function Select Register"]
7557pub type P201Pfs = crate::RegValueT<P201Pfs_SPEC>;
7558
7559impl P201Pfs {
7560    #[doc = "Port Output Data"]
7561    #[inline(always)]
7562    pub fn podr(
7563        self,
7564    ) -> crate::common::RegisterField<
7565        0,
7566        0x1,
7567        1,
7568        0,
7569        p201pfs::Podr,
7570        p201pfs::Podr,
7571        P201Pfs_SPEC,
7572        crate::common::RW,
7573    > {
7574        crate::common::RegisterField::<
7575            0,
7576            0x1,
7577            1,
7578            0,
7579            p201pfs::Podr,
7580            p201pfs::Podr,
7581            P201Pfs_SPEC,
7582            crate::common::RW,
7583        >::from_register(self, 0)
7584    }
7585
7586    #[doc = "Port State"]
7587    #[inline(always)]
7588    pub fn pidr(
7589        self,
7590    ) -> crate::common::RegisterField<
7591        1,
7592        0x1,
7593        1,
7594        0,
7595        p201pfs::Pidr,
7596        p201pfs::Pidr,
7597        P201Pfs_SPEC,
7598        crate::common::R,
7599    > {
7600        crate::common::RegisterField::<
7601            1,
7602            0x1,
7603            1,
7604            0,
7605            p201pfs::Pidr,
7606            p201pfs::Pidr,
7607            P201Pfs_SPEC,
7608            crate::common::R,
7609        >::from_register(self, 0)
7610    }
7611
7612    #[doc = "Port Direction"]
7613    #[inline(always)]
7614    pub fn pdr(
7615        self,
7616    ) -> crate::common::RegisterField<
7617        2,
7618        0x1,
7619        1,
7620        0,
7621        p201pfs::Pdr,
7622        p201pfs::Pdr,
7623        P201Pfs_SPEC,
7624        crate::common::RW,
7625    > {
7626        crate::common::RegisterField::<
7627            2,
7628            0x1,
7629            1,
7630            0,
7631            p201pfs::Pdr,
7632            p201pfs::Pdr,
7633            P201Pfs_SPEC,
7634            crate::common::RW,
7635        >::from_register(self, 0)
7636    }
7637
7638    #[doc = "Pull-up Control"]
7639    #[inline(always)]
7640    pub fn pcr(
7641        self,
7642    ) -> crate::common::RegisterField<
7643        4,
7644        0x1,
7645        1,
7646        0,
7647        p201pfs::Pcr,
7648        p201pfs::Pcr,
7649        P201Pfs_SPEC,
7650        crate::common::RW,
7651    > {
7652        crate::common::RegisterField::<
7653            4,
7654            0x1,
7655            1,
7656            0,
7657            p201pfs::Pcr,
7658            p201pfs::Pcr,
7659            P201Pfs_SPEC,
7660            crate::common::RW,
7661        >::from_register(self, 0)
7662    }
7663
7664    #[doc = "N-Channel Open-Drain Control"]
7665    #[inline(always)]
7666    pub fn ncodr(
7667        self,
7668    ) -> crate::common::RegisterField<
7669        6,
7670        0x1,
7671        1,
7672        0,
7673        p201pfs::Ncodr,
7674        p201pfs::Ncodr,
7675        P201Pfs_SPEC,
7676        crate::common::RW,
7677    > {
7678        crate::common::RegisterField::<
7679            6,
7680            0x1,
7681            1,
7682            0,
7683            p201pfs::Ncodr,
7684            p201pfs::Ncodr,
7685            P201Pfs_SPEC,
7686            crate::common::RW,
7687        >::from_register(self, 0)
7688    }
7689
7690    #[doc = "Event on Falling/Event on Rising"]
7691    #[inline(always)]
7692    pub fn eofr(
7693        self,
7694    ) -> crate::common::RegisterField<
7695        12,
7696        0x3,
7697        1,
7698        0,
7699        p201pfs::Eofr,
7700        p201pfs::Eofr,
7701        P201Pfs_SPEC,
7702        crate::common::RW,
7703    > {
7704        crate::common::RegisterField::<
7705            12,
7706            0x3,
7707            1,
7708            0,
7709            p201pfs::Eofr,
7710            p201pfs::Eofr,
7711            P201Pfs_SPEC,
7712            crate::common::RW,
7713        >::from_register(self, 0)
7714    }
7715
7716    #[doc = "IRQ Input Enable"]
7717    #[inline(always)]
7718    pub fn isel(
7719        self,
7720    ) -> crate::common::RegisterField<
7721        14,
7722        0x1,
7723        1,
7724        0,
7725        p201pfs::Isel,
7726        p201pfs::Isel,
7727        P201Pfs_SPEC,
7728        crate::common::RW,
7729    > {
7730        crate::common::RegisterField::<
7731            14,
7732            0x1,
7733            1,
7734            0,
7735            p201pfs::Isel,
7736            p201pfs::Isel,
7737            P201Pfs_SPEC,
7738            crate::common::RW,
7739        >::from_register(self, 0)
7740    }
7741
7742    #[doc = "Analog Input Enable"]
7743    #[inline(always)]
7744    pub fn asel(
7745        self,
7746    ) -> crate::common::RegisterField<
7747        15,
7748        0x1,
7749        1,
7750        0,
7751        p201pfs::Asel,
7752        p201pfs::Asel,
7753        P201Pfs_SPEC,
7754        crate::common::RW,
7755    > {
7756        crate::common::RegisterField::<
7757            15,
7758            0x1,
7759            1,
7760            0,
7761            p201pfs::Asel,
7762            p201pfs::Asel,
7763            P201Pfs_SPEC,
7764            crate::common::RW,
7765        >::from_register(self, 0)
7766    }
7767
7768    #[doc = "Port Mode Control"]
7769    #[inline(always)]
7770    pub fn pmr(
7771        self,
7772    ) -> crate::common::RegisterField<
7773        16,
7774        0x1,
7775        1,
7776        0,
7777        p201pfs::Pmr,
7778        p201pfs::Pmr,
7779        P201Pfs_SPEC,
7780        crate::common::RW,
7781    > {
7782        crate::common::RegisterField::<
7783            16,
7784            0x1,
7785            1,
7786            0,
7787            p201pfs::Pmr,
7788            p201pfs::Pmr,
7789            P201Pfs_SPEC,
7790            crate::common::RW,
7791        >::from_register(self, 0)
7792    }
7793
7794    #[doc = "Peripheral Select"]
7795    #[inline(always)]
7796    pub fn psel(
7797        self,
7798    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P201Pfs_SPEC, crate::common::RW> {
7799        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P201Pfs_SPEC,crate::common::RW>::from_register(self,0)
7800    }
7801}
7802impl ::core::default::Default for P201Pfs {
7803    #[inline(always)]
7804    fn default() -> P201Pfs {
7805        <crate::RegValueT<P201Pfs_SPEC> as RegisterValue<_>>::new(16)
7806    }
7807}
7808pub mod p201pfs {
7809
7810    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7811    pub struct Podr_SPEC;
7812    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
7813    impl Podr {
7814        #[doc = "Output low"]
7815        pub const _0: Self = Self::new(0);
7816
7817        #[doc = "Output high"]
7818        pub const _1: Self = Self::new(1);
7819    }
7820    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7821    pub struct Pidr_SPEC;
7822    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
7823    impl Pidr {
7824        #[doc = "Low level"]
7825        pub const _0: Self = Self::new(0);
7826
7827        #[doc = "High level"]
7828        pub const _1: Self = Self::new(1);
7829    }
7830    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7831    pub struct Pdr_SPEC;
7832    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
7833    impl Pdr {
7834        #[doc = "Input (functions as an input pin)"]
7835        pub const _0: Self = Self::new(0);
7836
7837        #[doc = "Output (functions as an output pin)"]
7838        pub const _1: Self = Self::new(1);
7839    }
7840    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7841    pub struct Pcr_SPEC;
7842    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
7843    impl Pcr {
7844        #[doc = "Disable input pull-up"]
7845        pub const _0: Self = Self::new(0);
7846
7847        #[doc = "Enable input pull-up"]
7848        pub const _1: Self = Self::new(1);
7849    }
7850    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7851    pub struct Ncodr_SPEC;
7852    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
7853    impl Ncodr {
7854        #[doc = "Output CMOS"]
7855        pub const _0: Self = Self::new(0);
7856
7857        #[doc = "Output NMOS open-drain"]
7858        pub const _1: Self = Self::new(1);
7859    }
7860    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7861    pub struct Eofr_SPEC;
7862    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
7863    impl Eofr {
7864        #[doc = "Don\'t care"]
7865        pub const _00: Self = Self::new(0);
7866
7867        #[doc = "Detect rising edge"]
7868        pub const _01: Self = Self::new(1);
7869
7870        #[doc = "Detect falling edge"]
7871        pub const _10: Self = Self::new(2);
7872
7873        #[doc = "Detect both edges"]
7874        pub const _11: Self = Self::new(3);
7875    }
7876    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7877    pub struct Isel_SPEC;
7878    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
7879    impl Isel {
7880        #[doc = "Do not use as IRQn input pin"]
7881        pub const _0: Self = Self::new(0);
7882
7883        #[doc = "Use as IRQn input pin"]
7884        pub const _1: Self = Self::new(1);
7885    }
7886    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7887    pub struct Asel_SPEC;
7888    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
7889    impl Asel {
7890        #[doc = "Do not use as analog pin"]
7891        pub const _0: Self = Self::new(0);
7892
7893        #[doc = "Use as analog pin"]
7894        pub const _1: Self = Self::new(1);
7895    }
7896    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7897    pub struct Pmr_SPEC;
7898    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
7899    impl Pmr {
7900        #[doc = "Use as general I/O pin"]
7901        pub const _0: Self = Self::new(0);
7902
7903        #[doc = "Use as I/O port for peripheral functions"]
7904        pub const _1: Self = Self::new(1);
7905    }
7906}
7907#[doc(hidden)]
7908#[derive(Copy, Clone, Eq, PartialEq)]
7909pub struct P201PfsHa_SPEC;
7910impl crate::sealed::RegSpec for P201PfsHa_SPEC {
7911    type DataType = u16;
7912}
7913
7914#[doc = "Port 201 Pin Function Select Register"]
7915pub type P201PfsHa = crate::RegValueT<P201PfsHa_SPEC>;
7916
7917impl P201PfsHa {
7918    #[doc = "Port Output Data"]
7919    #[inline(always)]
7920    pub fn podr(
7921        self,
7922    ) -> crate::common::RegisterField<
7923        0,
7924        0x1,
7925        1,
7926        0,
7927        p201pfs_ha::Podr,
7928        p201pfs_ha::Podr,
7929        P201PfsHa_SPEC,
7930        crate::common::RW,
7931    > {
7932        crate::common::RegisterField::<
7933            0,
7934            0x1,
7935            1,
7936            0,
7937            p201pfs_ha::Podr,
7938            p201pfs_ha::Podr,
7939            P201PfsHa_SPEC,
7940            crate::common::RW,
7941        >::from_register(self, 0)
7942    }
7943
7944    #[doc = "Port State"]
7945    #[inline(always)]
7946    pub fn pidr(
7947        self,
7948    ) -> crate::common::RegisterField<
7949        1,
7950        0x1,
7951        1,
7952        0,
7953        p201pfs_ha::Pidr,
7954        p201pfs_ha::Pidr,
7955        P201PfsHa_SPEC,
7956        crate::common::R,
7957    > {
7958        crate::common::RegisterField::<
7959            1,
7960            0x1,
7961            1,
7962            0,
7963            p201pfs_ha::Pidr,
7964            p201pfs_ha::Pidr,
7965            P201PfsHa_SPEC,
7966            crate::common::R,
7967        >::from_register(self, 0)
7968    }
7969
7970    #[doc = "Port Direction"]
7971    #[inline(always)]
7972    pub fn pdr(
7973        self,
7974    ) -> crate::common::RegisterField<
7975        2,
7976        0x1,
7977        1,
7978        0,
7979        p201pfs_ha::Pdr,
7980        p201pfs_ha::Pdr,
7981        P201PfsHa_SPEC,
7982        crate::common::RW,
7983    > {
7984        crate::common::RegisterField::<
7985            2,
7986            0x1,
7987            1,
7988            0,
7989            p201pfs_ha::Pdr,
7990            p201pfs_ha::Pdr,
7991            P201PfsHa_SPEC,
7992            crate::common::RW,
7993        >::from_register(self, 0)
7994    }
7995
7996    #[doc = "Pull-up Control"]
7997    #[inline(always)]
7998    pub fn pcr(
7999        self,
8000    ) -> crate::common::RegisterField<
8001        4,
8002        0x1,
8003        1,
8004        0,
8005        p201pfs_ha::Pcr,
8006        p201pfs_ha::Pcr,
8007        P201PfsHa_SPEC,
8008        crate::common::RW,
8009    > {
8010        crate::common::RegisterField::<
8011            4,
8012            0x1,
8013            1,
8014            0,
8015            p201pfs_ha::Pcr,
8016            p201pfs_ha::Pcr,
8017            P201PfsHa_SPEC,
8018            crate::common::RW,
8019        >::from_register(self, 0)
8020    }
8021
8022    #[doc = "N-Channel Open-Drain Control"]
8023    #[inline(always)]
8024    pub fn ncodr(
8025        self,
8026    ) -> crate::common::RegisterField<
8027        6,
8028        0x1,
8029        1,
8030        0,
8031        p201pfs_ha::Ncodr,
8032        p201pfs_ha::Ncodr,
8033        P201PfsHa_SPEC,
8034        crate::common::RW,
8035    > {
8036        crate::common::RegisterField::<
8037            6,
8038            0x1,
8039            1,
8040            0,
8041            p201pfs_ha::Ncodr,
8042            p201pfs_ha::Ncodr,
8043            P201PfsHa_SPEC,
8044            crate::common::RW,
8045        >::from_register(self, 0)
8046    }
8047
8048    #[doc = "Event on Falling/Event on Rising"]
8049    #[inline(always)]
8050    pub fn eofr(
8051        self,
8052    ) -> crate::common::RegisterField<
8053        12,
8054        0x3,
8055        1,
8056        0,
8057        p201pfs_ha::Eofr,
8058        p201pfs_ha::Eofr,
8059        P201PfsHa_SPEC,
8060        crate::common::RW,
8061    > {
8062        crate::common::RegisterField::<
8063            12,
8064            0x3,
8065            1,
8066            0,
8067            p201pfs_ha::Eofr,
8068            p201pfs_ha::Eofr,
8069            P201PfsHa_SPEC,
8070            crate::common::RW,
8071        >::from_register(self, 0)
8072    }
8073
8074    #[doc = "IRQ Input Enable"]
8075    #[inline(always)]
8076    pub fn isel(
8077        self,
8078    ) -> crate::common::RegisterField<
8079        14,
8080        0x1,
8081        1,
8082        0,
8083        p201pfs_ha::Isel,
8084        p201pfs_ha::Isel,
8085        P201PfsHa_SPEC,
8086        crate::common::RW,
8087    > {
8088        crate::common::RegisterField::<
8089            14,
8090            0x1,
8091            1,
8092            0,
8093            p201pfs_ha::Isel,
8094            p201pfs_ha::Isel,
8095            P201PfsHa_SPEC,
8096            crate::common::RW,
8097        >::from_register(self, 0)
8098    }
8099
8100    #[doc = "Analog Input Enable"]
8101    #[inline(always)]
8102    pub fn asel(
8103        self,
8104    ) -> crate::common::RegisterField<
8105        15,
8106        0x1,
8107        1,
8108        0,
8109        p201pfs_ha::Asel,
8110        p201pfs_ha::Asel,
8111        P201PfsHa_SPEC,
8112        crate::common::RW,
8113    > {
8114        crate::common::RegisterField::<
8115            15,
8116            0x1,
8117            1,
8118            0,
8119            p201pfs_ha::Asel,
8120            p201pfs_ha::Asel,
8121            P201PfsHa_SPEC,
8122            crate::common::RW,
8123        >::from_register(self, 0)
8124    }
8125}
8126impl ::core::default::Default for P201PfsHa {
8127    #[inline(always)]
8128    fn default() -> P201PfsHa {
8129        <crate::RegValueT<P201PfsHa_SPEC> as RegisterValue<_>>::new(16)
8130    }
8131}
8132pub mod p201pfs_ha {
8133
8134    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8135    pub struct Podr_SPEC;
8136    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
8137    impl Podr {
8138        #[doc = "Output low"]
8139        pub const _0: Self = Self::new(0);
8140
8141        #[doc = "Output high"]
8142        pub const _1: Self = Self::new(1);
8143    }
8144    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8145    pub struct Pidr_SPEC;
8146    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
8147    impl Pidr {
8148        #[doc = "Low level"]
8149        pub const _0: Self = Self::new(0);
8150
8151        #[doc = "High level"]
8152        pub const _1: Self = Self::new(1);
8153    }
8154    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8155    pub struct Pdr_SPEC;
8156    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
8157    impl Pdr {
8158        #[doc = "Input (functions as an input pin)"]
8159        pub const _0: Self = Self::new(0);
8160
8161        #[doc = "Output (functions as an output pin)"]
8162        pub const _1: Self = Self::new(1);
8163    }
8164    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8165    pub struct Pcr_SPEC;
8166    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
8167    impl Pcr {
8168        #[doc = "Disable input pull-up"]
8169        pub const _0: Self = Self::new(0);
8170
8171        #[doc = "Enable input pull-up"]
8172        pub const _1: Self = Self::new(1);
8173    }
8174    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8175    pub struct Ncodr_SPEC;
8176    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
8177    impl Ncodr {
8178        #[doc = "Output CMOS"]
8179        pub const _0: Self = Self::new(0);
8180
8181        #[doc = "Output NMOS open-drain"]
8182        pub const _1: Self = Self::new(1);
8183    }
8184    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8185    pub struct Eofr_SPEC;
8186    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
8187    impl Eofr {
8188        #[doc = "Don\'t care"]
8189        pub const _00: Self = Self::new(0);
8190
8191        #[doc = "Detect rising edge"]
8192        pub const _01: Self = Self::new(1);
8193
8194        #[doc = "Detect falling edge"]
8195        pub const _10: Self = Self::new(2);
8196
8197        #[doc = "Detect both edges"]
8198        pub const _11: Self = Self::new(3);
8199    }
8200    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8201    pub struct Isel_SPEC;
8202    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
8203    impl Isel {
8204        #[doc = "Do not use as IRQn input pin"]
8205        pub const _0: Self = Self::new(0);
8206
8207        #[doc = "Use as IRQn input pin"]
8208        pub const _1: Self = Self::new(1);
8209    }
8210    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8211    pub struct Asel_SPEC;
8212    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
8213    impl Asel {
8214        #[doc = "Do not use as analog pin"]
8215        pub const _0: Self = Self::new(0);
8216
8217        #[doc = "Use as analog pin"]
8218        pub const _1: Self = Self::new(1);
8219    }
8220}
8221#[doc(hidden)]
8222#[derive(Copy, Clone, Eq, PartialEq)]
8223pub struct P201PfsBy_SPEC;
8224impl crate::sealed::RegSpec for P201PfsBy_SPEC {
8225    type DataType = u8;
8226}
8227
8228#[doc = "Port 201 Pin Function Select Register"]
8229pub type P201PfsBy = crate::RegValueT<P201PfsBy_SPEC>;
8230
8231impl P201PfsBy {
8232    #[doc = "Port Output Data"]
8233    #[inline(always)]
8234    pub fn podr(
8235        self,
8236    ) -> crate::common::RegisterField<
8237        0,
8238        0x1,
8239        1,
8240        0,
8241        p201pfs_by::Podr,
8242        p201pfs_by::Podr,
8243        P201PfsBy_SPEC,
8244        crate::common::RW,
8245    > {
8246        crate::common::RegisterField::<
8247            0,
8248            0x1,
8249            1,
8250            0,
8251            p201pfs_by::Podr,
8252            p201pfs_by::Podr,
8253            P201PfsBy_SPEC,
8254            crate::common::RW,
8255        >::from_register(self, 0)
8256    }
8257
8258    #[doc = "Port State"]
8259    #[inline(always)]
8260    pub fn pidr(
8261        self,
8262    ) -> crate::common::RegisterField<
8263        1,
8264        0x1,
8265        1,
8266        0,
8267        p201pfs_by::Pidr,
8268        p201pfs_by::Pidr,
8269        P201PfsBy_SPEC,
8270        crate::common::R,
8271    > {
8272        crate::common::RegisterField::<
8273            1,
8274            0x1,
8275            1,
8276            0,
8277            p201pfs_by::Pidr,
8278            p201pfs_by::Pidr,
8279            P201PfsBy_SPEC,
8280            crate::common::R,
8281        >::from_register(self, 0)
8282    }
8283
8284    #[doc = "Port Direction"]
8285    #[inline(always)]
8286    pub fn pdr(
8287        self,
8288    ) -> crate::common::RegisterField<
8289        2,
8290        0x1,
8291        1,
8292        0,
8293        p201pfs_by::Pdr,
8294        p201pfs_by::Pdr,
8295        P201PfsBy_SPEC,
8296        crate::common::RW,
8297    > {
8298        crate::common::RegisterField::<
8299            2,
8300            0x1,
8301            1,
8302            0,
8303            p201pfs_by::Pdr,
8304            p201pfs_by::Pdr,
8305            P201PfsBy_SPEC,
8306            crate::common::RW,
8307        >::from_register(self, 0)
8308    }
8309
8310    #[doc = "Pull-up Control"]
8311    #[inline(always)]
8312    pub fn pcr(
8313        self,
8314    ) -> crate::common::RegisterField<
8315        4,
8316        0x1,
8317        1,
8318        0,
8319        p201pfs_by::Pcr,
8320        p201pfs_by::Pcr,
8321        P201PfsBy_SPEC,
8322        crate::common::RW,
8323    > {
8324        crate::common::RegisterField::<
8325            4,
8326            0x1,
8327            1,
8328            0,
8329            p201pfs_by::Pcr,
8330            p201pfs_by::Pcr,
8331            P201PfsBy_SPEC,
8332            crate::common::RW,
8333        >::from_register(self, 0)
8334    }
8335
8336    #[doc = "N-Channel Open-Drain Control"]
8337    #[inline(always)]
8338    pub fn ncodr(
8339        self,
8340    ) -> crate::common::RegisterField<
8341        6,
8342        0x1,
8343        1,
8344        0,
8345        p201pfs_by::Ncodr,
8346        p201pfs_by::Ncodr,
8347        P201PfsBy_SPEC,
8348        crate::common::RW,
8349    > {
8350        crate::common::RegisterField::<
8351            6,
8352            0x1,
8353            1,
8354            0,
8355            p201pfs_by::Ncodr,
8356            p201pfs_by::Ncodr,
8357            P201PfsBy_SPEC,
8358            crate::common::RW,
8359        >::from_register(self, 0)
8360    }
8361}
8362impl ::core::default::Default for P201PfsBy {
8363    #[inline(always)]
8364    fn default() -> P201PfsBy {
8365        <crate::RegValueT<P201PfsBy_SPEC> as RegisterValue<_>>::new(16)
8366    }
8367}
8368pub mod p201pfs_by {
8369
8370    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8371    pub struct Podr_SPEC;
8372    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
8373    impl Podr {
8374        #[doc = "Output low"]
8375        pub const _0: Self = Self::new(0);
8376
8377        #[doc = "Output high"]
8378        pub const _1: Self = Self::new(1);
8379    }
8380    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8381    pub struct Pidr_SPEC;
8382    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
8383    impl Pidr {
8384        #[doc = "Low level"]
8385        pub const _0: Self = Self::new(0);
8386
8387        #[doc = "High level"]
8388        pub const _1: Self = Self::new(1);
8389    }
8390    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8391    pub struct Pdr_SPEC;
8392    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
8393    impl Pdr {
8394        #[doc = "Input (functions as an input pin)"]
8395        pub const _0: Self = Self::new(0);
8396
8397        #[doc = "Output (functions as an output pin)"]
8398        pub const _1: Self = Self::new(1);
8399    }
8400    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8401    pub struct Pcr_SPEC;
8402    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
8403    impl Pcr {
8404        #[doc = "Disable input pull-up"]
8405        pub const _0: Self = Self::new(0);
8406
8407        #[doc = "Enable input pull-up"]
8408        pub const _1: Self = Self::new(1);
8409    }
8410    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8411    pub struct Ncodr_SPEC;
8412    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
8413    impl Ncodr {
8414        #[doc = "Output CMOS"]
8415        pub const _0: Self = Self::new(0);
8416
8417        #[doc = "Output NMOS open-drain"]
8418        pub const _1: Self = Self::new(1);
8419    }
8420}
8421#[doc(hidden)]
8422#[derive(Copy, Clone, Eq, PartialEq)]
8423pub struct P20Pfs_SPEC;
8424impl crate::sealed::RegSpec for P20Pfs_SPEC {
8425    type DataType = u32;
8426}
8427
8428#[doc = "Port 20%s Pin Function Select Register"]
8429pub type P20Pfs = crate::RegValueT<P20Pfs_SPEC>;
8430
8431impl P20Pfs {
8432    #[doc = "Port Output Data"]
8433    #[inline(always)]
8434    pub fn podr(
8435        self,
8436    ) -> crate::common::RegisterField<
8437        0,
8438        0x1,
8439        1,
8440        0,
8441        p20pfs::Podr,
8442        p20pfs::Podr,
8443        P20Pfs_SPEC,
8444        crate::common::RW,
8445    > {
8446        crate::common::RegisterField::<
8447            0,
8448            0x1,
8449            1,
8450            0,
8451            p20pfs::Podr,
8452            p20pfs::Podr,
8453            P20Pfs_SPEC,
8454            crate::common::RW,
8455        >::from_register(self, 0)
8456    }
8457
8458    #[doc = "Port State"]
8459    #[inline(always)]
8460    pub fn pidr(
8461        self,
8462    ) -> crate::common::RegisterField<
8463        1,
8464        0x1,
8465        1,
8466        0,
8467        p20pfs::Pidr,
8468        p20pfs::Pidr,
8469        P20Pfs_SPEC,
8470        crate::common::R,
8471    > {
8472        crate::common::RegisterField::<
8473            1,
8474            0x1,
8475            1,
8476            0,
8477            p20pfs::Pidr,
8478            p20pfs::Pidr,
8479            P20Pfs_SPEC,
8480            crate::common::R,
8481        >::from_register(self, 0)
8482    }
8483
8484    #[doc = "Port Direction"]
8485    #[inline(always)]
8486    pub fn pdr(
8487        self,
8488    ) -> crate::common::RegisterField<
8489        2,
8490        0x1,
8491        1,
8492        0,
8493        p20pfs::Pdr,
8494        p20pfs::Pdr,
8495        P20Pfs_SPEC,
8496        crate::common::RW,
8497    > {
8498        crate::common::RegisterField::<
8499            2,
8500            0x1,
8501            1,
8502            0,
8503            p20pfs::Pdr,
8504            p20pfs::Pdr,
8505            P20Pfs_SPEC,
8506            crate::common::RW,
8507        >::from_register(self, 0)
8508    }
8509
8510    #[doc = "Pull-up Control"]
8511    #[inline(always)]
8512    pub fn pcr(
8513        self,
8514    ) -> crate::common::RegisterField<
8515        4,
8516        0x1,
8517        1,
8518        0,
8519        p20pfs::Pcr,
8520        p20pfs::Pcr,
8521        P20Pfs_SPEC,
8522        crate::common::RW,
8523    > {
8524        crate::common::RegisterField::<
8525            4,
8526            0x1,
8527            1,
8528            0,
8529            p20pfs::Pcr,
8530            p20pfs::Pcr,
8531            P20Pfs_SPEC,
8532            crate::common::RW,
8533        >::from_register(self, 0)
8534    }
8535
8536    #[doc = "N-Channel Open-Drain Control"]
8537    #[inline(always)]
8538    pub fn ncodr(
8539        self,
8540    ) -> crate::common::RegisterField<
8541        6,
8542        0x1,
8543        1,
8544        0,
8545        p20pfs::Ncodr,
8546        p20pfs::Ncodr,
8547        P20Pfs_SPEC,
8548        crate::common::RW,
8549    > {
8550        crate::common::RegisterField::<
8551            6,
8552            0x1,
8553            1,
8554            0,
8555            p20pfs::Ncodr,
8556            p20pfs::Ncodr,
8557            P20Pfs_SPEC,
8558            crate::common::RW,
8559        >::from_register(self, 0)
8560    }
8561
8562    #[doc = "Event on Falling/Event on Rising"]
8563    #[inline(always)]
8564    pub fn eofr(
8565        self,
8566    ) -> crate::common::RegisterField<
8567        12,
8568        0x3,
8569        1,
8570        0,
8571        p20pfs::Eofr,
8572        p20pfs::Eofr,
8573        P20Pfs_SPEC,
8574        crate::common::RW,
8575    > {
8576        crate::common::RegisterField::<
8577            12,
8578            0x3,
8579            1,
8580            0,
8581            p20pfs::Eofr,
8582            p20pfs::Eofr,
8583            P20Pfs_SPEC,
8584            crate::common::RW,
8585        >::from_register(self, 0)
8586    }
8587
8588    #[doc = "IRQ Input Enable"]
8589    #[inline(always)]
8590    pub fn isel(
8591        self,
8592    ) -> crate::common::RegisterField<
8593        14,
8594        0x1,
8595        1,
8596        0,
8597        p20pfs::Isel,
8598        p20pfs::Isel,
8599        P20Pfs_SPEC,
8600        crate::common::RW,
8601    > {
8602        crate::common::RegisterField::<
8603            14,
8604            0x1,
8605            1,
8606            0,
8607            p20pfs::Isel,
8608            p20pfs::Isel,
8609            P20Pfs_SPEC,
8610            crate::common::RW,
8611        >::from_register(self, 0)
8612    }
8613
8614    #[doc = "Analog Input Enable"]
8615    #[inline(always)]
8616    pub fn asel(
8617        self,
8618    ) -> crate::common::RegisterField<
8619        15,
8620        0x1,
8621        1,
8622        0,
8623        p20pfs::Asel,
8624        p20pfs::Asel,
8625        P20Pfs_SPEC,
8626        crate::common::RW,
8627    > {
8628        crate::common::RegisterField::<
8629            15,
8630            0x1,
8631            1,
8632            0,
8633            p20pfs::Asel,
8634            p20pfs::Asel,
8635            P20Pfs_SPEC,
8636            crate::common::RW,
8637        >::from_register(self, 0)
8638    }
8639
8640    #[doc = "Port Mode Control"]
8641    #[inline(always)]
8642    pub fn pmr(
8643        self,
8644    ) -> crate::common::RegisterField<
8645        16,
8646        0x1,
8647        1,
8648        0,
8649        p20pfs::Pmr,
8650        p20pfs::Pmr,
8651        P20Pfs_SPEC,
8652        crate::common::RW,
8653    > {
8654        crate::common::RegisterField::<
8655            16,
8656            0x1,
8657            1,
8658            0,
8659            p20pfs::Pmr,
8660            p20pfs::Pmr,
8661            P20Pfs_SPEC,
8662            crate::common::RW,
8663        >::from_register(self, 0)
8664    }
8665
8666    #[doc = "Peripheral Select"]
8667    #[inline(always)]
8668    pub fn psel(
8669        self,
8670    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P20Pfs_SPEC, crate::common::RW> {
8671        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P20Pfs_SPEC,crate::common::RW>::from_register(self,0)
8672    }
8673}
8674impl ::core::default::Default for P20Pfs {
8675    #[inline(always)]
8676    fn default() -> P20Pfs {
8677        <crate::RegValueT<P20Pfs_SPEC> as RegisterValue<_>>::new(0)
8678    }
8679}
8680pub mod p20pfs {
8681
8682    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8683    pub struct Podr_SPEC;
8684    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
8685    impl Podr {
8686        #[doc = "Output low"]
8687        pub const _0: Self = Self::new(0);
8688
8689        #[doc = "Output high"]
8690        pub const _1: Self = Self::new(1);
8691    }
8692    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8693    pub struct Pidr_SPEC;
8694    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
8695    impl Pidr {
8696        #[doc = "Low level"]
8697        pub const _0: Self = Self::new(0);
8698
8699        #[doc = "High level"]
8700        pub const _1: Self = Self::new(1);
8701    }
8702    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8703    pub struct Pdr_SPEC;
8704    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
8705    impl Pdr {
8706        #[doc = "Input (functions as an input pin)"]
8707        pub const _0: Self = Self::new(0);
8708
8709        #[doc = "Output (functions as an output pin)"]
8710        pub const _1: Self = Self::new(1);
8711    }
8712    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8713    pub struct Pcr_SPEC;
8714    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
8715    impl Pcr {
8716        #[doc = "Disable input pull-up"]
8717        pub const _0: Self = Self::new(0);
8718
8719        #[doc = "Enable input pull-up"]
8720        pub const _1: Self = Self::new(1);
8721    }
8722    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8723    pub struct Ncodr_SPEC;
8724    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
8725    impl Ncodr {
8726        #[doc = "Output CMOS"]
8727        pub const _0: Self = Self::new(0);
8728
8729        #[doc = "Output NMOS open-drain"]
8730        pub const _1: Self = Self::new(1);
8731    }
8732    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8733    pub struct Eofr_SPEC;
8734    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
8735    impl Eofr {
8736        #[doc = "Don\'t care"]
8737        pub const _00: Self = Self::new(0);
8738
8739        #[doc = "Detect rising edge"]
8740        pub const _01: Self = Self::new(1);
8741
8742        #[doc = "Detect falling edge"]
8743        pub const _10: Self = Self::new(2);
8744
8745        #[doc = "Detect both edges"]
8746        pub const _11: Self = Self::new(3);
8747    }
8748    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8749    pub struct Isel_SPEC;
8750    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
8751    impl Isel {
8752        #[doc = "Do not use as IRQn input pin"]
8753        pub const _0: Self = Self::new(0);
8754
8755        #[doc = "Use as IRQn input pin"]
8756        pub const _1: Self = Self::new(1);
8757    }
8758    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8759    pub struct Asel_SPEC;
8760    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
8761    impl Asel {
8762        #[doc = "Do not use as analog pin"]
8763        pub const _0: Self = Self::new(0);
8764
8765        #[doc = "Use as analog pin"]
8766        pub const _1: Self = Self::new(1);
8767    }
8768    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8769    pub struct Pmr_SPEC;
8770    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
8771    impl Pmr {
8772        #[doc = "Use as general I/O pin"]
8773        pub const _0: Self = Self::new(0);
8774
8775        #[doc = "Use as I/O port for peripheral functions"]
8776        pub const _1: Self = Self::new(1);
8777    }
8778}
8779#[doc(hidden)]
8780#[derive(Copy, Clone, Eq, PartialEq)]
8781pub struct P20PfsHa_SPEC;
8782impl crate::sealed::RegSpec for P20PfsHa_SPEC {
8783    type DataType = u16;
8784}
8785
8786#[doc = "Port 20%s Pin Function Select Register"]
8787pub type P20PfsHa = crate::RegValueT<P20PfsHa_SPEC>;
8788
8789impl P20PfsHa {
8790    #[doc = "Port Output Data"]
8791    #[inline(always)]
8792    pub fn podr(
8793        self,
8794    ) -> crate::common::RegisterField<
8795        0,
8796        0x1,
8797        1,
8798        0,
8799        p20pfs_ha::Podr,
8800        p20pfs_ha::Podr,
8801        P20PfsHa_SPEC,
8802        crate::common::RW,
8803    > {
8804        crate::common::RegisterField::<
8805            0,
8806            0x1,
8807            1,
8808            0,
8809            p20pfs_ha::Podr,
8810            p20pfs_ha::Podr,
8811            P20PfsHa_SPEC,
8812            crate::common::RW,
8813        >::from_register(self, 0)
8814    }
8815
8816    #[doc = "Port State"]
8817    #[inline(always)]
8818    pub fn pidr(
8819        self,
8820    ) -> crate::common::RegisterField<
8821        1,
8822        0x1,
8823        1,
8824        0,
8825        p20pfs_ha::Pidr,
8826        p20pfs_ha::Pidr,
8827        P20PfsHa_SPEC,
8828        crate::common::R,
8829    > {
8830        crate::common::RegisterField::<
8831            1,
8832            0x1,
8833            1,
8834            0,
8835            p20pfs_ha::Pidr,
8836            p20pfs_ha::Pidr,
8837            P20PfsHa_SPEC,
8838            crate::common::R,
8839        >::from_register(self, 0)
8840    }
8841
8842    #[doc = "Port Direction"]
8843    #[inline(always)]
8844    pub fn pdr(
8845        self,
8846    ) -> crate::common::RegisterField<
8847        2,
8848        0x1,
8849        1,
8850        0,
8851        p20pfs_ha::Pdr,
8852        p20pfs_ha::Pdr,
8853        P20PfsHa_SPEC,
8854        crate::common::RW,
8855    > {
8856        crate::common::RegisterField::<
8857            2,
8858            0x1,
8859            1,
8860            0,
8861            p20pfs_ha::Pdr,
8862            p20pfs_ha::Pdr,
8863            P20PfsHa_SPEC,
8864            crate::common::RW,
8865        >::from_register(self, 0)
8866    }
8867
8868    #[doc = "Pull-up Control"]
8869    #[inline(always)]
8870    pub fn pcr(
8871        self,
8872    ) -> crate::common::RegisterField<
8873        4,
8874        0x1,
8875        1,
8876        0,
8877        p20pfs_ha::Pcr,
8878        p20pfs_ha::Pcr,
8879        P20PfsHa_SPEC,
8880        crate::common::RW,
8881    > {
8882        crate::common::RegisterField::<
8883            4,
8884            0x1,
8885            1,
8886            0,
8887            p20pfs_ha::Pcr,
8888            p20pfs_ha::Pcr,
8889            P20PfsHa_SPEC,
8890            crate::common::RW,
8891        >::from_register(self, 0)
8892    }
8893
8894    #[doc = "N-Channel Open-Drain Control"]
8895    #[inline(always)]
8896    pub fn ncodr(
8897        self,
8898    ) -> crate::common::RegisterField<
8899        6,
8900        0x1,
8901        1,
8902        0,
8903        p20pfs_ha::Ncodr,
8904        p20pfs_ha::Ncodr,
8905        P20PfsHa_SPEC,
8906        crate::common::RW,
8907    > {
8908        crate::common::RegisterField::<
8909            6,
8910            0x1,
8911            1,
8912            0,
8913            p20pfs_ha::Ncodr,
8914            p20pfs_ha::Ncodr,
8915            P20PfsHa_SPEC,
8916            crate::common::RW,
8917        >::from_register(self, 0)
8918    }
8919
8920    #[doc = "Event on Falling/Event on Rising"]
8921    #[inline(always)]
8922    pub fn eofr(
8923        self,
8924    ) -> crate::common::RegisterField<
8925        12,
8926        0x3,
8927        1,
8928        0,
8929        p20pfs_ha::Eofr,
8930        p20pfs_ha::Eofr,
8931        P20PfsHa_SPEC,
8932        crate::common::RW,
8933    > {
8934        crate::common::RegisterField::<
8935            12,
8936            0x3,
8937            1,
8938            0,
8939            p20pfs_ha::Eofr,
8940            p20pfs_ha::Eofr,
8941            P20PfsHa_SPEC,
8942            crate::common::RW,
8943        >::from_register(self, 0)
8944    }
8945
8946    #[doc = "IRQ Input Enable"]
8947    #[inline(always)]
8948    pub fn isel(
8949        self,
8950    ) -> crate::common::RegisterField<
8951        14,
8952        0x1,
8953        1,
8954        0,
8955        p20pfs_ha::Isel,
8956        p20pfs_ha::Isel,
8957        P20PfsHa_SPEC,
8958        crate::common::RW,
8959    > {
8960        crate::common::RegisterField::<
8961            14,
8962            0x1,
8963            1,
8964            0,
8965            p20pfs_ha::Isel,
8966            p20pfs_ha::Isel,
8967            P20PfsHa_SPEC,
8968            crate::common::RW,
8969        >::from_register(self, 0)
8970    }
8971
8972    #[doc = "Analog Input Enable"]
8973    #[inline(always)]
8974    pub fn asel(
8975        self,
8976    ) -> crate::common::RegisterField<
8977        15,
8978        0x1,
8979        1,
8980        0,
8981        p20pfs_ha::Asel,
8982        p20pfs_ha::Asel,
8983        P20PfsHa_SPEC,
8984        crate::common::RW,
8985    > {
8986        crate::common::RegisterField::<
8987            15,
8988            0x1,
8989            1,
8990            0,
8991            p20pfs_ha::Asel,
8992            p20pfs_ha::Asel,
8993            P20PfsHa_SPEC,
8994            crate::common::RW,
8995        >::from_register(self, 0)
8996    }
8997}
8998impl ::core::default::Default for P20PfsHa {
8999    #[inline(always)]
9000    fn default() -> P20PfsHa {
9001        <crate::RegValueT<P20PfsHa_SPEC> as RegisterValue<_>>::new(0)
9002    }
9003}
9004pub mod p20pfs_ha {
9005
9006    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9007    pub struct Podr_SPEC;
9008    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
9009    impl Podr {
9010        #[doc = "Output low"]
9011        pub const _0: Self = Self::new(0);
9012
9013        #[doc = "Output high"]
9014        pub const _1: Self = Self::new(1);
9015    }
9016    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9017    pub struct Pidr_SPEC;
9018    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
9019    impl Pidr {
9020        #[doc = "Low level"]
9021        pub const _0: Self = Self::new(0);
9022
9023        #[doc = "High level"]
9024        pub const _1: Self = Self::new(1);
9025    }
9026    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9027    pub struct Pdr_SPEC;
9028    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
9029    impl Pdr {
9030        #[doc = "Input (functions as an input pin)"]
9031        pub const _0: Self = Self::new(0);
9032
9033        #[doc = "Output (functions as an output pin)"]
9034        pub const _1: Self = Self::new(1);
9035    }
9036    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9037    pub struct Pcr_SPEC;
9038    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
9039    impl Pcr {
9040        #[doc = "Disable input pull-up"]
9041        pub const _0: Self = Self::new(0);
9042
9043        #[doc = "Enable input pull-up"]
9044        pub const _1: Self = Self::new(1);
9045    }
9046    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9047    pub struct Ncodr_SPEC;
9048    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
9049    impl Ncodr {
9050        #[doc = "Output CMOS"]
9051        pub const _0: Self = Self::new(0);
9052
9053        #[doc = "Output NMOS open-drain"]
9054        pub const _1: Self = Self::new(1);
9055    }
9056    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9057    pub struct Eofr_SPEC;
9058    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
9059    impl Eofr {
9060        #[doc = "Don\'t care"]
9061        pub const _00: Self = Self::new(0);
9062
9063        #[doc = "Detect rising edge"]
9064        pub const _01: Self = Self::new(1);
9065
9066        #[doc = "Detect falling edge"]
9067        pub const _10: Self = Self::new(2);
9068
9069        #[doc = "Detect both edges"]
9070        pub const _11: Self = Self::new(3);
9071    }
9072    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9073    pub struct Isel_SPEC;
9074    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
9075    impl Isel {
9076        #[doc = "Do not use as IRQn input pin"]
9077        pub const _0: Self = Self::new(0);
9078
9079        #[doc = "Use as IRQn input pin"]
9080        pub const _1: Self = Self::new(1);
9081    }
9082    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9083    pub struct Asel_SPEC;
9084    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
9085    impl Asel {
9086        #[doc = "Do not use as analog pin"]
9087        pub const _0: Self = Self::new(0);
9088
9089        #[doc = "Use as analog pin"]
9090        pub const _1: Self = Self::new(1);
9091    }
9092}
9093#[doc(hidden)]
9094#[derive(Copy, Clone, Eq, PartialEq)]
9095pub struct P20PfsBy_SPEC;
9096impl crate::sealed::RegSpec for P20PfsBy_SPEC {
9097    type DataType = u8;
9098}
9099
9100#[doc = "Port 20%s Pin Function Select Register"]
9101pub type P20PfsBy = crate::RegValueT<P20PfsBy_SPEC>;
9102
9103impl P20PfsBy {
9104    #[doc = "Port Output Data"]
9105    #[inline(always)]
9106    pub fn podr(
9107        self,
9108    ) -> crate::common::RegisterField<
9109        0,
9110        0x1,
9111        1,
9112        0,
9113        p20pfs_by::Podr,
9114        p20pfs_by::Podr,
9115        P20PfsBy_SPEC,
9116        crate::common::RW,
9117    > {
9118        crate::common::RegisterField::<
9119            0,
9120            0x1,
9121            1,
9122            0,
9123            p20pfs_by::Podr,
9124            p20pfs_by::Podr,
9125            P20PfsBy_SPEC,
9126            crate::common::RW,
9127        >::from_register(self, 0)
9128    }
9129
9130    #[doc = "Port State"]
9131    #[inline(always)]
9132    pub fn pidr(
9133        self,
9134    ) -> crate::common::RegisterField<
9135        1,
9136        0x1,
9137        1,
9138        0,
9139        p20pfs_by::Pidr,
9140        p20pfs_by::Pidr,
9141        P20PfsBy_SPEC,
9142        crate::common::R,
9143    > {
9144        crate::common::RegisterField::<
9145            1,
9146            0x1,
9147            1,
9148            0,
9149            p20pfs_by::Pidr,
9150            p20pfs_by::Pidr,
9151            P20PfsBy_SPEC,
9152            crate::common::R,
9153        >::from_register(self, 0)
9154    }
9155
9156    #[doc = "Port Direction"]
9157    #[inline(always)]
9158    pub fn pdr(
9159        self,
9160    ) -> crate::common::RegisterField<
9161        2,
9162        0x1,
9163        1,
9164        0,
9165        p20pfs_by::Pdr,
9166        p20pfs_by::Pdr,
9167        P20PfsBy_SPEC,
9168        crate::common::RW,
9169    > {
9170        crate::common::RegisterField::<
9171            2,
9172            0x1,
9173            1,
9174            0,
9175            p20pfs_by::Pdr,
9176            p20pfs_by::Pdr,
9177            P20PfsBy_SPEC,
9178            crate::common::RW,
9179        >::from_register(self, 0)
9180    }
9181
9182    #[doc = "Pull-up Control"]
9183    #[inline(always)]
9184    pub fn pcr(
9185        self,
9186    ) -> crate::common::RegisterField<
9187        4,
9188        0x1,
9189        1,
9190        0,
9191        p20pfs_by::Pcr,
9192        p20pfs_by::Pcr,
9193        P20PfsBy_SPEC,
9194        crate::common::RW,
9195    > {
9196        crate::common::RegisterField::<
9197            4,
9198            0x1,
9199            1,
9200            0,
9201            p20pfs_by::Pcr,
9202            p20pfs_by::Pcr,
9203            P20PfsBy_SPEC,
9204            crate::common::RW,
9205        >::from_register(self, 0)
9206    }
9207
9208    #[doc = "N-Channel Open-Drain Control"]
9209    #[inline(always)]
9210    pub fn ncodr(
9211        self,
9212    ) -> crate::common::RegisterField<
9213        6,
9214        0x1,
9215        1,
9216        0,
9217        p20pfs_by::Ncodr,
9218        p20pfs_by::Ncodr,
9219        P20PfsBy_SPEC,
9220        crate::common::RW,
9221    > {
9222        crate::common::RegisterField::<
9223            6,
9224            0x1,
9225            1,
9226            0,
9227            p20pfs_by::Ncodr,
9228            p20pfs_by::Ncodr,
9229            P20PfsBy_SPEC,
9230            crate::common::RW,
9231        >::from_register(self, 0)
9232    }
9233}
9234impl ::core::default::Default for P20PfsBy {
9235    #[inline(always)]
9236    fn default() -> P20PfsBy {
9237        <crate::RegValueT<P20PfsBy_SPEC> as RegisterValue<_>>::new(0)
9238    }
9239}
9240pub mod p20pfs_by {
9241
9242    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9243    pub struct Podr_SPEC;
9244    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
9245    impl Podr {
9246        #[doc = "Output low"]
9247        pub const _0: Self = Self::new(0);
9248
9249        #[doc = "Output high"]
9250        pub const _1: Self = Self::new(1);
9251    }
9252    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9253    pub struct Pidr_SPEC;
9254    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
9255    impl Pidr {
9256        #[doc = "Low level"]
9257        pub const _0: Self = Self::new(0);
9258
9259        #[doc = "High level"]
9260        pub const _1: Self = Self::new(1);
9261    }
9262    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9263    pub struct Pdr_SPEC;
9264    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
9265    impl Pdr {
9266        #[doc = "Input (functions as an input pin)"]
9267        pub const _0: Self = Self::new(0);
9268
9269        #[doc = "Output (functions as an output pin)"]
9270        pub const _1: Self = Self::new(1);
9271    }
9272    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9273    pub struct Pcr_SPEC;
9274    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
9275    impl Pcr {
9276        #[doc = "Disable input pull-up"]
9277        pub const _0: Self = Self::new(0);
9278
9279        #[doc = "Enable input pull-up"]
9280        pub const _1: Self = Self::new(1);
9281    }
9282    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9283    pub struct Ncodr_SPEC;
9284    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
9285    impl Ncodr {
9286        #[doc = "Output CMOS"]
9287        pub const _0: Self = Self::new(0);
9288
9289        #[doc = "Output NMOS open-drain"]
9290        pub const _1: Self = Self::new(1);
9291    }
9292}
9293#[doc(hidden)]
9294#[derive(Copy, Clone, Eq, PartialEq)]
9295pub struct P2Pfs_SPEC;
9296impl crate::sealed::RegSpec for P2Pfs_SPEC {
9297    type DataType = u32;
9298}
9299
9300#[doc = "Port 2%s Pin Function Select Register"]
9301pub type P2Pfs = crate::RegValueT<P2Pfs_SPEC>;
9302
9303impl P2Pfs {
9304    #[doc = "Port Output Data"]
9305    #[inline(always)]
9306    pub fn podr(
9307        self,
9308    ) -> crate::common::RegisterField<
9309        0,
9310        0x1,
9311        1,
9312        0,
9313        p2pfs::Podr,
9314        p2pfs::Podr,
9315        P2Pfs_SPEC,
9316        crate::common::RW,
9317    > {
9318        crate::common::RegisterField::<
9319            0,
9320            0x1,
9321            1,
9322            0,
9323            p2pfs::Podr,
9324            p2pfs::Podr,
9325            P2Pfs_SPEC,
9326            crate::common::RW,
9327        >::from_register(self, 0)
9328    }
9329
9330    #[doc = "Port State"]
9331    #[inline(always)]
9332    pub fn pidr(
9333        self,
9334    ) -> crate::common::RegisterField<
9335        1,
9336        0x1,
9337        1,
9338        0,
9339        p2pfs::Pidr,
9340        p2pfs::Pidr,
9341        P2Pfs_SPEC,
9342        crate::common::R,
9343    > {
9344        crate::common::RegisterField::<
9345            1,
9346            0x1,
9347            1,
9348            0,
9349            p2pfs::Pidr,
9350            p2pfs::Pidr,
9351            P2Pfs_SPEC,
9352            crate::common::R,
9353        >::from_register(self, 0)
9354    }
9355
9356    #[doc = "Port Direction"]
9357    #[inline(always)]
9358    pub fn pdr(
9359        self,
9360    ) -> crate::common::RegisterField<
9361        2,
9362        0x1,
9363        1,
9364        0,
9365        p2pfs::Pdr,
9366        p2pfs::Pdr,
9367        P2Pfs_SPEC,
9368        crate::common::RW,
9369    > {
9370        crate::common::RegisterField::<
9371            2,
9372            0x1,
9373            1,
9374            0,
9375            p2pfs::Pdr,
9376            p2pfs::Pdr,
9377            P2Pfs_SPEC,
9378            crate::common::RW,
9379        >::from_register(self, 0)
9380    }
9381
9382    #[doc = "Pull-up Control"]
9383    #[inline(always)]
9384    pub fn pcr(
9385        self,
9386    ) -> crate::common::RegisterField<
9387        4,
9388        0x1,
9389        1,
9390        0,
9391        p2pfs::Pcr,
9392        p2pfs::Pcr,
9393        P2Pfs_SPEC,
9394        crate::common::RW,
9395    > {
9396        crate::common::RegisterField::<
9397            4,
9398            0x1,
9399            1,
9400            0,
9401            p2pfs::Pcr,
9402            p2pfs::Pcr,
9403            P2Pfs_SPEC,
9404            crate::common::RW,
9405        >::from_register(self, 0)
9406    }
9407
9408    #[doc = "N-Channel Open-Drain Control"]
9409    #[inline(always)]
9410    pub fn ncodr(
9411        self,
9412    ) -> crate::common::RegisterField<
9413        6,
9414        0x1,
9415        1,
9416        0,
9417        p2pfs::Ncodr,
9418        p2pfs::Ncodr,
9419        P2Pfs_SPEC,
9420        crate::common::RW,
9421    > {
9422        crate::common::RegisterField::<
9423            6,
9424            0x1,
9425            1,
9426            0,
9427            p2pfs::Ncodr,
9428            p2pfs::Ncodr,
9429            P2Pfs_SPEC,
9430            crate::common::RW,
9431        >::from_register(self, 0)
9432    }
9433
9434    #[doc = "Event on Falling/Event on Rising"]
9435    #[inline(always)]
9436    pub fn eofr(
9437        self,
9438    ) -> crate::common::RegisterField<
9439        12,
9440        0x3,
9441        1,
9442        0,
9443        p2pfs::Eofr,
9444        p2pfs::Eofr,
9445        P2Pfs_SPEC,
9446        crate::common::RW,
9447    > {
9448        crate::common::RegisterField::<
9449            12,
9450            0x3,
9451            1,
9452            0,
9453            p2pfs::Eofr,
9454            p2pfs::Eofr,
9455            P2Pfs_SPEC,
9456            crate::common::RW,
9457        >::from_register(self, 0)
9458    }
9459
9460    #[doc = "IRQ Input Enable"]
9461    #[inline(always)]
9462    pub fn isel(
9463        self,
9464    ) -> crate::common::RegisterField<
9465        14,
9466        0x1,
9467        1,
9468        0,
9469        p2pfs::Isel,
9470        p2pfs::Isel,
9471        P2Pfs_SPEC,
9472        crate::common::RW,
9473    > {
9474        crate::common::RegisterField::<
9475            14,
9476            0x1,
9477            1,
9478            0,
9479            p2pfs::Isel,
9480            p2pfs::Isel,
9481            P2Pfs_SPEC,
9482            crate::common::RW,
9483        >::from_register(self, 0)
9484    }
9485
9486    #[doc = "Analog Input Enable"]
9487    #[inline(always)]
9488    pub fn asel(
9489        self,
9490    ) -> crate::common::RegisterField<
9491        15,
9492        0x1,
9493        1,
9494        0,
9495        p2pfs::Asel,
9496        p2pfs::Asel,
9497        P2Pfs_SPEC,
9498        crate::common::RW,
9499    > {
9500        crate::common::RegisterField::<
9501            15,
9502            0x1,
9503            1,
9504            0,
9505            p2pfs::Asel,
9506            p2pfs::Asel,
9507            P2Pfs_SPEC,
9508            crate::common::RW,
9509        >::from_register(self, 0)
9510    }
9511
9512    #[doc = "Port Mode Control"]
9513    #[inline(always)]
9514    pub fn pmr(
9515        self,
9516    ) -> crate::common::RegisterField<
9517        16,
9518        0x1,
9519        1,
9520        0,
9521        p2pfs::Pmr,
9522        p2pfs::Pmr,
9523        P2Pfs_SPEC,
9524        crate::common::RW,
9525    > {
9526        crate::common::RegisterField::<
9527            16,
9528            0x1,
9529            1,
9530            0,
9531            p2pfs::Pmr,
9532            p2pfs::Pmr,
9533            P2Pfs_SPEC,
9534            crate::common::RW,
9535        >::from_register(self, 0)
9536    }
9537
9538    #[doc = "Peripheral Select"]
9539    #[inline(always)]
9540    pub fn psel(
9541        self,
9542    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P2Pfs_SPEC, crate::common::RW> {
9543        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P2Pfs_SPEC,crate::common::RW>::from_register(self,0)
9544    }
9545}
9546impl ::core::default::Default for P2Pfs {
9547    #[inline(always)]
9548    fn default() -> P2Pfs {
9549        <crate::RegValueT<P2Pfs_SPEC> as RegisterValue<_>>::new(0)
9550    }
9551}
9552pub mod p2pfs {
9553
9554    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9555    pub struct Podr_SPEC;
9556    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
9557    impl Podr {
9558        #[doc = "Output low"]
9559        pub const _0: Self = Self::new(0);
9560
9561        #[doc = "Output high"]
9562        pub const _1: Self = Self::new(1);
9563    }
9564    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9565    pub struct Pidr_SPEC;
9566    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
9567    impl Pidr {
9568        #[doc = "Low level"]
9569        pub const _0: Self = Self::new(0);
9570
9571        #[doc = "High level"]
9572        pub const _1: Self = Self::new(1);
9573    }
9574    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9575    pub struct Pdr_SPEC;
9576    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
9577    impl Pdr {
9578        #[doc = "Input (functions as an input pin)"]
9579        pub const _0: Self = Self::new(0);
9580
9581        #[doc = "Output (functions as an output pin)"]
9582        pub const _1: Self = Self::new(1);
9583    }
9584    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9585    pub struct Pcr_SPEC;
9586    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
9587    impl Pcr {
9588        #[doc = "Disable input pull-up"]
9589        pub const _0: Self = Self::new(0);
9590
9591        #[doc = "Enable input pull-up"]
9592        pub const _1: Self = Self::new(1);
9593    }
9594    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9595    pub struct Ncodr_SPEC;
9596    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
9597    impl Ncodr {
9598        #[doc = "Output CMOS"]
9599        pub const _0: Self = Self::new(0);
9600
9601        #[doc = "Output NMOS open-drain"]
9602        pub const _1: Self = Self::new(1);
9603    }
9604    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9605    pub struct Eofr_SPEC;
9606    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
9607    impl Eofr {
9608        #[doc = "Don\'t care"]
9609        pub const _00: Self = Self::new(0);
9610
9611        #[doc = "Detect rising edge"]
9612        pub const _01: Self = Self::new(1);
9613
9614        #[doc = "Detect falling edge"]
9615        pub const _10: Self = Self::new(2);
9616
9617        #[doc = "Detect both edges"]
9618        pub const _11: Self = Self::new(3);
9619    }
9620    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9621    pub struct Isel_SPEC;
9622    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
9623    impl Isel {
9624        #[doc = "Do not use as IRQn input pin"]
9625        pub const _0: Self = Self::new(0);
9626
9627        #[doc = "Use as IRQn input pin"]
9628        pub const _1: Self = Self::new(1);
9629    }
9630    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9631    pub struct Asel_SPEC;
9632    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
9633    impl Asel {
9634        #[doc = "Do not use as analog pin"]
9635        pub const _0: Self = Self::new(0);
9636
9637        #[doc = "Use as analog pin"]
9638        pub const _1: Self = Self::new(1);
9639    }
9640    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9641    pub struct Pmr_SPEC;
9642    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
9643    impl Pmr {
9644        #[doc = "Use as general I/O pin"]
9645        pub const _0: Self = Self::new(0);
9646
9647        #[doc = "Use as I/O port for peripheral functions"]
9648        pub const _1: Self = Self::new(1);
9649    }
9650}
9651#[doc(hidden)]
9652#[derive(Copy, Clone, Eq, PartialEq)]
9653pub struct P2PfsHa_SPEC;
9654impl crate::sealed::RegSpec for P2PfsHa_SPEC {
9655    type DataType = u16;
9656}
9657
9658#[doc = "Port 2%s Pin Function Select Register"]
9659pub type P2PfsHa = crate::RegValueT<P2PfsHa_SPEC>;
9660
9661impl P2PfsHa {
9662    #[doc = "Port Output Data"]
9663    #[inline(always)]
9664    pub fn podr(
9665        self,
9666    ) -> crate::common::RegisterField<
9667        0,
9668        0x1,
9669        1,
9670        0,
9671        p2pfs_ha::Podr,
9672        p2pfs_ha::Podr,
9673        P2PfsHa_SPEC,
9674        crate::common::RW,
9675    > {
9676        crate::common::RegisterField::<
9677            0,
9678            0x1,
9679            1,
9680            0,
9681            p2pfs_ha::Podr,
9682            p2pfs_ha::Podr,
9683            P2PfsHa_SPEC,
9684            crate::common::RW,
9685        >::from_register(self, 0)
9686    }
9687
9688    #[doc = "Port State"]
9689    #[inline(always)]
9690    pub fn pidr(
9691        self,
9692    ) -> crate::common::RegisterField<
9693        1,
9694        0x1,
9695        1,
9696        0,
9697        p2pfs_ha::Pidr,
9698        p2pfs_ha::Pidr,
9699        P2PfsHa_SPEC,
9700        crate::common::R,
9701    > {
9702        crate::common::RegisterField::<
9703            1,
9704            0x1,
9705            1,
9706            0,
9707            p2pfs_ha::Pidr,
9708            p2pfs_ha::Pidr,
9709            P2PfsHa_SPEC,
9710            crate::common::R,
9711        >::from_register(self, 0)
9712    }
9713
9714    #[doc = "Port Direction"]
9715    #[inline(always)]
9716    pub fn pdr(
9717        self,
9718    ) -> crate::common::RegisterField<
9719        2,
9720        0x1,
9721        1,
9722        0,
9723        p2pfs_ha::Pdr,
9724        p2pfs_ha::Pdr,
9725        P2PfsHa_SPEC,
9726        crate::common::RW,
9727    > {
9728        crate::common::RegisterField::<
9729            2,
9730            0x1,
9731            1,
9732            0,
9733            p2pfs_ha::Pdr,
9734            p2pfs_ha::Pdr,
9735            P2PfsHa_SPEC,
9736            crate::common::RW,
9737        >::from_register(self, 0)
9738    }
9739
9740    #[doc = "Pull-up Control"]
9741    #[inline(always)]
9742    pub fn pcr(
9743        self,
9744    ) -> crate::common::RegisterField<
9745        4,
9746        0x1,
9747        1,
9748        0,
9749        p2pfs_ha::Pcr,
9750        p2pfs_ha::Pcr,
9751        P2PfsHa_SPEC,
9752        crate::common::RW,
9753    > {
9754        crate::common::RegisterField::<
9755            4,
9756            0x1,
9757            1,
9758            0,
9759            p2pfs_ha::Pcr,
9760            p2pfs_ha::Pcr,
9761            P2PfsHa_SPEC,
9762            crate::common::RW,
9763        >::from_register(self, 0)
9764    }
9765
9766    #[doc = "N-Channel Open-Drain Control"]
9767    #[inline(always)]
9768    pub fn ncodr(
9769        self,
9770    ) -> crate::common::RegisterField<
9771        6,
9772        0x1,
9773        1,
9774        0,
9775        p2pfs_ha::Ncodr,
9776        p2pfs_ha::Ncodr,
9777        P2PfsHa_SPEC,
9778        crate::common::RW,
9779    > {
9780        crate::common::RegisterField::<
9781            6,
9782            0x1,
9783            1,
9784            0,
9785            p2pfs_ha::Ncodr,
9786            p2pfs_ha::Ncodr,
9787            P2PfsHa_SPEC,
9788            crate::common::RW,
9789        >::from_register(self, 0)
9790    }
9791
9792    #[doc = "Event on Falling/Event on Rising"]
9793    #[inline(always)]
9794    pub fn eofr(
9795        self,
9796    ) -> crate::common::RegisterField<
9797        12,
9798        0x3,
9799        1,
9800        0,
9801        p2pfs_ha::Eofr,
9802        p2pfs_ha::Eofr,
9803        P2PfsHa_SPEC,
9804        crate::common::RW,
9805    > {
9806        crate::common::RegisterField::<
9807            12,
9808            0x3,
9809            1,
9810            0,
9811            p2pfs_ha::Eofr,
9812            p2pfs_ha::Eofr,
9813            P2PfsHa_SPEC,
9814            crate::common::RW,
9815        >::from_register(self, 0)
9816    }
9817
9818    #[doc = "IRQ Input Enable"]
9819    #[inline(always)]
9820    pub fn isel(
9821        self,
9822    ) -> crate::common::RegisterField<
9823        14,
9824        0x1,
9825        1,
9826        0,
9827        p2pfs_ha::Isel,
9828        p2pfs_ha::Isel,
9829        P2PfsHa_SPEC,
9830        crate::common::RW,
9831    > {
9832        crate::common::RegisterField::<
9833            14,
9834            0x1,
9835            1,
9836            0,
9837            p2pfs_ha::Isel,
9838            p2pfs_ha::Isel,
9839            P2PfsHa_SPEC,
9840            crate::common::RW,
9841        >::from_register(self, 0)
9842    }
9843
9844    #[doc = "Analog Input Enable"]
9845    #[inline(always)]
9846    pub fn asel(
9847        self,
9848    ) -> crate::common::RegisterField<
9849        15,
9850        0x1,
9851        1,
9852        0,
9853        p2pfs_ha::Asel,
9854        p2pfs_ha::Asel,
9855        P2PfsHa_SPEC,
9856        crate::common::RW,
9857    > {
9858        crate::common::RegisterField::<
9859            15,
9860            0x1,
9861            1,
9862            0,
9863            p2pfs_ha::Asel,
9864            p2pfs_ha::Asel,
9865            P2PfsHa_SPEC,
9866            crate::common::RW,
9867        >::from_register(self, 0)
9868    }
9869}
9870impl ::core::default::Default for P2PfsHa {
9871    #[inline(always)]
9872    fn default() -> P2PfsHa {
9873        <crate::RegValueT<P2PfsHa_SPEC> as RegisterValue<_>>::new(0)
9874    }
9875}
9876pub mod p2pfs_ha {
9877
9878    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9879    pub struct Podr_SPEC;
9880    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
9881    impl Podr {
9882        #[doc = "Output low"]
9883        pub const _0: Self = Self::new(0);
9884
9885        #[doc = "Output high"]
9886        pub const _1: Self = Self::new(1);
9887    }
9888    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9889    pub struct Pidr_SPEC;
9890    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
9891    impl Pidr {
9892        #[doc = "Low level"]
9893        pub const _0: Self = Self::new(0);
9894
9895        #[doc = "High level"]
9896        pub const _1: Self = Self::new(1);
9897    }
9898    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9899    pub struct Pdr_SPEC;
9900    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
9901    impl Pdr {
9902        #[doc = "Input (functions as an input pin)"]
9903        pub const _0: Self = Self::new(0);
9904
9905        #[doc = "Output (functions as an output pin)"]
9906        pub const _1: Self = Self::new(1);
9907    }
9908    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9909    pub struct Pcr_SPEC;
9910    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
9911    impl Pcr {
9912        #[doc = "Disable input pull-up"]
9913        pub const _0: Self = Self::new(0);
9914
9915        #[doc = "Enable input pull-up"]
9916        pub const _1: Self = Self::new(1);
9917    }
9918    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9919    pub struct Ncodr_SPEC;
9920    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
9921    impl Ncodr {
9922        #[doc = "Output CMOS"]
9923        pub const _0: Self = Self::new(0);
9924
9925        #[doc = "Output NMOS open-drain"]
9926        pub const _1: Self = Self::new(1);
9927    }
9928    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9929    pub struct Eofr_SPEC;
9930    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
9931    impl Eofr {
9932        #[doc = "Don\'t care"]
9933        pub const _00: Self = Self::new(0);
9934
9935        #[doc = "Detect rising edge"]
9936        pub const _01: Self = Self::new(1);
9937
9938        #[doc = "Detect falling edge"]
9939        pub const _10: Self = Self::new(2);
9940
9941        #[doc = "Detect both edges"]
9942        pub const _11: Self = Self::new(3);
9943    }
9944    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9945    pub struct Isel_SPEC;
9946    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
9947    impl Isel {
9948        #[doc = "Do not use as IRQn input pin"]
9949        pub const _0: Self = Self::new(0);
9950
9951        #[doc = "Use as IRQn input pin"]
9952        pub const _1: Self = Self::new(1);
9953    }
9954    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9955    pub struct Asel_SPEC;
9956    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
9957    impl Asel {
9958        #[doc = "Do not use as analog pin"]
9959        pub const _0: Self = Self::new(0);
9960
9961        #[doc = "Use as analog pin"]
9962        pub const _1: Self = Self::new(1);
9963    }
9964}
9965#[doc(hidden)]
9966#[derive(Copy, Clone, Eq, PartialEq)]
9967pub struct P2PfsBy_SPEC;
9968impl crate::sealed::RegSpec for P2PfsBy_SPEC {
9969    type DataType = u8;
9970}
9971
9972#[doc = "Port 2%s Pin Function Select Register"]
9973pub type P2PfsBy = crate::RegValueT<P2PfsBy_SPEC>;
9974
9975impl P2PfsBy {
9976    #[doc = "Port Output Data"]
9977    #[inline(always)]
9978    pub fn podr(
9979        self,
9980    ) -> crate::common::RegisterField<
9981        0,
9982        0x1,
9983        1,
9984        0,
9985        p2pfs_by::Podr,
9986        p2pfs_by::Podr,
9987        P2PfsBy_SPEC,
9988        crate::common::RW,
9989    > {
9990        crate::common::RegisterField::<
9991            0,
9992            0x1,
9993            1,
9994            0,
9995            p2pfs_by::Podr,
9996            p2pfs_by::Podr,
9997            P2PfsBy_SPEC,
9998            crate::common::RW,
9999        >::from_register(self, 0)
10000    }
10001
10002    #[doc = "Port State"]
10003    #[inline(always)]
10004    pub fn pidr(
10005        self,
10006    ) -> crate::common::RegisterField<
10007        1,
10008        0x1,
10009        1,
10010        0,
10011        p2pfs_by::Pidr,
10012        p2pfs_by::Pidr,
10013        P2PfsBy_SPEC,
10014        crate::common::R,
10015    > {
10016        crate::common::RegisterField::<
10017            1,
10018            0x1,
10019            1,
10020            0,
10021            p2pfs_by::Pidr,
10022            p2pfs_by::Pidr,
10023            P2PfsBy_SPEC,
10024            crate::common::R,
10025        >::from_register(self, 0)
10026    }
10027
10028    #[doc = "Port Direction"]
10029    #[inline(always)]
10030    pub fn pdr(
10031        self,
10032    ) -> crate::common::RegisterField<
10033        2,
10034        0x1,
10035        1,
10036        0,
10037        p2pfs_by::Pdr,
10038        p2pfs_by::Pdr,
10039        P2PfsBy_SPEC,
10040        crate::common::RW,
10041    > {
10042        crate::common::RegisterField::<
10043            2,
10044            0x1,
10045            1,
10046            0,
10047            p2pfs_by::Pdr,
10048            p2pfs_by::Pdr,
10049            P2PfsBy_SPEC,
10050            crate::common::RW,
10051        >::from_register(self, 0)
10052    }
10053
10054    #[doc = "Pull-up Control"]
10055    #[inline(always)]
10056    pub fn pcr(
10057        self,
10058    ) -> crate::common::RegisterField<
10059        4,
10060        0x1,
10061        1,
10062        0,
10063        p2pfs_by::Pcr,
10064        p2pfs_by::Pcr,
10065        P2PfsBy_SPEC,
10066        crate::common::RW,
10067    > {
10068        crate::common::RegisterField::<
10069            4,
10070            0x1,
10071            1,
10072            0,
10073            p2pfs_by::Pcr,
10074            p2pfs_by::Pcr,
10075            P2PfsBy_SPEC,
10076            crate::common::RW,
10077        >::from_register(self, 0)
10078    }
10079
10080    #[doc = "N-Channel Open-Drain Control"]
10081    #[inline(always)]
10082    pub fn ncodr(
10083        self,
10084    ) -> crate::common::RegisterField<
10085        6,
10086        0x1,
10087        1,
10088        0,
10089        p2pfs_by::Ncodr,
10090        p2pfs_by::Ncodr,
10091        P2PfsBy_SPEC,
10092        crate::common::RW,
10093    > {
10094        crate::common::RegisterField::<
10095            6,
10096            0x1,
10097            1,
10098            0,
10099            p2pfs_by::Ncodr,
10100            p2pfs_by::Ncodr,
10101            P2PfsBy_SPEC,
10102            crate::common::RW,
10103        >::from_register(self, 0)
10104    }
10105}
10106impl ::core::default::Default for P2PfsBy {
10107    #[inline(always)]
10108    fn default() -> P2PfsBy {
10109        <crate::RegValueT<P2PfsBy_SPEC> as RegisterValue<_>>::new(0)
10110    }
10111}
10112pub mod p2pfs_by {
10113
10114    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10115    pub struct Podr_SPEC;
10116    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
10117    impl Podr {
10118        #[doc = "Output low"]
10119        pub const _0: Self = Self::new(0);
10120
10121        #[doc = "Output high"]
10122        pub const _1: Self = Self::new(1);
10123    }
10124    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10125    pub struct Pidr_SPEC;
10126    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
10127    impl Pidr {
10128        #[doc = "Low level"]
10129        pub const _0: Self = Self::new(0);
10130
10131        #[doc = "High level"]
10132        pub const _1: Self = Self::new(1);
10133    }
10134    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10135    pub struct Pdr_SPEC;
10136    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
10137    impl Pdr {
10138        #[doc = "Input (functions as an input pin)"]
10139        pub const _0: Self = Self::new(0);
10140
10141        #[doc = "Output (functions as an output pin)"]
10142        pub const _1: Self = Self::new(1);
10143    }
10144    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10145    pub struct Pcr_SPEC;
10146    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
10147    impl Pcr {
10148        #[doc = "Disable input pull-up"]
10149        pub const _0: Self = Self::new(0);
10150
10151        #[doc = "Enable input pull-up"]
10152        pub const _1: Self = Self::new(1);
10153    }
10154    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10155    pub struct Ncodr_SPEC;
10156    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
10157    impl Ncodr {
10158        #[doc = "Output CMOS"]
10159        pub const _0: Self = Self::new(0);
10160
10161        #[doc = "Output NMOS open-drain"]
10162        pub const _1: Self = Self::new(1);
10163    }
10164}
10165#[doc(hidden)]
10166#[derive(Copy, Clone, Eq, PartialEq)]
10167pub struct P300Pfs_SPEC;
10168impl crate::sealed::RegSpec for P300Pfs_SPEC {
10169    type DataType = u32;
10170}
10171
10172#[doc = "Port 300 Pin Function Select Register"]
10173pub type P300Pfs = crate::RegValueT<P300Pfs_SPEC>;
10174
10175impl P300Pfs {
10176    #[doc = "Port Output Data"]
10177    #[inline(always)]
10178    pub fn podr(
10179        self,
10180    ) -> crate::common::RegisterField<
10181        0,
10182        0x1,
10183        1,
10184        0,
10185        p300pfs::Podr,
10186        p300pfs::Podr,
10187        P300Pfs_SPEC,
10188        crate::common::RW,
10189    > {
10190        crate::common::RegisterField::<
10191            0,
10192            0x1,
10193            1,
10194            0,
10195            p300pfs::Podr,
10196            p300pfs::Podr,
10197            P300Pfs_SPEC,
10198            crate::common::RW,
10199        >::from_register(self, 0)
10200    }
10201
10202    #[doc = "Port State"]
10203    #[inline(always)]
10204    pub fn pidr(
10205        self,
10206    ) -> crate::common::RegisterField<
10207        1,
10208        0x1,
10209        1,
10210        0,
10211        p300pfs::Pidr,
10212        p300pfs::Pidr,
10213        P300Pfs_SPEC,
10214        crate::common::R,
10215    > {
10216        crate::common::RegisterField::<
10217            1,
10218            0x1,
10219            1,
10220            0,
10221            p300pfs::Pidr,
10222            p300pfs::Pidr,
10223            P300Pfs_SPEC,
10224            crate::common::R,
10225        >::from_register(self, 0)
10226    }
10227
10228    #[doc = "Port Direction"]
10229    #[inline(always)]
10230    pub fn pdr(
10231        self,
10232    ) -> crate::common::RegisterField<
10233        2,
10234        0x1,
10235        1,
10236        0,
10237        p300pfs::Pdr,
10238        p300pfs::Pdr,
10239        P300Pfs_SPEC,
10240        crate::common::RW,
10241    > {
10242        crate::common::RegisterField::<
10243            2,
10244            0x1,
10245            1,
10246            0,
10247            p300pfs::Pdr,
10248            p300pfs::Pdr,
10249            P300Pfs_SPEC,
10250            crate::common::RW,
10251        >::from_register(self, 0)
10252    }
10253
10254    #[doc = "Pull-up Control"]
10255    #[inline(always)]
10256    pub fn pcr(
10257        self,
10258    ) -> crate::common::RegisterField<
10259        4,
10260        0x1,
10261        1,
10262        0,
10263        p300pfs::Pcr,
10264        p300pfs::Pcr,
10265        P300Pfs_SPEC,
10266        crate::common::RW,
10267    > {
10268        crate::common::RegisterField::<
10269            4,
10270            0x1,
10271            1,
10272            0,
10273            p300pfs::Pcr,
10274            p300pfs::Pcr,
10275            P300Pfs_SPEC,
10276            crate::common::RW,
10277        >::from_register(self, 0)
10278    }
10279
10280    #[doc = "N-Channel Open-Drain Control"]
10281    #[inline(always)]
10282    pub fn ncodr(
10283        self,
10284    ) -> crate::common::RegisterField<
10285        6,
10286        0x1,
10287        1,
10288        0,
10289        p300pfs::Ncodr,
10290        p300pfs::Ncodr,
10291        P300Pfs_SPEC,
10292        crate::common::RW,
10293    > {
10294        crate::common::RegisterField::<
10295            6,
10296            0x1,
10297            1,
10298            0,
10299            p300pfs::Ncodr,
10300            p300pfs::Ncodr,
10301            P300Pfs_SPEC,
10302            crate::common::RW,
10303        >::from_register(self, 0)
10304    }
10305
10306    #[doc = "IRQ Input Enable"]
10307    #[inline(always)]
10308    pub fn isel(
10309        self,
10310    ) -> crate::common::RegisterField<
10311        14,
10312        0x1,
10313        1,
10314        0,
10315        p300pfs::Isel,
10316        p300pfs::Isel,
10317        P300Pfs_SPEC,
10318        crate::common::RW,
10319    > {
10320        crate::common::RegisterField::<
10321            14,
10322            0x1,
10323            1,
10324            0,
10325            p300pfs::Isel,
10326            p300pfs::Isel,
10327            P300Pfs_SPEC,
10328            crate::common::RW,
10329        >::from_register(self, 0)
10330    }
10331
10332    #[doc = "Analog Input Enable"]
10333    #[inline(always)]
10334    pub fn asel(
10335        self,
10336    ) -> crate::common::RegisterField<
10337        15,
10338        0x1,
10339        1,
10340        0,
10341        p300pfs::Asel,
10342        p300pfs::Asel,
10343        P300Pfs_SPEC,
10344        crate::common::RW,
10345    > {
10346        crate::common::RegisterField::<
10347            15,
10348            0x1,
10349            1,
10350            0,
10351            p300pfs::Asel,
10352            p300pfs::Asel,
10353            P300Pfs_SPEC,
10354            crate::common::RW,
10355        >::from_register(self, 0)
10356    }
10357
10358    #[doc = "Port Mode Control"]
10359    #[inline(always)]
10360    pub fn pmr(
10361        self,
10362    ) -> crate::common::RegisterField<
10363        16,
10364        0x1,
10365        1,
10366        0,
10367        p300pfs::Pmr,
10368        p300pfs::Pmr,
10369        P300Pfs_SPEC,
10370        crate::common::RW,
10371    > {
10372        crate::common::RegisterField::<
10373            16,
10374            0x1,
10375            1,
10376            0,
10377            p300pfs::Pmr,
10378            p300pfs::Pmr,
10379            P300Pfs_SPEC,
10380            crate::common::RW,
10381        >::from_register(self, 0)
10382    }
10383
10384    #[doc = "Peripheral Select"]
10385    #[inline(always)]
10386    pub fn psel(
10387        self,
10388    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P300Pfs_SPEC, crate::common::RW> {
10389        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P300Pfs_SPEC,crate::common::RW>::from_register(self,0)
10390    }
10391}
10392impl ::core::default::Default for P300Pfs {
10393    #[inline(always)]
10394    fn default() -> P300Pfs {
10395        <crate::RegValueT<P300Pfs_SPEC> as RegisterValue<_>>::new(65536)
10396    }
10397}
10398pub mod p300pfs {
10399
10400    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10401    pub struct Podr_SPEC;
10402    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
10403    impl Podr {
10404        #[doc = "Output low"]
10405        pub const _0: Self = Self::new(0);
10406
10407        #[doc = "Output high"]
10408        pub const _1: Self = Self::new(1);
10409    }
10410    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10411    pub struct Pidr_SPEC;
10412    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
10413    impl Pidr {
10414        #[doc = "Low level"]
10415        pub const _0: Self = Self::new(0);
10416
10417        #[doc = "High level"]
10418        pub const _1: Self = Self::new(1);
10419    }
10420    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10421    pub struct Pdr_SPEC;
10422    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
10423    impl Pdr {
10424        #[doc = "Input (functions as an input pin)"]
10425        pub const _0: Self = Self::new(0);
10426
10427        #[doc = "Output (functions as an output pin)"]
10428        pub const _1: Self = Self::new(1);
10429    }
10430    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10431    pub struct Pcr_SPEC;
10432    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
10433    impl Pcr {
10434        #[doc = "Disable input pull-up"]
10435        pub const _0: Self = Self::new(0);
10436
10437        #[doc = "Enable input pull-up"]
10438        pub const _1: Self = Self::new(1);
10439    }
10440    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10441    pub struct Ncodr_SPEC;
10442    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
10443    impl Ncodr {
10444        #[doc = "Output CMOS"]
10445        pub const _0: Self = Self::new(0);
10446
10447        #[doc = "Output NMOS open-drain"]
10448        pub const _1: Self = Self::new(1);
10449    }
10450    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10451    pub struct Isel_SPEC;
10452    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
10453    impl Isel {
10454        #[doc = "Do not use as IRQn input pin"]
10455        pub const _0: Self = Self::new(0);
10456
10457        #[doc = "Use as IRQn input pin"]
10458        pub const _1: Self = Self::new(1);
10459    }
10460    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10461    pub struct Asel_SPEC;
10462    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
10463    impl Asel {
10464        #[doc = "Do not use as analog pin"]
10465        pub const _0: Self = Self::new(0);
10466
10467        #[doc = "Use as analog pin"]
10468        pub const _1: Self = Self::new(1);
10469    }
10470    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10471    pub struct Pmr_SPEC;
10472    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
10473    impl Pmr {
10474        #[doc = "Use as general I/O pin"]
10475        pub const _0: Self = Self::new(0);
10476
10477        #[doc = "Use as I/O port for peripheral functions"]
10478        pub const _1: Self = Self::new(1);
10479    }
10480}
10481#[doc(hidden)]
10482#[derive(Copy, Clone, Eq, PartialEq)]
10483pub struct P300PfsHa_SPEC;
10484impl crate::sealed::RegSpec for P300PfsHa_SPEC {
10485    type DataType = u16;
10486}
10487
10488#[doc = "Port 300 Pin Function Select Register"]
10489pub type P300PfsHa = crate::RegValueT<P300PfsHa_SPEC>;
10490
10491impl P300PfsHa {
10492    #[doc = "Port Output Data"]
10493    #[inline(always)]
10494    pub fn podr(
10495        self,
10496    ) -> crate::common::RegisterField<
10497        0,
10498        0x1,
10499        1,
10500        0,
10501        p300pfs_ha::Podr,
10502        p300pfs_ha::Podr,
10503        P300PfsHa_SPEC,
10504        crate::common::RW,
10505    > {
10506        crate::common::RegisterField::<
10507            0,
10508            0x1,
10509            1,
10510            0,
10511            p300pfs_ha::Podr,
10512            p300pfs_ha::Podr,
10513            P300PfsHa_SPEC,
10514            crate::common::RW,
10515        >::from_register(self, 0)
10516    }
10517
10518    #[doc = "Port State"]
10519    #[inline(always)]
10520    pub fn pidr(
10521        self,
10522    ) -> crate::common::RegisterField<
10523        1,
10524        0x1,
10525        1,
10526        0,
10527        p300pfs_ha::Pidr,
10528        p300pfs_ha::Pidr,
10529        P300PfsHa_SPEC,
10530        crate::common::R,
10531    > {
10532        crate::common::RegisterField::<
10533            1,
10534            0x1,
10535            1,
10536            0,
10537            p300pfs_ha::Pidr,
10538            p300pfs_ha::Pidr,
10539            P300PfsHa_SPEC,
10540            crate::common::R,
10541        >::from_register(self, 0)
10542    }
10543
10544    #[doc = "Port Direction"]
10545    #[inline(always)]
10546    pub fn pdr(
10547        self,
10548    ) -> crate::common::RegisterField<
10549        2,
10550        0x1,
10551        1,
10552        0,
10553        p300pfs_ha::Pdr,
10554        p300pfs_ha::Pdr,
10555        P300PfsHa_SPEC,
10556        crate::common::RW,
10557    > {
10558        crate::common::RegisterField::<
10559            2,
10560            0x1,
10561            1,
10562            0,
10563            p300pfs_ha::Pdr,
10564            p300pfs_ha::Pdr,
10565            P300PfsHa_SPEC,
10566            crate::common::RW,
10567        >::from_register(self, 0)
10568    }
10569
10570    #[doc = "Pull-up Control"]
10571    #[inline(always)]
10572    pub fn pcr(
10573        self,
10574    ) -> crate::common::RegisterField<
10575        4,
10576        0x1,
10577        1,
10578        0,
10579        p300pfs_ha::Pcr,
10580        p300pfs_ha::Pcr,
10581        P300PfsHa_SPEC,
10582        crate::common::RW,
10583    > {
10584        crate::common::RegisterField::<
10585            4,
10586            0x1,
10587            1,
10588            0,
10589            p300pfs_ha::Pcr,
10590            p300pfs_ha::Pcr,
10591            P300PfsHa_SPEC,
10592            crate::common::RW,
10593        >::from_register(self, 0)
10594    }
10595
10596    #[doc = "N-Channel Open-Drain Control"]
10597    #[inline(always)]
10598    pub fn ncodr(
10599        self,
10600    ) -> crate::common::RegisterField<
10601        6,
10602        0x1,
10603        1,
10604        0,
10605        p300pfs_ha::Ncodr,
10606        p300pfs_ha::Ncodr,
10607        P300PfsHa_SPEC,
10608        crate::common::RW,
10609    > {
10610        crate::common::RegisterField::<
10611            6,
10612            0x1,
10613            1,
10614            0,
10615            p300pfs_ha::Ncodr,
10616            p300pfs_ha::Ncodr,
10617            P300PfsHa_SPEC,
10618            crate::common::RW,
10619        >::from_register(self, 0)
10620    }
10621
10622    #[doc = "IRQ Input Enable"]
10623    #[inline(always)]
10624    pub fn isel(
10625        self,
10626    ) -> crate::common::RegisterField<
10627        14,
10628        0x1,
10629        1,
10630        0,
10631        p300pfs_ha::Isel,
10632        p300pfs_ha::Isel,
10633        P300PfsHa_SPEC,
10634        crate::common::RW,
10635    > {
10636        crate::common::RegisterField::<
10637            14,
10638            0x1,
10639            1,
10640            0,
10641            p300pfs_ha::Isel,
10642            p300pfs_ha::Isel,
10643            P300PfsHa_SPEC,
10644            crate::common::RW,
10645        >::from_register(self, 0)
10646    }
10647
10648    #[doc = "Analog Input Enable"]
10649    #[inline(always)]
10650    pub fn asel(
10651        self,
10652    ) -> crate::common::RegisterField<
10653        15,
10654        0x1,
10655        1,
10656        0,
10657        p300pfs_ha::Asel,
10658        p300pfs_ha::Asel,
10659        P300PfsHa_SPEC,
10660        crate::common::RW,
10661    > {
10662        crate::common::RegisterField::<
10663            15,
10664            0x1,
10665            1,
10666            0,
10667            p300pfs_ha::Asel,
10668            p300pfs_ha::Asel,
10669            P300PfsHa_SPEC,
10670            crate::common::RW,
10671        >::from_register(self, 0)
10672    }
10673}
10674impl ::core::default::Default for P300PfsHa {
10675    #[inline(always)]
10676    fn default() -> P300PfsHa {
10677        <crate::RegValueT<P300PfsHa_SPEC> as RegisterValue<_>>::new(0)
10678    }
10679}
10680pub mod p300pfs_ha {
10681
10682    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10683    pub struct Podr_SPEC;
10684    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
10685    impl Podr {
10686        #[doc = "Output low"]
10687        pub const _0: Self = Self::new(0);
10688
10689        #[doc = "Output high"]
10690        pub const _1: Self = Self::new(1);
10691    }
10692    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10693    pub struct Pidr_SPEC;
10694    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
10695    impl Pidr {
10696        #[doc = "Low level"]
10697        pub const _0: Self = Self::new(0);
10698
10699        #[doc = "High level"]
10700        pub const _1: Self = Self::new(1);
10701    }
10702    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10703    pub struct Pdr_SPEC;
10704    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
10705    impl Pdr {
10706        #[doc = "Input (functions as an input pin)"]
10707        pub const _0: Self = Self::new(0);
10708
10709        #[doc = "Output (functions as an output pin)"]
10710        pub const _1: Self = Self::new(1);
10711    }
10712    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10713    pub struct Pcr_SPEC;
10714    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
10715    impl Pcr {
10716        #[doc = "Disable input pull-up"]
10717        pub const _0: Self = Self::new(0);
10718
10719        #[doc = "Enable input pull-up"]
10720        pub const _1: Self = Self::new(1);
10721    }
10722    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10723    pub struct Ncodr_SPEC;
10724    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
10725    impl Ncodr {
10726        #[doc = "Output CMOS"]
10727        pub const _0: Self = Self::new(0);
10728
10729        #[doc = "Output NMOS open-drain"]
10730        pub const _1: Self = Self::new(1);
10731    }
10732    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10733    pub struct Isel_SPEC;
10734    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
10735    impl Isel {
10736        #[doc = "Do not use as IRQn input pin"]
10737        pub const _0: Self = Self::new(0);
10738
10739        #[doc = "Use as IRQn input pin"]
10740        pub const _1: Self = Self::new(1);
10741    }
10742    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10743    pub struct Asel_SPEC;
10744    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
10745    impl Asel {
10746        #[doc = "Do not use as analog pin"]
10747        pub const _0: Self = Self::new(0);
10748
10749        #[doc = "Use as analog pin"]
10750        pub const _1: Self = Self::new(1);
10751    }
10752}
10753#[doc(hidden)]
10754#[derive(Copy, Clone, Eq, PartialEq)]
10755pub struct P300PfsBy_SPEC;
10756impl crate::sealed::RegSpec for P300PfsBy_SPEC {
10757    type DataType = u8;
10758}
10759
10760#[doc = "Port 300 Pin Function Select Register"]
10761pub type P300PfsBy = crate::RegValueT<P300PfsBy_SPEC>;
10762
10763impl P300PfsBy {
10764    #[doc = "Port Output Data"]
10765    #[inline(always)]
10766    pub fn podr(
10767        self,
10768    ) -> crate::common::RegisterField<
10769        0,
10770        0x1,
10771        1,
10772        0,
10773        p300pfs_by::Podr,
10774        p300pfs_by::Podr,
10775        P300PfsBy_SPEC,
10776        crate::common::RW,
10777    > {
10778        crate::common::RegisterField::<
10779            0,
10780            0x1,
10781            1,
10782            0,
10783            p300pfs_by::Podr,
10784            p300pfs_by::Podr,
10785            P300PfsBy_SPEC,
10786            crate::common::RW,
10787        >::from_register(self, 0)
10788    }
10789
10790    #[doc = "Port State"]
10791    #[inline(always)]
10792    pub fn pidr(
10793        self,
10794    ) -> crate::common::RegisterField<
10795        1,
10796        0x1,
10797        1,
10798        0,
10799        p300pfs_by::Pidr,
10800        p300pfs_by::Pidr,
10801        P300PfsBy_SPEC,
10802        crate::common::R,
10803    > {
10804        crate::common::RegisterField::<
10805            1,
10806            0x1,
10807            1,
10808            0,
10809            p300pfs_by::Pidr,
10810            p300pfs_by::Pidr,
10811            P300PfsBy_SPEC,
10812            crate::common::R,
10813        >::from_register(self, 0)
10814    }
10815
10816    #[doc = "Port Direction"]
10817    #[inline(always)]
10818    pub fn pdr(
10819        self,
10820    ) -> crate::common::RegisterField<
10821        2,
10822        0x1,
10823        1,
10824        0,
10825        p300pfs_by::Pdr,
10826        p300pfs_by::Pdr,
10827        P300PfsBy_SPEC,
10828        crate::common::RW,
10829    > {
10830        crate::common::RegisterField::<
10831            2,
10832            0x1,
10833            1,
10834            0,
10835            p300pfs_by::Pdr,
10836            p300pfs_by::Pdr,
10837            P300PfsBy_SPEC,
10838            crate::common::RW,
10839        >::from_register(self, 0)
10840    }
10841
10842    #[doc = "Pull-up Control"]
10843    #[inline(always)]
10844    pub fn pcr(
10845        self,
10846    ) -> crate::common::RegisterField<
10847        4,
10848        0x1,
10849        1,
10850        0,
10851        p300pfs_by::Pcr,
10852        p300pfs_by::Pcr,
10853        P300PfsBy_SPEC,
10854        crate::common::RW,
10855    > {
10856        crate::common::RegisterField::<
10857            4,
10858            0x1,
10859            1,
10860            0,
10861            p300pfs_by::Pcr,
10862            p300pfs_by::Pcr,
10863            P300PfsBy_SPEC,
10864            crate::common::RW,
10865        >::from_register(self, 0)
10866    }
10867
10868    #[doc = "N-Channel Open-Drain Control"]
10869    #[inline(always)]
10870    pub fn ncodr(
10871        self,
10872    ) -> crate::common::RegisterField<
10873        6,
10874        0x1,
10875        1,
10876        0,
10877        p300pfs_by::Ncodr,
10878        p300pfs_by::Ncodr,
10879        P300PfsBy_SPEC,
10880        crate::common::RW,
10881    > {
10882        crate::common::RegisterField::<
10883            6,
10884            0x1,
10885            1,
10886            0,
10887            p300pfs_by::Ncodr,
10888            p300pfs_by::Ncodr,
10889            P300PfsBy_SPEC,
10890            crate::common::RW,
10891        >::from_register(self, 0)
10892    }
10893}
10894impl ::core::default::Default for P300PfsBy {
10895    #[inline(always)]
10896    fn default() -> P300PfsBy {
10897        <crate::RegValueT<P300PfsBy_SPEC> as RegisterValue<_>>::new(0)
10898    }
10899}
10900pub mod p300pfs_by {
10901
10902    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10903    pub struct Podr_SPEC;
10904    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
10905    impl Podr {
10906        #[doc = "Output low"]
10907        pub const _0: Self = Self::new(0);
10908
10909        #[doc = "Output high"]
10910        pub const _1: Self = Self::new(1);
10911    }
10912    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10913    pub struct Pidr_SPEC;
10914    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
10915    impl Pidr {
10916        #[doc = "Low level"]
10917        pub const _0: Self = Self::new(0);
10918
10919        #[doc = "High level"]
10920        pub const _1: Self = Self::new(1);
10921    }
10922    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10923    pub struct Pdr_SPEC;
10924    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
10925    impl Pdr {
10926        #[doc = "Input (functions as an input pin)"]
10927        pub const _0: Self = Self::new(0);
10928
10929        #[doc = "Output (functions as an output pin)"]
10930        pub const _1: Self = Self::new(1);
10931    }
10932    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10933    pub struct Pcr_SPEC;
10934    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
10935    impl Pcr {
10936        #[doc = "Disable input pull-up"]
10937        pub const _0: Self = Self::new(0);
10938
10939        #[doc = "Enable input pull-up"]
10940        pub const _1: Self = Self::new(1);
10941    }
10942    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10943    pub struct Ncodr_SPEC;
10944    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
10945    impl Ncodr {
10946        #[doc = "Output CMOS"]
10947        pub const _0: Self = Self::new(0);
10948
10949        #[doc = "Output NMOS open-drain"]
10950        pub const _1: Self = Self::new(1);
10951    }
10952}
10953#[doc(hidden)]
10954#[derive(Copy, Clone, Eq, PartialEq)]
10955pub struct P30Pfs_SPEC;
10956impl crate::sealed::RegSpec for P30Pfs_SPEC {
10957    type DataType = u32;
10958}
10959
10960#[doc = "Port 30%s Pin Function Select Register"]
10961pub type P30Pfs = crate::RegValueT<P30Pfs_SPEC>;
10962
10963impl P30Pfs {
10964    #[doc = "Port Output Data"]
10965    #[inline(always)]
10966    pub fn podr(
10967        self,
10968    ) -> crate::common::RegisterField<
10969        0,
10970        0x1,
10971        1,
10972        0,
10973        p30pfs::Podr,
10974        p30pfs::Podr,
10975        P30Pfs_SPEC,
10976        crate::common::RW,
10977    > {
10978        crate::common::RegisterField::<
10979            0,
10980            0x1,
10981            1,
10982            0,
10983            p30pfs::Podr,
10984            p30pfs::Podr,
10985            P30Pfs_SPEC,
10986            crate::common::RW,
10987        >::from_register(self, 0)
10988    }
10989
10990    #[doc = "Port State"]
10991    #[inline(always)]
10992    pub fn pidr(
10993        self,
10994    ) -> crate::common::RegisterField<
10995        1,
10996        0x1,
10997        1,
10998        0,
10999        p30pfs::Pidr,
11000        p30pfs::Pidr,
11001        P30Pfs_SPEC,
11002        crate::common::R,
11003    > {
11004        crate::common::RegisterField::<
11005            1,
11006            0x1,
11007            1,
11008            0,
11009            p30pfs::Pidr,
11010            p30pfs::Pidr,
11011            P30Pfs_SPEC,
11012            crate::common::R,
11013        >::from_register(self, 0)
11014    }
11015
11016    #[doc = "Port Direction"]
11017    #[inline(always)]
11018    pub fn pdr(
11019        self,
11020    ) -> crate::common::RegisterField<
11021        2,
11022        0x1,
11023        1,
11024        0,
11025        p30pfs::Pdr,
11026        p30pfs::Pdr,
11027        P30Pfs_SPEC,
11028        crate::common::RW,
11029    > {
11030        crate::common::RegisterField::<
11031            2,
11032            0x1,
11033            1,
11034            0,
11035            p30pfs::Pdr,
11036            p30pfs::Pdr,
11037            P30Pfs_SPEC,
11038            crate::common::RW,
11039        >::from_register(self, 0)
11040    }
11041
11042    #[doc = "Pull-up Control"]
11043    #[inline(always)]
11044    pub fn pcr(
11045        self,
11046    ) -> crate::common::RegisterField<
11047        4,
11048        0x1,
11049        1,
11050        0,
11051        p30pfs::Pcr,
11052        p30pfs::Pcr,
11053        P30Pfs_SPEC,
11054        crate::common::RW,
11055    > {
11056        crate::common::RegisterField::<
11057            4,
11058            0x1,
11059            1,
11060            0,
11061            p30pfs::Pcr,
11062            p30pfs::Pcr,
11063            P30Pfs_SPEC,
11064            crate::common::RW,
11065        >::from_register(self, 0)
11066    }
11067
11068    #[doc = "N-Channel Open-Drain Control"]
11069    #[inline(always)]
11070    pub fn ncodr(
11071        self,
11072    ) -> crate::common::RegisterField<
11073        6,
11074        0x1,
11075        1,
11076        0,
11077        p30pfs::Ncodr,
11078        p30pfs::Ncodr,
11079        P30Pfs_SPEC,
11080        crate::common::RW,
11081    > {
11082        crate::common::RegisterField::<
11083            6,
11084            0x1,
11085            1,
11086            0,
11087            p30pfs::Ncodr,
11088            p30pfs::Ncodr,
11089            P30Pfs_SPEC,
11090            crate::common::RW,
11091        >::from_register(self, 0)
11092    }
11093
11094    #[doc = "IRQ Input Enable"]
11095    #[inline(always)]
11096    pub fn isel(
11097        self,
11098    ) -> crate::common::RegisterField<
11099        14,
11100        0x1,
11101        1,
11102        0,
11103        p30pfs::Isel,
11104        p30pfs::Isel,
11105        P30Pfs_SPEC,
11106        crate::common::RW,
11107    > {
11108        crate::common::RegisterField::<
11109            14,
11110            0x1,
11111            1,
11112            0,
11113            p30pfs::Isel,
11114            p30pfs::Isel,
11115            P30Pfs_SPEC,
11116            crate::common::RW,
11117        >::from_register(self, 0)
11118    }
11119
11120    #[doc = "Analog Input Enable"]
11121    #[inline(always)]
11122    pub fn asel(
11123        self,
11124    ) -> crate::common::RegisterField<
11125        15,
11126        0x1,
11127        1,
11128        0,
11129        p30pfs::Asel,
11130        p30pfs::Asel,
11131        P30Pfs_SPEC,
11132        crate::common::RW,
11133    > {
11134        crate::common::RegisterField::<
11135            15,
11136            0x1,
11137            1,
11138            0,
11139            p30pfs::Asel,
11140            p30pfs::Asel,
11141            P30Pfs_SPEC,
11142            crate::common::RW,
11143        >::from_register(self, 0)
11144    }
11145
11146    #[doc = "Port Mode Control"]
11147    #[inline(always)]
11148    pub fn pmr(
11149        self,
11150    ) -> crate::common::RegisterField<
11151        16,
11152        0x1,
11153        1,
11154        0,
11155        p30pfs::Pmr,
11156        p30pfs::Pmr,
11157        P30Pfs_SPEC,
11158        crate::common::RW,
11159    > {
11160        crate::common::RegisterField::<
11161            16,
11162            0x1,
11163            1,
11164            0,
11165            p30pfs::Pmr,
11166            p30pfs::Pmr,
11167            P30Pfs_SPEC,
11168            crate::common::RW,
11169        >::from_register(self, 0)
11170    }
11171
11172    #[doc = "Peripheral Select"]
11173    #[inline(always)]
11174    pub fn psel(
11175        self,
11176    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P30Pfs_SPEC, crate::common::RW> {
11177        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P30Pfs_SPEC,crate::common::RW>::from_register(self,0)
11178    }
11179}
11180impl ::core::default::Default for P30Pfs {
11181    #[inline(always)]
11182    fn default() -> P30Pfs {
11183        <crate::RegValueT<P30Pfs_SPEC> as RegisterValue<_>>::new(0)
11184    }
11185}
11186pub mod p30pfs {
11187
11188    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11189    pub struct Podr_SPEC;
11190    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
11191    impl Podr {
11192        #[doc = "Output low"]
11193        pub const _0: Self = Self::new(0);
11194
11195        #[doc = "Output high"]
11196        pub const _1: Self = Self::new(1);
11197    }
11198    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11199    pub struct Pidr_SPEC;
11200    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
11201    impl Pidr {
11202        #[doc = "Low level"]
11203        pub const _0: Self = Self::new(0);
11204
11205        #[doc = "High level"]
11206        pub const _1: Self = Self::new(1);
11207    }
11208    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11209    pub struct Pdr_SPEC;
11210    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
11211    impl Pdr {
11212        #[doc = "Input (functions as an input pin)"]
11213        pub const _0: Self = Self::new(0);
11214
11215        #[doc = "Output (functions as an output pin)"]
11216        pub const _1: Self = Self::new(1);
11217    }
11218    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11219    pub struct Pcr_SPEC;
11220    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
11221    impl Pcr {
11222        #[doc = "Disable input pull-up"]
11223        pub const _0: Self = Self::new(0);
11224
11225        #[doc = "Enable input pull-up"]
11226        pub const _1: Self = Self::new(1);
11227    }
11228    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11229    pub struct Ncodr_SPEC;
11230    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
11231    impl Ncodr {
11232        #[doc = "Output CMOS"]
11233        pub const _0: Self = Self::new(0);
11234
11235        #[doc = "Output NMOS open-drain"]
11236        pub const _1: Self = Self::new(1);
11237    }
11238    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11239    pub struct Isel_SPEC;
11240    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
11241    impl Isel {
11242        #[doc = "Do not use as IRQn input pin"]
11243        pub const _0: Self = Self::new(0);
11244
11245        #[doc = "Use as IRQn input pin"]
11246        pub const _1: Self = Self::new(1);
11247    }
11248    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11249    pub struct Asel_SPEC;
11250    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
11251    impl Asel {
11252        #[doc = "Do not use as analog pin"]
11253        pub const _0: Self = Self::new(0);
11254
11255        #[doc = "Use as analog pin"]
11256        pub const _1: Self = Self::new(1);
11257    }
11258    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11259    pub struct Pmr_SPEC;
11260    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
11261    impl Pmr {
11262        #[doc = "Use as general I/O pin"]
11263        pub const _0: Self = Self::new(0);
11264
11265        #[doc = "Use as I/O port for peripheral functions"]
11266        pub const _1: Self = Self::new(1);
11267    }
11268}
11269#[doc(hidden)]
11270#[derive(Copy, Clone, Eq, PartialEq)]
11271pub struct P30PfsHa_SPEC;
11272impl crate::sealed::RegSpec for P30PfsHa_SPEC {
11273    type DataType = u16;
11274}
11275
11276#[doc = "Port 30%s Pin Function Select Register"]
11277pub type P30PfsHa = crate::RegValueT<P30PfsHa_SPEC>;
11278
11279impl P30PfsHa {
11280    #[doc = "Port Output Data"]
11281    #[inline(always)]
11282    pub fn podr(
11283        self,
11284    ) -> crate::common::RegisterField<
11285        0,
11286        0x1,
11287        1,
11288        0,
11289        p30pfs_ha::Podr,
11290        p30pfs_ha::Podr,
11291        P30PfsHa_SPEC,
11292        crate::common::RW,
11293    > {
11294        crate::common::RegisterField::<
11295            0,
11296            0x1,
11297            1,
11298            0,
11299            p30pfs_ha::Podr,
11300            p30pfs_ha::Podr,
11301            P30PfsHa_SPEC,
11302            crate::common::RW,
11303        >::from_register(self, 0)
11304    }
11305
11306    #[doc = "Port State"]
11307    #[inline(always)]
11308    pub fn pidr(
11309        self,
11310    ) -> crate::common::RegisterField<
11311        1,
11312        0x1,
11313        1,
11314        0,
11315        p30pfs_ha::Pidr,
11316        p30pfs_ha::Pidr,
11317        P30PfsHa_SPEC,
11318        crate::common::R,
11319    > {
11320        crate::common::RegisterField::<
11321            1,
11322            0x1,
11323            1,
11324            0,
11325            p30pfs_ha::Pidr,
11326            p30pfs_ha::Pidr,
11327            P30PfsHa_SPEC,
11328            crate::common::R,
11329        >::from_register(self, 0)
11330    }
11331
11332    #[doc = "Port Direction"]
11333    #[inline(always)]
11334    pub fn pdr(
11335        self,
11336    ) -> crate::common::RegisterField<
11337        2,
11338        0x1,
11339        1,
11340        0,
11341        p30pfs_ha::Pdr,
11342        p30pfs_ha::Pdr,
11343        P30PfsHa_SPEC,
11344        crate::common::RW,
11345    > {
11346        crate::common::RegisterField::<
11347            2,
11348            0x1,
11349            1,
11350            0,
11351            p30pfs_ha::Pdr,
11352            p30pfs_ha::Pdr,
11353            P30PfsHa_SPEC,
11354            crate::common::RW,
11355        >::from_register(self, 0)
11356    }
11357
11358    #[doc = "Pull-up Control"]
11359    #[inline(always)]
11360    pub fn pcr(
11361        self,
11362    ) -> crate::common::RegisterField<
11363        4,
11364        0x1,
11365        1,
11366        0,
11367        p30pfs_ha::Pcr,
11368        p30pfs_ha::Pcr,
11369        P30PfsHa_SPEC,
11370        crate::common::RW,
11371    > {
11372        crate::common::RegisterField::<
11373            4,
11374            0x1,
11375            1,
11376            0,
11377            p30pfs_ha::Pcr,
11378            p30pfs_ha::Pcr,
11379            P30PfsHa_SPEC,
11380            crate::common::RW,
11381        >::from_register(self, 0)
11382    }
11383
11384    #[doc = "N-Channel Open-Drain Control"]
11385    #[inline(always)]
11386    pub fn ncodr(
11387        self,
11388    ) -> crate::common::RegisterField<
11389        6,
11390        0x1,
11391        1,
11392        0,
11393        p30pfs_ha::Ncodr,
11394        p30pfs_ha::Ncodr,
11395        P30PfsHa_SPEC,
11396        crate::common::RW,
11397    > {
11398        crate::common::RegisterField::<
11399            6,
11400            0x1,
11401            1,
11402            0,
11403            p30pfs_ha::Ncodr,
11404            p30pfs_ha::Ncodr,
11405            P30PfsHa_SPEC,
11406            crate::common::RW,
11407        >::from_register(self, 0)
11408    }
11409
11410    #[doc = "IRQ Input Enable"]
11411    #[inline(always)]
11412    pub fn isel(
11413        self,
11414    ) -> crate::common::RegisterField<
11415        14,
11416        0x1,
11417        1,
11418        0,
11419        p30pfs_ha::Isel,
11420        p30pfs_ha::Isel,
11421        P30PfsHa_SPEC,
11422        crate::common::RW,
11423    > {
11424        crate::common::RegisterField::<
11425            14,
11426            0x1,
11427            1,
11428            0,
11429            p30pfs_ha::Isel,
11430            p30pfs_ha::Isel,
11431            P30PfsHa_SPEC,
11432            crate::common::RW,
11433        >::from_register(self, 0)
11434    }
11435
11436    #[doc = "Analog Input Enable"]
11437    #[inline(always)]
11438    pub fn asel(
11439        self,
11440    ) -> crate::common::RegisterField<
11441        15,
11442        0x1,
11443        1,
11444        0,
11445        p30pfs_ha::Asel,
11446        p30pfs_ha::Asel,
11447        P30PfsHa_SPEC,
11448        crate::common::RW,
11449    > {
11450        crate::common::RegisterField::<
11451            15,
11452            0x1,
11453            1,
11454            0,
11455            p30pfs_ha::Asel,
11456            p30pfs_ha::Asel,
11457            P30PfsHa_SPEC,
11458            crate::common::RW,
11459        >::from_register(self, 0)
11460    }
11461}
11462impl ::core::default::Default for P30PfsHa {
11463    #[inline(always)]
11464    fn default() -> P30PfsHa {
11465        <crate::RegValueT<P30PfsHa_SPEC> as RegisterValue<_>>::new(0)
11466    }
11467}
11468pub mod p30pfs_ha {
11469
11470    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11471    pub struct Podr_SPEC;
11472    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
11473    impl Podr {
11474        #[doc = "Output low"]
11475        pub const _0: Self = Self::new(0);
11476
11477        #[doc = "Output high"]
11478        pub const _1: Self = Self::new(1);
11479    }
11480    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11481    pub struct Pidr_SPEC;
11482    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
11483    impl Pidr {
11484        #[doc = "Low level"]
11485        pub const _0: Self = Self::new(0);
11486
11487        #[doc = "High level"]
11488        pub const _1: Self = Self::new(1);
11489    }
11490    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11491    pub struct Pdr_SPEC;
11492    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
11493    impl Pdr {
11494        #[doc = "Input (functions as an input pin)"]
11495        pub const _0: Self = Self::new(0);
11496
11497        #[doc = "Output (functions as an output pin)"]
11498        pub const _1: Self = Self::new(1);
11499    }
11500    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11501    pub struct Pcr_SPEC;
11502    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
11503    impl Pcr {
11504        #[doc = "Disable input pull-up"]
11505        pub const _0: Self = Self::new(0);
11506
11507        #[doc = "Enable input pull-up"]
11508        pub const _1: Self = Self::new(1);
11509    }
11510    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11511    pub struct Ncodr_SPEC;
11512    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
11513    impl Ncodr {
11514        #[doc = "Output CMOS"]
11515        pub const _0: Self = Self::new(0);
11516
11517        #[doc = "Output NMOS open-drain"]
11518        pub const _1: Self = Self::new(1);
11519    }
11520    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11521    pub struct Isel_SPEC;
11522    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
11523    impl Isel {
11524        #[doc = "Do not use as IRQn input pin"]
11525        pub const _0: Self = Self::new(0);
11526
11527        #[doc = "Use as IRQn input pin"]
11528        pub const _1: Self = Self::new(1);
11529    }
11530    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11531    pub struct Asel_SPEC;
11532    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
11533    impl Asel {
11534        #[doc = "Do not use as analog pin"]
11535        pub const _0: Self = Self::new(0);
11536
11537        #[doc = "Use as analog pin"]
11538        pub const _1: Self = Self::new(1);
11539    }
11540}
11541#[doc(hidden)]
11542#[derive(Copy, Clone, Eq, PartialEq)]
11543pub struct P30PfsBy_SPEC;
11544impl crate::sealed::RegSpec for P30PfsBy_SPEC {
11545    type DataType = u8;
11546}
11547
11548#[doc = "Port 30%s Pin Function Select Register"]
11549pub type P30PfsBy = crate::RegValueT<P30PfsBy_SPEC>;
11550
11551impl P30PfsBy {
11552    #[doc = "Port Output Data"]
11553    #[inline(always)]
11554    pub fn podr(
11555        self,
11556    ) -> crate::common::RegisterField<
11557        0,
11558        0x1,
11559        1,
11560        0,
11561        p30pfs_by::Podr,
11562        p30pfs_by::Podr,
11563        P30PfsBy_SPEC,
11564        crate::common::RW,
11565    > {
11566        crate::common::RegisterField::<
11567            0,
11568            0x1,
11569            1,
11570            0,
11571            p30pfs_by::Podr,
11572            p30pfs_by::Podr,
11573            P30PfsBy_SPEC,
11574            crate::common::RW,
11575        >::from_register(self, 0)
11576    }
11577
11578    #[doc = "Port State"]
11579    #[inline(always)]
11580    pub fn pidr(
11581        self,
11582    ) -> crate::common::RegisterField<
11583        1,
11584        0x1,
11585        1,
11586        0,
11587        p30pfs_by::Pidr,
11588        p30pfs_by::Pidr,
11589        P30PfsBy_SPEC,
11590        crate::common::R,
11591    > {
11592        crate::common::RegisterField::<
11593            1,
11594            0x1,
11595            1,
11596            0,
11597            p30pfs_by::Pidr,
11598            p30pfs_by::Pidr,
11599            P30PfsBy_SPEC,
11600            crate::common::R,
11601        >::from_register(self, 0)
11602    }
11603
11604    #[doc = "Port Direction"]
11605    #[inline(always)]
11606    pub fn pdr(
11607        self,
11608    ) -> crate::common::RegisterField<
11609        2,
11610        0x1,
11611        1,
11612        0,
11613        p30pfs_by::Pdr,
11614        p30pfs_by::Pdr,
11615        P30PfsBy_SPEC,
11616        crate::common::RW,
11617    > {
11618        crate::common::RegisterField::<
11619            2,
11620            0x1,
11621            1,
11622            0,
11623            p30pfs_by::Pdr,
11624            p30pfs_by::Pdr,
11625            P30PfsBy_SPEC,
11626            crate::common::RW,
11627        >::from_register(self, 0)
11628    }
11629
11630    #[doc = "Pull-up Control"]
11631    #[inline(always)]
11632    pub fn pcr(
11633        self,
11634    ) -> crate::common::RegisterField<
11635        4,
11636        0x1,
11637        1,
11638        0,
11639        p30pfs_by::Pcr,
11640        p30pfs_by::Pcr,
11641        P30PfsBy_SPEC,
11642        crate::common::RW,
11643    > {
11644        crate::common::RegisterField::<
11645            4,
11646            0x1,
11647            1,
11648            0,
11649            p30pfs_by::Pcr,
11650            p30pfs_by::Pcr,
11651            P30PfsBy_SPEC,
11652            crate::common::RW,
11653        >::from_register(self, 0)
11654    }
11655
11656    #[doc = "N-Channel Open-Drain Control"]
11657    #[inline(always)]
11658    pub fn ncodr(
11659        self,
11660    ) -> crate::common::RegisterField<
11661        6,
11662        0x1,
11663        1,
11664        0,
11665        p30pfs_by::Ncodr,
11666        p30pfs_by::Ncodr,
11667        P30PfsBy_SPEC,
11668        crate::common::RW,
11669    > {
11670        crate::common::RegisterField::<
11671            6,
11672            0x1,
11673            1,
11674            0,
11675            p30pfs_by::Ncodr,
11676            p30pfs_by::Ncodr,
11677            P30PfsBy_SPEC,
11678            crate::common::RW,
11679        >::from_register(self, 0)
11680    }
11681}
11682impl ::core::default::Default for P30PfsBy {
11683    #[inline(always)]
11684    fn default() -> P30PfsBy {
11685        <crate::RegValueT<P30PfsBy_SPEC> as RegisterValue<_>>::new(0)
11686    }
11687}
11688pub mod p30pfs_by {
11689
11690    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11691    pub struct Podr_SPEC;
11692    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
11693    impl Podr {
11694        #[doc = "Output low"]
11695        pub const _0: Self = Self::new(0);
11696
11697        #[doc = "Output high"]
11698        pub const _1: Self = Self::new(1);
11699    }
11700    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11701    pub struct Pidr_SPEC;
11702    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
11703    impl Pidr {
11704        #[doc = "Low level"]
11705        pub const _0: Self = Self::new(0);
11706
11707        #[doc = "High level"]
11708        pub const _1: Self = Self::new(1);
11709    }
11710    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11711    pub struct Pdr_SPEC;
11712    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
11713    impl Pdr {
11714        #[doc = "Input (functions as an input pin)"]
11715        pub const _0: Self = Self::new(0);
11716
11717        #[doc = "Output (functions as an output pin)"]
11718        pub const _1: Self = Self::new(1);
11719    }
11720    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11721    pub struct Pcr_SPEC;
11722    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
11723    impl Pcr {
11724        #[doc = "Disable input pull-up"]
11725        pub const _0: Self = Self::new(0);
11726
11727        #[doc = "Enable input pull-up"]
11728        pub const _1: Self = Self::new(1);
11729    }
11730    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11731    pub struct Ncodr_SPEC;
11732    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
11733    impl Ncodr {
11734        #[doc = "Output CMOS"]
11735        pub const _0: Self = Self::new(0);
11736
11737        #[doc = "Output NMOS open-drain"]
11738        pub const _1: Self = Self::new(1);
11739    }
11740}
11741#[doc(hidden)]
11742#[derive(Copy, Clone, Eq, PartialEq)]
11743pub struct P40Pfs_SPEC;
11744impl crate::sealed::RegSpec for P40Pfs_SPEC {
11745    type DataType = u32;
11746}
11747
11748#[doc = "Port 40%s Pin Function Select Register"]
11749pub type P40Pfs = crate::RegValueT<P40Pfs_SPEC>;
11750
11751impl P40Pfs {
11752    #[doc = "Port Output Data"]
11753    #[inline(always)]
11754    pub fn podr(
11755        self,
11756    ) -> crate::common::RegisterField<
11757        0,
11758        0x1,
11759        1,
11760        0,
11761        p40pfs::Podr,
11762        p40pfs::Podr,
11763        P40Pfs_SPEC,
11764        crate::common::RW,
11765    > {
11766        crate::common::RegisterField::<
11767            0,
11768            0x1,
11769            1,
11770            0,
11771            p40pfs::Podr,
11772            p40pfs::Podr,
11773            P40Pfs_SPEC,
11774            crate::common::RW,
11775        >::from_register(self, 0)
11776    }
11777
11778    #[doc = "Port State"]
11779    #[inline(always)]
11780    pub fn pidr(
11781        self,
11782    ) -> crate::common::RegisterField<
11783        1,
11784        0x1,
11785        1,
11786        0,
11787        p40pfs::Pidr,
11788        p40pfs::Pidr,
11789        P40Pfs_SPEC,
11790        crate::common::R,
11791    > {
11792        crate::common::RegisterField::<
11793            1,
11794            0x1,
11795            1,
11796            0,
11797            p40pfs::Pidr,
11798            p40pfs::Pidr,
11799            P40Pfs_SPEC,
11800            crate::common::R,
11801        >::from_register(self, 0)
11802    }
11803
11804    #[doc = "Port Direction"]
11805    #[inline(always)]
11806    pub fn pdr(
11807        self,
11808    ) -> crate::common::RegisterField<
11809        2,
11810        0x1,
11811        1,
11812        0,
11813        p40pfs::Pdr,
11814        p40pfs::Pdr,
11815        P40Pfs_SPEC,
11816        crate::common::RW,
11817    > {
11818        crate::common::RegisterField::<
11819            2,
11820            0x1,
11821            1,
11822            0,
11823            p40pfs::Pdr,
11824            p40pfs::Pdr,
11825            P40Pfs_SPEC,
11826            crate::common::RW,
11827        >::from_register(self, 0)
11828    }
11829
11830    #[doc = "Pull-up Control"]
11831    #[inline(always)]
11832    pub fn pcr(
11833        self,
11834    ) -> crate::common::RegisterField<
11835        4,
11836        0x1,
11837        1,
11838        0,
11839        p40pfs::Pcr,
11840        p40pfs::Pcr,
11841        P40Pfs_SPEC,
11842        crate::common::RW,
11843    > {
11844        crate::common::RegisterField::<
11845            4,
11846            0x1,
11847            1,
11848            0,
11849            p40pfs::Pcr,
11850            p40pfs::Pcr,
11851            P40Pfs_SPEC,
11852            crate::common::RW,
11853        >::from_register(self, 0)
11854    }
11855
11856    #[doc = "N-Channel Open-Drain Control"]
11857    #[inline(always)]
11858    pub fn ncodr(
11859        self,
11860    ) -> crate::common::RegisterField<
11861        6,
11862        0x1,
11863        1,
11864        0,
11865        p40pfs::Ncodr,
11866        p40pfs::Ncodr,
11867        P40Pfs_SPEC,
11868        crate::common::RW,
11869    > {
11870        crate::common::RegisterField::<
11871            6,
11872            0x1,
11873            1,
11874            0,
11875            p40pfs::Ncodr,
11876            p40pfs::Ncodr,
11877            P40Pfs_SPEC,
11878            crate::common::RW,
11879        >::from_register(self, 0)
11880    }
11881
11882    #[doc = "IRQ Input Enable"]
11883    #[inline(always)]
11884    pub fn isel(
11885        self,
11886    ) -> crate::common::RegisterField<
11887        14,
11888        0x1,
11889        1,
11890        0,
11891        p40pfs::Isel,
11892        p40pfs::Isel,
11893        P40Pfs_SPEC,
11894        crate::common::RW,
11895    > {
11896        crate::common::RegisterField::<
11897            14,
11898            0x1,
11899            1,
11900            0,
11901            p40pfs::Isel,
11902            p40pfs::Isel,
11903            P40Pfs_SPEC,
11904            crate::common::RW,
11905        >::from_register(self, 0)
11906    }
11907
11908    #[doc = "Analog Input Enable"]
11909    #[inline(always)]
11910    pub fn asel(
11911        self,
11912    ) -> crate::common::RegisterField<
11913        15,
11914        0x1,
11915        1,
11916        0,
11917        p40pfs::Asel,
11918        p40pfs::Asel,
11919        P40Pfs_SPEC,
11920        crate::common::RW,
11921    > {
11922        crate::common::RegisterField::<
11923            15,
11924            0x1,
11925            1,
11926            0,
11927            p40pfs::Asel,
11928            p40pfs::Asel,
11929            P40Pfs_SPEC,
11930            crate::common::RW,
11931        >::from_register(self, 0)
11932    }
11933
11934    #[doc = "Port Mode Control"]
11935    #[inline(always)]
11936    pub fn pmr(
11937        self,
11938    ) -> crate::common::RegisterField<
11939        16,
11940        0x1,
11941        1,
11942        0,
11943        p40pfs::Pmr,
11944        p40pfs::Pmr,
11945        P40Pfs_SPEC,
11946        crate::common::RW,
11947    > {
11948        crate::common::RegisterField::<
11949            16,
11950            0x1,
11951            1,
11952            0,
11953            p40pfs::Pmr,
11954            p40pfs::Pmr,
11955            P40Pfs_SPEC,
11956            crate::common::RW,
11957        >::from_register(self, 0)
11958    }
11959
11960    #[doc = "Peripheral Select"]
11961    #[inline(always)]
11962    pub fn psel(
11963        self,
11964    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P40Pfs_SPEC, crate::common::RW> {
11965        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P40Pfs_SPEC,crate::common::RW>::from_register(self,0)
11966    }
11967}
11968impl ::core::default::Default for P40Pfs {
11969    #[inline(always)]
11970    fn default() -> P40Pfs {
11971        <crate::RegValueT<P40Pfs_SPEC> as RegisterValue<_>>::new(0)
11972    }
11973}
11974pub mod p40pfs {
11975
11976    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11977    pub struct Podr_SPEC;
11978    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
11979    impl Podr {
11980        #[doc = "Output low"]
11981        pub const _0: Self = Self::new(0);
11982
11983        #[doc = "Output high"]
11984        pub const _1: Self = Self::new(1);
11985    }
11986    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11987    pub struct Pidr_SPEC;
11988    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
11989    impl Pidr {
11990        #[doc = "Low level"]
11991        pub const _0: Self = Self::new(0);
11992
11993        #[doc = "High level"]
11994        pub const _1: Self = Self::new(1);
11995    }
11996    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11997    pub struct Pdr_SPEC;
11998    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
11999    impl Pdr {
12000        #[doc = "Input (functions as an input pin)"]
12001        pub const _0: Self = Self::new(0);
12002
12003        #[doc = "Output (functions as an output pin)"]
12004        pub const _1: Self = Self::new(1);
12005    }
12006    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12007    pub struct Pcr_SPEC;
12008    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
12009    impl Pcr {
12010        #[doc = "Disable input pull-up"]
12011        pub const _0: Self = Self::new(0);
12012
12013        #[doc = "Enable input pull-up"]
12014        pub const _1: Self = Self::new(1);
12015    }
12016    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12017    pub struct Ncodr_SPEC;
12018    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
12019    impl Ncodr {
12020        #[doc = "Output CMOS"]
12021        pub const _0: Self = Self::new(0);
12022
12023        #[doc = "Output NMOS open-drain"]
12024        pub const _1: Self = Self::new(1);
12025    }
12026    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12027    pub struct Isel_SPEC;
12028    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
12029    impl Isel {
12030        #[doc = "Do not use as IRQn input pin"]
12031        pub const _0: Self = Self::new(0);
12032
12033        #[doc = "Use as IRQn input pin"]
12034        pub const _1: Self = Self::new(1);
12035    }
12036    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12037    pub struct Asel_SPEC;
12038    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
12039    impl Asel {
12040        #[doc = "Do not use as analog pin"]
12041        pub const _0: Self = Self::new(0);
12042
12043        #[doc = "Use as analog pin"]
12044        pub const _1: Self = Self::new(1);
12045    }
12046    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12047    pub struct Pmr_SPEC;
12048    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
12049    impl Pmr {
12050        #[doc = "Use as general I/O pin"]
12051        pub const _0: Self = Self::new(0);
12052
12053        #[doc = "Use as I/O port for peripheral functions"]
12054        pub const _1: Self = Self::new(1);
12055    }
12056}
12057#[doc(hidden)]
12058#[derive(Copy, Clone, Eq, PartialEq)]
12059pub struct P40PfsHa_SPEC;
12060impl crate::sealed::RegSpec for P40PfsHa_SPEC {
12061    type DataType = u16;
12062}
12063
12064#[doc = "Port 40%s Pin Function Select Register"]
12065pub type P40PfsHa = crate::RegValueT<P40PfsHa_SPEC>;
12066
12067impl P40PfsHa {
12068    #[doc = "Port Output Data"]
12069    #[inline(always)]
12070    pub fn podr(
12071        self,
12072    ) -> crate::common::RegisterField<
12073        0,
12074        0x1,
12075        1,
12076        0,
12077        p40pfs_ha::Podr,
12078        p40pfs_ha::Podr,
12079        P40PfsHa_SPEC,
12080        crate::common::RW,
12081    > {
12082        crate::common::RegisterField::<
12083            0,
12084            0x1,
12085            1,
12086            0,
12087            p40pfs_ha::Podr,
12088            p40pfs_ha::Podr,
12089            P40PfsHa_SPEC,
12090            crate::common::RW,
12091        >::from_register(self, 0)
12092    }
12093
12094    #[doc = "Port State"]
12095    #[inline(always)]
12096    pub fn pidr(
12097        self,
12098    ) -> crate::common::RegisterField<
12099        1,
12100        0x1,
12101        1,
12102        0,
12103        p40pfs_ha::Pidr,
12104        p40pfs_ha::Pidr,
12105        P40PfsHa_SPEC,
12106        crate::common::R,
12107    > {
12108        crate::common::RegisterField::<
12109            1,
12110            0x1,
12111            1,
12112            0,
12113            p40pfs_ha::Pidr,
12114            p40pfs_ha::Pidr,
12115            P40PfsHa_SPEC,
12116            crate::common::R,
12117        >::from_register(self, 0)
12118    }
12119
12120    #[doc = "Port Direction"]
12121    #[inline(always)]
12122    pub fn pdr(
12123        self,
12124    ) -> crate::common::RegisterField<
12125        2,
12126        0x1,
12127        1,
12128        0,
12129        p40pfs_ha::Pdr,
12130        p40pfs_ha::Pdr,
12131        P40PfsHa_SPEC,
12132        crate::common::RW,
12133    > {
12134        crate::common::RegisterField::<
12135            2,
12136            0x1,
12137            1,
12138            0,
12139            p40pfs_ha::Pdr,
12140            p40pfs_ha::Pdr,
12141            P40PfsHa_SPEC,
12142            crate::common::RW,
12143        >::from_register(self, 0)
12144    }
12145
12146    #[doc = "Pull-up Control"]
12147    #[inline(always)]
12148    pub fn pcr(
12149        self,
12150    ) -> crate::common::RegisterField<
12151        4,
12152        0x1,
12153        1,
12154        0,
12155        p40pfs_ha::Pcr,
12156        p40pfs_ha::Pcr,
12157        P40PfsHa_SPEC,
12158        crate::common::RW,
12159    > {
12160        crate::common::RegisterField::<
12161            4,
12162            0x1,
12163            1,
12164            0,
12165            p40pfs_ha::Pcr,
12166            p40pfs_ha::Pcr,
12167            P40PfsHa_SPEC,
12168            crate::common::RW,
12169        >::from_register(self, 0)
12170    }
12171
12172    #[doc = "N-Channel Open-Drain Control"]
12173    #[inline(always)]
12174    pub fn ncodr(
12175        self,
12176    ) -> crate::common::RegisterField<
12177        6,
12178        0x1,
12179        1,
12180        0,
12181        p40pfs_ha::Ncodr,
12182        p40pfs_ha::Ncodr,
12183        P40PfsHa_SPEC,
12184        crate::common::RW,
12185    > {
12186        crate::common::RegisterField::<
12187            6,
12188            0x1,
12189            1,
12190            0,
12191            p40pfs_ha::Ncodr,
12192            p40pfs_ha::Ncodr,
12193            P40PfsHa_SPEC,
12194            crate::common::RW,
12195        >::from_register(self, 0)
12196    }
12197
12198    #[doc = "IRQ Input Enable"]
12199    #[inline(always)]
12200    pub fn isel(
12201        self,
12202    ) -> crate::common::RegisterField<
12203        14,
12204        0x1,
12205        1,
12206        0,
12207        p40pfs_ha::Isel,
12208        p40pfs_ha::Isel,
12209        P40PfsHa_SPEC,
12210        crate::common::RW,
12211    > {
12212        crate::common::RegisterField::<
12213            14,
12214            0x1,
12215            1,
12216            0,
12217            p40pfs_ha::Isel,
12218            p40pfs_ha::Isel,
12219            P40PfsHa_SPEC,
12220            crate::common::RW,
12221        >::from_register(self, 0)
12222    }
12223
12224    #[doc = "Analog Input Enable"]
12225    #[inline(always)]
12226    pub fn asel(
12227        self,
12228    ) -> crate::common::RegisterField<
12229        15,
12230        0x1,
12231        1,
12232        0,
12233        p40pfs_ha::Asel,
12234        p40pfs_ha::Asel,
12235        P40PfsHa_SPEC,
12236        crate::common::RW,
12237    > {
12238        crate::common::RegisterField::<
12239            15,
12240            0x1,
12241            1,
12242            0,
12243            p40pfs_ha::Asel,
12244            p40pfs_ha::Asel,
12245            P40PfsHa_SPEC,
12246            crate::common::RW,
12247        >::from_register(self, 0)
12248    }
12249}
12250impl ::core::default::Default for P40PfsHa {
12251    #[inline(always)]
12252    fn default() -> P40PfsHa {
12253        <crate::RegValueT<P40PfsHa_SPEC> as RegisterValue<_>>::new(0)
12254    }
12255}
12256pub mod p40pfs_ha {
12257
12258    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12259    pub struct Podr_SPEC;
12260    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
12261    impl Podr {
12262        #[doc = "Output low"]
12263        pub const _0: Self = Self::new(0);
12264
12265        #[doc = "Output high"]
12266        pub const _1: Self = Self::new(1);
12267    }
12268    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12269    pub struct Pidr_SPEC;
12270    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
12271    impl Pidr {
12272        #[doc = "Low level"]
12273        pub const _0: Self = Self::new(0);
12274
12275        #[doc = "High level"]
12276        pub const _1: Self = Self::new(1);
12277    }
12278    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12279    pub struct Pdr_SPEC;
12280    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
12281    impl Pdr {
12282        #[doc = "Input (functions as an input pin)"]
12283        pub const _0: Self = Self::new(0);
12284
12285        #[doc = "Output (functions as an output pin)"]
12286        pub const _1: Self = Self::new(1);
12287    }
12288    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12289    pub struct Pcr_SPEC;
12290    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
12291    impl Pcr {
12292        #[doc = "Disable input pull-up"]
12293        pub const _0: Self = Self::new(0);
12294
12295        #[doc = "Enable input pull-up"]
12296        pub const _1: Self = Self::new(1);
12297    }
12298    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12299    pub struct Ncodr_SPEC;
12300    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
12301    impl Ncodr {
12302        #[doc = "Output CMOS"]
12303        pub const _0: Self = Self::new(0);
12304
12305        #[doc = "Output NMOS open-drain"]
12306        pub const _1: Self = Self::new(1);
12307    }
12308    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12309    pub struct Isel_SPEC;
12310    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
12311    impl Isel {
12312        #[doc = "Do not use as IRQn input pin"]
12313        pub const _0: Self = Self::new(0);
12314
12315        #[doc = "Use as IRQn input pin"]
12316        pub const _1: Self = Self::new(1);
12317    }
12318    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12319    pub struct Asel_SPEC;
12320    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
12321    impl Asel {
12322        #[doc = "Do not use as analog pin"]
12323        pub const _0: Self = Self::new(0);
12324
12325        #[doc = "Use as analog pin"]
12326        pub const _1: Self = Self::new(1);
12327    }
12328}
12329#[doc(hidden)]
12330#[derive(Copy, Clone, Eq, PartialEq)]
12331pub struct P40PfsBy_SPEC;
12332impl crate::sealed::RegSpec for P40PfsBy_SPEC {
12333    type DataType = u8;
12334}
12335
12336#[doc = "Port 40%s Pin Function Select Register"]
12337pub type P40PfsBy = crate::RegValueT<P40PfsBy_SPEC>;
12338
12339impl P40PfsBy {
12340    #[doc = "Port Output Data"]
12341    #[inline(always)]
12342    pub fn podr(
12343        self,
12344    ) -> crate::common::RegisterField<
12345        0,
12346        0x1,
12347        1,
12348        0,
12349        p40pfs_by::Podr,
12350        p40pfs_by::Podr,
12351        P40PfsBy_SPEC,
12352        crate::common::RW,
12353    > {
12354        crate::common::RegisterField::<
12355            0,
12356            0x1,
12357            1,
12358            0,
12359            p40pfs_by::Podr,
12360            p40pfs_by::Podr,
12361            P40PfsBy_SPEC,
12362            crate::common::RW,
12363        >::from_register(self, 0)
12364    }
12365
12366    #[doc = "Port State"]
12367    #[inline(always)]
12368    pub fn pidr(
12369        self,
12370    ) -> crate::common::RegisterField<
12371        1,
12372        0x1,
12373        1,
12374        0,
12375        p40pfs_by::Pidr,
12376        p40pfs_by::Pidr,
12377        P40PfsBy_SPEC,
12378        crate::common::R,
12379    > {
12380        crate::common::RegisterField::<
12381            1,
12382            0x1,
12383            1,
12384            0,
12385            p40pfs_by::Pidr,
12386            p40pfs_by::Pidr,
12387            P40PfsBy_SPEC,
12388            crate::common::R,
12389        >::from_register(self, 0)
12390    }
12391
12392    #[doc = "Port Direction"]
12393    #[inline(always)]
12394    pub fn pdr(
12395        self,
12396    ) -> crate::common::RegisterField<
12397        2,
12398        0x1,
12399        1,
12400        0,
12401        p40pfs_by::Pdr,
12402        p40pfs_by::Pdr,
12403        P40PfsBy_SPEC,
12404        crate::common::RW,
12405    > {
12406        crate::common::RegisterField::<
12407            2,
12408            0x1,
12409            1,
12410            0,
12411            p40pfs_by::Pdr,
12412            p40pfs_by::Pdr,
12413            P40PfsBy_SPEC,
12414            crate::common::RW,
12415        >::from_register(self, 0)
12416    }
12417
12418    #[doc = "Pull-up Control"]
12419    #[inline(always)]
12420    pub fn pcr(
12421        self,
12422    ) -> crate::common::RegisterField<
12423        4,
12424        0x1,
12425        1,
12426        0,
12427        p40pfs_by::Pcr,
12428        p40pfs_by::Pcr,
12429        P40PfsBy_SPEC,
12430        crate::common::RW,
12431    > {
12432        crate::common::RegisterField::<
12433            4,
12434            0x1,
12435            1,
12436            0,
12437            p40pfs_by::Pcr,
12438            p40pfs_by::Pcr,
12439            P40PfsBy_SPEC,
12440            crate::common::RW,
12441        >::from_register(self, 0)
12442    }
12443
12444    #[doc = "N-Channel Open-Drain Control"]
12445    #[inline(always)]
12446    pub fn ncodr(
12447        self,
12448    ) -> crate::common::RegisterField<
12449        6,
12450        0x1,
12451        1,
12452        0,
12453        p40pfs_by::Ncodr,
12454        p40pfs_by::Ncodr,
12455        P40PfsBy_SPEC,
12456        crate::common::RW,
12457    > {
12458        crate::common::RegisterField::<
12459            6,
12460            0x1,
12461            1,
12462            0,
12463            p40pfs_by::Ncodr,
12464            p40pfs_by::Ncodr,
12465            P40PfsBy_SPEC,
12466            crate::common::RW,
12467        >::from_register(self, 0)
12468    }
12469}
12470impl ::core::default::Default for P40PfsBy {
12471    #[inline(always)]
12472    fn default() -> P40PfsBy {
12473        <crate::RegValueT<P40PfsBy_SPEC> as RegisterValue<_>>::new(0)
12474    }
12475}
12476pub mod p40pfs_by {
12477
12478    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12479    pub struct Podr_SPEC;
12480    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
12481    impl Podr {
12482        #[doc = "Output low"]
12483        pub const _0: Self = Self::new(0);
12484
12485        #[doc = "Output high"]
12486        pub const _1: Self = Self::new(1);
12487    }
12488    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12489    pub struct Pidr_SPEC;
12490    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
12491    impl Pidr {
12492        #[doc = "Low level"]
12493        pub const _0: Self = Self::new(0);
12494
12495        #[doc = "High level"]
12496        pub const _1: Self = Self::new(1);
12497    }
12498    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12499    pub struct Pdr_SPEC;
12500    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
12501    impl Pdr {
12502        #[doc = "Input (functions as an input pin)"]
12503        pub const _0: Self = Self::new(0);
12504
12505        #[doc = "Output (functions as an output pin)"]
12506        pub const _1: Self = Self::new(1);
12507    }
12508    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12509    pub struct Pcr_SPEC;
12510    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
12511    impl Pcr {
12512        #[doc = "Disable input pull-up"]
12513        pub const _0: Self = Self::new(0);
12514
12515        #[doc = "Enable input pull-up"]
12516        pub const _1: Self = Self::new(1);
12517    }
12518    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12519    pub struct Ncodr_SPEC;
12520    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
12521    impl Ncodr {
12522        #[doc = "Output CMOS"]
12523        pub const _0: Self = Self::new(0);
12524
12525        #[doc = "Output NMOS open-drain"]
12526        pub const _1: Self = Self::new(1);
12527    }
12528}
12529#[doc(hidden)]
12530#[derive(Copy, Clone, Eq, PartialEq)]
12531pub struct P500Pfs_SPEC;
12532impl crate::sealed::RegSpec for P500Pfs_SPEC {
12533    type DataType = u32;
12534}
12535
12536#[doc = "Port 500 Pin Function Select Register"]
12537pub type P500Pfs = crate::RegValueT<P500Pfs_SPEC>;
12538
12539impl P500Pfs {
12540    #[doc = "Port Output Data"]
12541    #[inline(always)]
12542    pub fn podr(
12543        self,
12544    ) -> crate::common::RegisterField<
12545        0,
12546        0x1,
12547        1,
12548        0,
12549        p500pfs::Podr,
12550        p500pfs::Podr,
12551        P500Pfs_SPEC,
12552        crate::common::RW,
12553    > {
12554        crate::common::RegisterField::<
12555            0,
12556            0x1,
12557            1,
12558            0,
12559            p500pfs::Podr,
12560            p500pfs::Podr,
12561            P500Pfs_SPEC,
12562            crate::common::RW,
12563        >::from_register(self, 0)
12564    }
12565
12566    #[doc = "Port State"]
12567    #[inline(always)]
12568    pub fn pidr(
12569        self,
12570    ) -> crate::common::RegisterField<
12571        1,
12572        0x1,
12573        1,
12574        0,
12575        p500pfs::Pidr,
12576        p500pfs::Pidr,
12577        P500Pfs_SPEC,
12578        crate::common::R,
12579    > {
12580        crate::common::RegisterField::<
12581            1,
12582            0x1,
12583            1,
12584            0,
12585            p500pfs::Pidr,
12586            p500pfs::Pidr,
12587            P500Pfs_SPEC,
12588            crate::common::R,
12589        >::from_register(self, 0)
12590    }
12591
12592    #[doc = "Port Direction"]
12593    #[inline(always)]
12594    pub fn pdr(
12595        self,
12596    ) -> crate::common::RegisterField<
12597        2,
12598        0x1,
12599        1,
12600        0,
12601        p500pfs::Pdr,
12602        p500pfs::Pdr,
12603        P500Pfs_SPEC,
12604        crate::common::RW,
12605    > {
12606        crate::common::RegisterField::<
12607            2,
12608            0x1,
12609            1,
12610            0,
12611            p500pfs::Pdr,
12612            p500pfs::Pdr,
12613            P500Pfs_SPEC,
12614            crate::common::RW,
12615        >::from_register(self, 0)
12616    }
12617
12618    #[doc = "Pull-up Control"]
12619    #[inline(always)]
12620    pub fn pcr(
12621        self,
12622    ) -> crate::common::RegisterField<
12623        4,
12624        0x1,
12625        1,
12626        0,
12627        p500pfs::Pcr,
12628        p500pfs::Pcr,
12629        P500Pfs_SPEC,
12630        crate::common::RW,
12631    > {
12632        crate::common::RegisterField::<
12633            4,
12634            0x1,
12635            1,
12636            0,
12637            p500pfs::Pcr,
12638            p500pfs::Pcr,
12639            P500Pfs_SPEC,
12640            crate::common::RW,
12641        >::from_register(self, 0)
12642    }
12643
12644    #[doc = "N-Channel Open-Drain Control"]
12645    #[inline(always)]
12646    pub fn ncodr(
12647        self,
12648    ) -> crate::common::RegisterField<
12649        6,
12650        0x1,
12651        1,
12652        0,
12653        p500pfs::Ncodr,
12654        p500pfs::Ncodr,
12655        P500Pfs_SPEC,
12656        crate::common::RW,
12657    > {
12658        crate::common::RegisterField::<
12659            6,
12660            0x1,
12661            1,
12662            0,
12663            p500pfs::Ncodr,
12664            p500pfs::Ncodr,
12665            P500Pfs_SPEC,
12666            crate::common::RW,
12667        >::from_register(self, 0)
12668    }
12669
12670    #[doc = "IRQ Input Enable"]
12671    #[inline(always)]
12672    pub fn isel(
12673        self,
12674    ) -> crate::common::RegisterField<
12675        14,
12676        0x1,
12677        1,
12678        0,
12679        p500pfs::Isel,
12680        p500pfs::Isel,
12681        P500Pfs_SPEC,
12682        crate::common::RW,
12683    > {
12684        crate::common::RegisterField::<
12685            14,
12686            0x1,
12687            1,
12688            0,
12689            p500pfs::Isel,
12690            p500pfs::Isel,
12691            P500Pfs_SPEC,
12692            crate::common::RW,
12693        >::from_register(self, 0)
12694    }
12695
12696    #[doc = "Analog Input Enable"]
12697    #[inline(always)]
12698    pub fn asel(
12699        self,
12700    ) -> crate::common::RegisterField<
12701        15,
12702        0x1,
12703        1,
12704        0,
12705        p500pfs::Asel,
12706        p500pfs::Asel,
12707        P500Pfs_SPEC,
12708        crate::common::RW,
12709    > {
12710        crate::common::RegisterField::<
12711            15,
12712            0x1,
12713            1,
12714            0,
12715            p500pfs::Asel,
12716            p500pfs::Asel,
12717            P500Pfs_SPEC,
12718            crate::common::RW,
12719        >::from_register(self, 0)
12720    }
12721
12722    #[doc = "Port Mode Control"]
12723    #[inline(always)]
12724    pub fn pmr(
12725        self,
12726    ) -> crate::common::RegisterField<
12727        16,
12728        0x1,
12729        1,
12730        0,
12731        p500pfs::Pmr,
12732        p500pfs::Pmr,
12733        P500Pfs_SPEC,
12734        crate::common::RW,
12735    > {
12736        crate::common::RegisterField::<
12737            16,
12738            0x1,
12739            1,
12740            0,
12741            p500pfs::Pmr,
12742            p500pfs::Pmr,
12743            P500Pfs_SPEC,
12744            crate::common::RW,
12745        >::from_register(self, 0)
12746    }
12747
12748    #[doc = "Peripheral Select"]
12749    #[inline(always)]
12750    pub fn psel(
12751        self,
12752    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P500Pfs_SPEC, crate::common::RW> {
12753        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P500Pfs_SPEC,crate::common::RW>::from_register(self,0)
12754    }
12755}
12756impl ::core::default::Default for P500Pfs {
12757    #[inline(always)]
12758    fn default() -> P500Pfs {
12759        <crate::RegValueT<P500Pfs_SPEC> as RegisterValue<_>>::new(0)
12760    }
12761}
12762pub mod p500pfs {
12763
12764    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12765    pub struct Podr_SPEC;
12766    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
12767    impl Podr {
12768        #[doc = "Output low"]
12769        pub const _0: Self = Self::new(0);
12770
12771        #[doc = "Output high"]
12772        pub const _1: Self = Self::new(1);
12773    }
12774    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12775    pub struct Pidr_SPEC;
12776    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
12777    impl Pidr {
12778        #[doc = "Low level"]
12779        pub const _0: Self = Self::new(0);
12780
12781        #[doc = "High level"]
12782        pub const _1: Self = Self::new(1);
12783    }
12784    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12785    pub struct Pdr_SPEC;
12786    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
12787    impl Pdr {
12788        #[doc = "Input (functions as an input pin)"]
12789        pub const _0: Self = Self::new(0);
12790
12791        #[doc = "Output (functions as an output pin)"]
12792        pub const _1: Self = Self::new(1);
12793    }
12794    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12795    pub struct Pcr_SPEC;
12796    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
12797    impl Pcr {
12798        #[doc = "Disable input pull-up"]
12799        pub const _0: Self = Self::new(0);
12800
12801        #[doc = "Enable input pull-up"]
12802        pub const _1: Self = Self::new(1);
12803    }
12804    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12805    pub struct Ncodr_SPEC;
12806    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
12807    impl Ncodr {
12808        #[doc = "Output CMOS"]
12809        pub const _0: Self = Self::new(0);
12810
12811        #[doc = "Output NMOS open-drain"]
12812        pub const _1: Self = Self::new(1);
12813    }
12814    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12815    pub struct Isel_SPEC;
12816    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
12817    impl Isel {
12818        #[doc = "Do not use as IRQn input pin"]
12819        pub const _0: Self = Self::new(0);
12820
12821        #[doc = "Use as IRQn input pin"]
12822        pub const _1: Self = Self::new(1);
12823    }
12824    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12825    pub struct Asel_SPEC;
12826    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
12827    impl Asel {
12828        #[doc = "Do not use as analog pin"]
12829        pub const _0: Self = Self::new(0);
12830
12831        #[doc = "Use as analog pin"]
12832        pub const _1: Self = Self::new(1);
12833    }
12834    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12835    pub struct Pmr_SPEC;
12836    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
12837    impl Pmr {
12838        #[doc = "Use as general I/O pin"]
12839        pub const _0: Self = Self::new(0);
12840
12841        #[doc = "Use as I/O port for peripheral functions"]
12842        pub const _1: Self = Self::new(1);
12843    }
12844}
12845#[doc(hidden)]
12846#[derive(Copy, Clone, Eq, PartialEq)]
12847pub struct P500PfsHa_SPEC;
12848impl crate::sealed::RegSpec for P500PfsHa_SPEC {
12849    type DataType = u16;
12850}
12851
12852#[doc = "Port 500 Pin Function Select Register"]
12853pub type P500PfsHa = crate::RegValueT<P500PfsHa_SPEC>;
12854
12855impl P500PfsHa {
12856    #[doc = "Port Output Data"]
12857    #[inline(always)]
12858    pub fn podr(
12859        self,
12860    ) -> crate::common::RegisterField<
12861        0,
12862        0x1,
12863        1,
12864        0,
12865        p500pfs_ha::Podr,
12866        p500pfs_ha::Podr,
12867        P500PfsHa_SPEC,
12868        crate::common::RW,
12869    > {
12870        crate::common::RegisterField::<
12871            0,
12872            0x1,
12873            1,
12874            0,
12875            p500pfs_ha::Podr,
12876            p500pfs_ha::Podr,
12877            P500PfsHa_SPEC,
12878            crate::common::RW,
12879        >::from_register(self, 0)
12880    }
12881
12882    #[doc = "Port State"]
12883    #[inline(always)]
12884    pub fn pidr(
12885        self,
12886    ) -> crate::common::RegisterField<
12887        1,
12888        0x1,
12889        1,
12890        0,
12891        p500pfs_ha::Pidr,
12892        p500pfs_ha::Pidr,
12893        P500PfsHa_SPEC,
12894        crate::common::R,
12895    > {
12896        crate::common::RegisterField::<
12897            1,
12898            0x1,
12899            1,
12900            0,
12901            p500pfs_ha::Pidr,
12902            p500pfs_ha::Pidr,
12903            P500PfsHa_SPEC,
12904            crate::common::R,
12905        >::from_register(self, 0)
12906    }
12907
12908    #[doc = "Port Direction"]
12909    #[inline(always)]
12910    pub fn pdr(
12911        self,
12912    ) -> crate::common::RegisterField<
12913        2,
12914        0x1,
12915        1,
12916        0,
12917        p500pfs_ha::Pdr,
12918        p500pfs_ha::Pdr,
12919        P500PfsHa_SPEC,
12920        crate::common::RW,
12921    > {
12922        crate::common::RegisterField::<
12923            2,
12924            0x1,
12925            1,
12926            0,
12927            p500pfs_ha::Pdr,
12928            p500pfs_ha::Pdr,
12929            P500PfsHa_SPEC,
12930            crate::common::RW,
12931        >::from_register(self, 0)
12932    }
12933
12934    #[doc = "Pull-up Control"]
12935    #[inline(always)]
12936    pub fn pcr(
12937        self,
12938    ) -> crate::common::RegisterField<
12939        4,
12940        0x1,
12941        1,
12942        0,
12943        p500pfs_ha::Pcr,
12944        p500pfs_ha::Pcr,
12945        P500PfsHa_SPEC,
12946        crate::common::RW,
12947    > {
12948        crate::common::RegisterField::<
12949            4,
12950            0x1,
12951            1,
12952            0,
12953            p500pfs_ha::Pcr,
12954            p500pfs_ha::Pcr,
12955            P500PfsHa_SPEC,
12956            crate::common::RW,
12957        >::from_register(self, 0)
12958    }
12959
12960    #[doc = "N-Channel Open-Drain Control"]
12961    #[inline(always)]
12962    pub fn ncodr(
12963        self,
12964    ) -> crate::common::RegisterField<
12965        6,
12966        0x1,
12967        1,
12968        0,
12969        p500pfs_ha::Ncodr,
12970        p500pfs_ha::Ncodr,
12971        P500PfsHa_SPEC,
12972        crate::common::RW,
12973    > {
12974        crate::common::RegisterField::<
12975            6,
12976            0x1,
12977            1,
12978            0,
12979            p500pfs_ha::Ncodr,
12980            p500pfs_ha::Ncodr,
12981            P500PfsHa_SPEC,
12982            crate::common::RW,
12983        >::from_register(self, 0)
12984    }
12985
12986    #[doc = "IRQ Input Enable"]
12987    #[inline(always)]
12988    pub fn isel(
12989        self,
12990    ) -> crate::common::RegisterField<
12991        14,
12992        0x1,
12993        1,
12994        0,
12995        p500pfs_ha::Isel,
12996        p500pfs_ha::Isel,
12997        P500PfsHa_SPEC,
12998        crate::common::RW,
12999    > {
13000        crate::common::RegisterField::<
13001            14,
13002            0x1,
13003            1,
13004            0,
13005            p500pfs_ha::Isel,
13006            p500pfs_ha::Isel,
13007            P500PfsHa_SPEC,
13008            crate::common::RW,
13009        >::from_register(self, 0)
13010    }
13011
13012    #[doc = "Analog Input Enable"]
13013    #[inline(always)]
13014    pub fn asel(
13015        self,
13016    ) -> crate::common::RegisterField<
13017        15,
13018        0x1,
13019        1,
13020        0,
13021        p500pfs_ha::Asel,
13022        p500pfs_ha::Asel,
13023        P500PfsHa_SPEC,
13024        crate::common::RW,
13025    > {
13026        crate::common::RegisterField::<
13027            15,
13028            0x1,
13029            1,
13030            0,
13031            p500pfs_ha::Asel,
13032            p500pfs_ha::Asel,
13033            P500PfsHa_SPEC,
13034            crate::common::RW,
13035        >::from_register(self, 0)
13036    }
13037}
13038impl ::core::default::Default for P500PfsHa {
13039    #[inline(always)]
13040    fn default() -> P500PfsHa {
13041        <crate::RegValueT<P500PfsHa_SPEC> as RegisterValue<_>>::new(0)
13042    }
13043}
13044pub mod p500pfs_ha {
13045
13046    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13047    pub struct Podr_SPEC;
13048    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
13049    impl Podr {
13050        #[doc = "Output low"]
13051        pub const _0: Self = Self::new(0);
13052
13053        #[doc = "Output high"]
13054        pub const _1: Self = Self::new(1);
13055    }
13056    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13057    pub struct Pidr_SPEC;
13058    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
13059    impl Pidr {
13060        #[doc = "Low level"]
13061        pub const _0: Self = Self::new(0);
13062
13063        #[doc = "High level"]
13064        pub const _1: Self = Self::new(1);
13065    }
13066    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13067    pub struct Pdr_SPEC;
13068    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
13069    impl Pdr {
13070        #[doc = "Input (functions as an input pin)"]
13071        pub const _0: Self = Self::new(0);
13072
13073        #[doc = "Output (functions as an output pin)"]
13074        pub const _1: Self = Self::new(1);
13075    }
13076    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13077    pub struct Pcr_SPEC;
13078    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
13079    impl Pcr {
13080        #[doc = "Disable input pull-up"]
13081        pub const _0: Self = Self::new(0);
13082
13083        #[doc = "Enable input pull-up"]
13084        pub const _1: Self = Self::new(1);
13085    }
13086    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13087    pub struct Ncodr_SPEC;
13088    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
13089    impl Ncodr {
13090        #[doc = "Output CMOS"]
13091        pub const _0: Self = Self::new(0);
13092
13093        #[doc = "Output NMOS open-drain"]
13094        pub const _1: Self = Self::new(1);
13095    }
13096    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13097    pub struct Isel_SPEC;
13098    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
13099    impl Isel {
13100        #[doc = "Do not use as IRQn input pin"]
13101        pub const _0: Self = Self::new(0);
13102
13103        #[doc = "Use as IRQn input pin"]
13104        pub const _1: Self = Self::new(1);
13105    }
13106    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13107    pub struct Asel_SPEC;
13108    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
13109    impl Asel {
13110        #[doc = "Do not use as analog pin"]
13111        pub const _0: Self = Self::new(0);
13112
13113        #[doc = "Use as analog pin"]
13114        pub const _1: Self = Self::new(1);
13115    }
13116}
13117#[doc(hidden)]
13118#[derive(Copy, Clone, Eq, PartialEq)]
13119pub struct P500PfsBy_SPEC;
13120impl crate::sealed::RegSpec for P500PfsBy_SPEC {
13121    type DataType = u8;
13122}
13123
13124#[doc = "Port 500 Pin Function Select Register"]
13125pub type P500PfsBy = crate::RegValueT<P500PfsBy_SPEC>;
13126
13127impl P500PfsBy {
13128    #[doc = "Port Output Data"]
13129    #[inline(always)]
13130    pub fn podr(
13131        self,
13132    ) -> crate::common::RegisterField<
13133        0,
13134        0x1,
13135        1,
13136        0,
13137        p500pfs_by::Podr,
13138        p500pfs_by::Podr,
13139        P500PfsBy_SPEC,
13140        crate::common::RW,
13141    > {
13142        crate::common::RegisterField::<
13143            0,
13144            0x1,
13145            1,
13146            0,
13147            p500pfs_by::Podr,
13148            p500pfs_by::Podr,
13149            P500PfsBy_SPEC,
13150            crate::common::RW,
13151        >::from_register(self, 0)
13152    }
13153
13154    #[doc = "Port State"]
13155    #[inline(always)]
13156    pub fn pidr(
13157        self,
13158    ) -> crate::common::RegisterField<
13159        1,
13160        0x1,
13161        1,
13162        0,
13163        p500pfs_by::Pidr,
13164        p500pfs_by::Pidr,
13165        P500PfsBy_SPEC,
13166        crate::common::R,
13167    > {
13168        crate::common::RegisterField::<
13169            1,
13170            0x1,
13171            1,
13172            0,
13173            p500pfs_by::Pidr,
13174            p500pfs_by::Pidr,
13175            P500PfsBy_SPEC,
13176            crate::common::R,
13177        >::from_register(self, 0)
13178    }
13179
13180    #[doc = "Port Direction"]
13181    #[inline(always)]
13182    pub fn pdr(
13183        self,
13184    ) -> crate::common::RegisterField<
13185        2,
13186        0x1,
13187        1,
13188        0,
13189        p500pfs_by::Pdr,
13190        p500pfs_by::Pdr,
13191        P500PfsBy_SPEC,
13192        crate::common::RW,
13193    > {
13194        crate::common::RegisterField::<
13195            2,
13196            0x1,
13197            1,
13198            0,
13199            p500pfs_by::Pdr,
13200            p500pfs_by::Pdr,
13201            P500PfsBy_SPEC,
13202            crate::common::RW,
13203        >::from_register(self, 0)
13204    }
13205
13206    #[doc = "Pull-up Control"]
13207    #[inline(always)]
13208    pub fn pcr(
13209        self,
13210    ) -> crate::common::RegisterField<
13211        4,
13212        0x1,
13213        1,
13214        0,
13215        p500pfs_by::Pcr,
13216        p500pfs_by::Pcr,
13217        P500PfsBy_SPEC,
13218        crate::common::RW,
13219    > {
13220        crate::common::RegisterField::<
13221            4,
13222            0x1,
13223            1,
13224            0,
13225            p500pfs_by::Pcr,
13226            p500pfs_by::Pcr,
13227            P500PfsBy_SPEC,
13228            crate::common::RW,
13229        >::from_register(self, 0)
13230    }
13231
13232    #[doc = "N-Channel Open-Drain Control"]
13233    #[inline(always)]
13234    pub fn ncodr(
13235        self,
13236    ) -> crate::common::RegisterField<
13237        6,
13238        0x1,
13239        1,
13240        0,
13241        p500pfs_by::Ncodr,
13242        p500pfs_by::Ncodr,
13243        P500PfsBy_SPEC,
13244        crate::common::RW,
13245    > {
13246        crate::common::RegisterField::<
13247            6,
13248            0x1,
13249            1,
13250            0,
13251            p500pfs_by::Ncodr,
13252            p500pfs_by::Ncodr,
13253            P500PfsBy_SPEC,
13254            crate::common::RW,
13255        >::from_register(self, 0)
13256    }
13257}
13258impl ::core::default::Default for P500PfsBy {
13259    #[inline(always)]
13260    fn default() -> P500PfsBy {
13261        <crate::RegValueT<P500PfsBy_SPEC> as RegisterValue<_>>::new(0)
13262    }
13263}
13264pub mod p500pfs_by {
13265
13266    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13267    pub struct Podr_SPEC;
13268    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
13269    impl Podr {
13270        #[doc = "Output low"]
13271        pub const _0: Self = Self::new(0);
13272
13273        #[doc = "Output high"]
13274        pub const _1: Self = Self::new(1);
13275    }
13276    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13277    pub struct Pidr_SPEC;
13278    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
13279    impl Pidr {
13280        #[doc = "Low level"]
13281        pub const _0: Self = Self::new(0);
13282
13283        #[doc = "High level"]
13284        pub const _1: Self = Self::new(1);
13285    }
13286    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13287    pub struct Pdr_SPEC;
13288    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
13289    impl Pdr {
13290        #[doc = "Input (functions as an input pin)"]
13291        pub const _0: Self = Self::new(0);
13292
13293        #[doc = "Output (functions as an output pin)"]
13294        pub const _1: Self = Self::new(1);
13295    }
13296    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13297    pub struct Pcr_SPEC;
13298    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
13299    impl Pcr {
13300        #[doc = "Disable input pull-up"]
13301        pub const _0: Self = Self::new(0);
13302
13303        #[doc = "Enable input pull-up"]
13304        pub const _1: Self = Self::new(1);
13305    }
13306    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13307    pub struct Ncodr_SPEC;
13308    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
13309    impl Ncodr {
13310        #[doc = "Output CMOS"]
13311        pub const _0: Self = Self::new(0);
13312
13313        #[doc = "Output NMOS open-drain"]
13314        pub const _1: Self = Self::new(1);
13315    }
13316}
13317#[doc(hidden)]
13318#[derive(Copy, Clone, Eq, PartialEq)]
13319pub struct P9Pfs_SPEC;
13320impl crate::sealed::RegSpec for P9Pfs_SPEC {
13321    type DataType = u32;
13322}
13323
13324#[doc = "Port 9%s Pin Function Select Register"]
13325pub type P9Pfs = crate::RegValueT<P9Pfs_SPEC>;
13326
13327impl P9Pfs {
13328    #[doc = "Port Output Data"]
13329    #[inline(always)]
13330    pub fn podr(
13331        self,
13332    ) -> crate::common::RegisterField<
13333        0,
13334        0x1,
13335        1,
13336        0,
13337        p9pfs::Podr,
13338        p9pfs::Podr,
13339        P9Pfs_SPEC,
13340        crate::common::RW,
13341    > {
13342        crate::common::RegisterField::<
13343            0,
13344            0x1,
13345            1,
13346            0,
13347            p9pfs::Podr,
13348            p9pfs::Podr,
13349            P9Pfs_SPEC,
13350            crate::common::RW,
13351        >::from_register(self, 0)
13352    }
13353
13354    #[doc = "Port State"]
13355    #[inline(always)]
13356    pub fn pidr(
13357        self,
13358    ) -> crate::common::RegisterField<
13359        1,
13360        0x1,
13361        1,
13362        0,
13363        p9pfs::Pidr,
13364        p9pfs::Pidr,
13365        P9Pfs_SPEC,
13366        crate::common::R,
13367    > {
13368        crate::common::RegisterField::<
13369            1,
13370            0x1,
13371            1,
13372            0,
13373            p9pfs::Pidr,
13374            p9pfs::Pidr,
13375            P9Pfs_SPEC,
13376            crate::common::R,
13377        >::from_register(self, 0)
13378    }
13379
13380    #[doc = "Port Direction"]
13381    #[inline(always)]
13382    pub fn pdr(
13383        self,
13384    ) -> crate::common::RegisterField<
13385        2,
13386        0x1,
13387        1,
13388        0,
13389        p9pfs::Pdr,
13390        p9pfs::Pdr,
13391        P9Pfs_SPEC,
13392        crate::common::RW,
13393    > {
13394        crate::common::RegisterField::<
13395            2,
13396            0x1,
13397            1,
13398            0,
13399            p9pfs::Pdr,
13400            p9pfs::Pdr,
13401            P9Pfs_SPEC,
13402            crate::common::RW,
13403        >::from_register(self, 0)
13404    }
13405
13406    #[doc = "Pull-up Control"]
13407    #[inline(always)]
13408    pub fn pcr(
13409        self,
13410    ) -> crate::common::RegisterField<
13411        4,
13412        0x1,
13413        1,
13414        0,
13415        p9pfs::Pcr,
13416        p9pfs::Pcr,
13417        P9Pfs_SPEC,
13418        crate::common::RW,
13419    > {
13420        crate::common::RegisterField::<
13421            4,
13422            0x1,
13423            1,
13424            0,
13425            p9pfs::Pcr,
13426            p9pfs::Pcr,
13427            P9Pfs_SPEC,
13428            crate::common::RW,
13429        >::from_register(self, 0)
13430    }
13431
13432    #[doc = "N-Channel Open-Drain Control"]
13433    #[inline(always)]
13434    pub fn ncodr(
13435        self,
13436    ) -> crate::common::RegisterField<
13437        6,
13438        0x1,
13439        1,
13440        0,
13441        p9pfs::Ncodr,
13442        p9pfs::Ncodr,
13443        P9Pfs_SPEC,
13444        crate::common::RW,
13445    > {
13446        crate::common::RegisterField::<
13447            6,
13448            0x1,
13449            1,
13450            0,
13451            p9pfs::Ncodr,
13452            p9pfs::Ncodr,
13453            P9Pfs_SPEC,
13454            crate::common::RW,
13455        >::from_register(self, 0)
13456    }
13457
13458    #[doc = "IRQ Input Enable"]
13459    #[inline(always)]
13460    pub fn isel(
13461        self,
13462    ) -> crate::common::RegisterField<
13463        14,
13464        0x1,
13465        1,
13466        0,
13467        p9pfs::Isel,
13468        p9pfs::Isel,
13469        P9Pfs_SPEC,
13470        crate::common::RW,
13471    > {
13472        crate::common::RegisterField::<
13473            14,
13474            0x1,
13475            1,
13476            0,
13477            p9pfs::Isel,
13478            p9pfs::Isel,
13479            P9Pfs_SPEC,
13480            crate::common::RW,
13481        >::from_register(self, 0)
13482    }
13483
13484    #[doc = "Analog Input Enable"]
13485    #[inline(always)]
13486    pub fn asel(
13487        self,
13488    ) -> crate::common::RegisterField<
13489        15,
13490        0x1,
13491        1,
13492        0,
13493        p9pfs::Asel,
13494        p9pfs::Asel,
13495        P9Pfs_SPEC,
13496        crate::common::RW,
13497    > {
13498        crate::common::RegisterField::<
13499            15,
13500            0x1,
13501            1,
13502            0,
13503            p9pfs::Asel,
13504            p9pfs::Asel,
13505            P9Pfs_SPEC,
13506            crate::common::RW,
13507        >::from_register(self, 0)
13508    }
13509
13510    #[doc = "Port Mode Control"]
13511    #[inline(always)]
13512    pub fn pmr(
13513        self,
13514    ) -> crate::common::RegisterField<
13515        16,
13516        0x1,
13517        1,
13518        0,
13519        p9pfs::Pmr,
13520        p9pfs::Pmr,
13521        P9Pfs_SPEC,
13522        crate::common::RW,
13523    > {
13524        crate::common::RegisterField::<
13525            16,
13526            0x1,
13527            1,
13528            0,
13529            p9pfs::Pmr,
13530            p9pfs::Pmr,
13531            P9Pfs_SPEC,
13532            crate::common::RW,
13533        >::from_register(self, 0)
13534    }
13535
13536    #[doc = "Peripheral Select"]
13537    #[inline(always)]
13538    pub fn psel(
13539        self,
13540    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P9Pfs_SPEC, crate::common::RW> {
13541        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P9Pfs_SPEC,crate::common::RW>::from_register(self,0)
13542    }
13543}
13544impl ::core::default::Default for P9Pfs {
13545    #[inline(always)]
13546    fn default() -> P9Pfs {
13547        <crate::RegValueT<P9Pfs_SPEC> as RegisterValue<_>>::new(0)
13548    }
13549}
13550pub mod p9pfs {
13551
13552    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13553    pub struct Podr_SPEC;
13554    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
13555    impl Podr {
13556        #[doc = "Output low"]
13557        pub const _0: Self = Self::new(0);
13558
13559        #[doc = "Output high"]
13560        pub const _1: Self = Self::new(1);
13561    }
13562    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13563    pub struct Pidr_SPEC;
13564    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
13565    impl Pidr {
13566        #[doc = "Low level"]
13567        pub const _0: Self = Self::new(0);
13568
13569        #[doc = "High level"]
13570        pub const _1: Self = Self::new(1);
13571    }
13572    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13573    pub struct Pdr_SPEC;
13574    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
13575    impl Pdr {
13576        #[doc = "Input (functions as an input pin)"]
13577        pub const _0: Self = Self::new(0);
13578
13579        #[doc = "Output (functions as an output pin)"]
13580        pub const _1: Self = Self::new(1);
13581    }
13582    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13583    pub struct Pcr_SPEC;
13584    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
13585    impl Pcr {
13586        #[doc = "Disable input pull-up"]
13587        pub const _0: Self = Self::new(0);
13588
13589        #[doc = "Enable input pull-up"]
13590        pub const _1: Self = Self::new(1);
13591    }
13592    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13593    pub struct Ncodr_SPEC;
13594    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
13595    impl Ncodr {
13596        #[doc = "Output CMOS"]
13597        pub const _0: Self = Self::new(0);
13598
13599        #[doc = "Output NMOS open-drain"]
13600        pub const _1: Self = Self::new(1);
13601    }
13602    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13603    pub struct Isel_SPEC;
13604    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
13605    impl Isel {
13606        #[doc = "Do not use as IRQn input pin"]
13607        pub const _0: Self = Self::new(0);
13608
13609        #[doc = "Use as IRQn input pin"]
13610        pub const _1: Self = Self::new(1);
13611    }
13612    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13613    pub struct Asel_SPEC;
13614    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
13615    impl Asel {
13616        #[doc = "Do not use as analog pin"]
13617        pub const _0: Self = Self::new(0);
13618
13619        #[doc = "Use as analog pin"]
13620        pub const _1: Self = Self::new(1);
13621    }
13622    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13623    pub struct Pmr_SPEC;
13624    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
13625    impl Pmr {
13626        #[doc = "Use as general I/O pin"]
13627        pub const _0: Self = Self::new(0);
13628
13629        #[doc = "Use as I/O port for peripheral functions"]
13630        pub const _1: Self = Self::new(1);
13631    }
13632}
13633#[doc(hidden)]
13634#[derive(Copy, Clone, Eq, PartialEq)]
13635pub struct P9PfsHa_SPEC;
13636impl crate::sealed::RegSpec for P9PfsHa_SPEC {
13637    type DataType = u16;
13638}
13639
13640#[doc = "Port 9%s Pin Function Select Register"]
13641pub type P9PfsHa = crate::RegValueT<P9PfsHa_SPEC>;
13642
13643impl P9PfsHa {
13644    #[doc = "Port Output Data"]
13645    #[inline(always)]
13646    pub fn podr(
13647        self,
13648    ) -> crate::common::RegisterField<
13649        0,
13650        0x1,
13651        1,
13652        0,
13653        p9pfs_ha::Podr,
13654        p9pfs_ha::Podr,
13655        P9PfsHa_SPEC,
13656        crate::common::RW,
13657    > {
13658        crate::common::RegisterField::<
13659            0,
13660            0x1,
13661            1,
13662            0,
13663            p9pfs_ha::Podr,
13664            p9pfs_ha::Podr,
13665            P9PfsHa_SPEC,
13666            crate::common::RW,
13667        >::from_register(self, 0)
13668    }
13669
13670    #[doc = "Port State"]
13671    #[inline(always)]
13672    pub fn pidr(
13673        self,
13674    ) -> crate::common::RegisterField<
13675        1,
13676        0x1,
13677        1,
13678        0,
13679        p9pfs_ha::Pidr,
13680        p9pfs_ha::Pidr,
13681        P9PfsHa_SPEC,
13682        crate::common::R,
13683    > {
13684        crate::common::RegisterField::<
13685            1,
13686            0x1,
13687            1,
13688            0,
13689            p9pfs_ha::Pidr,
13690            p9pfs_ha::Pidr,
13691            P9PfsHa_SPEC,
13692            crate::common::R,
13693        >::from_register(self, 0)
13694    }
13695
13696    #[doc = "Port Direction"]
13697    #[inline(always)]
13698    pub fn pdr(
13699        self,
13700    ) -> crate::common::RegisterField<
13701        2,
13702        0x1,
13703        1,
13704        0,
13705        p9pfs_ha::Pdr,
13706        p9pfs_ha::Pdr,
13707        P9PfsHa_SPEC,
13708        crate::common::RW,
13709    > {
13710        crate::common::RegisterField::<
13711            2,
13712            0x1,
13713            1,
13714            0,
13715            p9pfs_ha::Pdr,
13716            p9pfs_ha::Pdr,
13717            P9PfsHa_SPEC,
13718            crate::common::RW,
13719        >::from_register(self, 0)
13720    }
13721
13722    #[doc = "Pull-up Control"]
13723    #[inline(always)]
13724    pub fn pcr(
13725        self,
13726    ) -> crate::common::RegisterField<
13727        4,
13728        0x1,
13729        1,
13730        0,
13731        p9pfs_ha::Pcr,
13732        p9pfs_ha::Pcr,
13733        P9PfsHa_SPEC,
13734        crate::common::RW,
13735    > {
13736        crate::common::RegisterField::<
13737            4,
13738            0x1,
13739            1,
13740            0,
13741            p9pfs_ha::Pcr,
13742            p9pfs_ha::Pcr,
13743            P9PfsHa_SPEC,
13744            crate::common::RW,
13745        >::from_register(self, 0)
13746    }
13747
13748    #[doc = "N-Channel Open-Drain Control"]
13749    #[inline(always)]
13750    pub fn ncodr(
13751        self,
13752    ) -> crate::common::RegisterField<
13753        6,
13754        0x1,
13755        1,
13756        0,
13757        p9pfs_ha::Ncodr,
13758        p9pfs_ha::Ncodr,
13759        P9PfsHa_SPEC,
13760        crate::common::RW,
13761    > {
13762        crate::common::RegisterField::<
13763            6,
13764            0x1,
13765            1,
13766            0,
13767            p9pfs_ha::Ncodr,
13768            p9pfs_ha::Ncodr,
13769            P9PfsHa_SPEC,
13770            crate::common::RW,
13771        >::from_register(self, 0)
13772    }
13773
13774    #[doc = "IRQ Input Enable"]
13775    #[inline(always)]
13776    pub fn isel(
13777        self,
13778    ) -> crate::common::RegisterField<
13779        14,
13780        0x1,
13781        1,
13782        0,
13783        p9pfs_ha::Isel,
13784        p9pfs_ha::Isel,
13785        P9PfsHa_SPEC,
13786        crate::common::RW,
13787    > {
13788        crate::common::RegisterField::<
13789            14,
13790            0x1,
13791            1,
13792            0,
13793            p9pfs_ha::Isel,
13794            p9pfs_ha::Isel,
13795            P9PfsHa_SPEC,
13796            crate::common::RW,
13797        >::from_register(self, 0)
13798    }
13799
13800    #[doc = "Analog Input Enable"]
13801    #[inline(always)]
13802    pub fn asel(
13803        self,
13804    ) -> crate::common::RegisterField<
13805        15,
13806        0x1,
13807        1,
13808        0,
13809        p9pfs_ha::Asel,
13810        p9pfs_ha::Asel,
13811        P9PfsHa_SPEC,
13812        crate::common::RW,
13813    > {
13814        crate::common::RegisterField::<
13815            15,
13816            0x1,
13817            1,
13818            0,
13819            p9pfs_ha::Asel,
13820            p9pfs_ha::Asel,
13821            P9PfsHa_SPEC,
13822            crate::common::RW,
13823        >::from_register(self, 0)
13824    }
13825}
13826impl ::core::default::Default for P9PfsHa {
13827    #[inline(always)]
13828    fn default() -> P9PfsHa {
13829        <crate::RegValueT<P9PfsHa_SPEC> as RegisterValue<_>>::new(0)
13830    }
13831}
13832pub mod p9pfs_ha {
13833
13834    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13835    pub struct Podr_SPEC;
13836    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
13837    impl Podr {
13838        #[doc = "Output low"]
13839        pub const _0: Self = Self::new(0);
13840
13841        #[doc = "Output high"]
13842        pub const _1: Self = Self::new(1);
13843    }
13844    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13845    pub struct Pidr_SPEC;
13846    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
13847    impl Pidr {
13848        #[doc = "Low level"]
13849        pub const _0: Self = Self::new(0);
13850
13851        #[doc = "High level"]
13852        pub const _1: Self = Self::new(1);
13853    }
13854    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13855    pub struct Pdr_SPEC;
13856    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
13857    impl Pdr {
13858        #[doc = "Input (functions as an input pin)"]
13859        pub const _0: Self = Self::new(0);
13860
13861        #[doc = "Output (functions as an output pin)"]
13862        pub const _1: Self = Self::new(1);
13863    }
13864    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13865    pub struct Pcr_SPEC;
13866    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
13867    impl Pcr {
13868        #[doc = "Disable input pull-up"]
13869        pub const _0: Self = Self::new(0);
13870
13871        #[doc = "Enable input pull-up"]
13872        pub const _1: Self = Self::new(1);
13873    }
13874    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13875    pub struct Ncodr_SPEC;
13876    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
13877    impl Ncodr {
13878        #[doc = "Output CMOS"]
13879        pub const _0: Self = Self::new(0);
13880
13881        #[doc = "Output NMOS open-drain"]
13882        pub const _1: Self = Self::new(1);
13883    }
13884    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13885    pub struct Isel_SPEC;
13886    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
13887    impl Isel {
13888        #[doc = "Do not use as IRQn input pin"]
13889        pub const _0: Self = Self::new(0);
13890
13891        #[doc = "Use as IRQn input pin"]
13892        pub const _1: Self = Self::new(1);
13893    }
13894    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13895    pub struct Asel_SPEC;
13896    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
13897    impl Asel {
13898        #[doc = "Do not use as analog pin"]
13899        pub const _0: Self = Self::new(0);
13900
13901        #[doc = "Use as analog pin"]
13902        pub const _1: Self = Self::new(1);
13903    }
13904}
13905#[doc(hidden)]
13906#[derive(Copy, Clone, Eq, PartialEq)]
13907pub struct P9PfsBy_SPEC;
13908impl crate::sealed::RegSpec for P9PfsBy_SPEC {
13909    type DataType = u8;
13910}
13911
13912#[doc = "Port 9%s Pin Function Select Register"]
13913pub type P9PfsBy = crate::RegValueT<P9PfsBy_SPEC>;
13914
13915impl P9PfsBy {
13916    #[doc = "Port Output Data"]
13917    #[inline(always)]
13918    pub fn podr(
13919        self,
13920    ) -> crate::common::RegisterField<
13921        0,
13922        0x1,
13923        1,
13924        0,
13925        p9pfs_by::Podr,
13926        p9pfs_by::Podr,
13927        P9PfsBy_SPEC,
13928        crate::common::RW,
13929    > {
13930        crate::common::RegisterField::<
13931            0,
13932            0x1,
13933            1,
13934            0,
13935            p9pfs_by::Podr,
13936            p9pfs_by::Podr,
13937            P9PfsBy_SPEC,
13938            crate::common::RW,
13939        >::from_register(self, 0)
13940    }
13941
13942    #[doc = "Port State"]
13943    #[inline(always)]
13944    pub fn pidr(
13945        self,
13946    ) -> crate::common::RegisterField<
13947        1,
13948        0x1,
13949        1,
13950        0,
13951        p9pfs_by::Pidr,
13952        p9pfs_by::Pidr,
13953        P9PfsBy_SPEC,
13954        crate::common::R,
13955    > {
13956        crate::common::RegisterField::<
13957            1,
13958            0x1,
13959            1,
13960            0,
13961            p9pfs_by::Pidr,
13962            p9pfs_by::Pidr,
13963            P9PfsBy_SPEC,
13964            crate::common::R,
13965        >::from_register(self, 0)
13966    }
13967
13968    #[doc = "Port Direction"]
13969    #[inline(always)]
13970    pub fn pdr(
13971        self,
13972    ) -> crate::common::RegisterField<
13973        2,
13974        0x1,
13975        1,
13976        0,
13977        p9pfs_by::Pdr,
13978        p9pfs_by::Pdr,
13979        P9PfsBy_SPEC,
13980        crate::common::RW,
13981    > {
13982        crate::common::RegisterField::<
13983            2,
13984            0x1,
13985            1,
13986            0,
13987            p9pfs_by::Pdr,
13988            p9pfs_by::Pdr,
13989            P9PfsBy_SPEC,
13990            crate::common::RW,
13991        >::from_register(self, 0)
13992    }
13993
13994    #[doc = "Pull-up Control"]
13995    #[inline(always)]
13996    pub fn pcr(
13997        self,
13998    ) -> crate::common::RegisterField<
13999        4,
14000        0x1,
14001        1,
14002        0,
14003        p9pfs_by::Pcr,
14004        p9pfs_by::Pcr,
14005        P9PfsBy_SPEC,
14006        crate::common::RW,
14007    > {
14008        crate::common::RegisterField::<
14009            4,
14010            0x1,
14011            1,
14012            0,
14013            p9pfs_by::Pcr,
14014            p9pfs_by::Pcr,
14015            P9PfsBy_SPEC,
14016            crate::common::RW,
14017        >::from_register(self, 0)
14018    }
14019
14020    #[doc = "N-Channel Open-Drain Control"]
14021    #[inline(always)]
14022    pub fn ncodr(
14023        self,
14024    ) -> crate::common::RegisterField<
14025        6,
14026        0x1,
14027        1,
14028        0,
14029        p9pfs_by::Ncodr,
14030        p9pfs_by::Ncodr,
14031        P9PfsBy_SPEC,
14032        crate::common::RW,
14033    > {
14034        crate::common::RegisterField::<
14035            6,
14036            0x1,
14037            1,
14038            0,
14039            p9pfs_by::Ncodr,
14040            p9pfs_by::Ncodr,
14041            P9PfsBy_SPEC,
14042            crate::common::RW,
14043        >::from_register(self, 0)
14044    }
14045}
14046impl ::core::default::Default for P9PfsBy {
14047    #[inline(always)]
14048    fn default() -> P9PfsBy {
14049        <crate::RegValueT<P9PfsBy_SPEC> as RegisterValue<_>>::new(0)
14050    }
14051}
14052pub mod p9pfs_by {
14053
14054    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14055    pub struct Podr_SPEC;
14056    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
14057    impl Podr {
14058        #[doc = "Output low"]
14059        pub const _0: Self = Self::new(0);
14060
14061        #[doc = "Output high"]
14062        pub const _1: Self = Self::new(1);
14063    }
14064    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14065    pub struct Pidr_SPEC;
14066    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
14067    impl Pidr {
14068        #[doc = "Low level"]
14069        pub const _0: Self = Self::new(0);
14070
14071        #[doc = "High level"]
14072        pub const _1: Self = Self::new(1);
14073    }
14074    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14075    pub struct Pdr_SPEC;
14076    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
14077    impl Pdr {
14078        #[doc = "Input (functions as an input pin)"]
14079        pub const _0: Self = Self::new(0);
14080
14081        #[doc = "Output (functions as an output pin)"]
14082        pub const _1: Self = Self::new(1);
14083    }
14084    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14085    pub struct Pcr_SPEC;
14086    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
14087    impl Pcr {
14088        #[doc = "Disable input pull-up"]
14089        pub const _0: Self = Self::new(0);
14090
14091        #[doc = "Enable input pull-up"]
14092        pub const _1: Self = Self::new(1);
14093    }
14094    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14095    pub struct Ncodr_SPEC;
14096    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
14097    impl Ncodr {
14098        #[doc = "Output CMOS"]
14099        pub const _0: Self = Self::new(0);
14100
14101        #[doc = "Output NMOS open-drain"]
14102        pub const _1: Self = Self::new(1);
14103    }
14104}
14105#[doc(hidden)]
14106#[derive(Copy, Clone, Eq, PartialEq)]
14107pub struct Pwpr_SPEC;
14108impl crate::sealed::RegSpec for Pwpr_SPEC {
14109    type DataType = u8;
14110}
14111
14112#[doc = "Write-Protect Register"]
14113pub type Pwpr = crate::RegValueT<Pwpr_SPEC>;
14114
14115impl Pwpr {
14116    #[doc = "PmnPFS Register Write Enable"]
14117    #[inline(always)]
14118    pub fn pfswe(
14119        self,
14120    ) -> crate::common::RegisterField<
14121        6,
14122        0x1,
14123        1,
14124        0,
14125        pwpr::Pfswe,
14126        pwpr::Pfswe,
14127        Pwpr_SPEC,
14128        crate::common::RW,
14129    > {
14130        crate::common::RegisterField::<
14131            6,
14132            0x1,
14133            1,
14134            0,
14135            pwpr::Pfswe,
14136            pwpr::Pfswe,
14137            Pwpr_SPEC,
14138            crate::common::RW,
14139        >::from_register(self, 0)
14140    }
14141
14142    #[doc = "PFSWE Bit Write Disable"]
14143    #[inline(always)]
14144    pub fn b0wi(
14145        self,
14146    ) -> crate::common::RegisterField<
14147        7,
14148        0x1,
14149        1,
14150        0,
14151        pwpr::B0Wi,
14152        pwpr::B0Wi,
14153        Pwpr_SPEC,
14154        crate::common::RW,
14155    > {
14156        crate::common::RegisterField::<
14157            7,
14158            0x1,
14159            1,
14160            0,
14161            pwpr::B0Wi,
14162            pwpr::B0Wi,
14163            Pwpr_SPEC,
14164            crate::common::RW,
14165        >::from_register(self, 0)
14166    }
14167}
14168impl ::core::default::Default for Pwpr {
14169    #[inline(always)]
14170    fn default() -> Pwpr {
14171        <crate::RegValueT<Pwpr_SPEC> as RegisterValue<_>>::new(128)
14172    }
14173}
14174pub mod pwpr {
14175
14176    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14177    pub struct Pfswe_SPEC;
14178    pub type Pfswe = crate::EnumBitfieldStruct<u8, Pfswe_SPEC>;
14179    impl Pfswe {
14180        #[doc = "Writing to the PmnPFS register is disabled"]
14181        pub const _0: Self = Self::new(0);
14182
14183        #[doc = "Writing to the PmnPFS register is enabled"]
14184        pub const _1: Self = Self::new(1);
14185    }
14186    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14187    pub struct B0Wi_SPEC;
14188    pub type B0Wi = crate::EnumBitfieldStruct<u8, B0Wi_SPEC>;
14189    impl B0Wi {
14190        #[doc = "Writing to the PFSWE bit is enabled"]
14191        pub const _0: Self = Self::new(0);
14192
14193        #[doc = "Writing to the PFSWE bit is disabled"]
14194        pub const _1: Self = Self::new(1);
14195    }
14196}
14197#[doc(hidden)]
14198#[derive(Copy, Clone, Eq, PartialEq)]
14199pub struct Prwcntr_SPEC;
14200impl crate::sealed::RegSpec for Prwcntr_SPEC {
14201    type DataType = u8;
14202}
14203
14204#[doc = "Port Read Wait Control Register"]
14205pub type Prwcntr = crate::RegValueT<Prwcntr_SPEC>;
14206
14207impl Prwcntr {
14208    #[doc = "Wait Cycle Control"]
14209    #[inline(always)]
14210    pub fn wait(
14211        self,
14212    ) -> crate::common::RegisterField<
14213        0,
14214        0x3,
14215        1,
14216        0,
14217        prwcntr::Wait,
14218        prwcntr::Wait,
14219        Prwcntr_SPEC,
14220        crate::common::RW,
14221    > {
14222        crate::common::RegisterField::<
14223            0,
14224            0x3,
14225            1,
14226            0,
14227            prwcntr::Wait,
14228            prwcntr::Wait,
14229            Prwcntr_SPEC,
14230            crate::common::RW,
14231        >::from_register(self, 0)
14232    }
14233}
14234impl ::core::default::Default for Prwcntr {
14235    #[inline(always)]
14236    fn default() -> Prwcntr {
14237        <crate::RegValueT<Prwcntr_SPEC> as RegisterValue<_>>::new(1)
14238    }
14239}
14240pub mod prwcntr {
14241
14242    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14243    pub struct Wait_SPEC;
14244    pub type Wait = crate::EnumBitfieldStruct<u8, Wait_SPEC>;
14245    impl Wait {
14246        #[doc = "Setting prohibited"]
14247        pub const _00: Self = Self::new(0);
14248
14249        #[doc = "Insert a 1-cycle wait"]
14250        pub const _01: Self = Self::new(1);
14251
14252        #[doc = "Insert a 2-cycle wait"]
14253        pub const _10: Self = Self::new(2);
14254
14255        #[doc = "Insert a 3-cycle wait"]
14256        pub const _11: Self = Self::new(3);
14257    }
14258}
ra2e3_pac/pfs.rs

ra2e3_pac/
pfs.rs
