ra2e2/agtw0/
agtmr1.rs

1#[doc = "Register `AGTMR1` reader"]
2pub struct R(crate::R<AGTMR1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<AGTMR1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<AGTMR1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<AGTMR1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `AGTMR1` writer"]
17pub struct W(crate::W<AGTMR1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<AGTMR1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<AGTMR1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<AGTMR1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TMOD` reader - Operating Mode"]
38pub type TMOD_R = crate::FieldReader<u8, TMOD_A>;
39#[doc = "Operating Mode\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum TMOD_A {
43    #[doc = "0: Timer mode"]
44    _000 = 0,
45    #[doc = "1: Pulse output mode"]
46    _001 = 1,
47    #[doc = "2: Event counter mode"]
48    _010 = 2,
49    #[doc = "3: Pulse width measurement mode"]
50    _011 = 3,
51    #[doc = "4: Pulse period measurement mode"]
52    _100 = 4,
53}
54impl From<TMOD_A> for u8 {
55    #[inline(always)]
56    fn from(variant: TMOD_A) -> Self {
57        variant as _
58    }
59}
60impl TMOD_R {
61    #[doc = "Get enumerated values variant"]
62    #[inline(always)]
63    pub fn variant(&self) -> Option<TMOD_A> {
64        match self.bits {
65            0 => Some(TMOD_A::_000),
66            1 => Some(TMOD_A::_001),
67            2 => Some(TMOD_A::_010),
68            3 => Some(TMOD_A::_011),
69            4 => Some(TMOD_A::_100),
70            _ => None,
71        }
72    }
73    #[doc = "Checks if the value of the field is `_000`"]
74    #[inline(always)]
75    pub fn is_000(&self) -> bool {
76        *self == TMOD_A::_000
77    }
78    #[doc = "Checks if the value of the field is `_001`"]
79    #[inline(always)]
80    pub fn is_001(&self) -> bool {
81        *self == TMOD_A::_001
82    }
83    #[doc = "Checks if the value of the field is `_010`"]
84    #[inline(always)]
85    pub fn is_010(&self) -> bool {
86        *self == TMOD_A::_010
87    }
88    #[doc = "Checks if the value of the field is `_011`"]
89    #[inline(always)]
90    pub fn is_011(&self) -> bool {
91        *self == TMOD_A::_011
92    }
93    #[doc = "Checks if the value of the field is `_100`"]
94    #[inline(always)]
95    pub fn is_100(&self) -> bool {
96        *self == TMOD_A::_100
97    }
98}
99#[doc = "Field `TMOD` writer - Operating Mode"]
100pub type TMOD_W<'a, const O: u8> = crate::FieldWriter<'a, u8, AGTMR1_SPEC, u8, TMOD_A, 3, O>;
101impl<'a, const O: u8> TMOD_W<'a, O> {
102    #[doc = "Timer mode"]
103    #[inline(always)]
104    pub fn _000(self) -> &'a mut W {
105        self.variant(TMOD_A::_000)
106    }
107    #[doc = "Pulse output mode"]
108    #[inline(always)]
109    pub fn _001(self) -> &'a mut W {
110        self.variant(TMOD_A::_001)
111    }
112    #[doc = "Event counter mode"]
113    #[inline(always)]
114    pub fn _010(self) -> &'a mut W {
115        self.variant(TMOD_A::_010)
116    }
117    #[doc = "Pulse width measurement mode"]
118    #[inline(always)]
119    pub fn _011(self) -> &'a mut W {
120        self.variant(TMOD_A::_011)
121    }
122    #[doc = "Pulse period measurement mode"]
123    #[inline(always)]
124    pub fn _100(self) -> &'a mut W {
125        self.variant(TMOD_A::_100)
126    }
127}
128#[doc = "Field `TEDGPL` reader - Edge Polarity"]
129pub type TEDGPL_R = crate::BitReader<TEDGPL_A>;
130#[doc = "Edge Polarity\n\nValue on reset: 0"]
131#[derive(Clone, Copy, Debug, PartialEq, Eq)]
132pub enum TEDGPL_A {
133    #[doc = "0: Single-edge"]
134    _0 = 0,
135    #[doc = "1: Both-edge"]
136    _1 = 1,
137}
138impl From<TEDGPL_A> for bool {
139    #[inline(always)]
140    fn from(variant: TEDGPL_A) -> Self {
141        variant as u8 != 0
142    }
143}
144impl TEDGPL_R {
145    #[doc = "Get enumerated values variant"]
146    #[inline(always)]
147    pub fn variant(&self) -> TEDGPL_A {
148        match self.bits {
149            false => TEDGPL_A::_0,
150            true => TEDGPL_A::_1,
151        }
152    }
153    #[doc = "Checks if the value of the field is `_0`"]
154    #[inline(always)]
155    pub fn is_0(&self) -> bool {
156        *self == TEDGPL_A::_0
157    }
158    #[doc = "Checks if the value of the field is `_1`"]
159    #[inline(always)]
160    pub fn is_1(&self) -> bool {
161        *self == TEDGPL_A::_1
162    }
163}
164#[doc = "Field `TEDGPL` writer - Edge Polarity"]
165pub type TEDGPL_W<'a, const O: u8> = crate::BitWriter<'a, u8, AGTMR1_SPEC, TEDGPL_A, O>;
166impl<'a, const O: u8> TEDGPL_W<'a, O> {
167    #[doc = "Single-edge"]
168    #[inline(always)]
169    pub fn _0(self) -> &'a mut W {
170        self.variant(TEDGPL_A::_0)
171    }
172    #[doc = "Both-edge"]
173    #[inline(always)]
174    pub fn _1(self) -> &'a mut W {
175        self.variant(TEDGPL_A::_1)
176    }
177}
178#[doc = "Field `TCK` reader - Count Source"]
179pub type TCK_R = crate::FieldReader<u8, TCK_A>;
180#[doc = "Count Source\n\nValue on reset: 4"]
181#[derive(Clone, Copy, Debug, PartialEq, Eq)]
182#[repr(u8)]
183pub enum TCK_A {
184    #[doc = "0: PCLKB"]
185    _000 = 0,
186    #[doc = "1: PCLKB/8"]
187    _001 = 1,
188    #[doc = "3: PCLKB/2"]
189    _011 = 3,
190    #[doc = "4: Divided clock AGTLCLK specified by CKS\\[2:0\\]
191bits in the AGTMR2 register"]
192    _100 = 4,
193    #[doc = "5: Underflow event signal from AGTW0"]
194    _101 = 5,
195    #[doc = "6: Setting prohibited"]
196    _110 = 6,
197}
198impl From<TCK_A> for u8 {
199    #[inline(always)]
200    fn from(variant: TCK_A) -> Self {
201        variant as _
202    }
203}
204impl TCK_R {
205    #[doc = "Get enumerated values variant"]
206    #[inline(always)]
207    pub fn variant(&self) -> Option<TCK_A> {
208        match self.bits {
209            0 => Some(TCK_A::_000),
210            1 => Some(TCK_A::_001),
211            3 => Some(TCK_A::_011),
212            4 => Some(TCK_A::_100),
213            5 => Some(TCK_A::_101),
214            6 => Some(TCK_A::_110),
215            _ => None,
216        }
217    }
218    #[doc = "Checks if the value of the field is `_000`"]
219    #[inline(always)]
220    pub fn is_000(&self) -> bool {
221        *self == TCK_A::_000
222    }
223    #[doc = "Checks if the value of the field is `_001`"]
224    #[inline(always)]
225    pub fn is_001(&self) -> bool {
226        *self == TCK_A::_001
227    }
228    #[doc = "Checks if the value of the field is `_011`"]
229    #[inline(always)]
230    pub fn is_011(&self) -> bool {
231        *self == TCK_A::_011
232    }
233    #[doc = "Checks if the value of the field is `_100`"]
234    #[inline(always)]
235    pub fn is_100(&self) -> bool {
236        *self == TCK_A::_100
237    }
238    #[doc = "Checks if the value of the field is `_101`"]
239    #[inline(always)]
240    pub fn is_101(&self) -> bool {
241        *self == TCK_A::_101
242    }
243    #[doc = "Checks if the value of the field is `_110`"]
244    #[inline(always)]
245    pub fn is_110(&self) -> bool {
246        *self == TCK_A::_110
247    }
248}
249#[doc = "Field `TCK` writer - Count Source"]
250pub type TCK_W<'a, const O: u8> = crate::FieldWriter<'a, u8, AGTMR1_SPEC, u8, TCK_A, 3, O>;
251impl<'a, const O: u8> TCK_W<'a, O> {
252    #[doc = "PCLKB"]
253    #[inline(always)]
254    pub fn _000(self) -> &'a mut W {
255        self.variant(TCK_A::_000)
256    }
257    #[doc = "PCLKB/8"]
258    #[inline(always)]
259    pub fn _001(self) -> &'a mut W {
260        self.variant(TCK_A::_001)
261    }
262    #[doc = "PCLKB/2"]
263    #[inline(always)]
264    pub fn _011(self) -> &'a mut W {
265        self.variant(TCK_A::_011)
266    }
267    #[doc = "Divided clock AGTLCLK specified by CKS\\[2:0\\]
268bits in the AGTMR2 register"]
269    #[inline(always)]
270    pub fn _100(self) -> &'a mut W {
271        self.variant(TCK_A::_100)
272    }
273    #[doc = "Underflow event signal from AGTW0"]
274    #[inline(always)]
275    pub fn _101(self) -> &'a mut W {
276        self.variant(TCK_A::_101)
277    }
278    #[doc = "Setting prohibited"]
279    #[inline(always)]
280    pub fn _110(self) -> &'a mut W {
281        self.variant(TCK_A::_110)
282    }
283}
284impl R {
285    #[doc = "Bits 0:2 - Operating Mode"]
286    #[inline(always)]
287    pub fn tmod(&self) -> TMOD_R {
288        TMOD_R::new(self.bits & 7)
289    }
290    #[doc = "Bit 3 - Edge Polarity"]
291    #[inline(always)]
292    pub fn tedgpl(&self) -> TEDGPL_R {
293        TEDGPL_R::new(((self.bits >> 3) & 1) != 0)
294    }
295    #[doc = "Bits 4:6 - Count Source"]
296    #[inline(always)]
297    pub fn tck(&self) -> TCK_R {
298        TCK_R::new((self.bits >> 4) & 7)
299    }
300}
301impl W {
302    #[doc = "Bits 0:2 - Operating Mode"]
303    #[inline(always)]
304    #[must_use]
305    pub fn tmod(&mut self) -> TMOD_W<0> {
306        TMOD_W::new(self)
307    }
308    #[doc = "Bit 3 - Edge Polarity"]
309    #[inline(always)]
310    #[must_use]
311    pub fn tedgpl(&mut self) -> TEDGPL_W<3> {
312        TEDGPL_W::new(self)
313    }
314    #[doc = "Bits 4:6 - Count Source"]
315    #[inline(always)]
316    #[must_use]
317    pub fn tck(&mut self) -> TCK_W<4> {
318        TCK_W::new(self)
319    }
320    #[doc = "Writes raw bits to the register."]
321    #[inline(always)]
322    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
323        self.0.bits(bits);
324        self
325    }
326}
327#[doc = "AGT Mode Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [agtmr1](index.html) module"]
328pub struct AGTMR1_SPEC;
329impl crate::RegisterSpec for AGTMR1_SPEC {
330    type Ux = u8;
331}
332#[doc = "`read()` method returns [agtmr1::R](R) reader structure"]
333impl crate::Readable for AGTMR1_SPEC {
334    type Reader = R;
335}
336#[doc = "`write(|w| ..)` method takes [agtmr1::W](W) writer structure"]
337impl crate::Writable for AGTMR1_SPEC {
338    type Writer = W;
339    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
340    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
341}
342#[doc = "`reset()` method sets AGTMR1 to value 0x40"]
343impl crate::Resettable for AGTMR1_SPEC {
344    const RESET_VALUE: Self::Ux = 0x40;
345}
ra2e2/agtw0/agtmr1.rs

ra2e2/agtw0/
agtmr1.rs
