1#[doc = "Register `MMPUCTLA` reader"]
2pub struct R(crate::R<MMPUCTLA_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<MMPUCTLA_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<MMPUCTLA_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<MMPUCTLA_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `MMPUCTLA` writer"]
17pub struct W(crate::W<MMPUCTLA_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<MMPUCTLA_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<MMPUCTLA_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<MMPUCTLA_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ENABLE` reader - Master Group Enable"]
38pub type ENABLE_R = crate::BitReader<ENABLE_A>;
39#[doc = "Master Group Enable\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum ENABLE_A {
42 #[doc = "0: Master group A disabled"]
43 _0 = 0,
44 #[doc = "1: Master group A enabled"]
45 _1 = 1,
46}
47impl From<ENABLE_A> for bool {
48 #[inline(always)]
49 fn from(variant: ENABLE_A) -> Self {
50 variant as u8 != 0
51 }
52}
53impl ENABLE_R {
54 #[doc = "Get enumerated values variant"]
55 #[inline(always)]
56 pub fn variant(&self) -> ENABLE_A {
57 match self.bits {
58 false => ENABLE_A::_0,
59 true => ENABLE_A::_1,
60 }
61 }
62 #[doc = "Checks if the value of the field is `_0`"]
63 #[inline(always)]
64 pub fn is_0(&self) -> bool {
65 *self == ENABLE_A::_0
66 }
67 #[doc = "Checks if the value of the field is `_1`"]
68 #[inline(always)]
69 pub fn is_1(&self) -> bool {
70 *self == ENABLE_A::_1
71 }
72}
73#[doc = "Field `ENABLE` writer - Master Group Enable"]
74pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, MMPUCTLA_SPEC, ENABLE_A, O>;
75impl<'a, const O: u8> ENABLE_W<'a, O> {
76 #[doc = "Master group A disabled"]
77 #[inline(always)]
78 pub fn _0(self) -> &'a mut W {
79 self.variant(ENABLE_A::_0)
80 }
81 #[doc = "Master group A enabled"]
82 #[inline(always)]
83 pub fn _1(self) -> &'a mut W {
84 self.variant(ENABLE_A::_1)
85 }
86}
87#[doc = "Field `OAD` reader - Operation After Detection"]
88pub type OAD_R = crate::BitReader<OAD_A>;
89#[doc = "Operation After Detection\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum OAD_A {
92 #[doc = "0: Non-maskable interrupt"]
93 _0 = 0,
94 #[doc = "1: Reset"]
95 _1 = 1,
96}
97impl From<OAD_A> for bool {
98 #[inline(always)]
99 fn from(variant: OAD_A) -> Self {
100 variant as u8 != 0
101 }
102}
103impl OAD_R {
104 #[doc = "Get enumerated values variant"]
105 #[inline(always)]
106 pub fn variant(&self) -> OAD_A {
107 match self.bits {
108 false => OAD_A::_0,
109 true => OAD_A::_1,
110 }
111 }
112 #[doc = "Checks if the value of the field is `_0`"]
113 #[inline(always)]
114 pub fn is_0(&self) -> bool {
115 *self == OAD_A::_0
116 }
117 #[doc = "Checks if the value of the field is `_1`"]
118 #[inline(always)]
119 pub fn is_1(&self) -> bool {
120 *self == OAD_A::_1
121 }
122}
123#[doc = "Field `OAD` writer - Operation After Detection"]
124pub type OAD_W<'a, const O: u8> = crate::BitWriter<'a, u16, MMPUCTLA_SPEC, OAD_A, O>;
125impl<'a, const O: u8> OAD_W<'a, O> {
126 #[doc = "Non-maskable interrupt"]
127 #[inline(always)]
128 pub fn _0(self) -> &'a mut W {
129 self.variant(OAD_A::_0)
130 }
131 #[doc = "Reset"]
132 #[inline(always)]
133 pub fn _1(self) -> &'a mut W {
134 self.variant(OAD_A::_1)
135 }
136}
137#[doc = "Field `KEY` reader - Key Code"]
138pub type KEY_R = crate::FieldReader<u8, u8>;
139#[doc = "Field `KEY` writer - Key Code"]
140pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, u16, MMPUCTLA_SPEC, u8, u8, 8, O>;
141impl R {
142 #[doc = "Bit 0 - Master Group Enable"]
143 #[inline(always)]
144 pub fn enable(&self) -> ENABLE_R {
145 ENABLE_R::new((self.bits & 1) != 0)
146 }
147 #[doc = "Bit 1 - Operation After Detection"]
148 #[inline(always)]
149 pub fn oad(&self) -> OAD_R {
150 OAD_R::new(((self.bits >> 1) & 1) != 0)
151 }
152 #[doc = "Bits 8:15 - Key Code"]
153 #[inline(always)]
154 pub fn key(&self) -> KEY_R {
155 KEY_R::new(((self.bits >> 8) & 0xff) as u8)
156 }
157}
158impl W {
159 #[doc = "Bit 0 - Master Group Enable"]
160 #[inline(always)]
161 #[must_use]
162 pub fn enable(&mut self) -> ENABLE_W<0> {
163 ENABLE_W::new(self)
164 }
165 #[doc = "Bit 1 - Operation After Detection"]
166 #[inline(always)]
167 #[must_use]
168 pub fn oad(&mut self) -> OAD_W<1> {
169 OAD_W::new(self)
170 }
171 #[doc = "Bits 8:15 - Key Code"]
172 #[inline(always)]
173 #[must_use]
174 pub fn key(&mut self) -> KEY_W<8> {
175 KEY_W::new(self)
176 }
177 #[doc = "Writes raw bits to the register."]
178 #[inline(always)]
179 pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
180 self.0.bits(bits);
181 self
182 }
183}
184#[doc = "Bus Master MPU Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmpuctla](index.html) module"]
185pub struct MMPUCTLA_SPEC;
186impl crate::RegisterSpec for MMPUCTLA_SPEC {
187 type Ux = u16;
188}
189#[doc = "`read()` method returns [mmpuctla::R](R) reader structure"]
190impl crate::Readable for MMPUCTLA_SPEC {
191 type Reader = R;
192}
193#[doc = "`write(|w| ..)` method takes [mmpuctla::W](W) writer structure"]
194impl crate::Writable for MMPUCTLA_SPEC {
195 type Writer = W;
196 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
197 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
198}
199#[doc = "`reset()` method sets MMPUCTLA to value 0"]
200impl crate::Resettable for MMPUCTLA_SPEC {
201 const RESET_VALUE: Self::Ux = 0;
202}