1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"ICU for CPU"]
28unsafe impl ::core::marker::Send for super::Icu {}
29unsafe impl ::core::marker::Sync for super::Icu {}
30impl super::Icu {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "IRQ Control Register %s"]
38 #[inline(always)]
39 pub const fn irqcr(
40 &self,
41 ) -> &'static crate::common::ClusterRegisterArray<
42 crate::common::Reg<self::Irqcr_SPEC, crate::common::RW>,
43 8,
44 0x1,
45 > {
46 unsafe {
47 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
48 }
49 }
50 #[inline(always)]
51 pub const fn irqcr0(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
52 unsafe {
53 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
54 self._svd2pac_as_ptr().add(0x0usize),
55 )
56 }
57 }
58 #[inline(always)]
59 pub const fn irqcr1(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(0x1usize),
63 )
64 }
65 }
66 #[inline(always)]
67 pub const fn irqcr2(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
68 unsafe {
69 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
70 self._svd2pac_as_ptr().add(0x2usize),
71 )
72 }
73 }
74 #[inline(always)]
75 pub const fn irqcr3(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
76 unsafe {
77 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
78 self._svd2pac_as_ptr().add(0x3usize),
79 )
80 }
81 }
82 #[inline(always)]
83 pub const fn irqcr4(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
84 unsafe {
85 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
86 self._svd2pac_as_ptr().add(0x4usize),
87 )
88 }
89 }
90 #[inline(always)]
91 pub const fn irqcr5(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
92 unsafe {
93 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
94 self._svd2pac_as_ptr().add(0x5usize),
95 )
96 }
97 }
98 #[inline(always)]
99 pub const fn irqcr6(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(0x6usize),
103 )
104 }
105 }
106 #[inline(always)]
107 pub const fn irqcr7(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
108 unsafe {
109 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
110 self._svd2pac_as_ptr().add(0x7usize),
111 )
112 }
113 }
114
115 #[doc = "NMI Pin Interrupt Control Register"]
116 #[inline(always)]
117 pub const fn nmicr(&self) -> &'static crate::common::Reg<self::Nmicr_SPEC, crate::common::RW> {
118 unsafe {
119 crate::common::Reg::<self::Nmicr_SPEC, crate::common::RW>::from_ptr(
120 self._svd2pac_as_ptr().add(256usize),
121 )
122 }
123 }
124
125 #[doc = "Non-Maskable Interrupt Enable Register"]
126 #[inline(always)]
127 pub const fn nmier(&self) -> &'static crate::common::Reg<self::Nmier_SPEC, crate::common::RW> {
128 unsafe {
129 crate::common::Reg::<self::Nmier_SPEC, crate::common::RW>::from_ptr(
130 self._svd2pac_as_ptr().add(288usize),
131 )
132 }
133 }
134
135 #[doc = "Non-Maskable Interrupt Status Clear Register"]
136 #[inline(always)]
137 pub const fn nmiclr(
138 &self,
139 ) -> &'static crate::common::Reg<self::Nmiclr_SPEC, crate::common::RW> {
140 unsafe {
141 crate::common::Reg::<self::Nmiclr_SPEC, crate::common::RW>::from_ptr(
142 self._svd2pac_as_ptr().add(304usize),
143 )
144 }
145 }
146
147 #[doc = "Non-Maskable Interrupt Status Register"]
148 #[inline(always)]
149 pub const fn nmisr(&self) -> &'static crate::common::Reg<self::Nmisr_SPEC, crate::common::R> {
150 unsafe {
151 crate::common::Reg::<self::Nmisr_SPEC, crate::common::R>::from_ptr(
152 self._svd2pac_as_ptr().add(320usize),
153 )
154 }
155 }
156
157 #[doc = "Wake Up Interrupt Enable Register"]
158 #[inline(always)]
159 pub const fn wupen(&self) -> &'static crate::common::Reg<self::Wupen_SPEC, crate::common::RW> {
160 unsafe {
161 crate::common::Reg::<self::Wupen_SPEC, crate::common::RW>::from_ptr(
162 self._svd2pac_as_ptr().add(416usize),
163 )
164 }
165 }
166
167 #[doc = "ICU event Enable Register"]
168 #[inline(always)]
169 pub const fn ielen(&self) -> &'static crate::common::Reg<self::Ielen_SPEC, crate::common::RW> {
170 unsafe {
171 crate::common::Reg::<self::Ielen_SPEC, crate::common::RW>::from_ptr(
172 self._svd2pac_as_ptr().add(448usize),
173 )
174 }
175 }
176
177 #[doc = "SYS Event Link Setting Register"]
178 #[inline(always)]
179 pub const fn selsr0(
180 &self,
181 ) -> &'static crate::common::Reg<self::Selsr0_SPEC, crate::common::RW> {
182 unsafe {
183 crate::common::Reg::<self::Selsr0_SPEC, crate::common::RW>::from_ptr(
184 self._svd2pac_as_ptr().add(512usize),
185 )
186 }
187 }
188
189 #[doc = "ICU Event Link Setting Register %s"]
190 #[inline(always)]
191 pub const fn ielsr(
192 &self,
193 ) -> &'static crate::common::ClusterRegisterArray<
194 crate::common::Reg<self::Ielsr_SPEC, crate::common::RW>,
195 32,
196 0x4,
197 > {
198 unsafe {
199 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x300usize))
200 }
201 }
202 #[inline(always)]
203 pub const fn ielsr0(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
204 unsafe {
205 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
206 self._svd2pac_as_ptr().add(0x300usize),
207 )
208 }
209 }
210 #[inline(always)]
211 pub const fn ielsr1(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
212 unsafe {
213 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
214 self._svd2pac_as_ptr().add(0x304usize),
215 )
216 }
217 }
218 #[inline(always)]
219 pub const fn ielsr2(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
220 unsafe {
221 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
222 self._svd2pac_as_ptr().add(0x308usize),
223 )
224 }
225 }
226 #[inline(always)]
227 pub const fn ielsr3(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
228 unsafe {
229 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
230 self._svd2pac_as_ptr().add(0x30cusize),
231 )
232 }
233 }
234 #[inline(always)]
235 pub const fn ielsr4(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
236 unsafe {
237 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
238 self._svd2pac_as_ptr().add(0x310usize),
239 )
240 }
241 }
242 #[inline(always)]
243 pub const fn ielsr5(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
244 unsafe {
245 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
246 self._svd2pac_as_ptr().add(0x314usize),
247 )
248 }
249 }
250 #[inline(always)]
251 pub const fn ielsr6(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
252 unsafe {
253 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
254 self._svd2pac_as_ptr().add(0x318usize),
255 )
256 }
257 }
258 #[inline(always)]
259 pub const fn ielsr7(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
260 unsafe {
261 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
262 self._svd2pac_as_ptr().add(0x31cusize),
263 )
264 }
265 }
266 #[inline(always)]
267 pub const fn ielsr8(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
268 unsafe {
269 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
270 self._svd2pac_as_ptr().add(0x320usize),
271 )
272 }
273 }
274 #[inline(always)]
275 pub const fn ielsr9(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
276 unsafe {
277 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
278 self._svd2pac_as_ptr().add(0x324usize),
279 )
280 }
281 }
282 #[inline(always)]
283 pub const fn ielsr10(
284 &self,
285 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
286 unsafe {
287 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
288 self._svd2pac_as_ptr().add(0x328usize),
289 )
290 }
291 }
292 #[inline(always)]
293 pub const fn ielsr11(
294 &self,
295 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
296 unsafe {
297 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
298 self._svd2pac_as_ptr().add(0x32cusize),
299 )
300 }
301 }
302 #[inline(always)]
303 pub const fn ielsr12(
304 &self,
305 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
306 unsafe {
307 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
308 self._svd2pac_as_ptr().add(0x330usize),
309 )
310 }
311 }
312 #[inline(always)]
313 pub const fn ielsr13(
314 &self,
315 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
316 unsafe {
317 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
318 self._svd2pac_as_ptr().add(0x334usize),
319 )
320 }
321 }
322 #[inline(always)]
323 pub const fn ielsr14(
324 &self,
325 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
326 unsafe {
327 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
328 self._svd2pac_as_ptr().add(0x338usize),
329 )
330 }
331 }
332 #[inline(always)]
333 pub const fn ielsr15(
334 &self,
335 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
336 unsafe {
337 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
338 self._svd2pac_as_ptr().add(0x33cusize),
339 )
340 }
341 }
342 #[inline(always)]
343 pub const fn ielsr16(
344 &self,
345 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
346 unsafe {
347 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
348 self._svd2pac_as_ptr().add(0x340usize),
349 )
350 }
351 }
352 #[inline(always)]
353 pub const fn ielsr17(
354 &self,
355 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
356 unsafe {
357 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
358 self._svd2pac_as_ptr().add(0x344usize),
359 )
360 }
361 }
362 #[inline(always)]
363 pub const fn ielsr18(
364 &self,
365 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
366 unsafe {
367 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
368 self._svd2pac_as_ptr().add(0x348usize),
369 )
370 }
371 }
372 #[inline(always)]
373 pub const fn ielsr19(
374 &self,
375 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
376 unsafe {
377 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
378 self._svd2pac_as_ptr().add(0x34cusize),
379 )
380 }
381 }
382 #[inline(always)]
383 pub const fn ielsr20(
384 &self,
385 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
386 unsafe {
387 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
388 self._svd2pac_as_ptr().add(0x350usize),
389 )
390 }
391 }
392 #[inline(always)]
393 pub const fn ielsr21(
394 &self,
395 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
396 unsafe {
397 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
398 self._svd2pac_as_ptr().add(0x354usize),
399 )
400 }
401 }
402 #[inline(always)]
403 pub const fn ielsr22(
404 &self,
405 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
406 unsafe {
407 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
408 self._svd2pac_as_ptr().add(0x358usize),
409 )
410 }
411 }
412 #[inline(always)]
413 pub const fn ielsr23(
414 &self,
415 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
416 unsafe {
417 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
418 self._svd2pac_as_ptr().add(0x35cusize),
419 )
420 }
421 }
422 #[inline(always)]
423 pub const fn ielsr24(
424 &self,
425 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
426 unsafe {
427 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
428 self._svd2pac_as_ptr().add(0x360usize),
429 )
430 }
431 }
432 #[inline(always)]
433 pub const fn ielsr25(
434 &self,
435 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
436 unsafe {
437 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
438 self._svd2pac_as_ptr().add(0x364usize),
439 )
440 }
441 }
442 #[inline(always)]
443 pub const fn ielsr26(
444 &self,
445 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
446 unsafe {
447 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
448 self._svd2pac_as_ptr().add(0x368usize),
449 )
450 }
451 }
452 #[inline(always)]
453 pub const fn ielsr27(
454 &self,
455 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
456 unsafe {
457 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
458 self._svd2pac_as_ptr().add(0x36cusize),
459 )
460 }
461 }
462 #[inline(always)]
463 pub const fn ielsr28(
464 &self,
465 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
466 unsafe {
467 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
468 self._svd2pac_as_ptr().add(0x370usize),
469 )
470 }
471 }
472 #[inline(always)]
473 pub const fn ielsr29(
474 &self,
475 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
476 unsafe {
477 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
478 self._svd2pac_as_ptr().add(0x374usize),
479 )
480 }
481 }
482 #[inline(always)]
483 pub const fn ielsr30(
484 &self,
485 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
486 unsafe {
487 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
488 self._svd2pac_as_ptr().add(0x378usize),
489 )
490 }
491 }
492 #[inline(always)]
493 pub const fn ielsr31(
494 &self,
495 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
496 unsafe {
497 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
498 self._svd2pac_as_ptr().add(0x37cusize),
499 )
500 }
501 }
502}
503#[doc(hidden)]
504#[derive(Copy, Clone, Eq, PartialEq)]
505pub struct Irqcr_SPEC;
506impl crate::sealed::RegSpec for Irqcr_SPEC {
507 type DataType = u8;
508}
509
510#[doc = "IRQ Control Register %s"]
511pub type Irqcr = crate::RegValueT<Irqcr_SPEC>;
512
513impl Irqcr {
514 #[doc = "IRQi Detection Sense Select"]
515 #[inline(always)]
516 pub fn irqmd(
517 self,
518 ) -> crate::common::RegisterField<
519 0,
520 0x3,
521 1,
522 0,
523 irqcr::Irqmd,
524 irqcr::Irqmd,
525 Irqcr_SPEC,
526 crate::common::RW,
527 > {
528 crate::common::RegisterField::<
529 0,
530 0x3,
531 1,
532 0,
533 irqcr::Irqmd,
534 irqcr::Irqmd,
535 Irqcr_SPEC,
536 crate::common::RW,
537 >::from_register(self, 0)
538 }
539
540 #[doc = "IRQi Digital Filter Sampling Clock Select"]
541 #[inline(always)]
542 pub fn fclksel(
543 self,
544 ) -> crate::common::RegisterField<
545 4,
546 0x3,
547 1,
548 0,
549 irqcr::Fclksel,
550 irqcr::Fclksel,
551 Irqcr_SPEC,
552 crate::common::RW,
553 > {
554 crate::common::RegisterField::<
555 4,
556 0x3,
557 1,
558 0,
559 irqcr::Fclksel,
560 irqcr::Fclksel,
561 Irqcr_SPEC,
562 crate::common::RW,
563 >::from_register(self, 0)
564 }
565
566 #[doc = "IRQi Digital Filter Enable"]
567 #[inline(always)]
568 pub fn flten(
569 self,
570 ) -> crate::common::RegisterField<
571 7,
572 0x1,
573 1,
574 0,
575 irqcr::Flten,
576 irqcr::Flten,
577 Irqcr_SPEC,
578 crate::common::RW,
579 > {
580 crate::common::RegisterField::<
581 7,
582 0x1,
583 1,
584 0,
585 irqcr::Flten,
586 irqcr::Flten,
587 Irqcr_SPEC,
588 crate::common::RW,
589 >::from_register(self, 0)
590 }
591}
592impl ::core::default::Default for Irqcr {
593 #[inline(always)]
594 fn default() -> Irqcr {
595 <crate::RegValueT<Irqcr_SPEC> as RegisterValue<_>>::new(0)
596 }
597}
598pub mod irqcr {
599
600 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
601 pub struct Irqmd_SPEC;
602 pub type Irqmd = crate::EnumBitfieldStruct<u8, Irqmd_SPEC>;
603 impl Irqmd {
604 #[doc = "Falling edge"]
605 pub const _00: Self = Self::new(0);
606
607 #[doc = "Rising edge"]
608 pub const _01: Self = Self::new(1);
609
610 #[doc = "Rising and falling edges"]
611 pub const _10: Self = Self::new(2);
612
613 #[doc = "Low level"]
614 pub const _11: Self = Self::new(3);
615 }
616 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
617 pub struct Fclksel_SPEC;
618 pub type Fclksel = crate::EnumBitfieldStruct<u8, Fclksel_SPEC>;
619 impl Fclksel {
620 #[doc = "PCLKB"]
621 pub const _00: Self = Self::new(0);
622
623 #[doc = "PCLKB/8"]
624 pub const _01: Self = Self::new(1);
625
626 #[doc = "PCLKB/32"]
627 pub const _10: Self = Self::new(2);
628
629 #[doc = "PCLKB/64"]
630 pub const _11: Self = Self::new(3);
631 }
632 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
633 pub struct Flten_SPEC;
634 pub type Flten = crate::EnumBitfieldStruct<u8, Flten_SPEC>;
635 impl Flten {
636 #[doc = "Digital filter is disabled"]
637 pub const _0: Self = Self::new(0);
638
639 #[doc = "Digital filter is enabled."]
640 pub const _1: Self = Self::new(1);
641 }
642}
643#[doc(hidden)]
644#[derive(Copy, Clone, Eq, PartialEq)]
645pub struct Nmicr_SPEC;
646impl crate::sealed::RegSpec for Nmicr_SPEC {
647 type DataType = u8;
648}
649
650#[doc = "NMI Pin Interrupt Control Register"]
651pub type Nmicr = crate::RegValueT<Nmicr_SPEC>;
652
653impl Nmicr {
654 #[doc = "NMI Detection Set"]
655 #[inline(always)]
656 pub fn nmimd(
657 self,
658 ) -> crate::common::RegisterField<
659 0,
660 0x1,
661 1,
662 0,
663 nmicr::Nmimd,
664 nmicr::Nmimd,
665 Nmicr_SPEC,
666 crate::common::RW,
667 > {
668 crate::common::RegisterField::<
669 0,
670 0x1,
671 1,
672 0,
673 nmicr::Nmimd,
674 nmicr::Nmimd,
675 Nmicr_SPEC,
676 crate::common::RW,
677 >::from_register(self, 0)
678 }
679
680 #[doc = "NMI Digital Filter Sampling Clock Select"]
681 #[inline(always)]
682 pub fn nfclksel(
683 self,
684 ) -> crate::common::RegisterField<
685 4,
686 0x3,
687 1,
688 0,
689 nmicr::Nfclksel,
690 nmicr::Nfclksel,
691 Nmicr_SPEC,
692 crate::common::RW,
693 > {
694 crate::common::RegisterField::<
695 4,
696 0x3,
697 1,
698 0,
699 nmicr::Nfclksel,
700 nmicr::Nfclksel,
701 Nmicr_SPEC,
702 crate::common::RW,
703 >::from_register(self, 0)
704 }
705
706 #[doc = "NMI Digital Filter Enable"]
707 #[inline(always)]
708 pub fn nflten(
709 self,
710 ) -> crate::common::RegisterField<
711 7,
712 0x1,
713 1,
714 0,
715 nmicr::Nflten,
716 nmicr::Nflten,
717 Nmicr_SPEC,
718 crate::common::RW,
719 > {
720 crate::common::RegisterField::<
721 7,
722 0x1,
723 1,
724 0,
725 nmicr::Nflten,
726 nmicr::Nflten,
727 Nmicr_SPEC,
728 crate::common::RW,
729 >::from_register(self, 0)
730 }
731}
732impl ::core::default::Default for Nmicr {
733 #[inline(always)]
734 fn default() -> Nmicr {
735 <crate::RegValueT<Nmicr_SPEC> as RegisterValue<_>>::new(0)
736 }
737}
738pub mod nmicr {
739
740 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
741 pub struct Nmimd_SPEC;
742 pub type Nmimd = crate::EnumBitfieldStruct<u8, Nmimd_SPEC>;
743 impl Nmimd {
744 #[doc = "Falling edge"]
745 pub const _0: Self = Self::new(0);
746
747 #[doc = "Rising edge"]
748 pub const _1: Self = Self::new(1);
749 }
750 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
751 pub struct Nfclksel_SPEC;
752 pub type Nfclksel = crate::EnumBitfieldStruct<u8, Nfclksel_SPEC>;
753 impl Nfclksel {
754 #[doc = "PCLKB"]
755 pub const _00: Self = Self::new(0);
756
757 #[doc = "PCLKB/8"]
758 pub const _01: Self = Self::new(1);
759
760 #[doc = "PCLKB/32"]
761 pub const _10: Self = Self::new(2);
762
763 #[doc = "PCLKB/64"]
764 pub const _11: Self = Self::new(3);
765 }
766 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
767 pub struct Nflten_SPEC;
768 pub type Nflten = crate::EnumBitfieldStruct<u8, Nflten_SPEC>;
769 impl Nflten {
770 #[doc = "Disabled."]
771 pub const _0: Self = Self::new(0);
772
773 #[doc = "Enabled."]
774 pub const _1: Self = Self::new(1);
775 }
776}
777#[doc(hidden)]
778#[derive(Copy, Clone, Eq, PartialEq)]
779pub struct Nmier_SPEC;
780impl crate::sealed::RegSpec for Nmier_SPEC {
781 type DataType = u16;
782}
783
784#[doc = "Non-Maskable Interrupt Enable Register"]
785pub type Nmier = crate::RegValueT<Nmier_SPEC>;
786
787impl Nmier {
788 #[doc = "IWDT Underflow/Refresh Error Interrupt Enable"]
789 #[inline(always)]
790 pub fn iwdten(
791 self,
792 ) -> crate::common::RegisterField<
793 0,
794 0x1,
795 1,
796 0,
797 nmier::Iwdten,
798 nmier::Iwdten,
799 Nmier_SPEC,
800 crate::common::RW,
801 > {
802 crate::common::RegisterField::<
803 0,
804 0x1,
805 1,
806 0,
807 nmier::Iwdten,
808 nmier::Iwdten,
809 Nmier_SPEC,
810 crate::common::RW,
811 >::from_register(self, 0)
812 }
813
814 #[doc = "WDT Underflow/Refresh Error Interrupt Enable"]
815 #[inline(always)]
816 pub fn wdten(
817 self,
818 ) -> crate::common::RegisterField<
819 1,
820 0x1,
821 1,
822 0,
823 nmier::Wdten,
824 nmier::Wdten,
825 Nmier_SPEC,
826 crate::common::RW,
827 > {
828 crate::common::RegisterField::<
829 1,
830 0x1,
831 1,
832 0,
833 nmier::Wdten,
834 nmier::Wdten,
835 Nmier_SPEC,
836 crate::common::RW,
837 >::from_register(self, 0)
838 }
839
840 #[doc = "Voltage monitor 1 Interrupt Enable"]
841 #[inline(always)]
842 pub fn lvd1en(
843 self,
844 ) -> crate::common::RegisterField<
845 2,
846 0x1,
847 1,
848 0,
849 nmier::Lvd1En,
850 nmier::Lvd1En,
851 Nmier_SPEC,
852 crate::common::RW,
853 > {
854 crate::common::RegisterField::<
855 2,
856 0x1,
857 1,
858 0,
859 nmier::Lvd1En,
860 nmier::Lvd1En,
861 Nmier_SPEC,
862 crate::common::RW,
863 >::from_register(self, 0)
864 }
865
866 #[doc = "Voltage monitor 2 Interrupt Enable"]
867 #[inline(always)]
868 pub fn lvd2en(
869 self,
870 ) -> crate::common::RegisterField<
871 3,
872 0x1,
873 1,
874 0,
875 nmier::Lvd2En,
876 nmier::Lvd2En,
877 Nmier_SPEC,
878 crate::common::RW,
879 > {
880 crate::common::RegisterField::<
881 3,
882 0x1,
883 1,
884 0,
885 nmier::Lvd2En,
886 nmier::Lvd2En,
887 Nmier_SPEC,
888 crate::common::RW,
889 >::from_register(self, 0)
890 }
891
892 #[doc = "NMI Pin Interrupt Enable"]
893 #[inline(always)]
894 pub fn nmien(
895 self,
896 ) -> crate::common::RegisterField<
897 7,
898 0x1,
899 1,
900 0,
901 nmier::Nmien,
902 nmier::Nmien,
903 Nmier_SPEC,
904 crate::common::RW,
905 > {
906 crate::common::RegisterField::<
907 7,
908 0x1,
909 1,
910 0,
911 nmier::Nmien,
912 nmier::Nmien,
913 Nmier_SPEC,
914 crate::common::RW,
915 >::from_register(self, 0)
916 }
917
918 #[doc = "SRAM Parity Error Interrupt Enable"]
919 #[inline(always)]
920 pub fn rpeen(
921 self,
922 ) -> crate::common::RegisterField<
923 8,
924 0x1,
925 1,
926 0,
927 nmier::Rpeen,
928 nmier::Rpeen,
929 Nmier_SPEC,
930 crate::common::RW,
931 > {
932 crate::common::RegisterField::<
933 8,
934 0x1,
935 1,
936 0,
937 nmier::Rpeen,
938 nmier::Rpeen,
939 Nmier_SPEC,
940 crate::common::RW,
941 >::from_register(self, 0)
942 }
943
944 #[doc = "Bus Slave MPU Error Interrupt Enable"]
945 #[inline(always)]
946 pub fn bussen(
947 self,
948 ) -> crate::common::RegisterField<
949 10,
950 0x1,
951 1,
952 0,
953 nmier::Bussen,
954 nmier::Bussen,
955 Nmier_SPEC,
956 crate::common::RW,
957 > {
958 crate::common::RegisterField::<
959 10,
960 0x1,
961 1,
962 0,
963 nmier::Bussen,
964 nmier::Bussen,
965 Nmier_SPEC,
966 crate::common::RW,
967 >::from_register(self, 0)
968 }
969
970 #[doc = "Bus Master MPU Error Interrupt Enable"]
971 #[inline(always)]
972 pub fn busmen(
973 self,
974 ) -> crate::common::RegisterField<
975 11,
976 0x1,
977 1,
978 0,
979 nmier::Busmen,
980 nmier::Busmen,
981 Nmier_SPEC,
982 crate::common::RW,
983 > {
984 crate::common::RegisterField::<
985 11,
986 0x1,
987 1,
988 0,
989 nmier::Busmen,
990 nmier::Busmen,
991 Nmier_SPEC,
992 crate::common::RW,
993 >::from_register(self, 0)
994 }
995
996 #[doc = "CPU Stack Pointer Monitor Interrupt Enable"]
997 #[inline(always)]
998 pub fn speen(
999 self,
1000 ) -> crate::common::RegisterField<
1001 12,
1002 0x1,
1003 1,
1004 0,
1005 nmier::Speen,
1006 nmier::Speen,
1007 Nmier_SPEC,
1008 crate::common::RW,
1009 > {
1010 crate::common::RegisterField::<
1011 12,
1012 0x1,
1013 1,
1014 0,
1015 nmier::Speen,
1016 nmier::Speen,
1017 Nmier_SPEC,
1018 crate::common::RW,
1019 >::from_register(self, 0)
1020 }
1021}
1022impl ::core::default::Default for Nmier {
1023 #[inline(always)]
1024 fn default() -> Nmier {
1025 <crate::RegValueT<Nmier_SPEC> as RegisterValue<_>>::new(0)
1026 }
1027}
1028pub mod nmier {
1029
1030 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1031 pub struct Iwdten_SPEC;
1032 pub type Iwdten = crate::EnumBitfieldStruct<u8, Iwdten_SPEC>;
1033 impl Iwdten {
1034 #[doc = "Disabled"]
1035 pub const _0: Self = Self::new(0);
1036
1037 #[doc = "Enabled."]
1038 pub const _1: Self = Self::new(1);
1039 }
1040 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1041 pub struct Wdten_SPEC;
1042 pub type Wdten = crate::EnumBitfieldStruct<u8, Wdten_SPEC>;
1043 impl Wdten {
1044 #[doc = "Disabled"]
1045 pub const _0: Self = Self::new(0);
1046
1047 #[doc = "Enabled"]
1048 pub const _1: Self = Self::new(1);
1049 }
1050 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1051 pub struct Lvd1En_SPEC;
1052 pub type Lvd1En = crate::EnumBitfieldStruct<u8, Lvd1En_SPEC>;
1053 impl Lvd1En {
1054 #[doc = "Disabled"]
1055 pub const _0: Self = Self::new(0);
1056
1057 #[doc = "Enabled"]
1058 pub const _1: Self = Self::new(1);
1059 }
1060 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1061 pub struct Lvd2En_SPEC;
1062 pub type Lvd2En = crate::EnumBitfieldStruct<u8, Lvd2En_SPEC>;
1063 impl Lvd2En {
1064 #[doc = "Disabled"]
1065 pub const _0: Self = Self::new(0);
1066
1067 #[doc = "Enabled"]
1068 pub const _1: Self = Self::new(1);
1069 }
1070 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1071 pub struct Nmien_SPEC;
1072 pub type Nmien = crate::EnumBitfieldStruct<u8, Nmien_SPEC>;
1073 impl Nmien {
1074 #[doc = "Disabled"]
1075 pub const _0: Self = Self::new(0);
1076
1077 #[doc = "Enabled"]
1078 pub const _1: Self = Self::new(1);
1079 }
1080 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1081 pub struct Rpeen_SPEC;
1082 pub type Rpeen = crate::EnumBitfieldStruct<u8, Rpeen_SPEC>;
1083 impl Rpeen {
1084 #[doc = "Disabled"]
1085 pub const _0: Self = Self::new(0);
1086
1087 #[doc = "Enabled"]
1088 pub const _1: Self = Self::new(1);
1089 }
1090 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1091 pub struct Bussen_SPEC;
1092 pub type Bussen = crate::EnumBitfieldStruct<u8, Bussen_SPEC>;
1093 impl Bussen {
1094 #[doc = "Disabled"]
1095 pub const _0: Self = Self::new(0);
1096
1097 #[doc = "Enabled"]
1098 pub const _1: Self = Self::new(1);
1099 }
1100 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1101 pub struct Busmen_SPEC;
1102 pub type Busmen = crate::EnumBitfieldStruct<u8, Busmen_SPEC>;
1103 impl Busmen {
1104 #[doc = "Disabled"]
1105 pub const _0: Self = Self::new(0);
1106
1107 #[doc = "Enabled"]
1108 pub const _1: Self = Self::new(1);
1109 }
1110 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1111 pub struct Speen_SPEC;
1112 pub type Speen = crate::EnumBitfieldStruct<u8, Speen_SPEC>;
1113 impl Speen {
1114 #[doc = "Disabled"]
1115 pub const _0: Self = Self::new(0);
1116
1117 #[doc = "Enabled"]
1118 pub const _1: Self = Self::new(1);
1119 }
1120}
1121#[doc(hidden)]
1122#[derive(Copy, Clone, Eq, PartialEq)]
1123pub struct Nmiclr_SPEC;
1124impl crate::sealed::RegSpec for Nmiclr_SPEC {
1125 type DataType = u16;
1126}
1127
1128#[doc = "Non-Maskable Interrupt Status Clear Register"]
1129pub type Nmiclr = crate::RegValueT<Nmiclr_SPEC>;
1130
1131impl Nmiclr {
1132 #[doc = "IWDT Underflow/Refresh Error Interrupt Status Flag Clear"]
1133 #[inline(always)]
1134 pub fn iwdtclr(
1135 self,
1136 ) -> crate::common::RegisterField<
1137 0,
1138 0x1,
1139 1,
1140 0,
1141 nmiclr::Iwdtclr,
1142 nmiclr::Iwdtclr,
1143 Nmiclr_SPEC,
1144 crate::common::RW,
1145 > {
1146 crate::common::RegisterField::<
1147 0,
1148 0x1,
1149 1,
1150 0,
1151 nmiclr::Iwdtclr,
1152 nmiclr::Iwdtclr,
1153 Nmiclr_SPEC,
1154 crate::common::RW,
1155 >::from_register(self, 0)
1156 }
1157
1158 #[doc = "WDT Underflow/Refresh Error Interrupt Status Flag Clear"]
1159 #[inline(always)]
1160 pub fn wdtclr(
1161 self,
1162 ) -> crate::common::RegisterField<
1163 1,
1164 0x1,
1165 1,
1166 0,
1167 nmiclr::Wdtclr,
1168 nmiclr::Wdtclr,
1169 Nmiclr_SPEC,
1170 crate::common::RW,
1171 > {
1172 crate::common::RegisterField::<
1173 1,
1174 0x1,
1175 1,
1176 0,
1177 nmiclr::Wdtclr,
1178 nmiclr::Wdtclr,
1179 Nmiclr_SPEC,
1180 crate::common::RW,
1181 >::from_register(self, 0)
1182 }
1183
1184 #[doc = "Voltage Monitor 1 Interrupt Status Flag Clear"]
1185 #[inline(always)]
1186 pub fn lvd1clr(
1187 self,
1188 ) -> crate::common::RegisterField<
1189 2,
1190 0x1,
1191 1,
1192 0,
1193 nmiclr::Lvd1Clr,
1194 nmiclr::Lvd1Clr,
1195 Nmiclr_SPEC,
1196 crate::common::RW,
1197 > {
1198 crate::common::RegisterField::<
1199 2,
1200 0x1,
1201 1,
1202 0,
1203 nmiclr::Lvd1Clr,
1204 nmiclr::Lvd1Clr,
1205 Nmiclr_SPEC,
1206 crate::common::RW,
1207 >::from_register(self, 0)
1208 }
1209
1210 #[doc = "Voltage Monitor 2 Interrupt Status Flag Clear"]
1211 #[inline(always)]
1212 pub fn lvd2clr(
1213 self,
1214 ) -> crate::common::RegisterField<
1215 3,
1216 0x1,
1217 1,
1218 0,
1219 nmiclr::Lvd2Clr,
1220 nmiclr::Lvd2Clr,
1221 Nmiclr_SPEC,
1222 crate::common::RW,
1223 > {
1224 crate::common::RegisterField::<
1225 3,
1226 0x1,
1227 1,
1228 0,
1229 nmiclr::Lvd2Clr,
1230 nmiclr::Lvd2Clr,
1231 Nmiclr_SPEC,
1232 crate::common::RW,
1233 >::from_register(self, 0)
1234 }
1235
1236 #[doc = "NMI Pin Interrupt Status Flag Clear"]
1237 #[inline(always)]
1238 pub fn nmiclr(
1239 self,
1240 ) -> crate::common::RegisterField<
1241 7,
1242 0x1,
1243 1,
1244 0,
1245 nmiclr::Nmiclr,
1246 nmiclr::Nmiclr,
1247 Nmiclr_SPEC,
1248 crate::common::RW,
1249 > {
1250 crate::common::RegisterField::<
1251 7,
1252 0x1,
1253 1,
1254 0,
1255 nmiclr::Nmiclr,
1256 nmiclr::Nmiclr,
1257 Nmiclr_SPEC,
1258 crate::common::RW,
1259 >::from_register(self, 0)
1260 }
1261
1262 #[doc = "SRAM Parity Error Interrupt Status Flag Clear"]
1263 #[inline(always)]
1264 pub fn rpeclr(
1265 self,
1266 ) -> crate::common::RegisterField<
1267 8,
1268 0x1,
1269 1,
1270 0,
1271 nmiclr::Rpeclr,
1272 nmiclr::Rpeclr,
1273 Nmiclr_SPEC,
1274 crate::common::RW,
1275 > {
1276 crate::common::RegisterField::<
1277 8,
1278 0x1,
1279 1,
1280 0,
1281 nmiclr::Rpeclr,
1282 nmiclr::Rpeclr,
1283 Nmiclr_SPEC,
1284 crate::common::RW,
1285 >::from_register(self, 0)
1286 }
1287
1288 #[doc = "Bus Slave MPU Error Interrupt Status Flag Clear"]
1289 #[inline(always)]
1290 pub fn bussclr(
1291 self,
1292 ) -> crate::common::RegisterField<
1293 10,
1294 0x1,
1295 1,
1296 0,
1297 nmiclr::Bussclr,
1298 nmiclr::Bussclr,
1299 Nmiclr_SPEC,
1300 crate::common::RW,
1301 > {
1302 crate::common::RegisterField::<
1303 10,
1304 0x1,
1305 1,
1306 0,
1307 nmiclr::Bussclr,
1308 nmiclr::Bussclr,
1309 Nmiclr_SPEC,
1310 crate::common::RW,
1311 >::from_register(self, 0)
1312 }
1313
1314 #[doc = "Bus Master MPU Error Interrupt Status Flag Clear"]
1315 #[inline(always)]
1316 pub fn busmclr(
1317 self,
1318 ) -> crate::common::RegisterField<
1319 11,
1320 0x1,
1321 1,
1322 0,
1323 nmiclr::Busmclr,
1324 nmiclr::Busmclr,
1325 Nmiclr_SPEC,
1326 crate::common::RW,
1327 > {
1328 crate::common::RegisterField::<
1329 11,
1330 0x1,
1331 1,
1332 0,
1333 nmiclr::Busmclr,
1334 nmiclr::Busmclr,
1335 Nmiclr_SPEC,
1336 crate::common::RW,
1337 >::from_register(self, 0)
1338 }
1339
1340 #[doc = "CPU Stack Pointer Monitor Interrupt Status Flag Clear"]
1341 #[inline(always)]
1342 pub fn speclr(
1343 self,
1344 ) -> crate::common::RegisterField<
1345 12,
1346 0x1,
1347 1,
1348 0,
1349 nmiclr::Speclr,
1350 nmiclr::Speclr,
1351 Nmiclr_SPEC,
1352 crate::common::RW,
1353 > {
1354 crate::common::RegisterField::<
1355 12,
1356 0x1,
1357 1,
1358 0,
1359 nmiclr::Speclr,
1360 nmiclr::Speclr,
1361 Nmiclr_SPEC,
1362 crate::common::RW,
1363 >::from_register(self, 0)
1364 }
1365}
1366impl ::core::default::Default for Nmiclr {
1367 #[inline(always)]
1368 fn default() -> Nmiclr {
1369 <crate::RegValueT<Nmiclr_SPEC> as RegisterValue<_>>::new(0)
1370 }
1371}
1372pub mod nmiclr {
1373
1374 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1375 pub struct Iwdtclr_SPEC;
1376 pub type Iwdtclr = crate::EnumBitfieldStruct<u8, Iwdtclr_SPEC>;
1377 impl Iwdtclr {
1378 #[doc = "No effect"]
1379 pub const _0: Self = Self::new(0);
1380
1381 #[doc = "Clear the NMISR.IWDTST flag"]
1382 pub const _1: Self = Self::new(1);
1383 }
1384 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1385 pub struct Wdtclr_SPEC;
1386 pub type Wdtclr = crate::EnumBitfieldStruct<u8, Wdtclr_SPEC>;
1387 impl Wdtclr {
1388 #[doc = "No effect"]
1389 pub const _0: Self = Self::new(0);
1390
1391 #[doc = "Clear the NMISR.WDTST flag"]
1392 pub const _1: Self = Self::new(1);
1393 }
1394 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1395 pub struct Lvd1Clr_SPEC;
1396 pub type Lvd1Clr = crate::EnumBitfieldStruct<u8, Lvd1Clr_SPEC>;
1397 impl Lvd1Clr {
1398 #[doc = "No effect"]
1399 pub const _0: Self = Self::new(0);
1400
1401 #[doc = "Clear the NMISR.LVD1ST flag"]
1402 pub const _1: Self = Self::new(1);
1403 }
1404 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1405 pub struct Lvd2Clr_SPEC;
1406 pub type Lvd2Clr = crate::EnumBitfieldStruct<u8, Lvd2Clr_SPEC>;
1407 impl Lvd2Clr {
1408 #[doc = "No effect"]
1409 pub const _0: Self = Self::new(0);
1410
1411 #[doc = "Clear the NMISR.LVD2ST flag."]
1412 pub const _1: Self = Self::new(1);
1413 }
1414 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1415 pub struct Nmiclr_SPEC;
1416 pub type Nmiclr = crate::EnumBitfieldStruct<u8, Nmiclr_SPEC>;
1417 impl Nmiclr {
1418 #[doc = "No effect"]
1419 pub const _0: Self = Self::new(0);
1420
1421 #[doc = "Clear the NMISR.NMIST flag"]
1422 pub const _1: Self = Self::new(1);
1423 }
1424 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1425 pub struct Rpeclr_SPEC;
1426 pub type Rpeclr = crate::EnumBitfieldStruct<u8, Rpeclr_SPEC>;
1427 impl Rpeclr {
1428 #[doc = "No effect"]
1429 pub const _0: Self = Self::new(0);
1430
1431 #[doc = "Clear the NMISR.RPEST flag"]
1432 pub const _1: Self = Self::new(1);
1433 }
1434 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1435 pub struct Bussclr_SPEC;
1436 pub type Bussclr = crate::EnumBitfieldStruct<u8, Bussclr_SPEC>;
1437 impl Bussclr {
1438 #[doc = "No effect"]
1439 pub const _0: Self = Self::new(0);
1440
1441 #[doc = "Clear the NMISR.BUSSST flag"]
1442 pub const _1: Self = Self::new(1);
1443 }
1444 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1445 pub struct Busmclr_SPEC;
1446 pub type Busmclr = crate::EnumBitfieldStruct<u8, Busmclr_SPEC>;
1447 impl Busmclr {
1448 #[doc = "No effect"]
1449 pub const _0: Self = Self::new(0);
1450
1451 #[doc = "Clear the NMISR.BUSMST flag"]
1452 pub const _1: Self = Self::new(1);
1453 }
1454 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1455 pub struct Speclr_SPEC;
1456 pub type Speclr = crate::EnumBitfieldStruct<u8, Speclr_SPEC>;
1457 impl Speclr {
1458 #[doc = "No effect"]
1459 pub const _0: Self = Self::new(0);
1460
1461 #[doc = "Clear the NMISR.SPEST flag"]
1462 pub const _1: Self = Self::new(1);
1463 }
1464}
1465#[doc(hidden)]
1466#[derive(Copy, Clone, Eq, PartialEq)]
1467pub struct Nmisr_SPEC;
1468impl crate::sealed::RegSpec for Nmisr_SPEC {
1469 type DataType = u16;
1470}
1471
1472#[doc = "Non-Maskable Interrupt Status Register"]
1473pub type Nmisr = crate::RegValueT<Nmisr_SPEC>;
1474
1475impl Nmisr {
1476 #[doc = "IWDT Underflow/Refresh Error Interrupt Status Flag"]
1477 #[inline(always)]
1478 pub fn iwdtst(
1479 self,
1480 ) -> crate::common::RegisterField<
1481 0,
1482 0x1,
1483 1,
1484 0,
1485 nmisr::Iwdtst,
1486 nmisr::Iwdtst,
1487 Nmisr_SPEC,
1488 crate::common::R,
1489 > {
1490 crate::common::RegisterField::<
1491 0,
1492 0x1,
1493 1,
1494 0,
1495 nmisr::Iwdtst,
1496 nmisr::Iwdtst,
1497 Nmisr_SPEC,
1498 crate::common::R,
1499 >::from_register(self, 0)
1500 }
1501
1502 #[doc = "WDT Underflow/Refresh Error Interrupt Status Flag"]
1503 #[inline(always)]
1504 pub fn wdtst(
1505 self,
1506 ) -> crate::common::RegisterField<
1507 1,
1508 0x1,
1509 1,
1510 0,
1511 nmisr::Wdtst,
1512 nmisr::Wdtst,
1513 Nmisr_SPEC,
1514 crate::common::R,
1515 > {
1516 crate::common::RegisterField::<
1517 1,
1518 0x1,
1519 1,
1520 0,
1521 nmisr::Wdtst,
1522 nmisr::Wdtst,
1523 Nmisr_SPEC,
1524 crate::common::R,
1525 >::from_register(self, 0)
1526 }
1527
1528 #[doc = "Voltage Monitor 1 Interrupt Status Flag"]
1529 #[inline(always)]
1530 pub fn lvd1st(
1531 self,
1532 ) -> crate::common::RegisterField<
1533 2,
1534 0x1,
1535 1,
1536 0,
1537 nmisr::Lvd1St,
1538 nmisr::Lvd1St,
1539 Nmisr_SPEC,
1540 crate::common::R,
1541 > {
1542 crate::common::RegisterField::<
1543 2,
1544 0x1,
1545 1,
1546 0,
1547 nmisr::Lvd1St,
1548 nmisr::Lvd1St,
1549 Nmisr_SPEC,
1550 crate::common::R,
1551 >::from_register(self, 0)
1552 }
1553
1554 #[doc = "Voltage Monitor 2 Interrupt Status Flag"]
1555 #[inline(always)]
1556 pub fn lvd2st(
1557 self,
1558 ) -> crate::common::RegisterField<
1559 3,
1560 0x1,
1561 1,
1562 0,
1563 nmisr::Lvd2St,
1564 nmisr::Lvd2St,
1565 Nmisr_SPEC,
1566 crate::common::R,
1567 > {
1568 crate::common::RegisterField::<
1569 3,
1570 0x1,
1571 1,
1572 0,
1573 nmisr::Lvd2St,
1574 nmisr::Lvd2St,
1575 Nmisr_SPEC,
1576 crate::common::R,
1577 >::from_register(self, 0)
1578 }
1579
1580 #[doc = "NMI Pin Interrupt Status Flag"]
1581 #[inline(always)]
1582 pub fn nmist(
1583 self,
1584 ) -> crate::common::RegisterField<
1585 7,
1586 0x1,
1587 1,
1588 0,
1589 nmisr::Nmist,
1590 nmisr::Nmist,
1591 Nmisr_SPEC,
1592 crate::common::R,
1593 > {
1594 crate::common::RegisterField::<
1595 7,
1596 0x1,
1597 1,
1598 0,
1599 nmisr::Nmist,
1600 nmisr::Nmist,
1601 Nmisr_SPEC,
1602 crate::common::R,
1603 >::from_register(self, 0)
1604 }
1605
1606 #[doc = "SRAM Parity Error Interrupt Status Flag"]
1607 #[inline(always)]
1608 pub fn rpest(
1609 self,
1610 ) -> crate::common::RegisterField<
1611 8,
1612 0x1,
1613 1,
1614 0,
1615 nmisr::Rpest,
1616 nmisr::Rpest,
1617 Nmisr_SPEC,
1618 crate::common::R,
1619 > {
1620 crate::common::RegisterField::<
1621 8,
1622 0x1,
1623 1,
1624 0,
1625 nmisr::Rpest,
1626 nmisr::Rpest,
1627 Nmisr_SPEC,
1628 crate::common::R,
1629 >::from_register(self, 0)
1630 }
1631
1632 #[doc = "Bus Slave MPU Error Interrupt Status Flag"]
1633 #[inline(always)]
1634 pub fn bussst(
1635 self,
1636 ) -> crate::common::RegisterField<
1637 10,
1638 0x1,
1639 1,
1640 0,
1641 nmisr::Bussst,
1642 nmisr::Bussst,
1643 Nmisr_SPEC,
1644 crate::common::R,
1645 > {
1646 crate::common::RegisterField::<
1647 10,
1648 0x1,
1649 1,
1650 0,
1651 nmisr::Bussst,
1652 nmisr::Bussst,
1653 Nmisr_SPEC,
1654 crate::common::R,
1655 >::from_register(self, 0)
1656 }
1657
1658 #[doc = "Bus Master MPU Error Interrupt Status Flag"]
1659 #[inline(always)]
1660 pub fn busmst(
1661 self,
1662 ) -> crate::common::RegisterField<
1663 11,
1664 0x1,
1665 1,
1666 0,
1667 nmisr::Busmst,
1668 nmisr::Busmst,
1669 Nmisr_SPEC,
1670 crate::common::R,
1671 > {
1672 crate::common::RegisterField::<
1673 11,
1674 0x1,
1675 1,
1676 0,
1677 nmisr::Busmst,
1678 nmisr::Busmst,
1679 Nmisr_SPEC,
1680 crate::common::R,
1681 >::from_register(self, 0)
1682 }
1683
1684 #[doc = "CPU Stack Pointer Monitor Interrupt Status Flag"]
1685 #[inline(always)]
1686 pub fn spest(
1687 self,
1688 ) -> crate::common::RegisterField<
1689 12,
1690 0x1,
1691 1,
1692 0,
1693 nmisr::Spest,
1694 nmisr::Spest,
1695 Nmisr_SPEC,
1696 crate::common::R,
1697 > {
1698 crate::common::RegisterField::<
1699 12,
1700 0x1,
1701 1,
1702 0,
1703 nmisr::Spest,
1704 nmisr::Spest,
1705 Nmisr_SPEC,
1706 crate::common::R,
1707 >::from_register(self, 0)
1708 }
1709}
1710impl ::core::default::Default for Nmisr {
1711 #[inline(always)]
1712 fn default() -> Nmisr {
1713 <crate::RegValueT<Nmisr_SPEC> as RegisterValue<_>>::new(0)
1714 }
1715}
1716pub mod nmisr {
1717
1718 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1719 pub struct Iwdtst_SPEC;
1720 pub type Iwdtst = crate::EnumBitfieldStruct<u8, Iwdtst_SPEC>;
1721 impl Iwdtst {
1722 #[doc = "Interrupt not requested"]
1723 pub const _0: Self = Self::new(0);
1724
1725 #[doc = "Interrupt requested"]
1726 pub const _1: Self = Self::new(1);
1727 }
1728 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1729 pub struct Wdtst_SPEC;
1730 pub type Wdtst = crate::EnumBitfieldStruct<u8, Wdtst_SPEC>;
1731 impl Wdtst {
1732 #[doc = "Interrupt not requested"]
1733 pub const _0: Self = Self::new(0);
1734
1735 #[doc = "Interrupt requested"]
1736 pub const _1: Self = Self::new(1);
1737 }
1738 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1739 pub struct Lvd1St_SPEC;
1740 pub type Lvd1St = crate::EnumBitfieldStruct<u8, Lvd1St_SPEC>;
1741 impl Lvd1St {
1742 #[doc = "Interrupt not requested"]
1743 pub const _0: Self = Self::new(0);
1744
1745 #[doc = "Interrupt requested"]
1746 pub const _1: Self = Self::new(1);
1747 }
1748 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1749 pub struct Lvd2St_SPEC;
1750 pub type Lvd2St = crate::EnumBitfieldStruct<u8, Lvd2St_SPEC>;
1751 impl Lvd2St {
1752 #[doc = "Interrupt not requested"]
1753 pub const _0: Self = Self::new(0);
1754
1755 #[doc = "Interrupt requested"]
1756 pub const _1: Self = Self::new(1);
1757 }
1758 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1759 pub struct Nmist_SPEC;
1760 pub type Nmist = crate::EnumBitfieldStruct<u8, Nmist_SPEC>;
1761 impl Nmist {
1762 #[doc = "Interrupt not requested"]
1763 pub const _0: Self = Self::new(0);
1764
1765 #[doc = "Interrupt requested"]
1766 pub const _1: Self = Self::new(1);
1767 }
1768 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1769 pub struct Rpest_SPEC;
1770 pub type Rpest = crate::EnumBitfieldStruct<u8, Rpest_SPEC>;
1771 impl Rpest {
1772 #[doc = "Interrupt not requested"]
1773 pub const _0: Self = Self::new(0);
1774
1775 #[doc = "Interrupt requested"]
1776 pub const _1: Self = Self::new(1);
1777 }
1778 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1779 pub struct Bussst_SPEC;
1780 pub type Bussst = crate::EnumBitfieldStruct<u8, Bussst_SPEC>;
1781 impl Bussst {
1782 #[doc = "Interrupt not requested"]
1783 pub const _0: Self = Self::new(0);
1784
1785 #[doc = "Interrupt requested."]
1786 pub const _1: Self = Self::new(1);
1787 }
1788 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1789 pub struct Busmst_SPEC;
1790 pub type Busmst = crate::EnumBitfieldStruct<u8, Busmst_SPEC>;
1791 impl Busmst {
1792 #[doc = "Interrupt not requested"]
1793 pub const _0: Self = Self::new(0);
1794
1795 #[doc = "Interrupt requested"]
1796 pub const _1: Self = Self::new(1);
1797 }
1798 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1799 pub struct Spest_SPEC;
1800 pub type Spest = crate::EnumBitfieldStruct<u8, Spest_SPEC>;
1801 impl Spest {
1802 #[doc = "Interrupt not requested"]
1803 pub const _0: Self = Self::new(0);
1804
1805 #[doc = "Interrupt requested"]
1806 pub const _1: Self = Self::new(1);
1807 }
1808}
1809#[doc(hidden)]
1810#[derive(Copy, Clone, Eq, PartialEq)]
1811pub struct Wupen_SPEC;
1812impl crate::sealed::RegSpec for Wupen_SPEC {
1813 type DataType = u32;
1814}
1815
1816#[doc = "Wake Up Interrupt Enable Register"]
1817pub type Wupen = crate::RegValueT<Wupen_SPEC>;
1818
1819impl Wupen {
1820 #[doc = "IRQ Interrupt Software Standby/Snooze Mode Returns Enable"]
1821 #[inline(always)]
1822 pub fn irqwupen(
1823 self,
1824 ) -> crate::common::RegisterField<
1825 0,
1826 0xff,
1827 1,
1828 0,
1829 wupen::Irqwupen,
1830 wupen::Irqwupen,
1831 Wupen_SPEC,
1832 crate::common::RW,
1833 > {
1834 crate::common::RegisterField::<
1835 0,
1836 0xff,
1837 1,
1838 0,
1839 wupen::Irqwupen,
1840 wupen::Irqwupen,
1841 Wupen_SPEC,
1842 crate::common::RW,
1843 >::from_register(self, 0)
1844 }
1845
1846 #[doc = "IWDT Interrupt Software Standby/Snooze Mode Returns Enable"]
1847 #[inline(always)]
1848 pub fn iwdtwupen(
1849 self,
1850 ) -> crate::common::RegisterField<
1851 16,
1852 0x1,
1853 1,
1854 0,
1855 wupen::Iwdtwupen,
1856 wupen::Iwdtwupen,
1857 Wupen_SPEC,
1858 crate::common::RW,
1859 > {
1860 crate::common::RegisterField::<
1861 16,
1862 0x1,
1863 1,
1864 0,
1865 wupen::Iwdtwupen,
1866 wupen::Iwdtwupen,
1867 Wupen_SPEC,
1868 crate::common::RW,
1869 >::from_register(self, 0)
1870 }
1871
1872 #[doc = "Key Interrupt Software Standby/Snooze Mode Returns Enable"]
1873 #[inline(always)]
1874 pub fn keywupen(
1875 self,
1876 ) -> crate::common::RegisterField<
1877 17,
1878 0x1,
1879 1,
1880 0,
1881 wupen::Keywupen,
1882 wupen::Keywupen,
1883 Wupen_SPEC,
1884 crate::common::RW,
1885 > {
1886 crate::common::RegisterField::<
1887 17,
1888 0x1,
1889 1,
1890 0,
1891 wupen::Keywupen,
1892 wupen::Keywupen,
1893 Wupen_SPEC,
1894 crate::common::RW,
1895 >::from_register(self, 0)
1896 }
1897
1898 #[doc = "LVD1 Interrupt Software Standby/Snooze Mode Returns Enable"]
1899 #[inline(always)]
1900 pub fn lvd1wupen(
1901 self,
1902 ) -> crate::common::RegisterField<
1903 18,
1904 0x1,
1905 1,
1906 0,
1907 wupen::Lvd1Wupen,
1908 wupen::Lvd1Wupen,
1909 Wupen_SPEC,
1910 crate::common::RW,
1911 > {
1912 crate::common::RegisterField::<
1913 18,
1914 0x1,
1915 1,
1916 0,
1917 wupen::Lvd1Wupen,
1918 wupen::Lvd1Wupen,
1919 Wupen_SPEC,
1920 crate::common::RW,
1921 >::from_register(self, 0)
1922 }
1923
1924 #[doc = "LVD2 Interrupt Software Standby/Snooze Mode Returns Enable"]
1925 #[inline(always)]
1926 pub fn lvd2wupen(
1927 self,
1928 ) -> crate::common::RegisterField<
1929 19,
1930 0x1,
1931 1,
1932 0,
1933 wupen::Lvd2Wupen,
1934 wupen::Lvd2Wupen,
1935 Wupen_SPEC,
1936 crate::common::RW,
1937 > {
1938 crate::common::RegisterField::<
1939 19,
1940 0x1,
1941 1,
1942 0,
1943 wupen::Lvd2Wupen,
1944 wupen::Lvd2Wupen,
1945 Wupen_SPEC,
1946 crate::common::RW,
1947 >::from_register(self, 0)
1948 }
1949
1950 #[doc = "AGT1 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
1951 #[inline(always)]
1952 pub fn agt1udwupen(
1953 self,
1954 ) -> crate::common::RegisterField<
1955 28,
1956 0x1,
1957 1,
1958 0,
1959 wupen::Agt1Udwupen,
1960 wupen::Agt1Udwupen,
1961 Wupen_SPEC,
1962 crate::common::RW,
1963 > {
1964 crate::common::RegisterField::<
1965 28,
1966 0x1,
1967 1,
1968 0,
1969 wupen::Agt1Udwupen,
1970 wupen::Agt1Udwupen,
1971 Wupen_SPEC,
1972 crate::common::RW,
1973 >::from_register(self, 0)
1974 }
1975
1976 #[doc = "AGT1 Compare Match A Interrupt Software Standby/Snooze Mode Returns Enable"]
1977 #[inline(always)]
1978 pub fn agt1cawupen(
1979 self,
1980 ) -> crate::common::RegisterField<
1981 29,
1982 0x1,
1983 1,
1984 0,
1985 wupen::Agt1Cawupen,
1986 wupen::Agt1Cawupen,
1987 Wupen_SPEC,
1988 crate::common::RW,
1989 > {
1990 crate::common::RegisterField::<
1991 29,
1992 0x1,
1993 1,
1994 0,
1995 wupen::Agt1Cawupen,
1996 wupen::Agt1Cawupen,
1997 Wupen_SPEC,
1998 crate::common::RW,
1999 >::from_register(self, 0)
2000 }
2001
2002 #[doc = "AGT1 Compare Match B Interrupt Software Standby/Snooze Mode Returns Enable"]
2003 #[inline(always)]
2004 pub fn agt1cbwupen(
2005 self,
2006 ) -> crate::common::RegisterField<
2007 30,
2008 0x1,
2009 1,
2010 0,
2011 wupen::Agt1Cbwupen,
2012 wupen::Agt1Cbwupen,
2013 Wupen_SPEC,
2014 crate::common::RW,
2015 > {
2016 crate::common::RegisterField::<
2017 30,
2018 0x1,
2019 1,
2020 0,
2021 wupen::Agt1Cbwupen,
2022 wupen::Agt1Cbwupen,
2023 Wupen_SPEC,
2024 crate::common::RW,
2025 >::from_register(self, 0)
2026 }
2027}
2028impl ::core::default::Default for Wupen {
2029 #[inline(always)]
2030 fn default() -> Wupen {
2031 <crate::RegValueT<Wupen_SPEC> as RegisterValue<_>>::new(0)
2032 }
2033}
2034pub mod wupen {
2035
2036 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2037 pub struct Irqwupen_SPEC;
2038 pub type Irqwupen = crate::EnumBitfieldStruct<u8, Irqwupen_SPEC>;
2039 impl Irqwupen {
2040 #[doc = "Software Standby/Snooze Mode returns by IRQn interrupt disabled"]
2041 pub const _0: Self = Self::new(0);
2042
2043 #[doc = "Software Standby/Snooze Mode returns by IRQn interrupt enabled"]
2044 pub const _1: Self = Self::new(1);
2045 }
2046 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2047 pub struct Iwdtwupen_SPEC;
2048 pub type Iwdtwupen = crate::EnumBitfieldStruct<u8, Iwdtwupen_SPEC>;
2049 impl Iwdtwupen {
2050 #[doc = "Software Standby/Snooze Mode returns by IWDT interrupt disabled"]
2051 pub const _0: Self = Self::new(0);
2052
2053 #[doc = "Software Standby/Snooze Mode returns by IWDT interrupt enabled"]
2054 pub const _1: Self = Self::new(1);
2055 }
2056 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2057 pub struct Keywupen_SPEC;
2058 pub type Keywupen = crate::EnumBitfieldStruct<u8, Keywupen_SPEC>;
2059 impl Keywupen {
2060 #[doc = "Software Standby/Snooze Mode returns by KEY interrupt disabled"]
2061 pub const _0: Self = Self::new(0);
2062
2063 #[doc = "Software Standby/Snooze Mode returns by KEY interrupt enabled"]
2064 pub const _1: Self = Self::new(1);
2065 }
2066 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2067 pub struct Lvd1Wupen_SPEC;
2068 pub type Lvd1Wupen = crate::EnumBitfieldStruct<u8, Lvd1Wupen_SPEC>;
2069 impl Lvd1Wupen {
2070 #[doc = "Software Standby/Snooze Mode returns by LVD1 interrupt disabled"]
2071 pub const _0: Self = Self::new(0);
2072
2073 #[doc = "Software Standby/Snooze Mode returns by LVD1 interrupt enabled"]
2074 pub const _1: Self = Self::new(1);
2075 }
2076 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2077 pub struct Lvd2Wupen_SPEC;
2078 pub type Lvd2Wupen = crate::EnumBitfieldStruct<u8, Lvd2Wupen_SPEC>;
2079 impl Lvd2Wupen {
2080 #[doc = "Software Standby/Snooze Mode returns by LVD2 interrupt disabled"]
2081 pub const _0: Self = Self::new(0);
2082
2083 #[doc = "Software Standby/Snooze Mode returns by LVD2 interrupt enabled"]
2084 pub const _1: Self = Self::new(1);
2085 }
2086 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2087 pub struct Agt1Udwupen_SPEC;
2088 pub type Agt1Udwupen = crate::EnumBitfieldStruct<u8, Agt1Udwupen_SPEC>;
2089 impl Agt1Udwupen {
2090 #[doc = "Software Standby/Snooze Mode returns by AGT1 underflow interrupt disabled"]
2091 pub const _0: Self = Self::new(0);
2092
2093 #[doc = "Software Standby/Snooze Mode returns by AGT1 underflow"]
2094 pub const _1: Self = Self::new(1);
2095 }
2096 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2097 pub struct Agt1Cawupen_SPEC;
2098 pub type Agt1Cawupen = crate::EnumBitfieldStruct<u8, Agt1Cawupen_SPEC>;
2099 impl Agt1Cawupen {
2100 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match A interrupt disabled."]
2101 pub const _0: Self = Self::new(0);
2102
2103 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match A interrupt enabled."]
2104 pub const _1: Self = Self::new(1);
2105 }
2106 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2107 pub struct Agt1Cbwupen_SPEC;
2108 pub type Agt1Cbwupen = crate::EnumBitfieldStruct<u8, Agt1Cbwupen_SPEC>;
2109 impl Agt1Cbwupen {
2110 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match B interrupt disabled."]
2111 pub const _0: Self = Self::new(0);
2112
2113 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match B interrupt enabled."]
2114 pub const _1: Self = Self::new(1);
2115 }
2116}
2117#[doc(hidden)]
2118#[derive(Copy, Clone, Eq, PartialEq)]
2119pub struct Ielen_SPEC;
2120impl crate::sealed::RegSpec for Ielen_SPEC {
2121 type DataType = u8;
2122}
2123
2124#[doc = "ICU event Enable Register"]
2125pub type Ielen = crate::RegValueT<Ielen_SPEC>;
2126
2127impl Ielen {
2128 #[doc = "Parts Asynchronous Interrupts Enable (when LPOPTEN bit = 1)"]
2129 #[inline(always)]
2130 pub fn ielen(
2131 self,
2132 ) -> crate::common::RegisterField<
2133 1,
2134 0x1,
2135 1,
2136 0,
2137 ielen::Ielen,
2138 ielen::Ielen,
2139 Ielen_SPEC,
2140 crate::common::RW,
2141 > {
2142 crate::common::RegisterField::<
2143 1,
2144 0x1,
2145 1,
2146 0,
2147 ielen::Ielen,
2148 ielen::Ielen,
2149 Ielen_SPEC,
2150 crate::common::RW,
2151 >::from_register(self, 0)
2152 }
2153}
2154impl ::core::default::Default for Ielen {
2155 #[inline(always)]
2156 fn default() -> Ielen {
2157 <crate::RegValueT<Ielen_SPEC> as RegisterValue<_>>::new(0)
2158 }
2159}
2160pub mod ielen {
2161
2162 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2163 pub struct Ielen_SPEC;
2164 pub type Ielen = crate::EnumBitfieldStruct<u8, Ielen_SPEC>;
2165 impl Ielen {
2166 #[doc = "Disabled"]
2167 pub const _0: Self = Self::new(0);
2168
2169 #[doc = "Enabled"]
2170 pub const _1: Self = Self::new(1);
2171 }
2172}
2173#[doc(hidden)]
2174#[derive(Copy, Clone, Eq, PartialEq)]
2175pub struct Selsr0_SPEC;
2176impl crate::sealed::RegSpec for Selsr0_SPEC {
2177 type DataType = u16;
2178}
2179
2180#[doc = "SYS Event Link Setting Register"]
2181pub type Selsr0 = crate::RegValueT<Selsr0_SPEC>;
2182
2183impl NoBitfieldReg<Selsr0_SPEC> for Selsr0 {}
2184impl ::core::default::Default for Selsr0 {
2185 #[inline(always)]
2186 fn default() -> Selsr0 {
2187 <crate::RegValueT<Selsr0_SPEC> as RegisterValue<_>>::new(0)
2188 }
2189}
2190
2191#[doc(hidden)]
2192#[derive(Copy, Clone, Eq, PartialEq)]
2193pub struct Ielsr_SPEC;
2194impl crate::sealed::RegSpec for Ielsr_SPEC {
2195 type DataType = u32;
2196}
2197
2198#[doc = "ICU Event Link Setting Register %s"]
2199pub type Ielsr = crate::RegValueT<Ielsr_SPEC>;
2200
2201impl NoBitfieldReg<Ielsr_SPEC> for Ielsr {}
2202impl ::core::default::Default for Ielsr {
2203 #[inline(always)]
2204 fn default() -> Ielsr {
2205 <crate::RegValueT<Ielsr_SPEC> as RegisterValue<_>>::new(0)
2206 }
2207}