1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"General PWM 16-bit Timer 4"]
28unsafe impl ::core::marker::Send for super::Gpt164 {}
29unsafe impl ::core::marker::Sync for super::Gpt164 {}
30impl super::Gpt164 {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "General PWM Timer Write-Protection Register"]
38 #[inline(always)]
39 pub const fn gtwp(&self) -> &'static crate::common::Reg<self::Gtwp_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Gtwp_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(0usize),
43 )
44 }
45 }
46
47 #[doc = "General PWM Timer Software Start Register"]
48 #[inline(always)]
49 pub const fn gtstr(&self) -> &'static crate::common::Reg<self::Gtstr_SPEC, crate::common::RW> {
50 unsafe {
51 crate::common::Reg::<self::Gtstr_SPEC, crate::common::RW>::from_ptr(
52 self._svd2pac_as_ptr().add(4usize),
53 )
54 }
55 }
56
57 #[doc = "General PWM Timer Software Stop Register"]
58 #[inline(always)]
59 pub const fn gtstp(&self) -> &'static crate::common::Reg<self::Gtstp_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Gtstp_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(8usize),
63 )
64 }
65 }
66
67 #[doc = "General PWM Timer Software Clear Register"]
68 #[inline(always)]
69 pub const fn gtclr(&self) -> &'static crate::common::Reg<self::Gtclr_SPEC, crate::common::W> {
70 unsafe {
71 crate::common::Reg::<self::Gtclr_SPEC, crate::common::W>::from_ptr(
72 self._svd2pac_as_ptr().add(12usize),
73 )
74 }
75 }
76
77 #[doc = "General PWM Timer Start Source Select Register"]
78 #[inline(always)]
79 pub const fn gtssr(&self) -> &'static crate::common::Reg<self::Gtssr_SPEC, crate::common::RW> {
80 unsafe {
81 crate::common::Reg::<self::Gtssr_SPEC, crate::common::RW>::from_ptr(
82 self._svd2pac_as_ptr().add(16usize),
83 )
84 }
85 }
86
87 #[doc = "General PWM Timer Stop Source Select Register"]
88 #[inline(always)]
89 pub const fn gtpsr(&self) -> &'static crate::common::Reg<self::Gtpsr_SPEC, crate::common::RW> {
90 unsafe {
91 crate::common::Reg::<self::Gtpsr_SPEC, crate::common::RW>::from_ptr(
92 self._svd2pac_as_ptr().add(20usize),
93 )
94 }
95 }
96
97 #[doc = "General PWM Timer Clear Source Select Register"]
98 #[inline(always)]
99 pub const fn gtcsr(&self) -> &'static crate::common::Reg<self::Gtcsr_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Gtcsr_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(24usize),
103 )
104 }
105 }
106
107 #[doc = "General PWM Timer Up Count Source Select Register"]
108 #[inline(always)]
109 pub const fn gtupsr(
110 &self,
111 ) -> &'static crate::common::Reg<self::Gtupsr_SPEC, crate::common::RW> {
112 unsafe {
113 crate::common::Reg::<self::Gtupsr_SPEC, crate::common::RW>::from_ptr(
114 self._svd2pac_as_ptr().add(28usize),
115 )
116 }
117 }
118
119 #[doc = "General PWM Timer Down Count Source Select Register"]
120 #[inline(always)]
121 pub const fn gtdnsr(
122 &self,
123 ) -> &'static crate::common::Reg<self::Gtdnsr_SPEC, crate::common::RW> {
124 unsafe {
125 crate::common::Reg::<self::Gtdnsr_SPEC, crate::common::RW>::from_ptr(
126 self._svd2pac_as_ptr().add(32usize),
127 )
128 }
129 }
130
131 #[doc = "General PWM Timer Input Capture Source Select Register A"]
132 #[inline(always)]
133 pub const fn gticasr(
134 &self,
135 ) -> &'static crate::common::Reg<self::Gticasr_SPEC, crate::common::RW> {
136 unsafe {
137 crate::common::Reg::<self::Gticasr_SPEC, crate::common::RW>::from_ptr(
138 self._svd2pac_as_ptr().add(36usize),
139 )
140 }
141 }
142
143 #[doc = "General PWM Timer Input Capture Source Select Register B"]
144 #[inline(always)]
145 pub const fn gticbsr(
146 &self,
147 ) -> &'static crate::common::Reg<self::Gticbsr_SPEC, crate::common::RW> {
148 unsafe {
149 crate::common::Reg::<self::Gticbsr_SPEC, crate::common::RW>::from_ptr(
150 self._svd2pac_as_ptr().add(40usize),
151 )
152 }
153 }
154
155 #[doc = "General PWM Timer Control Register"]
156 #[inline(always)]
157 pub const fn gtcr(&self) -> &'static crate::common::Reg<self::Gtcr_SPEC, crate::common::RW> {
158 unsafe {
159 crate::common::Reg::<self::Gtcr_SPEC, crate::common::RW>::from_ptr(
160 self._svd2pac_as_ptr().add(44usize),
161 )
162 }
163 }
164
165 #[doc = "General PWM Timer Count Direction and Duty Setting Register"]
166 #[inline(always)]
167 pub const fn gtuddtyc(
168 &self,
169 ) -> &'static crate::common::Reg<self::Gtuddtyc_SPEC, crate::common::RW> {
170 unsafe {
171 crate::common::Reg::<self::Gtuddtyc_SPEC, crate::common::RW>::from_ptr(
172 self._svd2pac_as_ptr().add(48usize),
173 )
174 }
175 }
176
177 #[doc = "General PWM Timer I/O Control Register"]
178 #[inline(always)]
179 pub const fn gtior(&self) -> &'static crate::common::Reg<self::Gtior_SPEC, crate::common::RW> {
180 unsafe {
181 crate::common::Reg::<self::Gtior_SPEC, crate::common::RW>::from_ptr(
182 self._svd2pac_as_ptr().add(52usize),
183 )
184 }
185 }
186
187 #[doc = "General PWM Timer Interrupt Output Setting Register"]
188 #[inline(always)]
189 pub const fn gtintad(
190 &self,
191 ) -> &'static crate::common::Reg<self::Gtintad_SPEC, crate::common::RW> {
192 unsafe {
193 crate::common::Reg::<self::Gtintad_SPEC, crate::common::RW>::from_ptr(
194 self._svd2pac_as_ptr().add(56usize),
195 )
196 }
197 }
198
199 #[doc = "General PWM Timer Status Register"]
200 #[inline(always)]
201 pub const fn gtst(&self) -> &'static crate::common::Reg<self::Gtst_SPEC, crate::common::RW> {
202 unsafe {
203 crate::common::Reg::<self::Gtst_SPEC, crate::common::RW>::from_ptr(
204 self._svd2pac_as_ptr().add(60usize),
205 )
206 }
207 }
208
209 #[doc = "General PWM Timer Buffer Enable Register"]
210 #[inline(always)]
211 pub const fn gtber(&self) -> &'static crate::common::Reg<self::Gtber_SPEC, crate::common::RW> {
212 unsafe {
213 crate::common::Reg::<self::Gtber_SPEC, crate::common::RW>::from_ptr(
214 self._svd2pac_as_ptr().add(64usize),
215 )
216 }
217 }
218
219 #[doc = "General PWM Timer Counter"]
220 #[inline(always)]
221 pub const fn gtcnt(&self) -> &'static crate::common::Reg<self::Gtcnt_SPEC, crate::common::RW> {
222 unsafe {
223 crate::common::Reg::<self::Gtcnt_SPEC, crate::common::RW>::from_ptr(
224 self._svd2pac_as_ptr().add(72usize),
225 )
226 }
227 }
228
229 #[doc = "General PWM Timer Compare Capture Register A"]
230 #[inline(always)]
231 pub const fn gtccra(
232 &self,
233 ) -> &'static crate::common::Reg<self::Gtccra_SPEC, crate::common::RW> {
234 unsafe {
235 crate::common::Reg::<self::Gtccra_SPEC, crate::common::RW>::from_ptr(
236 self._svd2pac_as_ptr().add(76usize),
237 )
238 }
239 }
240
241 #[doc = "General PWM Timer Compare Capture Register B"]
242 #[inline(always)]
243 pub const fn gtccrb(
244 &self,
245 ) -> &'static crate::common::Reg<self::Gtccrb_SPEC, crate::common::RW> {
246 unsafe {
247 crate::common::Reg::<self::Gtccrb_SPEC, crate::common::RW>::from_ptr(
248 self._svd2pac_as_ptr().add(80usize),
249 )
250 }
251 }
252
253 #[doc = "General PWM Timer Compare Capture Register C"]
254 #[inline(always)]
255 pub const fn gtccrc(
256 &self,
257 ) -> &'static crate::common::Reg<self::Gtccrc_SPEC, crate::common::RW> {
258 unsafe {
259 crate::common::Reg::<self::Gtccrc_SPEC, crate::common::RW>::from_ptr(
260 self._svd2pac_as_ptr().add(84usize),
261 )
262 }
263 }
264
265 #[doc = "General PWM Timer Compare Capture Register E"]
266 #[inline(always)]
267 pub const fn gtccre(
268 &self,
269 ) -> &'static crate::common::Reg<self::Gtccre_SPEC, crate::common::RW> {
270 unsafe {
271 crate::common::Reg::<self::Gtccre_SPEC, crate::common::RW>::from_ptr(
272 self._svd2pac_as_ptr().add(88usize),
273 )
274 }
275 }
276
277 #[doc = "General PWM Timer Compare Capture Register D"]
278 #[inline(always)]
279 pub const fn gtccrd(
280 &self,
281 ) -> &'static crate::common::Reg<self::Gtccrd_SPEC, crate::common::RW> {
282 unsafe {
283 crate::common::Reg::<self::Gtccrd_SPEC, crate::common::RW>::from_ptr(
284 self._svd2pac_as_ptr().add(92usize),
285 )
286 }
287 }
288
289 #[doc = "General PWM Timer Compare Capture Register F"]
290 #[inline(always)]
291 pub const fn gtccrf(
292 &self,
293 ) -> &'static crate::common::Reg<self::Gtccrf_SPEC, crate::common::RW> {
294 unsafe {
295 crate::common::Reg::<self::Gtccrf_SPEC, crate::common::RW>::from_ptr(
296 self._svd2pac_as_ptr().add(96usize),
297 )
298 }
299 }
300
301 #[doc = "General PWM Timer Cycle Setting Register"]
302 #[inline(always)]
303 pub const fn gtpr(&self) -> &'static crate::common::Reg<self::Gtpr_SPEC, crate::common::RW> {
304 unsafe {
305 crate::common::Reg::<self::Gtpr_SPEC, crate::common::RW>::from_ptr(
306 self._svd2pac_as_ptr().add(100usize),
307 )
308 }
309 }
310
311 #[doc = "General PWM Timer Cycle Setting Buffer Register"]
312 #[inline(always)]
313 pub const fn gtpbr(&self) -> &'static crate::common::Reg<self::Gtpbr_SPEC, crate::common::RW> {
314 unsafe {
315 crate::common::Reg::<self::Gtpbr_SPEC, crate::common::RW>::from_ptr(
316 self._svd2pac_as_ptr().add(104usize),
317 )
318 }
319 }
320
321 #[doc = "General PWM Timer Dead Time Control Register"]
322 #[inline(always)]
323 pub const fn gtdtcr(
324 &self,
325 ) -> &'static crate::common::Reg<self::Gtdtcr_SPEC, crate::common::RW> {
326 unsafe {
327 crate::common::Reg::<self::Gtdtcr_SPEC, crate::common::RW>::from_ptr(
328 self._svd2pac_as_ptr().add(136usize),
329 )
330 }
331 }
332
333 #[doc = "General PWM Timer Dead Time Value Register U"]
334 #[inline(always)]
335 pub const fn gtdvu(&self) -> &'static crate::common::Reg<self::Gtdvu_SPEC, crate::common::RW> {
336 unsafe {
337 crate::common::Reg::<self::Gtdvu_SPEC, crate::common::RW>::from_ptr(
338 self._svd2pac_as_ptr().add(140usize),
339 )
340 }
341 }
342}
343#[doc(hidden)]
344#[derive(Copy, Clone, Eq, PartialEq)]
345pub struct Gtwp_SPEC;
346impl crate::sealed::RegSpec for Gtwp_SPEC {
347 type DataType = u32;
348}
349
350#[doc = "General PWM Timer Write-Protection Register"]
351pub type Gtwp = crate::RegValueT<Gtwp_SPEC>;
352
353impl Gtwp {
354 #[doc = "Register Write Disable"]
355 #[inline(always)]
356 pub fn wp(
357 self,
358 ) -> crate::common::RegisterField<0, 0x1, 1, 0, gtwp::Wp, gtwp::Wp, Gtwp_SPEC, crate::common::RW>
359 {
360 crate::common::RegisterField::<0,0x1,1,0,gtwp::Wp,gtwp::Wp,Gtwp_SPEC,crate::common::RW>::from_register(self,0)
361 }
362
363 #[doc = "GTWP Key Code"]
364 #[inline(always)]
365 pub fn prkey(
366 self,
367 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Gtwp_SPEC, crate::common::W> {
368 crate::common::RegisterField::<8,0xff,1,0,u8,u8,Gtwp_SPEC,crate::common::W>::from_register(self,0)
369 }
370}
371impl ::core::default::Default for Gtwp {
372 #[inline(always)]
373 fn default() -> Gtwp {
374 <crate::RegValueT<Gtwp_SPEC> as RegisterValue<_>>::new(0)
375 }
376}
377pub mod gtwp {
378
379 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
380 pub struct Wp_SPEC;
381 pub type Wp = crate::EnumBitfieldStruct<u8, Wp_SPEC>;
382 impl Wp {
383 #[doc = "Write to the register enabled"]
384 pub const _0: Self = Self::new(0);
385
386 #[doc = "Write to the register disabled"]
387 pub const _1: Self = Self::new(1);
388 }
389}
390#[doc(hidden)]
391#[derive(Copy, Clone, Eq, PartialEq)]
392pub struct Gtstr_SPEC;
393impl crate::sealed::RegSpec for Gtstr_SPEC {
394 type DataType = u32;
395}
396
397#[doc = "General PWM Timer Software Start Register"]
398pub type Gtstr = crate::RegValueT<Gtstr_SPEC>;
399
400impl Gtstr {
401 #[doc = "Channel n GTCNT Count Start (n : the same as bit position value)"]
402 #[inline(always)]
403 pub fn cstrt4(
404 self,
405 ) -> crate::common::RegisterField<
406 4,
407 0x1,
408 1,
409 0,
410 gtstr::Cstrt4,
411 gtstr::Cstrt4,
412 Gtstr_SPEC,
413 crate::common::RW,
414 > {
415 crate::common::RegisterField::<
416 4,
417 0x1,
418 1,
419 0,
420 gtstr::Cstrt4,
421 gtstr::Cstrt4,
422 Gtstr_SPEC,
423 crate::common::RW,
424 >::from_register(self, 0)
425 }
426
427 #[doc = "Channel n GTCNT Count Start (n : the same as bit position value)"]
428 #[inline(always)]
429 pub fn cstrt5(
430 self,
431 ) -> crate::common::RegisterField<
432 5,
433 0x1,
434 1,
435 0,
436 gtstr::Cstrt5,
437 gtstr::Cstrt5,
438 Gtstr_SPEC,
439 crate::common::RW,
440 > {
441 crate::common::RegisterField::<
442 5,
443 0x1,
444 1,
445 0,
446 gtstr::Cstrt5,
447 gtstr::Cstrt5,
448 Gtstr_SPEC,
449 crate::common::RW,
450 >::from_register(self, 0)
451 }
452
453 #[doc = "Channel n GTCNT Count Start (n : the same as bit position value)"]
454 #[inline(always)]
455 pub fn cstrt6(
456 self,
457 ) -> crate::common::RegisterField<
458 6,
459 0x1,
460 1,
461 0,
462 gtstr::Cstrt6,
463 gtstr::Cstrt6,
464 Gtstr_SPEC,
465 crate::common::RW,
466 > {
467 crate::common::RegisterField::<
468 6,
469 0x1,
470 1,
471 0,
472 gtstr::Cstrt6,
473 gtstr::Cstrt6,
474 Gtstr_SPEC,
475 crate::common::RW,
476 >::from_register(self, 0)
477 }
478
479 #[doc = "Channel n GTCNT Count Start (n : the same as bit position value)"]
480 #[inline(always)]
481 pub fn cstrt7(
482 self,
483 ) -> crate::common::RegisterField<
484 7,
485 0x1,
486 1,
487 0,
488 gtstr::Cstrt7,
489 gtstr::Cstrt7,
490 Gtstr_SPEC,
491 crate::common::RW,
492 > {
493 crate::common::RegisterField::<
494 7,
495 0x1,
496 1,
497 0,
498 gtstr::Cstrt7,
499 gtstr::Cstrt7,
500 Gtstr_SPEC,
501 crate::common::RW,
502 >::from_register(self, 0)
503 }
504
505 #[doc = "Channel n GTCNT Count Start (n : the same as bit position value)"]
506 #[inline(always)]
507 pub fn cstrt8(
508 self,
509 ) -> crate::common::RegisterField<
510 8,
511 0x1,
512 1,
513 0,
514 gtstr::Cstrt8,
515 gtstr::Cstrt8,
516 Gtstr_SPEC,
517 crate::common::RW,
518 > {
519 crate::common::RegisterField::<
520 8,
521 0x1,
522 1,
523 0,
524 gtstr::Cstrt8,
525 gtstr::Cstrt8,
526 Gtstr_SPEC,
527 crate::common::RW,
528 >::from_register(self, 0)
529 }
530
531 #[doc = "Channel n GTCNT Count Start (n : the same as bit position value)"]
532 #[inline(always)]
533 pub fn cstrt9(
534 self,
535 ) -> crate::common::RegisterField<
536 9,
537 0x1,
538 1,
539 0,
540 gtstr::Cstrt9,
541 gtstr::Cstrt9,
542 Gtstr_SPEC,
543 crate::common::RW,
544 > {
545 crate::common::RegisterField::<
546 9,
547 0x1,
548 1,
549 0,
550 gtstr::Cstrt9,
551 gtstr::Cstrt9,
552 Gtstr_SPEC,
553 crate::common::RW,
554 >::from_register(self, 0)
555 }
556}
557impl ::core::default::Default for Gtstr {
558 #[inline(always)]
559 fn default() -> Gtstr {
560 <crate::RegValueT<Gtstr_SPEC> as RegisterValue<_>>::new(0)
561 }
562}
563pub mod gtstr {
564
565 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
566 pub struct Cstrt4_SPEC;
567 pub type Cstrt4 = crate::EnumBitfieldStruct<u8, Cstrt4_SPEC>;
568 impl Cstrt4 {
569 #[doc = "GTCNT counter not start"]
570 pub const _0: Self = Self::new(0);
571
572 #[doc = "GTCNT counter start"]
573 pub const _1: Self = Self::new(1);
574 }
575 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
576 pub struct Cstrt5_SPEC;
577 pub type Cstrt5 = crate::EnumBitfieldStruct<u8, Cstrt5_SPEC>;
578 impl Cstrt5 {
579 #[doc = "GTCNT counter not start"]
580 pub const _0: Self = Self::new(0);
581
582 #[doc = "GTCNT counter start"]
583 pub const _1: Self = Self::new(1);
584 }
585 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
586 pub struct Cstrt6_SPEC;
587 pub type Cstrt6 = crate::EnumBitfieldStruct<u8, Cstrt6_SPEC>;
588 impl Cstrt6 {
589 #[doc = "GTCNT counter not start"]
590 pub const _0: Self = Self::new(0);
591
592 #[doc = "GTCNT counter start"]
593 pub const _1: Self = Self::new(1);
594 }
595 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
596 pub struct Cstrt7_SPEC;
597 pub type Cstrt7 = crate::EnumBitfieldStruct<u8, Cstrt7_SPEC>;
598 impl Cstrt7 {
599 #[doc = "GTCNT counter not start"]
600 pub const _0: Self = Self::new(0);
601
602 #[doc = "GTCNT counter start"]
603 pub const _1: Self = Self::new(1);
604 }
605 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
606 pub struct Cstrt8_SPEC;
607 pub type Cstrt8 = crate::EnumBitfieldStruct<u8, Cstrt8_SPEC>;
608 impl Cstrt8 {
609 #[doc = "GTCNT counter not start"]
610 pub const _0: Self = Self::new(0);
611
612 #[doc = "GTCNT counter start"]
613 pub const _1: Self = Self::new(1);
614 }
615 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
616 pub struct Cstrt9_SPEC;
617 pub type Cstrt9 = crate::EnumBitfieldStruct<u8, Cstrt9_SPEC>;
618 impl Cstrt9 {
619 #[doc = "GTCNT counter not start"]
620 pub const _0: Self = Self::new(0);
621
622 #[doc = "GTCNT counter start"]
623 pub const _1: Self = Self::new(1);
624 }
625}
626#[doc(hidden)]
627#[derive(Copy, Clone, Eq, PartialEq)]
628pub struct Gtstp_SPEC;
629impl crate::sealed::RegSpec for Gtstp_SPEC {
630 type DataType = u32;
631}
632
633#[doc = "General PWM Timer Software Stop Register"]
634pub type Gtstp = crate::RegValueT<Gtstp_SPEC>;
635
636impl Gtstp {
637 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
638 #[inline(always)]
639 pub fn cstop4(
640 self,
641 ) -> crate::common::RegisterField<
642 4,
643 0x1,
644 1,
645 0,
646 gtstp::Cstop4,
647 gtstp::Cstop4,
648 Gtstp_SPEC,
649 crate::common::RW,
650 > {
651 crate::common::RegisterField::<
652 4,
653 0x1,
654 1,
655 0,
656 gtstp::Cstop4,
657 gtstp::Cstop4,
658 Gtstp_SPEC,
659 crate::common::RW,
660 >::from_register(self, 0)
661 }
662
663 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
664 #[inline(always)]
665 pub fn cstop5(
666 self,
667 ) -> crate::common::RegisterField<
668 5,
669 0x1,
670 1,
671 0,
672 gtstp::Cstop5,
673 gtstp::Cstop5,
674 Gtstp_SPEC,
675 crate::common::RW,
676 > {
677 crate::common::RegisterField::<
678 5,
679 0x1,
680 1,
681 0,
682 gtstp::Cstop5,
683 gtstp::Cstop5,
684 Gtstp_SPEC,
685 crate::common::RW,
686 >::from_register(self, 0)
687 }
688
689 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
690 #[inline(always)]
691 pub fn cstop6(
692 self,
693 ) -> crate::common::RegisterField<
694 6,
695 0x1,
696 1,
697 0,
698 gtstp::Cstop6,
699 gtstp::Cstop6,
700 Gtstp_SPEC,
701 crate::common::RW,
702 > {
703 crate::common::RegisterField::<
704 6,
705 0x1,
706 1,
707 0,
708 gtstp::Cstop6,
709 gtstp::Cstop6,
710 Gtstp_SPEC,
711 crate::common::RW,
712 >::from_register(self, 0)
713 }
714
715 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
716 #[inline(always)]
717 pub fn cstop7(
718 self,
719 ) -> crate::common::RegisterField<
720 7,
721 0x1,
722 1,
723 0,
724 gtstp::Cstop7,
725 gtstp::Cstop7,
726 Gtstp_SPEC,
727 crate::common::RW,
728 > {
729 crate::common::RegisterField::<
730 7,
731 0x1,
732 1,
733 0,
734 gtstp::Cstop7,
735 gtstp::Cstop7,
736 Gtstp_SPEC,
737 crate::common::RW,
738 >::from_register(self, 0)
739 }
740
741 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
742 #[inline(always)]
743 pub fn cstop8(
744 self,
745 ) -> crate::common::RegisterField<
746 8,
747 0x1,
748 1,
749 0,
750 gtstp::Cstop8,
751 gtstp::Cstop8,
752 Gtstp_SPEC,
753 crate::common::RW,
754 > {
755 crate::common::RegisterField::<
756 8,
757 0x1,
758 1,
759 0,
760 gtstp::Cstop8,
761 gtstp::Cstop8,
762 Gtstp_SPEC,
763 crate::common::RW,
764 >::from_register(self, 0)
765 }
766
767 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
768 #[inline(always)]
769 pub fn cstop9(
770 self,
771 ) -> crate::common::RegisterField<
772 9,
773 0x1,
774 1,
775 0,
776 gtstp::Cstop9,
777 gtstp::Cstop9,
778 Gtstp_SPEC,
779 crate::common::RW,
780 > {
781 crate::common::RegisterField::<
782 9,
783 0x1,
784 1,
785 0,
786 gtstp::Cstop9,
787 gtstp::Cstop9,
788 Gtstp_SPEC,
789 crate::common::RW,
790 >::from_register(self, 0)
791 }
792}
793impl ::core::default::Default for Gtstp {
794 #[inline(always)]
795 fn default() -> Gtstp {
796 <crate::RegValueT<Gtstp_SPEC> as RegisterValue<_>>::new(4294967295)
797 }
798}
799pub mod gtstp {
800
801 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
802 pub struct Cstop4_SPEC;
803 pub type Cstop4 = crate::EnumBitfieldStruct<u8, Cstop4_SPEC>;
804 impl Cstop4 {
805 #[doc = "GTCNT counter is not stop"]
806 pub const _0: Self = Self::new(0);
807
808 #[doc = "GTCNT counter stopped"]
809 pub const _1: Self = Self::new(1);
810 }
811 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
812 pub struct Cstop5_SPEC;
813 pub type Cstop5 = crate::EnumBitfieldStruct<u8, Cstop5_SPEC>;
814 impl Cstop5 {
815 #[doc = "GTCNT counter is not stop"]
816 pub const _0: Self = Self::new(0);
817
818 #[doc = "GTCNT counter stopped"]
819 pub const _1: Self = Self::new(1);
820 }
821 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
822 pub struct Cstop6_SPEC;
823 pub type Cstop6 = crate::EnumBitfieldStruct<u8, Cstop6_SPEC>;
824 impl Cstop6 {
825 #[doc = "GTCNT counter is not stop"]
826 pub const _0: Self = Self::new(0);
827
828 #[doc = "GTCNT counter stopped"]
829 pub const _1: Self = Self::new(1);
830 }
831 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
832 pub struct Cstop7_SPEC;
833 pub type Cstop7 = crate::EnumBitfieldStruct<u8, Cstop7_SPEC>;
834 impl Cstop7 {
835 #[doc = "GTCNT counter is not stop"]
836 pub const _0: Self = Self::new(0);
837
838 #[doc = "GTCNT counter stopped"]
839 pub const _1: Self = Self::new(1);
840 }
841 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
842 pub struct Cstop8_SPEC;
843 pub type Cstop8 = crate::EnumBitfieldStruct<u8, Cstop8_SPEC>;
844 impl Cstop8 {
845 #[doc = "GTCNT counter is not stop"]
846 pub const _0: Self = Self::new(0);
847
848 #[doc = "GTCNT counter stopped"]
849 pub const _1: Self = Self::new(1);
850 }
851 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
852 pub struct Cstop9_SPEC;
853 pub type Cstop9 = crate::EnumBitfieldStruct<u8, Cstop9_SPEC>;
854 impl Cstop9 {
855 #[doc = "GTCNT counter is not stop"]
856 pub const _0: Self = Self::new(0);
857
858 #[doc = "GTCNT counter stopped"]
859 pub const _1: Self = Self::new(1);
860 }
861}
862#[doc(hidden)]
863#[derive(Copy, Clone, Eq, PartialEq)]
864pub struct Gtclr_SPEC;
865impl crate::sealed::RegSpec for Gtclr_SPEC {
866 type DataType = u32;
867}
868
869#[doc = "General PWM Timer Software Clear Register"]
870pub type Gtclr = crate::RegValueT<Gtclr_SPEC>;
871
872impl Gtclr {
873 #[doc = "Channel n GTCNT Count Clear (n : the same as bit position value)"]
874 #[inline(always)]
875 pub fn cclr0(
876 self,
877 ) -> crate::common::RegisterField<
878 4,
879 0x1,
880 1,
881 0,
882 gtclr::Cclr0,
883 gtclr::Cclr0,
884 Gtclr_SPEC,
885 crate::common::W,
886 > {
887 crate::common::RegisterField::<
888 4,
889 0x1,
890 1,
891 0,
892 gtclr::Cclr0,
893 gtclr::Cclr0,
894 Gtclr_SPEC,
895 crate::common::W,
896 >::from_register(self, 0)
897 }
898
899 #[doc = "Channel n GTCNT Count Clear (n : the same as bit position value)"]
900 #[inline(always)]
901 pub fn cclr1(
902 self,
903 ) -> crate::common::RegisterField<
904 5,
905 0x1,
906 1,
907 0,
908 gtclr::Cclr1,
909 gtclr::Cclr1,
910 Gtclr_SPEC,
911 crate::common::W,
912 > {
913 crate::common::RegisterField::<
914 5,
915 0x1,
916 1,
917 0,
918 gtclr::Cclr1,
919 gtclr::Cclr1,
920 Gtclr_SPEC,
921 crate::common::W,
922 >::from_register(self, 0)
923 }
924
925 #[doc = "Channel n GTCNT Count Clear (n : the same as bit position value)"]
926 #[inline(always)]
927 pub fn cclr2(
928 self,
929 ) -> crate::common::RegisterField<
930 6,
931 0x1,
932 1,
933 0,
934 gtclr::Cclr2,
935 gtclr::Cclr2,
936 Gtclr_SPEC,
937 crate::common::W,
938 > {
939 crate::common::RegisterField::<
940 6,
941 0x1,
942 1,
943 0,
944 gtclr::Cclr2,
945 gtclr::Cclr2,
946 Gtclr_SPEC,
947 crate::common::W,
948 >::from_register(self, 0)
949 }
950
951 #[doc = "Channel n GTCNT Count Clear (n : the same as bit position value)"]
952 #[inline(always)]
953 pub fn cclr3(
954 self,
955 ) -> crate::common::RegisterField<
956 7,
957 0x1,
958 1,
959 0,
960 gtclr::Cclr3,
961 gtclr::Cclr3,
962 Gtclr_SPEC,
963 crate::common::W,
964 > {
965 crate::common::RegisterField::<
966 7,
967 0x1,
968 1,
969 0,
970 gtclr::Cclr3,
971 gtclr::Cclr3,
972 Gtclr_SPEC,
973 crate::common::W,
974 >::from_register(self, 0)
975 }
976
977 #[doc = "Channel n GTCNT Count Clear (n : the same as bit position value)"]
978 #[inline(always)]
979 pub fn cclr4(
980 self,
981 ) -> crate::common::RegisterField<
982 8,
983 0x1,
984 1,
985 0,
986 gtclr::Cclr4,
987 gtclr::Cclr4,
988 Gtclr_SPEC,
989 crate::common::W,
990 > {
991 crate::common::RegisterField::<
992 8,
993 0x1,
994 1,
995 0,
996 gtclr::Cclr4,
997 gtclr::Cclr4,
998 Gtclr_SPEC,
999 crate::common::W,
1000 >::from_register(self, 0)
1001 }
1002
1003 #[doc = "Channel n GTCNT Count Clear (n : the same as bit position value)"]
1004 #[inline(always)]
1005 pub fn cclr5(
1006 self,
1007 ) -> crate::common::RegisterField<
1008 9,
1009 0x1,
1010 1,
1011 0,
1012 gtclr::Cclr5,
1013 gtclr::Cclr5,
1014 Gtclr_SPEC,
1015 crate::common::W,
1016 > {
1017 crate::common::RegisterField::<
1018 9,
1019 0x1,
1020 1,
1021 0,
1022 gtclr::Cclr5,
1023 gtclr::Cclr5,
1024 Gtclr_SPEC,
1025 crate::common::W,
1026 >::from_register(self, 0)
1027 }
1028
1029 #[doc = "Channel n GTCNT Count Clear (n : the same as bit position value)"]
1030 #[inline(always)]
1031 pub fn cclr6(
1032 self,
1033 ) -> crate::common::RegisterField<
1034 10,
1035 0x1,
1036 1,
1037 0,
1038 gtclr::Cclr6,
1039 gtclr::Cclr6,
1040 Gtclr_SPEC,
1041 crate::common::W,
1042 > {
1043 crate::common::RegisterField::<
1044 10,
1045 0x1,
1046 1,
1047 0,
1048 gtclr::Cclr6,
1049 gtclr::Cclr6,
1050 Gtclr_SPEC,
1051 crate::common::W,
1052 >::from_register(self, 0)
1053 }
1054
1055 #[doc = "Channel n GTCNT Count Clear (n : the same as bit position value)"]
1056 #[inline(always)]
1057 pub fn cclr7(
1058 self,
1059 ) -> crate::common::RegisterField<
1060 11,
1061 0x1,
1062 1,
1063 0,
1064 gtclr::Cclr7,
1065 gtclr::Cclr7,
1066 Gtclr_SPEC,
1067 crate::common::W,
1068 > {
1069 crate::common::RegisterField::<
1070 11,
1071 0x1,
1072 1,
1073 0,
1074 gtclr::Cclr7,
1075 gtclr::Cclr7,
1076 Gtclr_SPEC,
1077 crate::common::W,
1078 >::from_register(self, 0)
1079 }
1080
1081 #[doc = "Channel n GTCNT Count Clear (n : the same as bit position value)"]
1082 #[inline(always)]
1083 pub fn cclr8(
1084 self,
1085 ) -> crate::common::RegisterField<
1086 12,
1087 0x1,
1088 1,
1089 0,
1090 gtclr::Cclr8,
1091 gtclr::Cclr8,
1092 Gtclr_SPEC,
1093 crate::common::W,
1094 > {
1095 crate::common::RegisterField::<
1096 12,
1097 0x1,
1098 1,
1099 0,
1100 gtclr::Cclr8,
1101 gtclr::Cclr8,
1102 Gtclr_SPEC,
1103 crate::common::W,
1104 >::from_register(self, 0)
1105 }
1106
1107 #[doc = "Channel n GTCNT Count Clear (n : the same as bit position value)"]
1108 #[inline(always)]
1109 pub fn cclr9(
1110 self,
1111 ) -> crate::common::RegisterField<
1112 13,
1113 0x1,
1114 1,
1115 0,
1116 gtclr::Cclr9,
1117 gtclr::Cclr9,
1118 Gtclr_SPEC,
1119 crate::common::W,
1120 > {
1121 crate::common::RegisterField::<
1122 13,
1123 0x1,
1124 1,
1125 0,
1126 gtclr::Cclr9,
1127 gtclr::Cclr9,
1128 Gtclr_SPEC,
1129 crate::common::W,
1130 >::from_register(self, 0)
1131 }
1132}
1133impl ::core::default::Default for Gtclr {
1134 #[inline(always)]
1135 fn default() -> Gtclr {
1136 <crate::RegValueT<Gtclr_SPEC> as RegisterValue<_>>::new(0)
1137 }
1138}
1139pub mod gtclr {
1140
1141 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1142 pub struct Cclr0_SPEC;
1143 pub type Cclr0 = crate::EnumBitfieldStruct<u8, Cclr0_SPEC>;
1144 impl Cclr0 {
1145 #[doc = "GTCNT counter is not cleared"]
1146 pub const _0: Self = Self::new(0);
1147
1148 #[doc = "GTCNT counter is cleared"]
1149 pub const _1: Self = Self::new(1);
1150 }
1151 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1152 pub struct Cclr1_SPEC;
1153 pub type Cclr1 = crate::EnumBitfieldStruct<u8, Cclr1_SPEC>;
1154 impl Cclr1 {
1155 #[doc = "GTCNT counter is not cleared"]
1156 pub const _0: Self = Self::new(0);
1157
1158 #[doc = "GTCNT counter is cleared"]
1159 pub const _1: Self = Self::new(1);
1160 }
1161 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1162 pub struct Cclr2_SPEC;
1163 pub type Cclr2 = crate::EnumBitfieldStruct<u8, Cclr2_SPEC>;
1164 impl Cclr2 {
1165 #[doc = "GTCNT counter is not cleared"]
1166 pub const _0: Self = Self::new(0);
1167
1168 #[doc = "GTCNT counter is cleared"]
1169 pub const _1: Self = Self::new(1);
1170 }
1171 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1172 pub struct Cclr3_SPEC;
1173 pub type Cclr3 = crate::EnumBitfieldStruct<u8, Cclr3_SPEC>;
1174 impl Cclr3 {
1175 #[doc = "GTCNT counter is not cleared"]
1176 pub const _0: Self = Self::new(0);
1177
1178 #[doc = "GTCNT counter is cleared"]
1179 pub const _1: Self = Self::new(1);
1180 }
1181 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1182 pub struct Cclr4_SPEC;
1183 pub type Cclr4 = crate::EnumBitfieldStruct<u8, Cclr4_SPEC>;
1184 impl Cclr4 {
1185 #[doc = "GTCNT counter is not cleared"]
1186 pub const _0: Self = Self::new(0);
1187
1188 #[doc = "GTCNT counter is cleared"]
1189 pub const _1: Self = Self::new(1);
1190 }
1191 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1192 pub struct Cclr5_SPEC;
1193 pub type Cclr5 = crate::EnumBitfieldStruct<u8, Cclr5_SPEC>;
1194 impl Cclr5 {
1195 #[doc = "GTCNT counter is not cleared"]
1196 pub const _0: Self = Self::new(0);
1197
1198 #[doc = "GTCNT counter is cleared"]
1199 pub const _1: Self = Self::new(1);
1200 }
1201 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1202 pub struct Cclr6_SPEC;
1203 pub type Cclr6 = crate::EnumBitfieldStruct<u8, Cclr6_SPEC>;
1204 impl Cclr6 {
1205 #[doc = "GTCNT counter is not cleared"]
1206 pub const _0: Self = Self::new(0);
1207
1208 #[doc = "GTCNT counter is cleared"]
1209 pub const _1: Self = Self::new(1);
1210 }
1211 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1212 pub struct Cclr7_SPEC;
1213 pub type Cclr7 = crate::EnumBitfieldStruct<u8, Cclr7_SPEC>;
1214 impl Cclr7 {
1215 #[doc = "GTCNT counter is not cleared"]
1216 pub const _0: Self = Self::new(0);
1217
1218 #[doc = "GTCNT counter is cleared"]
1219 pub const _1: Self = Self::new(1);
1220 }
1221 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1222 pub struct Cclr8_SPEC;
1223 pub type Cclr8 = crate::EnumBitfieldStruct<u8, Cclr8_SPEC>;
1224 impl Cclr8 {
1225 #[doc = "GTCNT counter is not cleared"]
1226 pub const _0: Self = Self::new(0);
1227
1228 #[doc = "GTCNT counter is cleared"]
1229 pub const _1: Self = Self::new(1);
1230 }
1231 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1232 pub struct Cclr9_SPEC;
1233 pub type Cclr9 = crate::EnumBitfieldStruct<u8, Cclr9_SPEC>;
1234 impl Cclr9 {
1235 #[doc = "GTCNT counter is not cleared"]
1236 pub const _0: Self = Self::new(0);
1237
1238 #[doc = "GTCNT counter is cleared"]
1239 pub const _1: Self = Self::new(1);
1240 }
1241}
1242#[doc(hidden)]
1243#[derive(Copy, Clone, Eq, PartialEq)]
1244pub struct Gtssr_SPEC;
1245impl crate::sealed::RegSpec for Gtssr_SPEC {
1246 type DataType = u32;
1247}
1248
1249#[doc = "General PWM Timer Start Source Select Register"]
1250pub type Gtssr = crate::RegValueT<Gtssr_SPEC>;
1251
1252impl Gtssr {
1253 #[doc = "GTETRGA Pin Rising Input Source Counter Start Enable"]
1254 #[inline(always)]
1255 pub fn ssgtrgar(
1256 self,
1257 ) -> crate::common::RegisterField<
1258 0,
1259 0x1,
1260 1,
1261 0,
1262 gtssr::Ssgtrgar,
1263 gtssr::Ssgtrgar,
1264 Gtssr_SPEC,
1265 crate::common::RW,
1266 > {
1267 crate::common::RegisterField::<
1268 0,
1269 0x1,
1270 1,
1271 0,
1272 gtssr::Ssgtrgar,
1273 gtssr::Ssgtrgar,
1274 Gtssr_SPEC,
1275 crate::common::RW,
1276 >::from_register(self, 0)
1277 }
1278
1279 #[doc = "GTETRGA Pin Falling Input Source Counter Start Enable"]
1280 #[inline(always)]
1281 pub fn ssgtrgaf(
1282 self,
1283 ) -> crate::common::RegisterField<
1284 1,
1285 0x1,
1286 1,
1287 0,
1288 gtssr::Ssgtrgaf,
1289 gtssr::Ssgtrgaf,
1290 Gtssr_SPEC,
1291 crate::common::RW,
1292 > {
1293 crate::common::RegisterField::<
1294 1,
1295 0x1,
1296 1,
1297 0,
1298 gtssr::Ssgtrgaf,
1299 gtssr::Ssgtrgaf,
1300 Gtssr_SPEC,
1301 crate::common::RW,
1302 >::from_register(self, 0)
1303 }
1304
1305 #[doc = "GTETRGB Pin Rising Input Source Counter Start Enable"]
1306 #[inline(always)]
1307 pub fn ssgtrgbr(
1308 self,
1309 ) -> crate::common::RegisterField<
1310 2,
1311 0x1,
1312 1,
1313 0,
1314 gtssr::Ssgtrgbr,
1315 gtssr::Ssgtrgbr,
1316 Gtssr_SPEC,
1317 crate::common::RW,
1318 > {
1319 crate::common::RegisterField::<
1320 2,
1321 0x1,
1322 1,
1323 0,
1324 gtssr::Ssgtrgbr,
1325 gtssr::Ssgtrgbr,
1326 Gtssr_SPEC,
1327 crate::common::RW,
1328 >::from_register(self, 0)
1329 }
1330
1331 #[doc = "GTETRGB Pin Falling Input Source Counter Start Enable"]
1332 #[inline(always)]
1333 pub fn ssgtrgbf(
1334 self,
1335 ) -> crate::common::RegisterField<
1336 3,
1337 0x1,
1338 1,
1339 0,
1340 gtssr::Ssgtrgbf,
1341 gtssr::Ssgtrgbf,
1342 Gtssr_SPEC,
1343 crate::common::RW,
1344 > {
1345 crate::common::RegisterField::<
1346 3,
1347 0x1,
1348 1,
1349 0,
1350 gtssr::Ssgtrgbf,
1351 gtssr::Ssgtrgbf,
1352 Gtssr_SPEC,
1353 crate::common::RW,
1354 >::from_register(self, 0)
1355 }
1356
1357 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable"]
1358 #[inline(always)]
1359 pub fn sscarbl(
1360 self,
1361 ) -> crate::common::RegisterField<
1362 8,
1363 0x1,
1364 1,
1365 0,
1366 gtssr::Sscarbl,
1367 gtssr::Sscarbl,
1368 Gtssr_SPEC,
1369 crate::common::RW,
1370 > {
1371 crate::common::RegisterField::<
1372 8,
1373 0x1,
1374 1,
1375 0,
1376 gtssr::Sscarbl,
1377 gtssr::Sscarbl,
1378 Gtssr_SPEC,
1379 crate::common::RW,
1380 >::from_register(self, 0)
1381 }
1382
1383 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable"]
1384 #[inline(always)]
1385 pub fn sscarbh(
1386 self,
1387 ) -> crate::common::RegisterField<
1388 9,
1389 0x1,
1390 1,
1391 0,
1392 gtssr::Sscarbh,
1393 gtssr::Sscarbh,
1394 Gtssr_SPEC,
1395 crate::common::RW,
1396 > {
1397 crate::common::RegisterField::<
1398 9,
1399 0x1,
1400 1,
1401 0,
1402 gtssr::Sscarbh,
1403 gtssr::Sscarbh,
1404 Gtssr_SPEC,
1405 crate::common::RW,
1406 >::from_register(self, 0)
1407 }
1408
1409 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable"]
1410 #[inline(always)]
1411 pub fn sscafbl(
1412 self,
1413 ) -> crate::common::RegisterField<
1414 10,
1415 0x1,
1416 1,
1417 0,
1418 gtssr::Sscafbl,
1419 gtssr::Sscafbl,
1420 Gtssr_SPEC,
1421 crate::common::RW,
1422 > {
1423 crate::common::RegisterField::<
1424 10,
1425 0x1,
1426 1,
1427 0,
1428 gtssr::Sscafbl,
1429 gtssr::Sscafbl,
1430 Gtssr_SPEC,
1431 crate::common::RW,
1432 >::from_register(self, 0)
1433 }
1434
1435 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable"]
1436 #[inline(always)]
1437 pub fn sscafbh(
1438 self,
1439 ) -> crate::common::RegisterField<
1440 11,
1441 0x1,
1442 1,
1443 0,
1444 gtssr::Sscafbh,
1445 gtssr::Sscafbh,
1446 Gtssr_SPEC,
1447 crate::common::RW,
1448 > {
1449 crate::common::RegisterField::<
1450 11,
1451 0x1,
1452 1,
1453 0,
1454 gtssr::Sscafbh,
1455 gtssr::Sscafbh,
1456 Gtssr_SPEC,
1457 crate::common::RW,
1458 >::from_register(self, 0)
1459 }
1460
1461 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable"]
1462 #[inline(always)]
1463 pub fn sscbral(
1464 self,
1465 ) -> crate::common::RegisterField<
1466 12,
1467 0x1,
1468 1,
1469 0,
1470 gtssr::Sscbral,
1471 gtssr::Sscbral,
1472 Gtssr_SPEC,
1473 crate::common::RW,
1474 > {
1475 crate::common::RegisterField::<
1476 12,
1477 0x1,
1478 1,
1479 0,
1480 gtssr::Sscbral,
1481 gtssr::Sscbral,
1482 Gtssr_SPEC,
1483 crate::common::RW,
1484 >::from_register(self, 0)
1485 }
1486
1487 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable"]
1488 #[inline(always)]
1489 pub fn sscbrah(
1490 self,
1491 ) -> crate::common::RegisterField<
1492 13,
1493 0x1,
1494 1,
1495 0,
1496 gtssr::Sscbrah,
1497 gtssr::Sscbrah,
1498 Gtssr_SPEC,
1499 crate::common::RW,
1500 > {
1501 crate::common::RegisterField::<
1502 13,
1503 0x1,
1504 1,
1505 0,
1506 gtssr::Sscbrah,
1507 gtssr::Sscbrah,
1508 Gtssr_SPEC,
1509 crate::common::RW,
1510 >::from_register(self, 0)
1511 }
1512
1513 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable"]
1514 #[inline(always)]
1515 pub fn sscbfal(
1516 self,
1517 ) -> crate::common::RegisterField<
1518 14,
1519 0x1,
1520 1,
1521 0,
1522 gtssr::Sscbfal,
1523 gtssr::Sscbfal,
1524 Gtssr_SPEC,
1525 crate::common::RW,
1526 > {
1527 crate::common::RegisterField::<
1528 14,
1529 0x1,
1530 1,
1531 0,
1532 gtssr::Sscbfal,
1533 gtssr::Sscbfal,
1534 Gtssr_SPEC,
1535 crate::common::RW,
1536 >::from_register(self, 0)
1537 }
1538
1539 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable"]
1540 #[inline(always)]
1541 pub fn sscbfah(
1542 self,
1543 ) -> crate::common::RegisterField<
1544 15,
1545 0x1,
1546 1,
1547 0,
1548 gtssr::Sscbfah,
1549 gtssr::Sscbfah,
1550 Gtssr_SPEC,
1551 crate::common::RW,
1552 > {
1553 crate::common::RegisterField::<
1554 15,
1555 0x1,
1556 1,
1557 0,
1558 gtssr::Sscbfah,
1559 gtssr::Sscbfah,
1560 Gtssr_SPEC,
1561 crate::common::RW,
1562 >::from_register(self, 0)
1563 }
1564
1565 #[doc = "ELC_GPTA Event Source Counter Start Enable"]
1566 #[inline(always)]
1567 pub fn sselca(
1568 self,
1569 ) -> crate::common::RegisterField<
1570 16,
1571 0x1,
1572 1,
1573 0,
1574 gtssr::Sselca,
1575 gtssr::Sselca,
1576 Gtssr_SPEC,
1577 crate::common::RW,
1578 > {
1579 crate::common::RegisterField::<
1580 16,
1581 0x1,
1582 1,
1583 0,
1584 gtssr::Sselca,
1585 gtssr::Sselca,
1586 Gtssr_SPEC,
1587 crate::common::RW,
1588 >::from_register(self, 0)
1589 }
1590
1591 #[doc = "ELC_GPTB Event Source Counter Start Enable"]
1592 #[inline(always)]
1593 pub fn sselcb(
1594 self,
1595 ) -> crate::common::RegisterField<
1596 17,
1597 0x1,
1598 1,
1599 0,
1600 gtssr::Sselcb,
1601 gtssr::Sselcb,
1602 Gtssr_SPEC,
1603 crate::common::RW,
1604 > {
1605 crate::common::RegisterField::<
1606 17,
1607 0x1,
1608 1,
1609 0,
1610 gtssr::Sselcb,
1611 gtssr::Sselcb,
1612 Gtssr_SPEC,
1613 crate::common::RW,
1614 >::from_register(self, 0)
1615 }
1616
1617 #[doc = "ELC_GPTC Event Source Counter Start Enable"]
1618 #[inline(always)]
1619 pub fn sselcc(
1620 self,
1621 ) -> crate::common::RegisterField<
1622 18,
1623 0x1,
1624 1,
1625 0,
1626 gtssr::Sselcc,
1627 gtssr::Sselcc,
1628 Gtssr_SPEC,
1629 crate::common::RW,
1630 > {
1631 crate::common::RegisterField::<
1632 18,
1633 0x1,
1634 1,
1635 0,
1636 gtssr::Sselcc,
1637 gtssr::Sselcc,
1638 Gtssr_SPEC,
1639 crate::common::RW,
1640 >::from_register(self, 0)
1641 }
1642
1643 #[doc = "ELC_GPTD Event Source Counter Start Enable"]
1644 #[inline(always)]
1645 pub fn sselcd(
1646 self,
1647 ) -> crate::common::RegisterField<
1648 19,
1649 0x1,
1650 1,
1651 0,
1652 gtssr::Sselcd,
1653 gtssr::Sselcd,
1654 Gtssr_SPEC,
1655 crate::common::RW,
1656 > {
1657 crate::common::RegisterField::<
1658 19,
1659 0x1,
1660 1,
1661 0,
1662 gtssr::Sselcd,
1663 gtssr::Sselcd,
1664 Gtssr_SPEC,
1665 crate::common::RW,
1666 >::from_register(self, 0)
1667 }
1668
1669 #[doc = "Software Source Counter Start Enable"]
1670 #[inline(always)]
1671 pub fn cstrt(
1672 self,
1673 ) -> crate::common::RegisterField<
1674 31,
1675 0x1,
1676 1,
1677 0,
1678 gtssr::Cstrt,
1679 gtssr::Cstrt,
1680 Gtssr_SPEC,
1681 crate::common::RW,
1682 > {
1683 crate::common::RegisterField::<
1684 31,
1685 0x1,
1686 1,
1687 0,
1688 gtssr::Cstrt,
1689 gtssr::Cstrt,
1690 Gtssr_SPEC,
1691 crate::common::RW,
1692 >::from_register(self, 0)
1693 }
1694}
1695impl ::core::default::Default for Gtssr {
1696 #[inline(always)]
1697 fn default() -> Gtssr {
1698 <crate::RegValueT<Gtssr_SPEC> as RegisterValue<_>>::new(0)
1699 }
1700}
1701pub mod gtssr {
1702
1703 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1704 pub struct Ssgtrgar_SPEC;
1705 pub type Ssgtrgar = crate::EnumBitfieldStruct<u8, Ssgtrgar_SPEC>;
1706 impl Ssgtrgar {
1707 #[doc = "Counter start disabled on the rising edge of GTETRGA input"]
1708 pub const _0: Self = Self::new(0);
1709
1710 #[doc = "Counter start enabled on the rising edge of GTETRGA input"]
1711 pub const _1: Self = Self::new(1);
1712 }
1713 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1714 pub struct Ssgtrgaf_SPEC;
1715 pub type Ssgtrgaf = crate::EnumBitfieldStruct<u8, Ssgtrgaf_SPEC>;
1716 impl Ssgtrgaf {
1717 #[doc = "Counter start disabled on the falling edge of GTETRGA input"]
1718 pub const _0: Self = Self::new(0);
1719
1720 #[doc = "Counter start enabled on the falling edge of GTETRGA input"]
1721 pub const _1: Self = Self::new(1);
1722 }
1723 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1724 pub struct Ssgtrgbr_SPEC;
1725 pub type Ssgtrgbr = crate::EnumBitfieldStruct<u8, Ssgtrgbr_SPEC>;
1726 impl Ssgtrgbr {
1727 #[doc = "Counter start disabled on the rising edge of GTETRGB input"]
1728 pub const _0: Self = Self::new(0);
1729
1730 #[doc = "Counter start enabled on the rising edge of GTETRGB input"]
1731 pub const _1: Self = Self::new(1);
1732 }
1733 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1734 pub struct Ssgtrgbf_SPEC;
1735 pub type Ssgtrgbf = crate::EnumBitfieldStruct<u8, Ssgtrgbf_SPEC>;
1736 impl Ssgtrgbf {
1737 #[doc = "Counter start disabled on the falling edge of GTETRGB input"]
1738 pub const _0: Self = Self::new(0);
1739
1740 #[doc = "Counter start enabled on the falling edge of GTETRGB input"]
1741 pub const _1: Self = Self::new(1);
1742 }
1743 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1744 pub struct Sscarbl_SPEC;
1745 pub type Sscarbl = crate::EnumBitfieldStruct<u8, Sscarbl_SPEC>;
1746 impl Sscarbl {
1747 #[doc = "Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
1748 pub const _0: Self = Self::new(0);
1749
1750 #[doc = "Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
1751 pub const _1: Self = Self::new(1);
1752 }
1753 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1754 pub struct Sscarbh_SPEC;
1755 pub type Sscarbh = crate::EnumBitfieldStruct<u8, Sscarbh_SPEC>;
1756 impl Sscarbh {
1757 #[doc = "Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
1758 pub const _0: Self = Self::new(0);
1759
1760 #[doc = "Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
1761 pub const _1: Self = Self::new(1);
1762 }
1763 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1764 pub struct Sscafbl_SPEC;
1765 pub type Sscafbl = crate::EnumBitfieldStruct<u8, Sscafbl_SPEC>;
1766 impl Sscafbl {
1767 #[doc = "Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
1768 pub const _0: Self = Self::new(0);
1769
1770 #[doc = "Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
1771 pub const _1: Self = Self::new(1);
1772 }
1773 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1774 pub struct Sscafbh_SPEC;
1775 pub type Sscafbh = crate::EnumBitfieldStruct<u8, Sscafbh_SPEC>;
1776 impl Sscafbh {
1777 #[doc = "Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
1778 pub const _0: Self = Self::new(0);
1779
1780 #[doc = "Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
1781 pub const _1: Self = Self::new(1);
1782 }
1783 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1784 pub struct Sscbral_SPEC;
1785 pub type Sscbral = crate::EnumBitfieldStruct<u8, Sscbral_SPEC>;
1786 impl Sscbral {
1787 #[doc = "Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
1788 pub const _0: Self = Self::new(0);
1789
1790 #[doc = "Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
1791 pub const _1: Self = Self::new(1);
1792 }
1793 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1794 pub struct Sscbrah_SPEC;
1795 pub type Sscbrah = crate::EnumBitfieldStruct<u8, Sscbrah_SPEC>;
1796 impl Sscbrah {
1797 #[doc = "Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
1798 pub const _0: Self = Self::new(0);
1799
1800 #[doc = "Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
1801 pub const _1: Self = Self::new(1);
1802 }
1803 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1804 pub struct Sscbfal_SPEC;
1805 pub type Sscbfal = crate::EnumBitfieldStruct<u8, Sscbfal_SPEC>;
1806 impl Sscbfal {
1807 #[doc = "Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
1808 pub const _0: Self = Self::new(0);
1809
1810 #[doc = "Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
1811 pub const _1: Self = Self::new(1);
1812 }
1813 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1814 pub struct Sscbfah_SPEC;
1815 pub type Sscbfah = crate::EnumBitfieldStruct<u8, Sscbfah_SPEC>;
1816 impl Sscbfah {
1817 #[doc = "Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
1818 pub const _0: Self = Self::new(0);
1819
1820 #[doc = "Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
1821 pub const _1: Self = Self::new(1);
1822 }
1823 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1824 pub struct Sselca_SPEC;
1825 pub type Sselca = crate::EnumBitfieldStruct<u8, Sselca_SPEC>;
1826 impl Sselca {
1827 #[doc = "Counter start disabled at the ELC_GPTA input"]
1828 pub const _0: Self = Self::new(0);
1829
1830 #[doc = "Counter start enabled at the ELC_GPTA input"]
1831 pub const _1: Self = Self::new(1);
1832 }
1833 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1834 pub struct Sselcb_SPEC;
1835 pub type Sselcb = crate::EnumBitfieldStruct<u8, Sselcb_SPEC>;
1836 impl Sselcb {
1837 #[doc = "Counter start disabled at the ELC_GPTB input"]
1838 pub const _0: Self = Self::new(0);
1839
1840 #[doc = "Counter start enabled at the ELC_GPTB input"]
1841 pub const _1: Self = Self::new(1);
1842 }
1843 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1844 pub struct Sselcc_SPEC;
1845 pub type Sselcc = crate::EnumBitfieldStruct<u8, Sselcc_SPEC>;
1846 impl Sselcc {
1847 #[doc = "Counter start disabled at the ELC_GPTC input"]
1848 pub const _0: Self = Self::new(0);
1849
1850 #[doc = "Counter start enabled at the ELC_GPTC input"]
1851 pub const _1: Self = Self::new(1);
1852 }
1853 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1854 pub struct Sselcd_SPEC;
1855 pub type Sselcd = crate::EnumBitfieldStruct<u8, Sselcd_SPEC>;
1856 impl Sselcd {
1857 #[doc = "Counter start disabled at the ELC_GPTD input"]
1858 pub const _0: Self = Self::new(0);
1859
1860 #[doc = "Counter start enabled at the ELC_GPTD input"]
1861 pub const _1: Self = Self::new(1);
1862 }
1863 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1864 pub struct Cstrt_SPEC;
1865 pub type Cstrt = crate::EnumBitfieldStruct<u8, Cstrt_SPEC>;
1866 impl Cstrt {
1867 #[doc = "Counter start disabled by the GTSTR register"]
1868 pub const _0: Self = Self::new(0);
1869
1870 #[doc = "Counter start enabled by the GTSTR register"]
1871 pub const _1: Self = Self::new(1);
1872 }
1873}
1874#[doc(hidden)]
1875#[derive(Copy, Clone, Eq, PartialEq)]
1876pub struct Gtpsr_SPEC;
1877impl crate::sealed::RegSpec for Gtpsr_SPEC {
1878 type DataType = u32;
1879}
1880
1881#[doc = "General PWM Timer Stop Source Select Register"]
1882pub type Gtpsr = crate::RegValueT<Gtpsr_SPEC>;
1883
1884impl Gtpsr {
1885 #[doc = "GTETRGA Pin Rising Input Source Counter Stop Enable"]
1886 #[inline(always)]
1887 pub fn psgtrgar(
1888 self,
1889 ) -> crate::common::RegisterField<
1890 0,
1891 0x1,
1892 1,
1893 0,
1894 gtpsr::Psgtrgar,
1895 gtpsr::Psgtrgar,
1896 Gtpsr_SPEC,
1897 crate::common::RW,
1898 > {
1899 crate::common::RegisterField::<
1900 0,
1901 0x1,
1902 1,
1903 0,
1904 gtpsr::Psgtrgar,
1905 gtpsr::Psgtrgar,
1906 Gtpsr_SPEC,
1907 crate::common::RW,
1908 >::from_register(self, 0)
1909 }
1910
1911 #[doc = "GTETRGA Pin Falling Input Source Counter Stop Enable"]
1912 #[inline(always)]
1913 pub fn psgtrgaf(
1914 self,
1915 ) -> crate::common::RegisterField<
1916 1,
1917 0x1,
1918 1,
1919 0,
1920 gtpsr::Psgtrgaf,
1921 gtpsr::Psgtrgaf,
1922 Gtpsr_SPEC,
1923 crate::common::RW,
1924 > {
1925 crate::common::RegisterField::<
1926 1,
1927 0x1,
1928 1,
1929 0,
1930 gtpsr::Psgtrgaf,
1931 gtpsr::Psgtrgaf,
1932 Gtpsr_SPEC,
1933 crate::common::RW,
1934 >::from_register(self, 0)
1935 }
1936
1937 #[doc = "GTETRGB Pin Rising Input Source Counter Stop Enable"]
1938 #[inline(always)]
1939 pub fn psgtrgbr(
1940 self,
1941 ) -> crate::common::RegisterField<
1942 2,
1943 0x1,
1944 1,
1945 0,
1946 gtpsr::Psgtrgbr,
1947 gtpsr::Psgtrgbr,
1948 Gtpsr_SPEC,
1949 crate::common::RW,
1950 > {
1951 crate::common::RegisterField::<
1952 2,
1953 0x1,
1954 1,
1955 0,
1956 gtpsr::Psgtrgbr,
1957 gtpsr::Psgtrgbr,
1958 Gtpsr_SPEC,
1959 crate::common::RW,
1960 >::from_register(self, 0)
1961 }
1962
1963 #[doc = "GTETRGB Pin Falling Input Source Counter Stop Enable"]
1964 #[inline(always)]
1965 pub fn psgtrgbf(
1966 self,
1967 ) -> crate::common::RegisterField<
1968 3,
1969 0x1,
1970 1,
1971 0,
1972 gtpsr::Psgtrgbf,
1973 gtpsr::Psgtrgbf,
1974 Gtpsr_SPEC,
1975 crate::common::RW,
1976 > {
1977 crate::common::RegisterField::<
1978 3,
1979 0x1,
1980 1,
1981 0,
1982 gtpsr::Psgtrgbf,
1983 gtpsr::Psgtrgbf,
1984 Gtpsr_SPEC,
1985 crate::common::RW,
1986 >::from_register(self, 0)
1987 }
1988
1989 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable"]
1990 #[inline(always)]
1991 pub fn pscarbl(
1992 self,
1993 ) -> crate::common::RegisterField<
1994 8,
1995 0x1,
1996 1,
1997 0,
1998 gtpsr::Pscarbl,
1999 gtpsr::Pscarbl,
2000 Gtpsr_SPEC,
2001 crate::common::RW,
2002 > {
2003 crate::common::RegisterField::<
2004 8,
2005 0x1,
2006 1,
2007 0,
2008 gtpsr::Pscarbl,
2009 gtpsr::Pscarbl,
2010 Gtpsr_SPEC,
2011 crate::common::RW,
2012 >::from_register(self, 0)
2013 }
2014
2015 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable"]
2016 #[inline(always)]
2017 pub fn pscarbh(
2018 self,
2019 ) -> crate::common::RegisterField<
2020 9,
2021 0x1,
2022 1,
2023 0,
2024 gtpsr::Pscarbh,
2025 gtpsr::Pscarbh,
2026 Gtpsr_SPEC,
2027 crate::common::RW,
2028 > {
2029 crate::common::RegisterField::<
2030 9,
2031 0x1,
2032 1,
2033 0,
2034 gtpsr::Pscarbh,
2035 gtpsr::Pscarbh,
2036 Gtpsr_SPEC,
2037 crate::common::RW,
2038 >::from_register(self, 0)
2039 }
2040
2041 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable"]
2042 #[inline(always)]
2043 pub fn pscafbl(
2044 self,
2045 ) -> crate::common::RegisterField<
2046 10,
2047 0x1,
2048 1,
2049 0,
2050 gtpsr::Pscafbl,
2051 gtpsr::Pscafbl,
2052 Gtpsr_SPEC,
2053 crate::common::RW,
2054 > {
2055 crate::common::RegisterField::<
2056 10,
2057 0x1,
2058 1,
2059 0,
2060 gtpsr::Pscafbl,
2061 gtpsr::Pscafbl,
2062 Gtpsr_SPEC,
2063 crate::common::RW,
2064 >::from_register(self, 0)
2065 }
2066
2067 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable"]
2068 #[inline(always)]
2069 pub fn pscafbh(
2070 self,
2071 ) -> crate::common::RegisterField<
2072 11,
2073 0x1,
2074 1,
2075 0,
2076 gtpsr::Pscafbh,
2077 gtpsr::Pscafbh,
2078 Gtpsr_SPEC,
2079 crate::common::RW,
2080 > {
2081 crate::common::RegisterField::<
2082 11,
2083 0x1,
2084 1,
2085 0,
2086 gtpsr::Pscafbh,
2087 gtpsr::Pscafbh,
2088 Gtpsr_SPEC,
2089 crate::common::RW,
2090 >::from_register(self, 0)
2091 }
2092
2093 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable"]
2094 #[inline(always)]
2095 pub fn pscbral(
2096 self,
2097 ) -> crate::common::RegisterField<
2098 12,
2099 0x1,
2100 1,
2101 0,
2102 gtpsr::Pscbral,
2103 gtpsr::Pscbral,
2104 Gtpsr_SPEC,
2105 crate::common::RW,
2106 > {
2107 crate::common::RegisterField::<
2108 12,
2109 0x1,
2110 1,
2111 0,
2112 gtpsr::Pscbral,
2113 gtpsr::Pscbral,
2114 Gtpsr_SPEC,
2115 crate::common::RW,
2116 >::from_register(self, 0)
2117 }
2118
2119 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable"]
2120 #[inline(always)]
2121 pub fn pscbrah(
2122 self,
2123 ) -> crate::common::RegisterField<
2124 13,
2125 0x1,
2126 1,
2127 0,
2128 gtpsr::Pscbrah,
2129 gtpsr::Pscbrah,
2130 Gtpsr_SPEC,
2131 crate::common::RW,
2132 > {
2133 crate::common::RegisterField::<
2134 13,
2135 0x1,
2136 1,
2137 0,
2138 gtpsr::Pscbrah,
2139 gtpsr::Pscbrah,
2140 Gtpsr_SPEC,
2141 crate::common::RW,
2142 >::from_register(self, 0)
2143 }
2144
2145 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable"]
2146 #[inline(always)]
2147 pub fn pscbfal(
2148 self,
2149 ) -> crate::common::RegisterField<
2150 14,
2151 0x1,
2152 1,
2153 0,
2154 gtpsr::Pscbfal,
2155 gtpsr::Pscbfal,
2156 Gtpsr_SPEC,
2157 crate::common::RW,
2158 > {
2159 crate::common::RegisterField::<
2160 14,
2161 0x1,
2162 1,
2163 0,
2164 gtpsr::Pscbfal,
2165 gtpsr::Pscbfal,
2166 Gtpsr_SPEC,
2167 crate::common::RW,
2168 >::from_register(self, 0)
2169 }
2170
2171 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable"]
2172 #[inline(always)]
2173 pub fn pscbfah(
2174 self,
2175 ) -> crate::common::RegisterField<
2176 15,
2177 0x1,
2178 1,
2179 0,
2180 gtpsr::Pscbfah,
2181 gtpsr::Pscbfah,
2182 Gtpsr_SPEC,
2183 crate::common::RW,
2184 > {
2185 crate::common::RegisterField::<
2186 15,
2187 0x1,
2188 1,
2189 0,
2190 gtpsr::Pscbfah,
2191 gtpsr::Pscbfah,
2192 Gtpsr_SPEC,
2193 crate::common::RW,
2194 >::from_register(self, 0)
2195 }
2196
2197 #[doc = "ELC_GPTA Event Source Counter Stop Enable"]
2198 #[inline(always)]
2199 pub fn pselca(
2200 self,
2201 ) -> crate::common::RegisterField<
2202 16,
2203 0x1,
2204 1,
2205 0,
2206 gtpsr::Pselca,
2207 gtpsr::Pselca,
2208 Gtpsr_SPEC,
2209 crate::common::RW,
2210 > {
2211 crate::common::RegisterField::<
2212 16,
2213 0x1,
2214 1,
2215 0,
2216 gtpsr::Pselca,
2217 gtpsr::Pselca,
2218 Gtpsr_SPEC,
2219 crate::common::RW,
2220 >::from_register(self, 0)
2221 }
2222
2223 #[doc = "ELC_GPTB Event Source Counter Stop Enable"]
2224 #[inline(always)]
2225 pub fn pselcb(
2226 self,
2227 ) -> crate::common::RegisterField<
2228 17,
2229 0x1,
2230 1,
2231 0,
2232 gtpsr::Pselcb,
2233 gtpsr::Pselcb,
2234 Gtpsr_SPEC,
2235 crate::common::RW,
2236 > {
2237 crate::common::RegisterField::<
2238 17,
2239 0x1,
2240 1,
2241 0,
2242 gtpsr::Pselcb,
2243 gtpsr::Pselcb,
2244 Gtpsr_SPEC,
2245 crate::common::RW,
2246 >::from_register(self, 0)
2247 }
2248
2249 #[doc = "ELC_GPTC Event Source Counter Stop Enable"]
2250 #[inline(always)]
2251 pub fn pselcc(
2252 self,
2253 ) -> crate::common::RegisterField<
2254 18,
2255 0x1,
2256 1,
2257 0,
2258 gtpsr::Pselcc,
2259 gtpsr::Pselcc,
2260 Gtpsr_SPEC,
2261 crate::common::RW,
2262 > {
2263 crate::common::RegisterField::<
2264 18,
2265 0x1,
2266 1,
2267 0,
2268 gtpsr::Pselcc,
2269 gtpsr::Pselcc,
2270 Gtpsr_SPEC,
2271 crate::common::RW,
2272 >::from_register(self, 0)
2273 }
2274
2275 #[doc = "ELC_GPTD Event Source Counter Stop Enable"]
2276 #[inline(always)]
2277 pub fn pselcd(
2278 self,
2279 ) -> crate::common::RegisterField<
2280 19,
2281 0x1,
2282 1,
2283 0,
2284 gtpsr::Pselcd,
2285 gtpsr::Pselcd,
2286 Gtpsr_SPEC,
2287 crate::common::RW,
2288 > {
2289 crate::common::RegisterField::<
2290 19,
2291 0x1,
2292 1,
2293 0,
2294 gtpsr::Pselcd,
2295 gtpsr::Pselcd,
2296 Gtpsr_SPEC,
2297 crate::common::RW,
2298 >::from_register(self, 0)
2299 }
2300
2301 #[doc = "Software Source Counter Stop Enable"]
2302 #[inline(always)]
2303 pub fn cstop(
2304 self,
2305 ) -> crate::common::RegisterField<
2306 31,
2307 0x1,
2308 1,
2309 0,
2310 gtpsr::Cstop,
2311 gtpsr::Cstop,
2312 Gtpsr_SPEC,
2313 crate::common::RW,
2314 > {
2315 crate::common::RegisterField::<
2316 31,
2317 0x1,
2318 1,
2319 0,
2320 gtpsr::Cstop,
2321 gtpsr::Cstop,
2322 Gtpsr_SPEC,
2323 crate::common::RW,
2324 >::from_register(self, 0)
2325 }
2326}
2327impl ::core::default::Default for Gtpsr {
2328 #[inline(always)]
2329 fn default() -> Gtpsr {
2330 <crate::RegValueT<Gtpsr_SPEC> as RegisterValue<_>>::new(0)
2331 }
2332}
2333pub mod gtpsr {
2334
2335 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2336 pub struct Psgtrgar_SPEC;
2337 pub type Psgtrgar = crate::EnumBitfieldStruct<u8, Psgtrgar_SPEC>;
2338 impl Psgtrgar {
2339 #[doc = "Counter stop disabled on the rising edge of GTETRGA input"]
2340 pub const _0: Self = Self::new(0);
2341
2342 #[doc = "Counter stop enabled on the rising edge of GTETRGA input"]
2343 pub const _1: Self = Self::new(1);
2344 }
2345 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2346 pub struct Psgtrgaf_SPEC;
2347 pub type Psgtrgaf = crate::EnumBitfieldStruct<u8, Psgtrgaf_SPEC>;
2348 impl Psgtrgaf {
2349 #[doc = "Counter stop disabled on the falling edge of GTETRGA input"]
2350 pub const _0: Self = Self::new(0);
2351
2352 #[doc = "Counter stop enabled on the falling edge of GTETRGA input"]
2353 pub const _1: Self = Self::new(1);
2354 }
2355 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2356 pub struct Psgtrgbr_SPEC;
2357 pub type Psgtrgbr = crate::EnumBitfieldStruct<u8, Psgtrgbr_SPEC>;
2358 impl Psgtrgbr {
2359 #[doc = "Counter stop disabled on the rising edge of GTETRGB input"]
2360 pub const _0: Self = Self::new(0);
2361
2362 #[doc = "Counter stop enabled on the rising edge of GTETRGB input"]
2363 pub const _1: Self = Self::new(1);
2364 }
2365 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2366 pub struct Psgtrgbf_SPEC;
2367 pub type Psgtrgbf = crate::EnumBitfieldStruct<u8, Psgtrgbf_SPEC>;
2368 impl Psgtrgbf {
2369 #[doc = "Counter stop disabled on the falling edge of GTETRGB input"]
2370 pub const _0: Self = Self::new(0);
2371
2372 #[doc = "Counter stop enabled on the falling edge of GTETRGB input"]
2373 pub const _1: Self = Self::new(1);
2374 }
2375 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2376 pub struct Pscarbl_SPEC;
2377 pub type Pscarbl = crate::EnumBitfieldStruct<u8, Pscarbl_SPEC>;
2378 impl Pscarbl {
2379 #[doc = "Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
2380 pub const _0: Self = Self::new(0);
2381
2382 #[doc = "Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
2383 pub const _1: Self = Self::new(1);
2384 }
2385 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2386 pub struct Pscarbh_SPEC;
2387 pub type Pscarbh = crate::EnumBitfieldStruct<u8, Pscarbh_SPEC>;
2388 impl Pscarbh {
2389 #[doc = "Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
2390 pub const _0: Self = Self::new(0);
2391
2392 #[doc = "Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
2393 pub const _1: Self = Self::new(1);
2394 }
2395 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2396 pub struct Pscafbl_SPEC;
2397 pub type Pscafbl = crate::EnumBitfieldStruct<u8, Pscafbl_SPEC>;
2398 impl Pscafbl {
2399 #[doc = "Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
2400 pub const _0: Self = Self::new(0);
2401
2402 #[doc = "Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
2403 pub const _1: Self = Self::new(1);
2404 }
2405 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2406 pub struct Pscafbh_SPEC;
2407 pub type Pscafbh = crate::EnumBitfieldStruct<u8, Pscafbh_SPEC>;
2408 impl Pscafbh {
2409 #[doc = "Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
2410 pub const _0: Self = Self::new(0);
2411
2412 #[doc = "Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
2413 pub const _1: Self = Self::new(1);
2414 }
2415 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2416 pub struct Pscbral_SPEC;
2417 pub type Pscbral = crate::EnumBitfieldStruct<u8, Pscbral_SPEC>;
2418 impl Pscbral {
2419 #[doc = "Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
2420 pub const _0: Self = Self::new(0);
2421
2422 #[doc = "Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
2423 pub const _1: Self = Self::new(1);
2424 }
2425 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2426 pub struct Pscbrah_SPEC;
2427 pub type Pscbrah = crate::EnumBitfieldStruct<u8, Pscbrah_SPEC>;
2428 impl Pscbrah {
2429 #[doc = "Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
2430 pub const _0: Self = Self::new(0);
2431
2432 #[doc = "Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
2433 pub const _1: Self = Self::new(1);
2434 }
2435 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2436 pub struct Pscbfal_SPEC;
2437 pub type Pscbfal = crate::EnumBitfieldStruct<u8, Pscbfal_SPEC>;
2438 impl Pscbfal {
2439 #[doc = "Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
2440 pub const _0: Self = Self::new(0);
2441
2442 #[doc = "Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
2443 pub const _1: Self = Self::new(1);
2444 }
2445 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2446 pub struct Pscbfah_SPEC;
2447 pub type Pscbfah = crate::EnumBitfieldStruct<u8, Pscbfah_SPEC>;
2448 impl Pscbfah {
2449 #[doc = "Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
2450 pub const _0: Self = Self::new(0);
2451
2452 #[doc = "Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
2453 pub const _1: Self = Self::new(1);
2454 }
2455 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2456 pub struct Pselca_SPEC;
2457 pub type Pselca = crate::EnumBitfieldStruct<u8, Pselca_SPEC>;
2458 impl Pselca {
2459 #[doc = "Counter stop disabled at the ELC_GPTA input"]
2460 pub const _0: Self = Self::new(0);
2461
2462 #[doc = "Counter stop enabled at the ELC_GPTA input"]
2463 pub const _1: Self = Self::new(1);
2464 }
2465 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2466 pub struct Pselcb_SPEC;
2467 pub type Pselcb = crate::EnumBitfieldStruct<u8, Pselcb_SPEC>;
2468 impl Pselcb {
2469 #[doc = "Counter stop disabled at the ELC_GPTB input"]
2470 pub const _0: Self = Self::new(0);
2471
2472 #[doc = "Counter stop enabled at the ELC_GPTB input"]
2473 pub const _1: Self = Self::new(1);
2474 }
2475 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2476 pub struct Pselcc_SPEC;
2477 pub type Pselcc = crate::EnumBitfieldStruct<u8, Pselcc_SPEC>;
2478 impl Pselcc {
2479 #[doc = "Counter stop disabled at the ELC_GPTC input"]
2480 pub const _0: Self = Self::new(0);
2481
2482 #[doc = "Counter stop enabled at the ELC_GPTC input"]
2483 pub const _1: Self = Self::new(1);
2484 }
2485 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2486 pub struct Pselcd_SPEC;
2487 pub type Pselcd = crate::EnumBitfieldStruct<u8, Pselcd_SPEC>;
2488 impl Pselcd {
2489 #[doc = "Counter stop disabled at the ELC_GPTD input"]
2490 pub const _0: Self = Self::new(0);
2491
2492 #[doc = "Counter stop enabled at the ELC_GPTD input"]
2493 pub const _1: Self = Self::new(1);
2494 }
2495 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2496 pub struct Cstop_SPEC;
2497 pub type Cstop = crate::EnumBitfieldStruct<u8, Cstop_SPEC>;
2498 impl Cstop {
2499 #[doc = "Counter stop disabled by the GTSTP register"]
2500 pub const _0: Self = Self::new(0);
2501
2502 #[doc = "Counter stop enabled by the GTSTP register"]
2503 pub const _1: Self = Self::new(1);
2504 }
2505}
2506#[doc(hidden)]
2507#[derive(Copy, Clone, Eq, PartialEq)]
2508pub struct Gtcsr_SPEC;
2509impl crate::sealed::RegSpec for Gtcsr_SPEC {
2510 type DataType = u32;
2511}
2512
2513#[doc = "General PWM Timer Clear Source Select Register"]
2514pub type Gtcsr = crate::RegValueT<Gtcsr_SPEC>;
2515
2516impl Gtcsr {
2517 #[doc = "GTETRGA Pin Rising Input Source Counter Clear Enable"]
2518 #[inline(always)]
2519 pub fn csgtrgar(
2520 self,
2521 ) -> crate::common::RegisterField<
2522 0,
2523 0x1,
2524 1,
2525 0,
2526 gtcsr::Csgtrgar,
2527 gtcsr::Csgtrgar,
2528 Gtcsr_SPEC,
2529 crate::common::RW,
2530 > {
2531 crate::common::RegisterField::<
2532 0,
2533 0x1,
2534 1,
2535 0,
2536 gtcsr::Csgtrgar,
2537 gtcsr::Csgtrgar,
2538 Gtcsr_SPEC,
2539 crate::common::RW,
2540 >::from_register(self, 0)
2541 }
2542
2543 #[doc = "GTETRGA Pin Falling Input Source Counter Clear Enable"]
2544 #[inline(always)]
2545 pub fn csgtrgaf(
2546 self,
2547 ) -> crate::common::RegisterField<
2548 1,
2549 0x1,
2550 1,
2551 0,
2552 gtcsr::Csgtrgaf,
2553 gtcsr::Csgtrgaf,
2554 Gtcsr_SPEC,
2555 crate::common::RW,
2556 > {
2557 crate::common::RegisterField::<
2558 1,
2559 0x1,
2560 1,
2561 0,
2562 gtcsr::Csgtrgaf,
2563 gtcsr::Csgtrgaf,
2564 Gtcsr_SPEC,
2565 crate::common::RW,
2566 >::from_register(self, 0)
2567 }
2568
2569 #[doc = "GTETRGB Pin Rising Input Source Counter Clear Enable"]
2570 #[inline(always)]
2571 pub fn csgtrgbr(
2572 self,
2573 ) -> crate::common::RegisterField<
2574 2,
2575 0x1,
2576 1,
2577 0,
2578 gtcsr::Csgtrgbr,
2579 gtcsr::Csgtrgbr,
2580 Gtcsr_SPEC,
2581 crate::common::RW,
2582 > {
2583 crate::common::RegisterField::<
2584 2,
2585 0x1,
2586 1,
2587 0,
2588 gtcsr::Csgtrgbr,
2589 gtcsr::Csgtrgbr,
2590 Gtcsr_SPEC,
2591 crate::common::RW,
2592 >::from_register(self, 0)
2593 }
2594
2595 #[doc = "GTETRGB Pin Falling Input Source Counter Clear Enable"]
2596 #[inline(always)]
2597 pub fn csgtrgbf(
2598 self,
2599 ) -> crate::common::RegisterField<
2600 3,
2601 0x1,
2602 1,
2603 0,
2604 gtcsr::Csgtrgbf,
2605 gtcsr::Csgtrgbf,
2606 Gtcsr_SPEC,
2607 crate::common::RW,
2608 > {
2609 crate::common::RegisterField::<
2610 3,
2611 0x1,
2612 1,
2613 0,
2614 gtcsr::Csgtrgbf,
2615 gtcsr::Csgtrgbf,
2616 Gtcsr_SPEC,
2617 crate::common::RW,
2618 >::from_register(self, 0)
2619 }
2620
2621 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable"]
2622 #[inline(always)]
2623 pub fn cscarbl(
2624 self,
2625 ) -> crate::common::RegisterField<
2626 8,
2627 0x1,
2628 1,
2629 0,
2630 gtcsr::Cscarbl,
2631 gtcsr::Cscarbl,
2632 Gtcsr_SPEC,
2633 crate::common::RW,
2634 > {
2635 crate::common::RegisterField::<
2636 8,
2637 0x1,
2638 1,
2639 0,
2640 gtcsr::Cscarbl,
2641 gtcsr::Cscarbl,
2642 Gtcsr_SPEC,
2643 crate::common::RW,
2644 >::from_register(self, 0)
2645 }
2646
2647 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable"]
2648 #[inline(always)]
2649 pub fn cscarbh(
2650 self,
2651 ) -> crate::common::RegisterField<
2652 9,
2653 0x1,
2654 1,
2655 0,
2656 gtcsr::Cscarbh,
2657 gtcsr::Cscarbh,
2658 Gtcsr_SPEC,
2659 crate::common::RW,
2660 > {
2661 crate::common::RegisterField::<
2662 9,
2663 0x1,
2664 1,
2665 0,
2666 gtcsr::Cscarbh,
2667 gtcsr::Cscarbh,
2668 Gtcsr_SPEC,
2669 crate::common::RW,
2670 >::from_register(self, 0)
2671 }
2672
2673 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable"]
2674 #[inline(always)]
2675 pub fn cscafbl(
2676 self,
2677 ) -> crate::common::RegisterField<
2678 10,
2679 0x1,
2680 1,
2681 0,
2682 gtcsr::Cscafbl,
2683 gtcsr::Cscafbl,
2684 Gtcsr_SPEC,
2685 crate::common::RW,
2686 > {
2687 crate::common::RegisterField::<
2688 10,
2689 0x1,
2690 1,
2691 0,
2692 gtcsr::Cscafbl,
2693 gtcsr::Cscafbl,
2694 Gtcsr_SPEC,
2695 crate::common::RW,
2696 >::from_register(self, 0)
2697 }
2698
2699 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable"]
2700 #[inline(always)]
2701 pub fn cscafbh(
2702 self,
2703 ) -> crate::common::RegisterField<
2704 11,
2705 0x1,
2706 1,
2707 0,
2708 gtcsr::Cscafbh,
2709 gtcsr::Cscafbh,
2710 Gtcsr_SPEC,
2711 crate::common::RW,
2712 > {
2713 crate::common::RegisterField::<
2714 11,
2715 0x1,
2716 1,
2717 0,
2718 gtcsr::Cscafbh,
2719 gtcsr::Cscafbh,
2720 Gtcsr_SPEC,
2721 crate::common::RW,
2722 >::from_register(self, 0)
2723 }
2724
2725 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable"]
2726 #[inline(always)]
2727 pub fn cscbral(
2728 self,
2729 ) -> crate::common::RegisterField<
2730 12,
2731 0x1,
2732 1,
2733 0,
2734 gtcsr::Cscbral,
2735 gtcsr::Cscbral,
2736 Gtcsr_SPEC,
2737 crate::common::RW,
2738 > {
2739 crate::common::RegisterField::<
2740 12,
2741 0x1,
2742 1,
2743 0,
2744 gtcsr::Cscbral,
2745 gtcsr::Cscbral,
2746 Gtcsr_SPEC,
2747 crate::common::RW,
2748 >::from_register(self, 0)
2749 }
2750
2751 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable"]
2752 #[inline(always)]
2753 pub fn cscbrah(
2754 self,
2755 ) -> crate::common::RegisterField<
2756 13,
2757 0x1,
2758 1,
2759 0,
2760 gtcsr::Cscbrah,
2761 gtcsr::Cscbrah,
2762 Gtcsr_SPEC,
2763 crate::common::RW,
2764 > {
2765 crate::common::RegisterField::<
2766 13,
2767 0x1,
2768 1,
2769 0,
2770 gtcsr::Cscbrah,
2771 gtcsr::Cscbrah,
2772 Gtcsr_SPEC,
2773 crate::common::RW,
2774 >::from_register(self, 0)
2775 }
2776
2777 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable"]
2778 #[inline(always)]
2779 pub fn cscbfal(
2780 self,
2781 ) -> crate::common::RegisterField<
2782 14,
2783 0x1,
2784 1,
2785 0,
2786 gtcsr::Cscbfal,
2787 gtcsr::Cscbfal,
2788 Gtcsr_SPEC,
2789 crate::common::RW,
2790 > {
2791 crate::common::RegisterField::<
2792 14,
2793 0x1,
2794 1,
2795 0,
2796 gtcsr::Cscbfal,
2797 gtcsr::Cscbfal,
2798 Gtcsr_SPEC,
2799 crate::common::RW,
2800 >::from_register(self, 0)
2801 }
2802
2803 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable"]
2804 #[inline(always)]
2805 pub fn cscbfah(
2806 self,
2807 ) -> crate::common::RegisterField<
2808 15,
2809 0x1,
2810 1,
2811 0,
2812 gtcsr::Cscbfah,
2813 gtcsr::Cscbfah,
2814 Gtcsr_SPEC,
2815 crate::common::RW,
2816 > {
2817 crate::common::RegisterField::<
2818 15,
2819 0x1,
2820 1,
2821 0,
2822 gtcsr::Cscbfah,
2823 gtcsr::Cscbfah,
2824 Gtcsr_SPEC,
2825 crate::common::RW,
2826 >::from_register(self, 0)
2827 }
2828
2829 #[doc = "ELC_GPTA Event Source Counter Clear Enable"]
2830 #[inline(always)]
2831 pub fn cselca(
2832 self,
2833 ) -> crate::common::RegisterField<
2834 16,
2835 0x1,
2836 1,
2837 0,
2838 gtcsr::Cselca,
2839 gtcsr::Cselca,
2840 Gtcsr_SPEC,
2841 crate::common::RW,
2842 > {
2843 crate::common::RegisterField::<
2844 16,
2845 0x1,
2846 1,
2847 0,
2848 gtcsr::Cselca,
2849 gtcsr::Cselca,
2850 Gtcsr_SPEC,
2851 crate::common::RW,
2852 >::from_register(self, 0)
2853 }
2854
2855 #[doc = "ELC_GPTB Event Source Counter Clear Enable"]
2856 #[inline(always)]
2857 pub fn cselcb(
2858 self,
2859 ) -> crate::common::RegisterField<
2860 17,
2861 0x1,
2862 1,
2863 0,
2864 gtcsr::Cselcb,
2865 gtcsr::Cselcb,
2866 Gtcsr_SPEC,
2867 crate::common::RW,
2868 > {
2869 crate::common::RegisterField::<
2870 17,
2871 0x1,
2872 1,
2873 0,
2874 gtcsr::Cselcb,
2875 gtcsr::Cselcb,
2876 Gtcsr_SPEC,
2877 crate::common::RW,
2878 >::from_register(self, 0)
2879 }
2880
2881 #[doc = "ELC_GPTC Event Source Counter Clear Enable"]
2882 #[inline(always)]
2883 pub fn cselcc(
2884 self,
2885 ) -> crate::common::RegisterField<
2886 18,
2887 0x1,
2888 1,
2889 0,
2890 gtcsr::Cselcc,
2891 gtcsr::Cselcc,
2892 Gtcsr_SPEC,
2893 crate::common::RW,
2894 > {
2895 crate::common::RegisterField::<
2896 18,
2897 0x1,
2898 1,
2899 0,
2900 gtcsr::Cselcc,
2901 gtcsr::Cselcc,
2902 Gtcsr_SPEC,
2903 crate::common::RW,
2904 >::from_register(self, 0)
2905 }
2906
2907 #[doc = "ELC_GPTD Event Source Counter Clear Enable"]
2908 #[inline(always)]
2909 pub fn cselcd(
2910 self,
2911 ) -> crate::common::RegisterField<
2912 19,
2913 0x1,
2914 1,
2915 0,
2916 gtcsr::Cselcd,
2917 gtcsr::Cselcd,
2918 Gtcsr_SPEC,
2919 crate::common::RW,
2920 > {
2921 crate::common::RegisterField::<
2922 19,
2923 0x1,
2924 1,
2925 0,
2926 gtcsr::Cselcd,
2927 gtcsr::Cselcd,
2928 Gtcsr_SPEC,
2929 crate::common::RW,
2930 >::from_register(self, 0)
2931 }
2932
2933 #[doc = "Software Source Counter Clear Enable"]
2934 #[inline(always)]
2935 pub fn cclr(
2936 self,
2937 ) -> crate::common::RegisterField<
2938 31,
2939 0x1,
2940 1,
2941 0,
2942 gtcsr::Cclr,
2943 gtcsr::Cclr,
2944 Gtcsr_SPEC,
2945 crate::common::RW,
2946 > {
2947 crate::common::RegisterField::<
2948 31,
2949 0x1,
2950 1,
2951 0,
2952 gtcsr::Cclr,
2953 gtcsr::Cclr,
2954 Gtcsr_SPEC,
2955 crate::common::RW,
2956 >::from_register(self, 0)
2957 }
2958}
2959impl ::core::default::Default for Gtcsr {
2960 #[inline(always)]
2961 fn default() -> Gtcsr {
2962 <crate::RegValueT<Gtcsr_SPEC> as RegisterValue<_>>::new(0)
2963 }
2964}
2965pub mod gtcsr {
2966
2967 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2968 pub struct Csgtrgar_SPEC;
2969 pub type Csgtrgar = crate::EnumBitfieldStruct<u8, Csgtrgar_SPEC>;
2970 impl Csgtrgar {
2971 #[doc = "Counter clear disabled on the rising edge of GTETRGA input"]
2972 pub const _0: Self = Self::new(0);
2973
2974 #[doc = "Counter clear enabled on the rising edge of GTETRGA input"]
2975 pub const _1: Self = Self::new(1);
2976 }
2977 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2978 pub struct Csgtrgaf_SPEC;
2979 pub type Csgtrgaf = crate::EnumBitfieldStruct<u8, Csgtrgaf_SPEC>;
2980 impl Csgtrgaf {
2981 #[doc = "Counter clear disabled on the falling edge of GTETRGA input"]
2982 pub const _0: Self = Self::new(0);
2983
2984 #[doc = "Counter clear enabled on the falling edge of GTETRGA input"]
2985 pub const _1: Self = Self::new(1);
2986 }
2987 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2988 pub struct Csgtrgbr_SPEC;
2989 pub type Csgtrgbr = crate::EnumBitfieldStruct<u8, Csgtrgbr_SPEC>;
2990 impl Csgtrgbr {
2991 #[doc = "Disable counter clear on the rising edge of GTETRGB input"]
2992 pub const _0: Self = Self::new(0);
2993
2994 #[doc = "Enable counter clear on the rising edge of GTETRGB input"]
2995 pub const _1: Self = Self::new(1);
2996 }
2997 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2998 pub struct Csgtrgbf_SPEC;
2999 pub type Csgtrgbf = crate::EnumBitfieldStruct<u8, Csgtrgbf_SPEC>;
3000 impl Csgtrgbf {
3001 #[doc = "Counter clear disabled on the falling edge of GTETRGB input"]
3002 pub const _0: Self = Self::new(0);
3003
3004 #[doc = "Counter clear enabled on the falling edge of GTETRGB input"]
3005 pub const _1: Self = Self::new(1);
3006 }
3007 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3008 pub struct Cscarbl_SPEC;
3009 pub type Cscarbl = crate::EnumBitfieldStruct<u8, Cscarbl_SPEC>;
3010 impl Cscarbl {
3011 #[doc = "Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
3012 pub const _0: Self = Self::new(0);
3013
3014 #[doc = "Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
3015 pub const _1: Self = Self::new(1);
3016 }
3017 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3018 pub struct Cscarbh_SPEC;
3019 pub type Cscarbh = crate::EnumBitfieldStruct<u8, Cscarbh_SPEC>;
3020 impl Cscarbh {
3021 #[doc = "Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
3022 pub const _0: Self = Self::new(0);
3023
3024 #[doc = "Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
3025 pub const _1: Self = Self::new(1);
3026 }
3027 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3028 pub struct Cscafbl_SPEC;
3029 pub type Cscafbl = crate::EnumBitfieldStruct<u8, Cscafbl_SPEC>;
3030 impl Cscafbl {
3031 #[doc = "Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
3032 pub const _0: Self = Self::new(0);
3033
3034 #[doc = "Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
3035 pub const _1: Self = Self::new(1);
3036 }
3037 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3038 pub struct Cscafbh_SPEC;
3039 pub type Cscafbh = crate::EnumBitfieldStruct<u8, Cscafbh_SPEC>;
3040 impl Cscafbh {
3041 #[doc = "Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
3042 pub const _0: Self = Self::new(0);
3043
3044 #[doc = "Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
3045 pub const _1: Self = Self::new(1);
3046 }
3047 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3048 pub struct Cscbral_SPEC;
3049 pub type Cscbral = crate::EnumBitfieldStruct<u8, Cscbral_SPEC>;
3050 impl Cscbral {
3051 #[doc = "Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
3052 pub const _0: Self = Self::new(0);
3053
3054 #[doc = "Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
3055 pub const _1: Self = Self::new(1);
3056 }
3057 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3058 pub struct Cscbrah_SPEC;
3059 pub type Cscbrah = crate::EnumBitfieldStruct<u8, Cscbrah_SPEC>;
3060 impl Cscbrah {
3061 #[doc = "Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
3062 pub const _0: Self = Self::new(0);
3063
3064 #[doc = "Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
3065 pub const _1: Self = Self::new(1);
3066 }
3067 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3068 pub struct Cscbfal_SPEC;
3069 pub type Cscbfal = crate::EnumBitfieldStruct<u8, Cscbfal_SPEC>;
3070 impl Cscbfal {
3071 #[doc = "Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
3072 pub const _0: Self = Self::new(0);
3073
3074 #[doc = "Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
3075 pub const _1: Self = Self::new(1);
3076 }
3077 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3078 pub struct Cscbfah_SPEC;
3079 pub type Cscbfah = crate::EnumBitfieldStruct<u8, Cscbfah_SPEC>;
3080 impl Cscbfah {
3081 #[doc = "Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
3082 pub const _0: Self = Self::new(0);
3083
3084 #[doc = "Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
3085 pub const _1: Self = Self::new(1);
3086 }
3087 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3088 pub struct Cselca_SPEC;
3089 pub type Cselca = crate::EnumBitfieldStruct<u8, Cselca_SPEC>;
3090 impl Cselca {
3091 #[doc = "Counter clear disabled at the ELC_GPTA input"]
3092 pub const _0: Self = Self::new(0);
3093
3094 #[doc = "Counter clear enabled at the ELC_GPTA input"]
3095 pub const _1: Self = Self::new(1);
3096 }
3097 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3098 pub struct Cselcb_SPEC;
3099 pub type Cselcb = crate::EnumBitfieldStruct<u8, Cselcb_SPEC>;
3100 impl Cselcb {
3101 #[doc = "Counter clear disabled at the ELC_GPTB input"]
3102 pub const _0: Self = Self::new(0);
3103
3104 #[doc = "Counter clear enabled at the ELC_GPTB input"]
3105 pub const _1: Self = Self::new(1);
3106 }
3107 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3108 pub struct Cselcc_SPEC;
3109 pub type Cselcc = crate::EnumBitfieldStruct<u8, Cselcc_SPEC>;
3110 impl Cselcc {
3111 #[doc = "Counter clear disabled at the ELC_GPTC input"]
3112 pub const _0: Self = Self::new(0);
3113
3114 #[doc = "Counter clear enabled at the ELC_GPTC input"]
3115 pub const _1: Self = Self::new(1);
3116 }
3117 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3118 pub struct Cselcd_SPEC;
3119 pub type Cselcd = crate::EnumBitfieldStruct<u8, Cselcd_SPEC>;
3120 impl Cselcd {
3121 #[doc = "Counter clear disabled at the ELC_GPTD input"]
3122 pub const _0: Self = Self::new(0);
3123
3124 #[doc = "Counter clear enabled at the ELC_GPTD input"]
3125 pub const _1: Self = Self::new(1);
3126 }
3127 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3128 pub struct Cclr_SPEC;
3129 pub type Cclr = crate::EnumBitfieldStruct<u8, Cclr_SPEC>;
3130 impl Cclr {
3131 #[doc = "Counter clear disabled by the GTCLR register"]
3132 pub const _0: Self = Self::new(0);
3133
3134 #[doc = "Counter clear enabled by the GTCLR register"]
3135 pub const _1: Self = Self::new(1);
3136 }
3137}
3138#[doc(hidden)]
3139#[derive(Copy, Clone, Eq, PartialEq)]
3140pub struct Gtupsr_SPEC;
3141impl crate::sealed::RegSpec for Gtupsr_SPEC {
3142 type DataType = u32;
3143}
3144
3145#[doc = "General PWM Timer Up Count Source Select Register"]
3146pub type Gtupsr = crate::RegValueT<Gtupsr_SPEC>;
3147
3148impl Gtupsr {
3149 #[doc = "GTETRGA Pin Rising Input Source Counter Count Up Enable"]
3150 #[inline(always)]
3151 pub fn usgtrgar(
3152 self,
3153 ) -> crate::common::RegisterField<
3154 0,
3155 0x1,
3156 1,
3157 0,
3158 gtupsr::Usgtrgar,
3159 gtupsr::Usgtrgar,
3160 Gtupsr_SPEC,
3161 crate::common::RW,
3162 > {
3163 crate::common::RegisterField::<
3164 0,
3165 0x1,
3166 1,
3167 0,
3168 gtupsr::Usgtrgar,
3169 gtupsr::Usgtrgar,
3170 Gtupsr_SPEC,
3171 crate::common::RW,
3172 >::from_register(self, 0)
3173 }
3174
3175 #[doc = "GTETRGA Pin Falling Input Source Counter Count Up Enable"]
3176 #[inline(always)]
3177 pub fn usgtrgaf(
3178 self,
3179 ) -> crate::common::RegisterField<
3180 1,
3181 0x1,
3182 1,
3183 0,
3184 gtupsr::Usgtrgaf,
3185 gtupsr::Usgtrgaf,
3186 Gtupsr_SPEC,
3187 crate::common::RW,
3188 > {
3189 crate::common::RegisterField::<
3190 1,
3191 0x1,
3192 1,
3193 0,
3194 gtupsr::Usgtrgaf,
3195 gtupsr::Usgtrgaf,
3196 Gtupsr_SPEC,
3197 crate::common::RW,
3198 >::from_register(self, 0)
3199 }
3200
3201 #[doc = "GTETRGB Pin Rising Input Source Counter Count Up Enable"]
3202 #[inline(always)]
3203 pub fn usgtrgbr(
3204 self,
3205 ) -> crate::common::RegisterField<
3206 2,
3207 0x1,
3208 1,
3209 0,
3210 gtupsr::Usgtrgbr,
3211 gtupsr::Usgtrgbr,
3212 Gtupsr_SPEC,
3213 crate::common::RW,
3214 > {
3215 crate::common::RegisterField::<
3216 2,
3217 0x1,
3218 1,
3219 0,
3220 gtupsr::Usgtrgbr,
3221 gtupsr::Usgtrgbr,
3222 Gtupsr_SPEC,
3223 crate::common::RW,
3224 >::from_register(self, 0)
3225 }
3226
3227 #[doc = "GTETRGB Pin Falling Input Source Counter Count Up Enable"]
3228 #[inline(always)]
3229 pub fn usgtrgbf(
3230 self,
3231 ) -> crate::common::RegisterField<
3232 3,
3233 0x1,
3234 1,
3235 0,
3236 gtupsr::Usgtrgbf,
3237 gtupsr::Usgtrgbf,
3238 Gtupsr_SPEC,
3239 crate::common::RW,
3240 > {
3241 crate::common::RegisterField::<
3242 3,
3243 0x1,
3244 1,
3245 0,
3246 gtupsr::Usgtrgbf,
3247 gtupsr::Usgtrgbf,
3248 Gtupsr_SPEC,
3249 crate::common::RW,
3250 >::from_register(self, 0)
3251 }
3252
3253 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable"]
3254 #[inline(always)]
3255 pub fn uscarbl(
3256 self,
3257 ) -> crate::common::RegisterField<
3258 8,
3259 0x1,
3260 1,
3261 0,
3262 gtupsr::Uscarbl,
3263 gtupsr::Uscarbl,
3264 Gtupsr_SPEC,
3265 crate::common::RW,
3266 > {
3267 crate::common::RegisterField::<
3268 8,
3269 0x1,
3270 1,
3271 0,
3272 gtupsr::Uscarbl,
3273 gtupsr::Uscarbl,
3274 Gtupsr_SPEC,
3275 crate::common::RW,
3276 >::from_register(self, 0)
3277 }
3278
3279 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable"]
3280 #[inline(always)]
3281 pub fn uscarbh(
3282 self,
3283 ) -> crate::common::RegisterField<
3284 9,
3285 0x1,
3286 1,
3287 0,
3288 gtupsr::Uscarbh,
3289 gtupsr::Uscarbh,
3290 Gtupsr_SPEC,
3291 crate::common::RW,
3292 > {
3293 crate::common::RegisterField::<
3294 9,
3295 0x1,
3296 1,
3297 0,
3298 gtupsr::Uscarbh,
3299 gtupsr::Uscarbh,
3300 Gtupsr_SPEC,
3301 crate::common::RW,
3302 >::from_register(self, 0)
3303 }
3304
3305 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable"]
3306 #[inline(always)]
3307 pub fn uscafbl(
3308 self,
3309 ) -> crate::common::RegisterField<
3310 10,
3311 0x1,
3312 1,
3313 0,
3314 gtupsr::Uscafbl,
3315 gtupsr::Uscafbl,
3316 Gtupsr_SPEC,
3317 crate::common::RW,
3318 > {
3319 crate::common::RegisterField::<
3320 10,
3321 0x1,
3322 1,
3323 0,
3324 gtupsr::Uscafbl,
3325 gtupsr::Uscafbl,
3326 Gtupsr_SPEC,
3327 crate::common::RW,
3328 >::from_register(self, 0)
3329 }
3330
3331 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable"]
3332 #[inline(always)]
3333 pub fn uscafbh(
3334 self,
3335 ) -> crate::common::RegisterField<
3336 11,
3337 0x1,
3338 1,
3339 0,
3340 gtupsr::Uscafbh,
3341 gtupsr::Uscafbh,
3342 Gtupsr_SPEC,
3343 crate::common::RW,
3344 > {
3345 crate::common::RegisterField::<
3346 11,
3347 0x1,
3348 1,
3349 0,
3350 gtupsr::Uscafbh,
3351 gtupsr::Uscafbh,
3352 Gtupsr_SPEC,
3353 crate::common::RW,
3354 >::from_register(self, 0)
3355 }
3356
3357 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable"]
3358 #[inline(always)]
3359 pub fn uscbral(
3360 self,
3361 ) -> crate::common::RegisterField<
3362 12,
3363 0x1,
3364 1,
3365 0,
3366 gtupsr::Uscbral,
3367 gtupsr::Uscbral,
3368 Gtupsr_SPEC,
3369 crate::common::RW,
3370 > {
3371 crate::common::RegisterField::<
3372 12,
3373 0x1,
3374 1,
3375 0,
3376 gtupsr::Uscbral,
3377 gtupsr::Uscbral,
3378 Gtupsr_SPEC,
3379 crate::common::RW,
3380 >::from_register(self, 0)
3381 }
3382
3383 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable"]
3384 #[inline(always)]
3385 pub fn uscbrah(
3386 self,
3387 ) -> crate::common::RegisterField<
3388 13,
3389 0x1,
3390 1,
3391 0,
3392 gtupsr::Uscbrah,
3393 gtupsr::Uscbrah,
3394 Gtupsr_SPEC,
3395 crate::common::RW,
3396 > {
3397 crate::common::RegisterField::<
3398 13,
3399 0x1,
3400 1,
3401 0,
3402 gtupsr::Uscbrah,
3403 gtupsr::Uscbrah,
3404 Gtupsr_SPEC,
3405 crate::common::RW,
3406 >::from_register(self, 0)
3407 }
3408
3409 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable"]
3410 #[inline(always)]
3411 pub fn uscbfal(
3412 self,
3413 ) -> crate::common::RegisterField<
3414 14,
3415 0x1,
3416 1,
3417 0,
3418 gtupsr::Uscbfal,
3419 gtupsr::Uscbfal,
3420 Gtupsr_SPEC,
3421 crate::common::RW,
3422 > {
3423 crate::common::RegisterField::<
3424 14,
3425 0x1,
3426 1,
3427 0,
3428 gtupsr::Uscbfal,
3429 gtupsr::Uscbfal,
3430 Gtupsr_SPEC,
3431 crate::common::RW,
3432 >::from_register(self, 0)
3433 }
3434
3435 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable"]
3436 #[inline(always)]
3437 pub fn uscbfah(
3438 self,
3439 ) -> crate::common::RegisterField<
3440 15,
3441 0x1,
3442 1,
3443 0,
3444 gtupsr::Uscbfah,
3445 gtupsr::Uscbfah,
3446 Gtupsr_SPEC,
3447 crate::common::RW,
3448 > {
3449 crate::common::RegisterField::<
3450 15,
3451 0x1,
3452 1,
3453 0,
3454 gtupsr::Uscbfah,
3455 gtupsr::Uscbfah,
3456 Gtupsr_SPEC,
3457 crate::common::RW,
3458 >::from_register(self, 0)
3459 }
3460
3461 #[doc = "ELC_GPTA Event Source Counter Count Up Enable"]
3462 #[inline(always)]
3463 pub fn uselca(
3464 self,
3465 ) -> crate::common::RegisterField<
3466 16,
3467 0x1,
3468 1,
3469 0,
3470 gtupsr::Uselca,
3471 gtupsr::Uselca,
3472 Gtupsr_SPEC,
3473 crate::common::RW,
3474 > {
3475 crate::common::RegisterField::<
3476 16,
3477 0x1,
3478 1,
3479 0,
3480 gtupsr::Uselca,
3481 gtupsr::Uselca,
3482 Gtupsr_SPEC,
3483 crate::common::RW,
3484 >::from_register(self, 0)
3485 }
3486
3487 #[doc = "ELC_GPTB Event Source Counter Count Up Enable"]
3488 #[inline(always)]
3489 pub fn uselcb(
3490 self,
3491 ) -> crate::common::RegisterField<
3492 17,
3493 0x1,
3494 1,
3495 0,
3496 gtupsr::Uselcb,
3497 gtupsr::Uselcb,
3498 Gtupsr_SPEC,
3499 crate::common::RW,
3500 > {
3501 crate::common::RegisterField::<
3502 17,
3503 0x1,
3504 1,
3505 0,
3506 gtupsr::Uselcb,
3507 gtupsr::Uselcb,
3508 Gtupsr_SPEC,
3509 crate::common::RW,
3510 >::from_register(self, 0)
3511 }
3512
3513 #[doc = "ELC_GPTC Event Source Counter Count Up Enable"]
3514 #[inline(always)]
3515 pub fn uselcc(
3516 self,
3517 ) -> crate::common::RegisterField<
3518 18,
3519 0x1,
3520 1,
3521 0,
3522 gtupsr::Uselcc,
3523 gtupsr::Uselcc,
3524 Gtupsr_SPEC,
3525 crate::common::RW,
3526 > {
3527 crate::common::RegisterField::<
3528 18,
3529 0x1,
3530 1,
3531 0,
3532 gtupsr::Uselcc,
3533 gtupsr::Uselcc,
3534 Gtupsr_SPEC,
3535 crate::common::RW,
3536 >::from_register(self, 0)
3537 }
3538
3539 #[doc = "ELC_GPTD Event Source Counter Count Up Enable"]
3540 #[inline(always)]
3541 pub fn uselcd(
3542 self,
3543 ) -> crate::common::RegisterField<
3544 19,
3545 0x1,
3546 1,
3547 0,
3548 gtupsr::Uselcd,
3549 gtupsr::Uselcd,
3550 Gtupsr_SPEC,
3551 crate::common::RW,
3552 > {
3553 crate::common::RegisterField::<
3554 19,
3555 0x1,
3556 1,
3557 0,
3558 gtupsr::Uselcd,
3559 gtupsr::Uselcd,
3560 Gtupsr_SPEC,
3561 crate::common::RW,
3562 >::from_register(self, 0)
3563 }
3564}
3565impl ::core::default::Default for Gtupsr {
3566 #[inline(always)]
3567 fn default() -> Gtupsr {
3568 <crate::RegValueT<Gtupsr_SPEC> as RegisterValue<_>>::new(0)
3569 }
3570}
3571pub mod gtupsr {
3572
3573 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3574 pub struct Usgtrgar_SPEC;
3575 pub type Usgtrgar = crate::EnumBitfieldStruct<u8, Usgtrgar_SPEC>;
3576 impl Usgtrgar {
3577 #[doc = "Counter count up disabled on the rising edge of GTETRGA input"]
3578 pub const _0: Self = Self::new(0);
3579
3580 #[doc = "Counter count up enabled on the rising edge of GTETRGA input"]
3581 pub const _1: Self = Self::new(1);
3582 }
3583 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3584 pub struct Usgtrgaf_SPEC;
3585 pub type Usgtrgaf = crate::EnumBitfieldStruct<u8, Usgtrgaf_SPEC>;
3586 impl Usgtrgaf {
3587 #[doc = "Counter count up disabled on the falling edge of GTETRGA input"]
3588 pub const _0: Self = Self::new(0);
3589
3590 #[doc = "Counter count up enabled on the falling edge of GTETRGA input"]
3591 pub const _1: Self = Self::new(1);
3592 }
3593 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3594 pub struct Usgtrgbr_SPEC;
3595 pub type Usgtrgbr = crate::EnumBitfieldStruct<u8, Usgtrgbr_SPEC>;
3596 impl Usgtrgbr {
3597 #[doc = "Counter count up disabled on the rising edge of GTETRGB input"]
3598 pub const _0: Self = Self::new(0);
3599
3600 #[doc = "Counter count up enabled on the rising edge of GTETRGB input"]
3601 pub const _1: Self = Self::new(1);
3602 }
3603 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3604 pub struct Usgtrgbf_SPEC;
3605 pub type Usgtrgbf = crate::EnumBitfieldStruct<u8, Usgtrgbf_SPEC>;
3606 impl Usgtrgbf {
3607 #[doc = "Counter count up disabled on the falling edge of GTETRGB input"]
3608 pub const _0: Self = Self::new(0);
3609
3610 #[doc = "Counter count up enabled on the falling edge of GTETRGB input"]
3611 pub const _1: Self = Self::new(1);
3612 }
3613 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3614 pub struct Uscarbl_SPEC;
3615 pub type Uscarbl = crate::EnumBitfieldStruct<u8, Uscarbl_SPEC>;
3616 impl Uscarbl {
3617 #[doc = "Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
3618 pub const _0: Self = Self::new(0);
3619
3620 #[doc = "Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
3621 pub const _1: Self = Self::new(1);
3622 }
3623 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3624 pub struct Uscarbh_SPEC;
3625 pub type Uscarbh = crate::EnumBitfieldStruct<u8, Uscarbh_SPEC>;
3626 impl Uscarbh {
3627 #[doc = "Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
3628 pub const _0: Self = Self::new(0);
3629
3630 #[doc = "Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
3631 pub const _1: Self = Self::new(1);
3632 }
3633 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3634 pub struct Uscafbl_SPEC;
3635 pub type Uscafbl = crate::EnumBitfieldStruct<u8, Uscafbl_SPEC>;
3636 impl Uscafbl {
3637 #[doc = "Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
3638 pub const _0: Self = Self::new(0);
3639
3640 #[doc = "Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
3641 pub const _1: Self = Self::new(1);
3642 }
3643 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3644 pub struct Uscafbh_SPEC;
3645 pub type Uscafbh = crate::EnumBitfieldStruct<u8, Uscafbh_SPEC>;
3646 impl Uscafbh {
3647 #[doc = "Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
3648 pub const _0: Self = Self::new(0);
3649
3650 #[doc = "Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
3651 pub const _1: Self = Self::new(1);
3652 }
3653 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3654 pub struct Uscbral_SPEC;
3655 pub type Uscbral = crate::EnumBitfieldStruct<u8, Uscbral_SPEC>;
3656 impl Uscbral {
3657 #[doc = "Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
3658 pub const _0: Self = Self::new(0);
3659
3660 #[doc = "Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
3661 pub const _1: Self = Self::new(1);
3662 }
3663 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3664 pub struct Uscbrah_SPEC;
3665 pub type Uscbrah = crate::EnumBitfieldStruct<u8, Uscbrah_SPEC>;
3666 impl Uscbrah {
3667 #[doc = "Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
3668 pub const _0: Self = Self::new(0);
3669
3670 #[doc = "Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
3671 pub const _1: Self = Self::new(1);
3672 }
3673 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3674 pub struct Uscbfal_SPEC;
3675 pub type Uscbfal = crate::EnumBitfieldStruct<u8, Uscbfal_SPEC>;
3676 impl Uscbfal {
3677 #[doc = "Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
3678 pub const _0: Self = Self::new(0);
3679
3680 #[doc = "Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
3681 pub const _1: Self = Self::new(1);
3682 }
3683 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3684 pub struct Uscbfah_SPEC;
3685 pub type Uscbfah = crate::EnumBitfieldStruct<u8, Uscbfah_SPEC>;
3686 impl Uscbfah {
3687 #[doc = "Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
3688 pub const _0: Self = Self::new(0);
3689
3690 #[doc = "Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
3691 pub const _1: Self = Self::new(1);
3692 }
3693 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3694 pub struct Uselca_SPEC;
3695 pub type Uselca = crate::EnumBitfieldStruct<u8, Uselca_SPEC>;
3696 impl Uselca {
3697 #[doc = "Counter count up disabled at the ELC_GPTA input"]
3698 pub const _0: Self = Self::new(0);
3699
3700 #[doc = "Counter count up enabled at the ELC_GPTA input"]
3701 pub const _1: Self = Self::new(1);
3702 }
3703 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3704 pub struct Uselcb_SPEC;
3705 pub type Uselcb = crate::EnumBitfieldStruct<u8, Uselcb_SPEC>;
3706 impl Uselcb {
3707 #[doc = "Counter count up disabled at the ELC_GPTB input"]
3708 pub const _0: Self = Self::new(0);
3709
3710 #[doc = "Counter count up enabled at the ELC_GPTB input"]
3711 pub const _1: Self = Self::new(1);
3712 }
3713 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3714 pub struct Uselcc_SPEC;
3715 pub type Uselcc = crate::EnumBitfieldStruct<u8, Uselcc_SPEC>;
3716 impl Uselcc {
3717 #[doc = "Counter count up disabled at the ELC_GPTC input"]
3718 pub const _0: Self = Self::new(0);
3719
3720 #[doc = "Counter count up enabled at the ELC_GPTC input"]
3721 pub const _1: Self = Self::new(1);
3722 }
3723 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3724 pub struct Uselcd_SPEC;
3725 pub type Uselcd = crate::EnumBitfieldStruct<u8, Uselcd_SPEC>;
3726 impl Uselcd {
3727 #[doc = "Counter count up disabled at the ELC_GPTD input"]
3728 pub const _0: Self = Self::new(0);
3729
3730 #[doc = "Counter count up enabled at the ELC_GPTD input"]
3731 pub const _1: Self = Self::new(1);
3732 }
3733}
3734#[doc(hidden)]
3735#[derive(Copy, Clone, Eq, PartialEq)]
3736pub struct Gtdnsr_SPEC;
3737impl crate::sealed::RegSpec for Gtdnsr_SPEC {
3738 type DataType = u32;
3739}
3740
3741#[doc = "General PWM Timer Down Count Source Select Register"]
3742pub type Gtdnsr = crate::RegValueT<Gtdnsr_SPEC>;
3743
3744impl Gtdnsr {
3745 #[doc = "GTETRGA Pin Rising Input Source Counter Count Down Enable"]
3746 #[inline(always)]
3747 pub fn dsgtrgar(
3748 self,
3749 ) -> crate::common::RegisterField<
3750 0,
3751 0x1,
3752 1,
3753 0,
3754 gtdnsr::Dsgtrgar,
3755 gtdnsr::Dsgtrgar,
3756 Gtdnsr_SPEC,
3757 crate::common::RW,
3758 > {
3759 crate::common::RegisterField::<
3760 0,
3761 0x1,
3762 1,
3763 0,
3764 gtdnsr::Dsgtrgar,
3765 gtdnsr::Dsgtrgar,
3766 Gtdnsr_SPEC,
3767 crate::common::RW,
3768 >::from_register(self, 0)
3769 }
3770
3771 #[doc = "GTETRGA Pin Falling Input Source Counter Count Down Enable"]
3772 #[inline(always)]
3773 pub fn dsgtrgaf(
3774 self,
3775 ) -> crate::common::RegisterField<
3776 1,
3777 0x1,
3778 1,
3779 0,
3780 gtdnsr::Dsgtrgaf,
3781 gtdnsr::Dsgtrgaf,
3782 Gtdnsr_SPEC,
3783 crate::common::RW,
3784 > {
3785 crate::common::RegisterField::<
3786 1,
3787 0x1,
3788 1,
3789 0,
3790 gtdnsr::Dsgtrgaf,
3791 gtdnsr::Dsgtrgaf,
3792 Gtdnsr_SPEC,
3793 crate::common::RW,
3794 >::from_register(self, 0)
3795 }
3796
3797 #[doc = "GTETRGB Pin Rising Input Source Counter Count Down Enable"]
3798 #[inline(always)]
3799 pub fn dsgtrgbr(
3800 self,
3801 ) -> crate::common::RegisterField<
3802 2,
3803 0x1,
3804 1,
3805 0,
3806 gtdnsr::Dsgtrgbr,
3807 gtdnsr::Dsgtrgbr,
3808 Gtdnsr_SPEC,
3809 crate::common::RW,
3810 > {
3811 crate::common::RegisterField::<
3812 2,
3813 0x1,
3814 1,
3815 0,
3816 gtdnsr::Dsgtrgbr,
3817 gtdnsr::Dsgtrgbr,
3818 Gtdnsr_SPEC,
3819 crate::common::RW,
3820 >::from_register(self, 0)
3821 }
3822
3823 #[doc = "GTETRGB Pin Falling Input Source Counter Count Down Enable"]
3824 #[inline(always)]
3825 pub fn dsgtrgbf(
3826 self,
3827 ) -> crate::common::RegisterField<
3828 3,
3829 0x1,
3830 1,
3831 0,
3832 gtdnsr::Dsgtrgbf,
3833 gtdnsr::Dsgtrgbf,
3834 Gtdnsr_SPEC,
3835 crate::common::RW,
3836 > {
3837 crate::common::RegisterField::<
3838 3,
3839 0x1,
3840 1,
3841 0,
3842 gtdnsr::Dsgtrgbf,
3843 gtdnsr::Dsgtrgbf,
3844 Gtdnsr_SPEC,
3845 crate::common::RW,
3846 >::from_register(self, 0)
3847 }
3848
3849 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable"]
3850 #[inline(always)]
3851 pub fn dscarbl(
3852 self,
3853 ) -> crate::common::RegisterField<
3854 8,
3855 0x1,
3856 1,
3857 0,
3858 gtdnsr::Dscarbl,
3859 gtdnsr::Dscarbl,
3860 Gtdnsr_SPEC,
3861 crate::common::RW,
3862 > {
3863 crate::common::RegisterField::<
3864 8,
3865 0x1,
3866 1,
3867 0,
3868 gtdnsr::Dscarbl,
3869 gtdnsr::Dscarbl,
3870 Gtdnsr_SPEC,
3871 crate::common::RW,
3872 >::from_register(self, 0)
3873 }
3874
3875 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable"]
3876 #[inline(always)]
3877 pub fn dscarbh(
3878 self,
3879 ) -> crate::common::RegisterField<
3880 9,
3881 0x1,
3882 1,
3883 0,
3884 gtdnsr::Dscarbh,
3885 gtdnsr::Dscarbh,
3886 Gtdnsr_SPEC,
3887 crate::common::RW,
3888 > {
3889 crate::common::RegisterField::<
3890 9,
3891 0x1,
3892 1,
3893 0,
3894 gtdnsr::Dscarbh,
3895 gtdnsr::Dscarbh,
3896 Gtdnsr_SPEC,
3897 crate::common::RW,
3898 >::from_register(self, 0)
3899 }
3900
3901 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable"]
3902 #[inline(always)]
3903 pub fn dscafbl(
3904 self,
3905 ) -> crate::common::RegisterField<
3906 10,
3907 0x1,
3908 1,
3909 0,
3910 gtdnsr::Dscafbl,
3911 gtdnsr::Dscafbl,
3912 Gtdnsr_SPEC,
3913 crate::common::RW,
3914 > {
3915 crate::common::RegisterField::<
3916 10,
3917 0x1,
3918 1,
3919 0,
3920 gtdnsr::Dscafbl,
3921 gtdnsr::Dscafbl,
3922 Gtdnsr_SPEC,
3923 crate::common::RW,
3924 >::from_register(self, 0)
3925 }
3926
3927 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable"]
3928 #[inline(always)]
3929 pub fn dscafbh(
3930 self,
3931 ) -> crate::common::RegisterField<
3932 11,
3933 0x1,
3934 1,
3935 0,
3936 gtdnsr::Dscafbh,
3937 gtdnsr::Dscafbh,
3938 Gtdnsr_SPEC,
3939 crate::common::RW,
3940 > {
3941 crate::common::RegisterField::<
3942 11,
3943 0x1,
3944 1,
3945 0,
3946 gtdnsr::Dscafbh,
3947 gtdnsr::Dscafbh,
3948 Gtdnsr_SPEC,
3949 crate::common::RW,
3950 >::from_register(self, 0)
3951 }
3952
3953 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable"]
3954 #[inline(always)]
3955 pub fn dscbral(
3956 self,
3957 ) -> crate::common::RegisterField<
3958 12,
3959 0x1,
3960 1,
3961 0,
3962 gtdnsr::Dscbral,
3963 gtdnsr::Dscbral,
3964 Gtdnsr_SPEC,
3965 crate::common::RW,
3966 > {
3967 crate::common::RegisterField::<
3968 12,
3969 0x1,
3970 1,
3971 0,
3972 gtdnsr::Dscbral,
3973 gtdnsr::Dscbral,
3974 Gtdnsr_SPEC,
3975 crate::common::RW,
3976 >::from_register(self, 0)
3977 }
3978
3979 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable"]
3980 #[inline(always)]
3981 pub fn dscbrah(
3982 self,
3983 ) -> crate::common::RegisterField<
3984 13,
3985 0x1,
3986 1,
3987 0,
3988 gtdnsr::Dscbrah,
3989 gtdnsr::Dscbrah,
3990 Gtdnsr_SPEC,
3991 crate::common::RW,
3992 > {
3993 crate::common::RegisterField::<
3994 13,
3995 0x1,
3996 1,
3997 0,
3998 gtdnsr::Dscbrah,
3999 gtdnsr::Dscbrah,
4000 Gtdnsr_SPEC,
4001 crate::common::RW,
4002 >::from_register(self, 0)
4003 }
4004
4005 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable"]
4006 #[inline(always)]
4007 pub fn dscbfal(
4008 self,
4009 ) -> crate::common::RegisterField<
4010 14,
4011 0x1,
4012 1,
4013 0,
4014 gtdnsr::Dscbfal,
4015 gtdnsr::Dscbfal,
4016 Gtdnsr_SPEC,
4017 crate::common::RW,
4018 > {
4019 crate::common::RegisterField::<
4020 14,
4021 0x1,
4022 1,
4023 0,
4024 gtdnsr::Dscbfal,
4025 gtdnsr::Dscbfal,
4026 Gtdnsr_SPEC,
4027 crate::common::RW,
4028 >::from_register(self, 0)
4029 }
4030
4031 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable"]
4032 #[inline(always)]
4033 pub fn dscbfah(
4034 self,
4035 ) -> crate::common::RegisterField<
4036 15,
4037 0x1,
4038 1,
4039 0,
4040 gtdnsr::Dscbfah,
4041 gtdnsr::Dscbfah,
4042 Gtdnsr_SPEC,
4043 crate::common::RW,
4044 > {
4045 crate::common::RegisterField::<
4046 15,
4047 0x1,
4048 1,
4049 0,
4050 gtdnsr::Dscbfah,
4051 gtdnsr::Dscbfah,
4052 Gtdnsr_SPEC,
4053 crate::common::RW,
4054 >::from_register(self, 0)
4055 }
4056
4057 #[doc = "ELC_GPTA Event Source Counter Count Down Enable"]
4058 #[inline(always)]
4059 pub fn dselca(
4060 self,
4061 ) -> crate::common::RegisterField<
4062 16,
4063 0x1,
4064 1,
4065 0,
4066 gtdnsr::Dselca,
4067 gtdnsr::Dselca,
4068 Gtdnsr_SPEC,
4069 crate::common::RW,
4070 > {
4071 crate::common::RegisterField::<
4072 16,
4073 0x1,
4074 1,
4075 0,
4076 gtdnsr::Dselca,
4077 gtdnsr::Dselca,
4078 Gtdnsr_SPEC,
4079 crate::common::RW,
4080 >::from_register(self, 0)
4081 }
4082
4083 #[doc = "ELC_GPTB Event Source Counter Count Down Enable"]
4084 #[inline(always)]
4085 pub fn dselcb(
4086 self,
4087 ) -> crate::common::RegisterField<
4088 17,
4089 0x1,
4090 1,
4091 0,
4092 gtdnsr::Dselcb,
4093 gtdnsr::Dselcb,
4094 Gtdnsr_SPEC,
4095 crate::common::RW,
4096 > {
4097 crate::common::RegisterField::<
4098 17,
4099 0x1,
4100 1,
4101 0,
4102 gtdnsr::Dselcb,
4103 gtdnsr::Dselcb,
4104 Gtdnsr_SPEC,
4105 crate::common::RW,
4106 >::from_register(self, 0)
4107 }
4108
4109 #[doc = "ELC_GPTC Event Source Counter Count Down Enable"]
4110 #[inline(always)]
4111 pub fn dselcc(
4112 self,
4113 ) -> crate::common::RegisterField<
4114 18,
4115 0x1,
4116 1,
4117 0,
4118 gtdnsr::Dselcc,
4119 gtdnsr::Dselcc,
4120 Gtdnsr_SPEC,
4121 crate::common::RW,
4122 > {
4123 crate::common::RegisterField::<
4124 18,
4125 0x1,
4126 1,
4127 0,
4128 gtdnsr::Dselcc,
4129 gtdnsr::Dselcc,
4130 Gtdnsr_SPEC,
4131 crate::common::RW,
4132 >::from_register(self, 0)
4133 }
4134
4135 #[doc = "ELC_GPTD Event Source Counter Count Down Enable"]
4136 #[inline(always)]
4137 pub fn dselcd(
4138 self,
4139 ) -> crate::common::RegisterField<
4140 19,
4141 0x1,
4142 1,
4143 0,
4144 gtdnsr::Dselcd,
4145 gtdnsr::Dselcd,
4146 Gtdnsr_SPEC,
4147 crate::common::RW,
4148 > {
4149 crate::common::RegisterField::<
4150 19,
4151 0x1,
4152 1,
4153 0,
4154 gtdnsr::Dselcd,
4155 gtdnsr::Dselcd,
4156 Gtdnsr_SPEC,
4157 crate::common::RW,
4158 >::from_register(self, 0)
4159 }
4160}
4161impl ::core::default::Default for Gtdnsr {
4162 #[inline(always)]
4163 fn default() -> Gtdnsr {
4164 <crate::RegValueT<Gtdnsr_SPEC> as RegisterValue<_>>::new(0)
4165 }
4166}
4167pub mod gtdnsr {
4168
4169 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4170 pub struct Dsgtrgar_SPEC;
4171 pub type Dsgtrgar = crate::EnumBitfieldStruct<u8, Dsgtrgar_SPEC>;
4172 impl Dsgtrgar {
4173 #[doc = "Counter count down disabled on the rising edge of GTETRGA input"]
4174 pub const _0: Self = Self::new(0);
4175
4176 #[doc = "Counter count down enabled on the rising edge of GTETRGA input"]
4177 pub const _1: Self = Self::new(1);
4178 }
4179 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4180 pub struct Dsgtrgaf_SPEC;
4181 pub type Dsgtrgaf = crate::EnumBitfieldStruct<u8, Dsgtrgaf_SPEC>;
4182 impl Dsgtrgaf {
4183 #[doc = "Counter count down disabled on the falling edge of GTETRGA input"]
4184 pub const _0: Self = Self::new(0);
4185
4186 #[doc = "Counter count down enabled on the falling edge of GTETRGA input"]
4187 pub const _1: Self = Self::new(1);
4188 }
4189 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4190 pub struct Dsgtrgbr_SPEC;
4191 pub type Dsgtrgbr = crate::EnumBitfieldStruct<u8, Dsgtrgbr_SPEC>;
4192 impl Dsgtrgbr {
4193 #[doc = "Counter count down disabled on the rising edge of GTETRGB input"]
4194 pub const _0: Self = Self::new(0);
4195
4196 #[doc = "Counter count down enabled on the rising edge of GTETRGB input"]
4197 pub const _1: Self = Self::new(1);
4198 }
4199 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4200 pub struct Dsgtrgbf_SPEC;
4201 pub type Dsgtrgbf = crate::EnumBitfieldStruct<u8, Dsgtrgbf_SPEC>;
4202 impl Dsgtrgbf {
4203 #[doc = "Counter count down disabled on the falling edge of GTETRGB input"]
4204 pub const _0: Self = Self::new(0);
4205
4206 #[doc = "Counter count down enabled on the falling edge of GTETRGB input"]
4207 pub const _1: Self = Self::new(1);
4208 }
4209 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4210 pub struct Dscarbl_SPEC;
4211 pub type Dscarbl = crate::EnumBitfieldStruct<u8, Dscarbl_SPEC>;
4212 impl Dscarbl {
4213 #[doc = "Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
4214 pub const _0: Self = Self::new(0);
4215
4216 #[doc = "Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
4217 pub const _1: Self = Self::new(1);
4218 }
4219 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4220 pub struct Dscarbh_SPEC;
4221 pub type Dscarbh = crate::EnumBitfieldStruct<u8, Dscarbh_SPEC>;
4222 impl Dscarbh {
4223 #[doc = "Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
4224 pub const _0: Self = Self::new(0);
4225
4226 #[doc = "Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
4227 pub const _1: Self = Self::new(1);
4228 }
4229 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4230 pub struct Dscafbl_SPEC;
4231 pub type Dscafbl = crate::EnumBitfieldStruct<u8, Dscafbl_SPEC>;
4232 impl Dscafbl {
4233 #[doc = "Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
4234 pub const _0: Self = Self::new(0);
4235
4236 #[doc = "Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
4237 pub const _1: Self = Self::new(1);
4238 }
4239 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4240 pub struct Dscafbh_SPEC;
4241 pub type Dscafbh = crate::EnumBitfieldStruct<u8, Dscafbh_SPEC>;
4242 impl Dscafbh {
4243 #[doc = "Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
4244 pub const _0: Self = Self::new(0);
4245
4246 #[doc = "Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
4247 pub const _1: Self = Self::new(1);
4248 }
4249 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4250 pub struct Dscbral_SPEC;
4251 pub type Dscbral = crate::EnumBitfieldStruct<u8, Dscbral_SPEC>;
4252 impl Dscbral {
4253 #[doc = "Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
4254 pub const _0: Self = Self::new(0);
4255
4256 #[doc = "Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
4257 pub const _1: Self = Self::new(1);
4258 }
4259 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4260 pub struct Dscbrah_SPEC;
4261 pub type Dscbrah = crate::EnumBitfieldStruct<u8, Dscbrah_SPEC>;
4262 impl Dscbrah {
4263 #[doc = "Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
4264 pub const _0: Self = Self::new(0);
4265
4266 #[doc = "Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
4267 pub const _1: Self = Self::new(1);
4268 }
4269 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4270 pub struct Dscbfal_SPEC;
4271 pub type Dscbfal = crate::EnumBitfieldStruct<u8, Dscbfal_SPEC>;
4272 impl Dscbfal {
4273 #[doc = "Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
4274 pub const _0: Self = Self::new(0);
4275
4276 #[doc = "Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
4277 pub const _1: Self = Self::new(1);
4278 }
4279 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4280 pub struct Dscbfah_SPEC;
4281 pub type Dscbfah = crate::EnumBitfieldStruct<u8, Dscbfah_SPEC>;
4282 impl Dscbfah {
4283 #[doc = "Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
4284 pub const _0: Self = Self::new(0);
4285
4286 #[doc = "Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
4287 pub const _1: Self = Self::new(1);
4288 }
4289 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4290 pub struct Dselca_SPEC;
4291 pub type Dselca = crate::EnumBitfieldStruct<u8, Dselca_SPEC>;
4292 impl Dselca {
4293 #[doc = "Counter count down disabled at the ELC_GPTA input"]
4294 pub const _0: Self = Self::new(0);
4295
4296 #[doc = "Counter count down enabled at the ELC_GPTA input"]
4297 pub const _1: Self = Self::new(1);
4298 }
4299 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4300 pub struct Dselcb_SPEC;
4301 pub type Dselcb = crate::EnumBitfieldStruct<u8, Dselcb_SPEC>;
4302 impl Dselcb {
4303 #[doc = "Counter count down disabled at the ELC_GPTB input"]
4304 pub const _0: Self = Self::new(0);
4305
4306 #[doc = "Counter count down enabled at the ELC_GPTB input"]
4307 pub const _1: Self = Self::new(1);
4308 }
4309 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4310 pub struct Dselcc_SPEC;
4311 pub type Dselcc = crate::EnumBitfieldStruct<u8, Dselcc_SPEC>;
4312 impl Dselcc {
4313 #[doc = "Counter count down disabled at the ELC_GPTC input"]
4314 pub const _0: Self = Self::new(0);
4315
4316 #[doc = "Counter count down enabled at the ELC_GPTC input"]
4317 pub const _1: Self = Self::new(1);
4318 }
4319 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4320 pub struct Dselcd_SPEC;
4321 pub type Dselcd = crate::EnumBitfieldStruct<u8, Dselcd_SPEC>;
4322 impl Dselcd {
4323 #[doc = "Counter count down disabled at the ELC_GPTD input"]
4324 pub const _0: Self = Self::new(0);
4325
4326 #[doc = "Counter count down enabled at the ELC_GPTD input"]
4327 pub const _1: Self = Self::new(1);
4328 }
4329}
4330#[doc(hidden)]
4331#[derive(Copy, Clone, Eq, PartialEq)]
4332pub struct Gticasr_SPEC;
4333impl crate::sealed::RegSpec for Gticasr_SPEC {
4334 type DataType = u32;
4335}
4336
4337#[doc = "General PWM Timer Input Capture Source Select Register A"]
4338pub type Gticasr = crate::RegValueT<Gticasr_SPEC>;
4339
4340impl Gticasr {
4341 #[doc = "GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable"]
4342 #[inline(always)]
4343 pub fn asgtrgar(
4344 self,
4345 ) -> crate::common::RegisterField<
4346 0,
4347 0x1,
4348 1,
4349 0,
4350 gticasr::Asgtrgar,
4351 gticasr::Asgtrgar,
4352 Gticasr_SPEC,
4353 crate::common::RW,
4354 > {
4355 crate::common::RegisterField::<
4356 0,
4357 0x1,
4358 1,
4359 0,
4360 gticasr::Asgtrgar,
4361 gticasr::Asgtrgar,
4362 Gticasr_SPEC,
4363 crate::common::RW,
4364 >::from_register(self, 0)
4365 }
4366
4367 #[doc = "GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable"]
4368 #[inline(always)]
4369 pub fn asgtrgaf(
4370 self,
4371 ) -> crate::common::RegisterField<
4372 1,
4373 0x1,
4374 1,
4375 0,
4376 gticasr::Asgtrgaf,
4377 gticasr::Asgtrgaf,
4378 Gticasr_SPEC,
4379 crate::common::RW,
4380 > {
4381 crate::common::RegisterField::<
4382 1,
4383 0x1,
4384 1,
4385 0,
4386 gticasr::Asgtrgaf,
4387 gticasr::Asgtrgaf,
4388 Gticasr_SPEC,
4389 crate::common::RW,
4390 >::from_register(self, 0)
4391 }
4392
4393 #[doc = "GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable"]
4394 #[inline(always)]
4395 pub fn asgtrgbr(
4396 self,
4397 ) -> crate::common::RegisterField<
4398 2,
4399 0x1,
4400 1,
4401 0,
4402 gticasr::Asgtrgbr,
4403 gticasr::Asgtrgbr,
4404 Gticasr_SPEC,
4405 crate::common::RW,
4406 > {
4407 crate::common::RegisterField::<
4408 2,
4409 0x1,
4410 1,
4411 0,
4412 gticasr::Asgtrgbr,
4413 gticasr::Asgtrgbr,
4414 Gticasr_SPEC,
4415 crate::common::RW,
4416 >::from_register(self, 0)
4417 }
4418
4419 #[doc = "GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable"]
4420 #[inline(always)]
4421 pub fn asgtrgbf(
4422 self,
4423 ) -> crate::common::RegisterField<
4424 3,
4425 0x1,
4426 1,
4427 0,
4428 gticasr::Asgtrgbf,
4429 gticasr::Asgtrgbf,
4430 Gticasr_SPEC,
4431 crate::common::RW,
4432 > {
4433 crate::common::RegisterField::<
4434 3,
4435 0x1,
4436 1,
4437 0,
4438 gticasr::Asgtrgbf,
4439 gticasr::Asgtrgbf,
4440 Gticasr_SPEC,
4441 crate::common::RW,
4442 >::from_register(self, 0)
4443 }
4444
4445 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable"]
4446 #[inline(always)]
4447 pub fn ascarbl(
4448 self,
4449 ) -> crate::common::RegisterField<
4450 8,
4451 0x1,
4452 1,
4453 0,
4454 gticasr::Ascarbl,
4455 gticasr::Ascarbl,
4456 Gticasr_SPEC,
4457 crate::common::RW,
4458 > {
4459 crate::common::RegisterField::<
4460 8,
4461 0x1,
4462 1,
4463 0,
4464 gticasr::Ascarbl,
4465 gticasr::Ascarbl,
4466 Gticasr_SPEC,
4467 crate::common::RW,
4468 >::from_register(self, 0)
4469 }
4470
4471 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable"]
4472 #[inline(always)]
4473 pub fn ascarbh(
4474 self,
4475 ) -> crate::common::RegisterField<
4476 9,
4477 0x1,
4478 1,
4479 0,
4480 gticasr::Ascarbh,
4481 gticasr::Ascarbh,
4482 Gticasr_SPEC,
4483 crate::common::RW,
4484 > {
4485 crate::common::RegisterField::<
4486 9,
4487 0x1,
4488 1,
4489 0,
4490 gticasr::Ascarbh,
4491 gticasr::Ascarbh,
4492 Gticasr_SPEC,
4493 crate::common::RW,
4494 >::from_register(self, 0)
4495 }
4496
4497 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable"]
4498 #[inline(always)]
4499 pub fn ascafbl(
4500 self,
4501 ) -> crate::common::RegisterField<
4502 10,
4503 0x1,
4504 1,
4505 0,
4506 gticasr::Ascafbl,
4507 gticasr::Ascafbl,
4508 Gticasr_SPEC,
4509 crate::common::RW,
4510 > {
4511 crate::common::RegisterField::<
4512 10,
4513 0x1,
4514 1,
4515 0,
4516 gticasr::Ascafbl,
4517 gticasr::Ascafbl,
4518 Gticasr_SPEC,
4519 crate::common::RW,
4520 >::from_register(self, 0)
4521 }
4522
4523 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable"]
4524 #[inline(always)]
4525 pub fn ascafbh(
4526 self,
4527 ) -> crate::common::RegisterField<
4528 11,
4529 0x1,
4530 1,
4531 0,
4532 gticasr::Ascafbh,
4533 gticasr::Ascafbh,
4534 Gticasr_SPEC,
4535 crate::common::RW,
4536 > {
4537 crate::common::RegisterField::<
4538 11,
4539 0x1,
4540 1,
4541 0,
4542 gticasr::Ascafbh,
4543 gticasr::Ascafbh,
4544 Gticasr_SPEC,
4545 crate::common::RW,
4546 >::from_register(self, 0)
4547 }
4548
4549 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable"]
4550 #[inline(always)]
4551 pub fn ascbral(
4552 self,
4553 ) -> crate::common::RegisterField<
4554 12,
4555 0x1,
4556 1,
4557 0,
4558 gticasr::Ascbral,
4559 gticasr::Ascbral,
4560 Gticasr_SPEC,
4561 crate::common::RW,
4562 > {
4563 crate::common::RegisterField::<
4564 12,
4565 0x1,
4566 1,
4567 0,
4568 gticasr::Ascbral,
4569 gticasr::Ascbral,
4570 Gticasr_SPEC,
4571 crate::common::RW,
4572 >::from_register(self, 0)
4573 }
4574
4575 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable"]
4576 #[inline(always)]
4577 pub fn ascbrah(
4578 self,
4579 ) -> crate::common::RegisterField<
4580 13,
4581 0x1,
4582 1,
4583 0,
4584 gticasr::Ascbrah,
4585 gticasr::Ascbrah,
4586 Gticasr_SPEC,
4587 crate::common::RW,
4588 > {
4589 crate::common::RegisterField::<
4590 13,
4591 0x1,
4592 1,
4593 0,
4594 gticasr::Ascbrah,
4595 gticasr::Ascbrah,
4596 Gticasr_SPEC,
4597 crate::common::RW,
4598 >::from_register(self, 0)
4599 }
4600
4601 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable"]
4602 #[inline(always)]
4603 pub fn ascbfal(
4604 self,
4605 ) -> crate::common::RegisterField<
4606 14,
4607 0x1,
4608 1,
4609 0,
4610 gticasr::Ascbfal,
4611 gticasr::Ascbfal,
4612 Gticasr_SPEC,
4613 crate::common::RW,
4614 > {
4615 crate::common::RegisterField::<
4616 14,
4617 0x1,
4618 1,
4619 0,
4620 gticasr::Ascbfal,
4621 gticasr::Ascbfal,
4622 Gticasr_SPEC,
4623 crate::common::RW,
4624 >::from_register(self, 0)
4625 }
4626
4627 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable"]
4628 #[inline(always)]
4629 pub fn ascbfah(
4630 self,
4631 ) -> crate::common::RegisterField<
4632 15,
4633 0x1,
4634 1,
4635 0,
4636 gticasr::Ascbfah,
4637 gticasr::Ascbfah,
4638 Gticasr_SPEC,
4639 crate::common::RW,
4640 > {
4641 crate::common::RegisterField::<
4642 15,
4643 0x1,
4644 1,
4645 0,
4646 gticasr::Ascbfah,
4647 gticasr::Ascbfah,
4648 Gticasr_SPEC,
4649 crate::common::RW,
4650 >::from_register(self, 0)
4651 }
4652
4653 #[doc = "ELC_GPTA Event Source GTCCRA Input Capture Enable"]
4654 #[inline(always)]
4655 pub fn aselca(
4656 self,
4657 ) -> crate::common::RegisterField<
4658 16,
4659 0x1,
4660 1,
4661 0,
4662 gticasr::Aselca,
4663 gticasr::Aselca,
4664 Gticasr_SPEC,
4665 crate::common::RW,
4666 > {
4667 crate::common::RegisterField::<
4668 16,
4669 0x1,
4670 1,
4671 0,
4672 gticasr::Aselca,
4673 gticasr::Aselca,
4674 Gticasr_SPEC,
4675 crate::common::RW,
4676 >::from_register(self, 0)
4677 }
4678
4679 #[doc = "ELC_GPTB Event Source GTCCRA Input Capture Enable"]
4680 #[inline(always)]
4681 pub fn aselcb(
4682 self,
4683 ) -> crate::common::RegisterField<
4684 17,
4685 0x1,
4686 1,
4687 0,
4688 gticasr::Aselcb,
4689 gticasr::Aselcb,
4690 Gticasr_SPEC,
4691 crate::common::RW,
4692 > {
4693 crate::common::RegisterField::<
4694 17,
4695 0x1,
4696 1,
4697 0,
4698 gticasr::Aselcb,
4699 gticasr::Aselcb,
4700 Gticasr_SPEC,
4701 crate::common::RW,
4702 >::from_register(self, 0)
4703 }
4704
4705 #[doc = "ELC_GPTC Event Source GTCCRA Input Capture Enable"]
4706 #[inline(always)]
4707 pub fn aselcc(
4708 self,
4709 ) -> crate::common::RegisterField<
4710 18,
4711 0x1,
4712 1,
4713 0,
4714 gticasr::Aselcc,
4715 gticasr::Aselcc,
4716 Gticasr_SPEC,
4717 crate::common::RW,
4718 > {
4719 crate::common::RegisterField::<
4720 18,
4721 0x1,
4722 1,
4723 0,
4724 gticasr::Aselcc,
4725 gticasr::Aselcc,
4726 Gticasr_SPEC,
4727 crate::common::RW,
4728 >::from_register(self, 0)
4729 }
4730
4731 #[doc = "ELC_GPTD Event Source GTCCRA Input Capture Enable"]
4732 #[inline(always)]
4733 pub fn aselcd(
4734 self,
4735 ) -> crate::common::RegisterField<
4736 19,
4737 0x1,
4738 1,
4739 0,
4740 gticasr::Aselcd,
4741 gticasr::Aselcd,
4742 Gticasr_SPEC,
4743 crate::common::RW,
4744 > {
4745 crate::common::RegisterField::<
4746 19,
4747 0x1,
4748 1,
4749 0,
4750 gticasr::Aselcd,
4751 gticasr::Aselcd,
4752 Gticasr_SPEC,
4753 crate::common::RW,
4754 >::from_register(self, 0)
4755 }
4756}
4757impl ::core::default::Default for Gticasr {
4758 #[inline(always)]
4759 fn default() -> Gticasr {
4760 <crate::RegValueT<Gticasr_SPEC> as RegisterValue<_>>::new(0)
4761 }
4762}
4763pub mod gticasr {
4764
4765 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4766 pub struct Asgtrgar_SPEC;
4767 pub type Asgtrgar = crate::EnumBitfieldStruct<u8, Asgtrgar_SPEC>;
4768 impl Asgtrgar {
4769 #[doc = "GTCCRA input capture disabled on the rising edge of GTETRGA input"]
4770 pub const _0: Self = Self::new(0);
4771
4772 #[doc = "GTCCRA input capture enabled on the rising edge of GTETRGA input"]
4773 pub const _1: Self = Self::new(1);
4774 }
4775 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4776 pub struct Asgtrgaf_SPEC;
4777 pub type Asgtrgaf = crate::EnumBitfieldStruct<u8, Asgtrgaf_SPEC>;
4778 impl Asgtrgaf {
4779 #[doc = "GTCCRA input capture disabled on the falling edge of GTETRGA input"]
4780 pub const _0: Self = Self::new(0);
4781
4782 #[doc = "GTCCRA input capture enabled on the falling edge of GTETRGA input"]
4783 pub const _1: Self = Self::new(1);
4784 }
4785 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4786 pub struct Asgtrgbr_SPEC;
4787 pub type Asgtrgbr = crate::EnumBitfieldStruct<u8, Asgtrgbr_SPEC>;
4788 impl Asgtrgbr {
4789 #[doc = "GTCCRA input capture disabled on the rising edge of GTETRGB input"]
4790 pub const _0: Self = Self::new(0);
4791
4792 #[doc = "GTCCRA input capture enabled on the rising edge of GTETRGB input"]
4793 pub const _1: Self = Self::new(1);
4794 }
4795 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4796 pub struct Asgtrgbf_SPEC;
4797 pub type Asgtrgbf = crate::EnumBitfieldStruct<u8, Asgtrgbf_SPEC>;
4798 impl Asgtrgbf {
4799 #[doc = "GTCCRA input capture disabled on the falling edge of GTETRGB input"]
4800 pub const _0: Self = Self::new(0);
4801
4802 #[doc = "GTCCRA input capture enabled on the falling edge of GTETRGB input"]
4803 pub const _1: Self = Self::new(1);
4804 }
4805 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4806 pub struct Ascarbl_SPEC;
4807 pub type Ascarbl = crate::EnumBitfieldStruct<u8, Ascarbl_SPEC>;
4808 impl Ascarbl {
4809 #[doc = "GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
4810 pub const _0: Self = Self::new(0);
4811
4812 #[doc = "GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
4813 pub const _1: Self = Self::new(1);
4814 }
4815 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4816 pub struct Ascarbh_SPEC;
4817 pub type Ascarbh = crate::EnumBitfieldStruct<u8, Ascarbh_SPEC>;
4818 impl Ascarbh {
4819 #[doc = "GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
4820 pub const _0: Self = Self::new(0);
4821
4822 #[doc = "GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
4823 pub const _1: Self = Self::new(1);
4824 }
4825 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4826 pub struct Ascafbl_SPEC;
4827 pub type Ascafbl = crate::EnumBitfieldStruct<u8, Ascafbl_SPEC>;
4828 impl Ascafbl {
4829 #[doc = "GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
4830 pub const _0: Self = Self::new(0);
4831
4832 #[doc = "GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
4833 pub const _1: Self = Self::new(1);
4834 }
4835 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4836 pub struct Ascafbh_SPEC;
4837 pub type Ascafbh = crate::EnumBitfieldStruct<u8, Ascafbh_SPEC>;
4838 impl Ascafbh {
4839 #[doc = "GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
4840 pub const _0: Self = Self::new(0);
4841
4842 #[doc = "GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
4843 pub const _1: Self = Self::new(1);
4844 }
4845 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4846 pub struct Ascbral_SPEC;
4847 pub type Ascbral = crate::EnumBitfieldStruct<u8, Ascbral_SPEC>;
4848 impl Ascbral {
4849 #[doc = "GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
4850 pub const _0: Self = Self::new(0);
4851
4852 #[doc = "GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
4853 pub const _1: Self = Self::new(1);
4854 }
4855 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4856 pub struct Ascbrah_SPEC;
4857 pub type Ascbrah = crate::EnumBitfieldStruct<u8, Ascbrah_SPEC>;
4858 impl Ascbrah {
4859 #[doc = "GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
4860 pub const _0: Self = Self::new(0);
4861
4862 #[doc = "GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
4863 pub const _1: Self = Self::new(1);
4864 }
4865 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4866 pub struct Ascbfal_SPEC;
4867 pub type Ascbfal = crate::EnumBitfieldStruct<u8, Ascbfal_SPEC>;
4868 impl Ascbfal {
4869 #[doc = "GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
4870 pub const _0: Self = Self::new(0);
4871
4872 #[doc = "GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
4873 pub const _1: Self = Self::new(1);
4874 }
4875 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4876 pub struct Ascbfah_SPEC;
4877 pub type Ascbfah = crate::EnumBitfieldStruct<u8, Ascbfah_SPEC>;
4878 impl Ascbfah {
4879 #[doc = "GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
4880 pub const _0: Self = Self::new(0);
4881
4882 #[doc = "GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
4883 pub const _1: Self = Self::new(1);
4884 }
4885 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4886 pub struct Aselca_SPEC;
4887 pub type Aselca = crate::EnumBitfieldStruct<u8, Aselca_SPEC>;
4888 impl Aselca {
4889 #[doc = "GTCCRA input capture disabled at the ELC_GPTA input"]
4890 pub const _0: Self = Self::new(0);
4891
4892 #[doc = "GTCCRA input capture enabled at the ELC_GPTA input"]
4893 pub const _1: Self = Self::new(1);
4894 }
4895 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4896 pub struct Aselcb_SPEC;
4897 pub type Aselcb = crate::EnumBitfieldStruct<u8, Aselcb_SPEC>;
4898 impl Aselcb {
4899 #[doc = "GTCCRA input capture disabled at the ELC_GPTB input"]
4900 pub const _0: Self = Self::new(0);
4901
4902 #[doc = "GTCCRA input capture enabled at the ELC_GPTB input"]
4903 pub const _1: Self = Self::new(1);
4904 }
4905 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4906 pub struct Aselcc_SPEC;
4907 pub type Aselcc = crate::EnumBitfieldStruct<u8, Aselcc_SPEC>;
4908 impl Aselcc {
4909 #[doc = "GTCCRA input capture disabled at the ELC_GPTC input"]
4910 pub const _0: Self = Self::new(0);
4911
4912 #[doc = "GTCCRA input capture enabled at the ELC_GPTC input"]
4913 pub const _1: Self = Self::new(1);
4914 }
4915 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4916 pub struct Aselcd_SPEC;
4917 pub type Aselcd = crate::EnumBitfieldStruct<u8, Aselcd_SPEC>;
4918 impl Aselcd {
4919 #[doc = "GTCCRA input capture disabled at the ELC_GPTD input"]
4920 pub const _0: Self = Self::new(0);
4921
4922 #[doc = "GTCCRA input capture enabled at the ELC_GPTD input"]
4923 pub const _1: Self = Self::new(1);
4924 }
4925}
4926#[doc(hidden)]
4927#[derive(Copy, Clone, Eq, PartialEq)]
4928pub struct Gticbsr_SPEC;
4929impl crate::sealed::RegSpec for Gticbsr_SPEC {
4930 type DataType = u32;
4931}
4932
4933#[doc = "General PWM Timer Input Capture Source Select Register B"]
4934pub type Gticbsr = crate::RegValueT<Gticbsr_SPEC>;
4935
4936impl Gticbsr {
4937 #[doc = "GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable"]
4938 #[inline(always)]
4939 pub fn bsgtrgar(
4940 self,
4941 ) -> crate::common::RegisterField<
4942 0,
4943 0x1,
4944 1,
4945 0,
4946 gticbsr::Bsgtrgar,
4947 gticbsr::Bsgtrgar,
4948 Gticbsr_SPEC,
4949 crate::common::RW,
4950 > {
4951 crate::common::RegisterField::<
4952 0,
4953 0x1,
4954 1,
4955 0,
4956 gticbsr::Bsgtrgar,
4957 gticbsr::Bsgtrgar,
4958 Gticbsr_SPEC,
4959 crate::common::RW,
4960 >::from_register(self, 0)
4961 }
4962
4963 #[doc = "GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable"]
4964 #[inline(always)]
4965 pub fn bsgtrgaf(
4966 self,
4967 ) -> crate::common::RegisterField<
4968 1,
4969 0x1,
4970 1,
4971 0,
4972 gticbsr::Bsgtrgaf,
4973 gticbsr::Bsgtrgaf,
4974 Gticbsr_SPEC,
4975 crate::common::RW,
4976 > {
4977 crate::common::RegisterField::<
4978 1,
4979 0x1,
4980 1,
4981 0,
4982 gticbsr::Bsgtrgaf,
4983 gticbsr::Bsgtrgaf,
4984 Gticbsr_SPEC,
4985 crate::common::RW,
4986 >::from_register(self, 0)
4987 }
4988
4989 #[doc = "GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable"]
4990 #[inline(always)]
4991 pub fn bsgtrgbr(
4992 self,
4993 ) -> crate::common::RegisterField<
4994 2,
4995 0x1,
4996 1,
4997 0,
4998 gticbsr::Bsgtrgbr,
4999 gticbsr::Bsgtrgbr,
5000 Gticbsr_SPEC,
5001 crate::common::RW,
5002 > {
5003 crate::common::RegisterField::<
5004 2,
5005 0x1,
5006 1,
5007 0,
5008 gticbsr::Bsgtrgbr,
5009 gticbsr::Bsgtrgbr,
5010 Gticbsr_SPEC,
5011 crate::common::RW,
5012 >::from_register(self, 0)
5013 }
5014
5015 #[doc = "GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable"]
5016 #[inline(always)]
5017 pub fn bsgtrgbf(
5018 self,
5019 ) -> crate::common::RegisterField<
5020 3,
5021 0x1,
5022 1,
5023 0,
5024 gticbsr::Bsgtrgbf,
5025 gticbsr::Bsgtrgbf,
5026 Gticbsr_SPEC,
5027 crate::common::RW,
5028 > {
5029 crate::common::RegisterField::<
5030 3,
5031 0x1,
5032 1,
5033 0,
5034 gticbsr::Bsgtrgbf,
5035 gticbsr::Bsgtrgbf,
5036 Gticbsr_SPEC,
5037 crate::common::RW,
5038 >::from_register(self, 0)
5039 }
5040
5041 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable"]
5042 #[inline(always)]
5043 pub fn bscarbl(
5044 self,
5045 ) -> crate::common::RegisterField<
5046 8,
5047 0x1,
5048 1,
5049 0,
5050 gticbsr::Bscarbl,
5051 gticbsr::Bscarbl,
5052 Gticbsr_SPEC,
5053 crate::common::RW,
5054 > {
5055 crate::common::RegisterField::<
5056 8,
5057 0x1,
5058 1,
5059 0,
5060 gticbsr::Bscarbl,
5061 gticbsr::Bscarbl,
5062 Gticbsr_SPEC,
5063 crate::common::RW,
5064 >::from_register(self, 0)
5065 }
5066
5067 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable"]
5068 #[inline(always)]
5069 pub fn bscarbh(
5070 self,
5071 ) -> crate::common::RegisterField<
5072 9,
5073 0x1,
5074 1,
5075 0,
5076 gticbsr::Bscarbh,
5077 gticbsr::Bscarbh,
5078 Gticbsr_SPEC,
5079 crate::common::RW,
5080 > {
5081 crate::common::RegisterField::<
5082 9,
5083 0x1,
5084 1,
5085 0,
5086 gticbsr::Bscarbh,
5087 gticbsr::Bscarbh,
5088 Gticbsr_SPEC,
5089 crate::common::RW,
5090 >::from_register(self, 0)
5091 }
5092
5093 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable"]
5094 #[inline(always)]
5095 pub fn bscafbl(
5096 self,
5097 ) -> crate::common::RegisterField<
5098 10,
5099 0x1,
5100 1,
5101 0,
5102 gticbsr::Bscafbl,
5103 gticbsr::Bscafbl,
5104 Gticbsr_SPEC,
5105 crate::common::RW,
5106 > {
5107 crate::common::RegisterField::<
5108 10,
5109 0x1,
5110 1,
5111 0,
5112 gticbsr::Bscafbl,
5113 gticbsr::Bscafbl,
5114 Gticbsr_SPEC,
5115 crate::common::RW,
5116 >::from_register(self, 0)
5117 }
5118
5119 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable"]
5120 #[inline(always)]
5121 pub fn bscafbh(
5122 self,
5123 ) -> crate::common::RegisterField<
5124 11,
5125 0x1,
5126 1,
5127 0,
5128 gticbsr::Bscafbh,
5129 gticbsr::Bscafbh,
5130 Gticbsr_SPEC,
5131 crate::common::RW,
5132 > {
5133 crate::common::RegisterField::<
5134 11,
5135 0x1,
5136 1,
5137 0,
5138 gticbsr::Bscafbh,
5139 gticbsr::Bscafbh,
5140 Gticbsr_SPEC,
5141 crate::common::RW,
5142 >::from_register(self, 0)
5143 }
5144
5145 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable"]
5146 #[inline(always)]
5147 pub fn bscbral(
5148 self,
5149 ) -> crate::common::RegisterField<
5150 12,
5151 0x1,
5152 1,
5153 0,
5154 gticbsr::Bscbral,
5155 gticbsr::Bscbral,
5156 Gticbsr_SPEC,
5157 crate::common::RW,
5158 > {
5159 crate::common::RegisterField::<
5160 12,
5161 0x1,
5162 1,
5163 0,
5164 gticbsr::Bscbral,
5165 gticbsr::Bscbral,
5166 Gticbsr_SPEC,
5167 crate::common::RW,
5168 >::from_register(self, 0)
5169 }
5170
5171 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable"]
5172 #[inline(always)]
5173 pub fn bscbrah(
5174 self,
5175 ) -> crate::common::RegisterField<
5176 13,
5177 0x1,
5178 1,
5179 0,
5180 gticbsr::Bscbrah,
5181 gticbsr::Bscbrah,
5182 Gticbsr_SPEC,
5183 crate::common::RW,
5184 > {
5185 crate::common::RegisterField::<
5186 13,
5187 0x1,
5188 1,
5189 0,
5190 gticbsr::Bscbrah,
5191 gticbsr::Bscbrah,
5192 Gticbsr_SPEC,
5193 crate::common::RW,
5194 >::from_register(self, 0)
5195 }
5196
5197 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable"]
5198 #[inline(always)]
5199 pub fn bscbfal(
5200 self,
5201 ) -> crate::common::RegisterField<
5202 14,
5203 0x1,
5204 1,
5205 0,
5206 gticbsr::Bscbfal,
5207 gticbsr::Bscbfal,
5208 Gticbsr_SPEC,
5209 crate::common::RW,
5210 > {
5211 crate::common::RegisterField::<
5212 14,
5213 0x1,
5214 1,
5215 0,
5216 gticbsr::Bscbfal,
5217 gticbsr::Bscbfal,
5218 Gticbsr_SPEC,
5219 crate::common::RW,
5220 >::from_register(self, 0)
5221 }
5222
5223 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable"]
5224 #[inline(always)]
5225 pub fn bscbfah(
5226 self,
5227 ) -> crate::common::RegisterField<
5228 15,
5229 0x1,
5230 1,
5231 0,
5232 gticbsr::Bscbfah,
5233 gticbsr::Bscbfah,
5234 Gticbsr_SPEC,
5235 crate::common::RW,
5236 > {
5237 crate::common::RegisterField::<
5238 15,
5239 0x1,
5240 1,
5241 0,
5242 gticbsr::Bscbfah,
5243 gticbsr::Bscbfah,
5244 Gticbsr_SPEC,
5245 crate::common::RW,
5246 >::from_register(self, 0)
5247 }
5248
5249 #[doc = "ELC_GPTA Event Source GTCCRB Input Capture Enable"]
5250 #[inline(always)]
5251 pub fn bselca(
5252 self,
5253 ) -> crate::common::RegisterField<
5254 16,
5255 0x1,
5256 1,
5257 0,
5258 gticbsr::Bselca,
5259 gticbsr::Bselca,
5260 Gticbsr_SPEC,
5261 crate::common::RW,
5262 > {
5263 crate::common::RegisterField::<
5264 16,
5265 0x1,
5266 1,
5267 0,
5268 gticbsr::Bselca,
5269 gticbsr::Bselca,
5270 Gticbsr_SPEC,
5271 crate::common::RW,
5272 >::from_register(self, 0)
5273 }
5274
5275 #[doc = "ELC_GPTB Event Source GTCCRB Input Capture Enable"]
5276 #[inline(always)]
5277 pub fn bselcb(
5278 self,
5279 ) -> crate::common::RegisterField<
5280 17,
5281 0x1,
5282 1,
5283 0,
5284 gticbsr::Bselcb,
5285 gticbsr::Bselcb,
5286 Gticbsr_SPEC,
5287 crate::common::RW,
5288 > {
5289 crate::common::RegisterField::<
5290 17,
5291 0x1,
5292 1,
5293 0,
5294 gticbsr::Bselcb,
5295 gticbsr::Bselcb,
5296 Gticbsr_SPEC,
5297 crate::common::RW,
5298 >::from_register(self, 0)
5299 }
5300
5301 #[doc = "ELC_GPTC Event Source GTCCRB Input Capture Enable"]
5302 #[inline(always)]
5303 pub fn bselcc(
5304 self,
5305 ) -> crate::common::RegisterField<
5306 18,
5307 0x1,
5308 1,
5309 0,
5310 gticbsr::Bselcc,
5311 gticbsr::Bselcc,
5312 Gticbsr_SPEC,
5313 crate::common::RW,
5314 > {
5315 crate::common::RegisterField::<
5316 18,
5317 0x1,
5318 1,
5319 0,
5320 gticbsr::Bselcc,
5321 gticbsr::Bselcc,
5322 Gticbsr_SPEC,
5323 crate::common::RW,
5324 >::from_register(self, 0)
5325 }
5326
5327 #[doc = "ELC_GPTD Event Source GTCCRB Input Capture Enable"]
5328 #[inline(always)]
5329 pub fn bselcd(
5330 self,
5331 ) -> crate::common::RegisterField<
5332 19,
5333 0x1,
5334 1,
5335 0,
5336 gticbsr::Bselcd,
5337 gticbsr::Bselcd,
5338 Gticbsr_SPEC,
5339 crate::common::RW,
5340 > {
5341 crate::common::RegisterField::<
5342 19,
5343 0x1,
5344 1,
5345 0,
5346 gticbsr::Bselcd,
5347 gticbsr::Bselcd,
5348 Gticbsr_SPEC,
5349 crate::common::RW,
5350 >::from_register(self, 0)
5351 }
5352}
5353impl ::core::default::Default for Gticbsr {
5354 #[inline(always)]
5355 fn default() -> Gticbsr {
5356 <crate::RegValueT<Gticbsr_SPEC> as RegisterValue<_>>::new(0)
5357 }
5358}
5359pub mod gticbsr {
5360
5361 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5362 pub struct Bsgtrgar_SPEC;
5363 pub type Bsgtrgar = crate::EnumBitfieldStruct<u8, Bsgtrgar_SPEC>;
5364 impl Bsgtrgar {
5365 #[doc = "GTCCRB input capture disabled on the rising edge of GTETRGA input"]
5366 pub const _0: Self = Self::new(0);
5367
5368 #[doc = "GTCCRB input capture enabled on the rising edge of GTETRGA input"]
5369 pub const _1: Self = Self::new(1);
5370 }
5371 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5372 pub struct Bsgtrgaf_SPEC;
5373 pub type Bsgtrgaf = crate::EnumBitfieldStruct<u8, Bsgtrgaf_SPEC>;
5374 impl Bsgtrgaf {
5375 #[doc = "GTCCRB input capture disabled on the falling edge of GTETRGA input"]
5376 pub const _0: Self = Self::new(0);
5377
5378 #[doc = "GTCCRB input capture enabled on the falling edge of GTETRGA input"]
5379 pub const _1: Self = Self::new(1);
5380 }
5381 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5382 pub struct Bsgtrgbr_SPEC;
5383 pub type Bsgtrgbr = crate::EnumBitfieldStruct<u8, Bsgtrgbr_SPEC>;
5384 impl Bsgtrgbr {
5385 #[doc = "GTCCRB input capture disabled on the rising edge of GTETRGB input"]
5386 pub const _0: Self = Self::new(0);
5387
5388 #[doc = "GTCCRB input capture enabled on the rising edge of GTETRGB input"]
5389 pub const _1: Self = Self::new(1);
5390 }
5391 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5392 pub struct Bsgtrgbf_SPEC;
5393 pub type Bsgtrgbf = crate::EnumBitfieldStruct<u8, Bsgtrgbf_SPEC>;
5394 impl Bsgtrgbf {
5395 #[doc = "GTCCRB input capture disabled on the falling edge of GTETRGB input"]
5396 pub const _0: Self = Self::new(0);
5397
5398 #[doc = "GTCCRB input capture enabled on the falling edge of GTETRGB input"]
5399 pub const _1: Self = Self::new(1);
5400 }
5401 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5402 pub struct Bscarbl_SPEC;
5403 pub type Bscarbl = crate::EnumBitfieldStruct<u8, Bscarbl_SPEC>;
5404 impl Bscarbl {
5405 #[doc = "GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
5406 pub const _0: Self = Self::new(0);
5407
5408 #[doc = "GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
5409 pub const _1: Self = Self::new(1);
5410 }
5411 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5412 pub struct Bscarbh_SPEC;
5413 pub type Bscarbh = crate::EnumBitfieldStruct<u8, Bscarbh_SPEC>;
5414 impl Bscarbh {
5415 #[doc = "GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
5416 pub const _0: Self = Self::new(0);
5417
5418 #[doc = "GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
5419 pub const _1: Self = Self::new(1);
5420 }
5421 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5422 pub struct Bscafbl_SPEC;
5423 pub type Bscafbl = crate::EnumBitfieldStruct<u8, Bscafbl_SPEC>;
5424 impl Bscafbl {
5425 #[doc = "GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
5426 pub const _0: Self = Self::new(0);
5427
5428 #[doc = "GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
5429 pub const _1: Self = Self::new(1);
5430 }
5431 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5432 pub struct Bscafbh_SPEC;
5433 pub type Bscafbh = crate::EnumBitfieldStruct<u8, Bscafbh_SPEC>;
5434 impl Bscafbh {
5435 #[doc = "GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
5436 pub const _0: Self = Self::new(0);
5437
5438 #[doc = "GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
5439 pub const _1: Self = Self::new(1);
5440 }
5441 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5442 pub struct Bscbral_SPEC;
5443 pub type Bscbral = crate::EnumBitfieldStruct<u8, Bscbral_SPEC>;
5444 impl Bscbral {
5445 #[doc = "GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
5446 pub const _0: Self = Self::new(0);
5447
5448 #[doc = "GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
5449 pub const _1: Self = Self::new(1);
5450 }
5451 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5452 pub struct Bscbrah_SPEC;
5453 pub type Bscbrah = crate::EnumBitfieldStruct<u8, Bscbrah_SPEC>;
5454 impl Bscbrah {
5455 #[doc = "GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
5456 pub const _0: Self = Self::new(0);
5457
5458 #[doc = "GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
5459 pub const _1: Self = Self::new(1);
5460 }
5461 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5462 pub struct Bscbfal_SPEC;
5463 pub type Bscbfal = crate::EnumBitfieldStruct<u8, Bscbfal_SPEC>;
5464 impl Bscbfal {
5465 #[doc = "GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
5466 pub const _0: Self = Self::new(0);
5467
5468 #[doc = "GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
5469 pub const _1: Self = Self::new(1);
5470 }
5471 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5472 pub struct Bscbfah_SPEC;
5473 pub type Bscbfah = crate::EnumBitfieldStruct<u8, Bscbfah_SPEC>;
5474 impl Bscbfah {
5475 #[doc = "GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
5476 pub const _0: Self = Self::new(0);
5477
5478 #[doc = "GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
5479 pub const _1: Self = Self::new(1);
5480 }
5481 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5482 pub struct Bselca_SPEC;
5483 pub type Bselca = crate::EnumBitfieldStruct<u8, Bselca_SPEC>;
5484 impl Bselca {
5485 #[doc = "GTCCRB input capture disabled at the ELC_GPTA input"]
5486 pub const _0: Self = Self::new(0);
5487
5488 #[doc = "GTCCRB input capture enabled at the ELC_GPTA input"]
5489 pub const _1: Self = Self::new(1);
5490 }
5491 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5492 pub struct Bselcb_SPEC;
5493 pub type Bselcb = crate::EnumBitfieldStruct<u8, Bselcb_SPEC>;
5494 impl Bselcb {
5495 #[doc = "GTCCRB input capture disabled at the ELC_GPTB input"]
5496 pub const _0: Self = Self::new(0);
5497
5498 #[doc = "GTCCRB input capture enabled at the ELC_GPTB input"]
5499 pub const _1: Self = Self::new(1);
5500 }
5501 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5502 pub struct Bselcc_SPEC;
5503 pub type Bselcc = crate::EnumBitfieldStruct<u8, Bselcc_SPEC>;
5504 impl Bselcc {
5505 #[doc = "GTCCRB input capture disabled at the ELC_GPTC input"]
5506 pub const _0: Self = Self::new(0);
5507
5508 #[doc = "GTCCRB input capture enabled at the ELC_GPTC input"]
5509 pub const _1: Self = Self::new(1);
5510 }
5511 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5512 pub struct Bselcd_SPEC;
5513 pub type Bselcd = crate::EnumBitfieldStruct<u8, Bselcd_SPEC>;
5514 impl Bselcd {
5515 #[doc = "GTCCRB input capture disabled at the ELC_GPTD input"]
5516 pub const _0: Self = Self::new(0);
5517
5518 #[doc = "GTCCRB input capture enabled at the ELC_GPTD input"]
5519 pub const _1: Self = Self::new(1);
5520 }
5521}
5522#[doc(hidden)]
5523#[derive(Copy, Clone, Eq, PartialEq)]
5524pub struct Gtcr_SPEC;
5525impl crate::sealed::RegSpec for Gtcr_SPEC {
5526 type DataType = u32;
5527}
5528
5529#[doc = "General PWM Timer Control Register"]
5530pub type Gtcr = crate::RegValueT<Gtcr_SPEC>;
5531
5532impl Gtcr {
5533 #[doc = "Count Start"]
5534 #[inline(always)]
5535 pub fn cst(
5536 self,
5537 ) -> crate::common::RegisterField<
5538 0,
5539 0x1,
5540 1,
5541 0,
5542 gtcr::Cst,
5543 gtcr::Cst,
5544 Gtcr_SPEC,
5545 crate::common::RW,
5546 > {
5547 crate::common::RegisterField::<
5548 0,
5549 0x1,
5550 1,
5551 0,
5552 gtcr::Cst,
5553 gtcr::Cst,
5554 Gtcr_SPEC,
5555 crate::common::RW,
5556 >::from_register(self, 0)
5557 }
5558
5559 #[doc = "Mode Select"]
5560 #[inline(always)]
5561 pub fn md(
5562 self,
5563 ) -> crate::common::RegisterField<16, 0x7, 1, 0, gtcr::Md, gtcr::Md, Gtcr_SPEC, crate::common::RW>
5564 {
5565 crate::common::RegisterField::<
5566 16,
5567 0x7,
5568 1,
5569 0,
5570 gtcr::Md,
5571 gtcr::Md,
5572 Gtcr_SPEC,
5573 crate::common::RW,
5574 >::from_register(self, 0)
5575 }
5576
5577 #[doc = "Timer Prescaler Select"]
5578 #[inline(always)]
5579 pub fn tpcs(
5580 self,
5581 ) -> crate::common::RegisterField<
5582 24,
5583 0x7,
5584 1,
5585 0,
5586 gtcr::Tpcs,
5587 gtcr::Tpcs,
5588 Gtcr_SPEC,
5589 crate::common::RW,
5590 > {
5591 crate::common::RegisterField::<
5592 24,
5593 0x7,
5594 1,
5595 0,
5596 gtcr::Tpcs,
5597 gtcr::Tpcs,
5598 Gtcr_SPEC,
5599 crate::common::RW,
5600 >::from_register(self, 0)
5601 }
5602}
5603impl ::core::default::Default for Gtcr {
5604 #[inline(always)]
5605 fn default() -> Gtcr {
5606 <crate::RegValueT<Gtcr_SPEC> as RegisterValue<_>>::new(0)
5607 }
5608}
5609pub mod gtcr {
5610
5611 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5612 pub struct Cst_SPEC;
5613 pub type Cst = crate::EnumBitfieldStruct<u8, Cst_SPEC>;
5614 impl Cst {
5615 #[doc = "Count operation is stopped"]
5616 pub const _0: Self = Self::new(0);
5617
5618 #[doc = "Count operation is performed"]
5619 pub const _1: Self = Self::new(1);
5620 }
5621 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5622 pub struct Md_SPEC;
5623 pub type Md = crate::EnumBitfieldStruct<u8, Md_SPEC>;
5624 impl Md {
5625 #[doc = "Saw-wave PWM mode (single buffer or double buffer possible)"]
5626 pub const _000: Self = Self::new(0);
5627
5628 #[doc = "Saw-wave one-shot pulse mode (fixed buffer operation)"]
5629 pub const _001: Self = Self::new(1);
5630
5631 #[doc = "Setting prohibited"]
5632 pub const _010: Self = Self::new(2);
5633
5634 #[doc = "Setting prohibited"]
5635 pub const _011: Self = Self::new(3);
5636
5637 #[doc = "Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible)"]
5638 pub const _100: Self = Self::new(4);
5639
5640 #[doc = "Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible)"]
5641 pub const _101: Self = Self::new(5);
5642
5643 #[doc = "Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation)"]
5644 pub const _110: Self = Self::new(6);
5645
5646 #[doc = "Setting prohibited"]
5647 pub const _111: Self = Self::new(7);
5648 }
5649 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5650 pub struct Tpcs_SPEC;
5651 pub type Tpcs = crate::EnumBitfieldStruct<u8, Tpcs_SPEC>;
5652 impl Tpcs {
5653 #[doc = "PCLKD/1"]
5654 pub const _000: Self = Self::new(0);
5655
5656 #[doc = "PCLKD/4"]
5657 pub const _001: Self = Self::new(1);
5658
5659 #[doc = "PCLKD/16"]
5660 pub const _010: Self = Self::new(2);
5661
5662 #[doc = "PCLKD/64"]
5663 pub const _011: Self = Self::new(3);
5664
5665 #[doc = "PCLKD/256"]
5666 pub const _100: Self = Self::new(4);
5667
5668 #[doc = "PCLKD/1024"]
5669 pub const _101: Self = Self::new(5);
5670 }
5671}
5672#[doc(hidden)]
5673#[derive(Copy, Clone, Eq, PartialEq)]
5674pub struct Gtuddtyc_SPEC;
5675impl crate::sealed::RegSpec for Gtuddtyc_SPEC {
5676 type DataType = u32;
5677}
5678
5679#[doc = "General PWM Timer Count Direction and Duty Setting Register"]
5680pub type Gtuddtyc = crate::RegValueT<Gtuddtyc_SPEC>;
5681
5682impl Gtuddtyc {
5683 #[doc = "Count Direction Setting"]
5684 #[inline(always)]
5685 pub fn ud(
5686 self,
5687 ) -> crate::common::RegisterField<
5688 0,
5689 0x1,
5690 1,
5691 0,
5692 gtuddtyc::Ud,
5693 gtuddtyc::Ud,
5694 Gtuddtyc_SPEC,
5695 crate::common::RW,
5696 > {
5697 crate::common::RegisterField::<
5698 0,
5699 0x1,
5700 1,
5701 0,
5702 gtuddtyc::Ud,
5703 gtuddtyc::Ud,
5704 Gtuddtyc_SPEC,
5705 crate::common::RW,
5706 >::from_register(self, 0)
5707 }
5708
5709 #[doc = "Forcible Count Direction Setting"]
5710 #[inline(always)]
5711 pub fn udf(
5712 self,
5713 ) -> crate::common::RegisterField<
5714 1,
5715 0x1,
5716 1,
5717 0,
5718 gtuddtyc::Udf,
5719 gtuddtyc::Udf,
5720 Gtuddtyc_SPEC,
5721 crate::common::RW,
5722 > {
5723 crate::common::RegisterField::<
5724 1,
5725 0x1,
5726 1,
5727 0,
5728 gtuddtyc::Udf,
5729 gtuddtyc::Udf,
5730 Gtuddtyc_SPEC,
5731 crate::common::RW,
5732 >::from_register(self, 0)
5733 }
5734
5735 #[doc = "GTIOCnA Output Duty Setting"]
5736 #[inline(always)]
5737 pub fn oadty(
5738 self,
5739 ) -> crate::common::RegisterField<
5740 16,
5741 0x3,
5742 1,
5743 0,
5744 gtuddtyc::Oadty,
5745 gtuddtyc::Oadty,
5746 Gtuddtyc_SPEC,
5747 crate::common::RW,
5748 > {
5749 crate::common::RegisterField::<
5750 16,
5751 0x3,
5752 1,
5753 0,
5754 gtuddtyc::Oadty,
5755 gtuddtyc::Oadty,
5756 Gtuddtyc_SPEC,
5757 crate::common::RW,
5758 >::from_register(self, 0)
5759 }
5760
5761 #[doc = "Forcible GTIOCnA Output Duty Setting"]
5762 #[inline(always)]
5763 pub fn oadtyf(
5764 self,
5765 ) -> crate::common::RegisterField<
5766 18,
5767 0x1,
5768 1,
5769 0,
5770 gtuddtyc::Oadtyf,
5771 gtuddtyc::Oadtyf,
5772 Gtuddtyc_SPEC,
5773 crate::common::RW,
5774 > {
5775 crate::common::RegisterField::<
5776 18,
5777 0x1,
5778 1,
5779 0,
5780 gtuddtyc::Oadtyf,
5781 gtuddtyc::Oadtyf,
5782 Gtuddtyc_SPEC,
5783 crate::common::RW,
5784 >::from_register(self, 0)
5785 }
5786
5787 #[doc = "GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting"]
5788 #[inline(always)]
5789 pub fn oadtyr(
5790 self,
5791 ) -> crate::common::RegisterField<
5792 19,
5793 0x1,
5794 1,
5795 0,
5796 gtuddtyc::Oadtyr,
5797 gtuddtyc::Oadtyr,
5798 Gtuddtyc_SPEC,
5799 crate::common::RW,
5800 > {
5801 crate::common::RegisterField::<
5802 19,
5803 0x1,
5804 1,
5805 0,
5806 gtuddtyc::Oadtyr,
5807 gtuddtyc::Oadtyr,
5808 Gtuddtyc_SPEC,
5809 crate::common::RW,
5810 >::from_register(self, 0)
5811 }
5812
5813 #[doc = "GTIOCnB Output Duty Setting"]
5814 #[inline(always)]
5815 pub fn obdty(
5816 self,
5817 ) -> crate::common::RegisterField<
5818 24,
5819 0x3,
5820 1,
5821 0,
5822 gtuddtyc::Obdty,
5823 gtuddtyc::Obdty,
5824 Gtuddtyc_SPEC,
5825 crate::common::RW,
5826 > {
5827 crate::common::RegisterField::<
5828 24,
5829 0x3,
5830 1,
5831 0,
5832 gtuddtyc::Obdty,
5833 gtuddtyc::Obdty,
5834 Gtuddtyc_SPEC,
5835 crate::common::RW,
5836 >::from_register(self, 0)
5837 }
5838
5839 #[doc = "Forcible GTIOCnB Output Duty Setting"]
5840 #[inline(always)]
5841 pub fn obdtyf(
5842 self,
5843 ) -> crate::common::RegisterField<
5844 26,
5845 0x1,
5846 1,
5847 0,
5848 gtuddtyc::Obdtyf,
5849 gtuddtyc::Obdtyf,
5850 Gtuddtyc_SPEC,
5851 crate::common::RW,
5852 > {
5853 crate::common::RegisterField::<
5854 26,
5855 0x1,
5856 1,
5857 0,
5858 gtuddtyc::Obdtyf,
5859 gtuddtyc::Obdtyf,
5860 Gtuddtyc_SPEC,
5861 crate::common::RW,
5862 >::from_register(self, 0)
5863 }
5864
5865 #[doc = "GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting"]
5866 #[inline(always)]
5867 pub fn obdtyr(
5868 self,
5869 ) -> crate::common::RegisterField<
5870 27,
5871 0x1,
5872 1,
5873 0,
5874 gtuddtyc::Obdtyr,
5875 gtuddtyc::Obdtyr,
5876 Gtuddtyc_SPEC,
5877 crate::common::RW,
5878 > {
5879 crate::common::RegisterField::<
5880 27,
5881 0x1,
5882 1,
5883 0,
5884 gtuddtyc::Obdtyr,
5885 gtuddtyc::Obdtyr,
5886 Gtuddtyc_SPEC,
5887 crate::common::RW,
5888 >::from_register(self, 0)
5889 }
5890}
5891impl ::core::default::Default for Gtuddtyc {
5892 #[inline(always)]
5893 fn default() -> Gtuddtyc {
5894 <crate::RegValueT<Gtuddtyc_SPEC> as RegisterValue<_>>::new(1)
5895 }
5896}
5897pub mod gtuddtyc {
5898
5899 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5900 pub struct Ud_SPEC;
5901 pub type Ud = crate::EnumBitfieldStruct<u8, Ud_SPEC>;
5902 impl Ud {
5903 #[doc = "GTCNT counts down"]
5904 pub const _0: Self = Self::new(0);
5905
5906 #[doc = "GTCNT counts up"]
5907 pub const _1: Self = Self::new(1);
5908 }
5909 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5910 pub struct Udf_SPEC;
5911 pub type Udf = crate::EnumBitfieldStruct<u8, Udf_SPEC>;
5912 impl Udf {
5913 #[doc = "Not forcibly set"]
5914 pub const _0: Self = Self::new(0);
5915
5916 #[doc = "Forcibly set"]
5917 pub const _1: Self = Self::new(1);
5918 }
5919 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5920 pub struct Oadty_SPEC;
5921 pub type Oadty = crate::EnumBitfieldStruct<u8, Oadty_SPEC>;
5922 impl Oadty {
5923 #[doc = "GTIOCnA pin duty depends on the compare match"]
5924 pub const _00: Self = Self::new(0);
5925
5926 #[doc = "GTIOCnA pin duty depends on the compare match"]
5927 pub const _01: Self = Self::new(1);
5928
5929 #[doc = "GTIOCnA pin duty 0%"]
5930 pub const _10: Self = Self::new(2);
5931
5932 #[doc = "GTIOCnA pin duty 100%"]
5933 pub const _11: Self = Self::new(3);
5934 }
5935 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5936 pub struct Oadtyf_SPEC;
5937 pub type Oadtyf = crate::EnumBitfieldStruct<u8, Oadtyf_SPEC>;
5938 impl Oadtyf {
5939 #[doc = "Not forcibly set"]
5940 pub const _0: Self = Self::new(0);
5941
5942 #[doc = "Forcibly set"]
5943 pub const _1: Self = Self::new(1);
5944 }
5945 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5946 pub struct Oadtyr_SPEC;
5947 pub type Oadtyr = crate::EnumBitfieldStruct<u8, Oadtyr_SPEC>;
5948 impl Oadtyr {
5949 #[doc = "The function selected by the GTIOA\\[3:2\\] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting."]
5950 pub const _0: Self = Self::new(0);
5951
5952 #[doc = "The function selected by the GTIOA\\[3:2\\] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting."]
5953 pub const _1: Self = Self::new(1);
5954 }
5955 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5956 pub struct Obdty_SPEC;
5957 pub type Obdty = crate::EnumBitfieldStruct<u8, Obdty_SPEC>;
5958 impl Obdty {
5959 #[doc = "GTIOCnB pin duty depends on the compare match"]
5960 pub const _00: Self = Self::new(0);
5961
5962 #[doc = "GTIOCnB pin duty depends on the compare match"]
5963 pub const _01: Self = Self::new(1);
5964
5965 #[doc = "GTIOCnB pin duty 0%"]
5966 pub const _10: Self = Self::new(2);
5967
5968 #[doc = "GTIOCnB pin duty 100%"]
5969 pub const _11: Self = Self::new(3);
5970 }
5971 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5972 pub struct Obdtyf_SPEC;
5973 pub type Obdtyf = crate::EnumBitfieldStruct<u8, Obdtyf_SPEC>;
5974 impl Obdtyf {
5975 #[doc = "Not forcibly set"]
5976 pub const _0: Self = Self::new(0);
5977
5978 #[doc = "Forcibly set"]
5979 pub const _1: Self = Self::new(1);
5980 }
5981 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5982 pub struct Obdtyr_SPEC;
5983 pub type Obdtyr = crate::EnumBitfieldStruct<u8, Obdtyr_SPEC>;
5984 impl Obdtyr {
5985 #[doc = "The function selected by the GTIOB\\[3:2\\] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting."]
5986 pub const _0: Self = Self::new(0);
5987
5988 #[doc = "The function selected by the GTIOB\\[3:2\\] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting."]
5989 pub const _1: Self = Self::new(1);
5990 }
5991}
5992#[doc(hidden)]
5993#[derive(Copy, Clone, Eq, PartialEq)]
5994pub struct Gtior_SPEC;
5995impl crate::sealed::RegSpec for Gtior_SPEC {
5996 type DataType = u32;
5997}
5998
5999#[doc = "General PWM Timer I/O Control Register"]
6000pub type Gtior = crate::RegValueT<Gtior_SPEC>;
6001
6002impl Gtior {
6003 #[doc = "GTIOCnA Pin Function Select"]
6004 #[inline(always)]
6005 pub fn gtioa(
6006 self,
6007 ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Gtior_SPEC, crate::common::RW> {
6008 crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Gtior_SPEC,crate::common::RW>::from_register(self,0)
6009 }
6010
6011 #[doc = "GTIOCnA Pin Output Value Setting at the Count Stop"]
6012 #[inline(always)]
6013 pub fn oadflt(
6014 self,
6015 ) -> crate::common::RegisterField<
6016 6,
6017 0x1,
6018 1,
6019 0,
6020 gtior::Oadflt,
6021 gtior::Oadflt,
6022 Gtior_SPEC,
6023 crate::common::RW,
6024 > {
6025 crate::common::RegisterField::<
6026 6,
6027 0x1,
6028 1,
6029 0,
6030 gtior::Oadflt,
6031 gtior::Oadflt,
6032 Gtior_SPEC,
6033 crate::common::RW,
6034 >::from_register(self, 0)
6035 }
6036
6037 #[doc = "GTIOCnA Pin Output Setting at the Start/Stop Count"]
6038 #[inline(always)]
6039 pub fn oahld(
6040 self,
6041 ) -> crate::common::RegisterField<
6042 7,
6043 0x1,
6044 1,
6045 0,
6046 gtior::Oahld,
6047 gtior::Oahld,
6048 Gtior_SPEC,
6049 crate::common::RW,
6050 > {
6051 crate::common::RegisterField::<
6052 7,
6053 0x1,
6054 1,
6055 0,
6056 gtior::Oahld,
6057 gtior::Oahld,
6058 Gtior_SPEC,
6059 crate::common::RW,
6060 >::from_register(self, 0)
6061 }
6062
6063 #[doc = "GTIOCnA Pin Output Enable"]
6064 #[inline(always)]
6065 pub fn oae(
6066 self,
6067 ) -> crate::common::RegisterField<
6068 8,
6069 0x1,
6070 1,
6071 0,
6072 gtior::Oae,
6073 gtior::Oae,
6074 Gtior_SPEC,
6075 crate::common::RW,
6076 > {
6077 crate::common::RegisterField::<
6078 8,
6079 0x1,
6080 1,
6081 0,
6082 gtior::Oae,
6083 gtior::Oae,
6084 Gtior_SPEC,
6085 crate::common::RW,
6086 >::from_register(self, 0)
6087 }
6088
6089 #[doc = "GTIOCnA Pin Disable Value Setting"]
6090 #[inline(always)]
6091 pub fn oadf(
6092 self,
6093 ) -> crate::common::RegisterField<
6094 9,
6095 0x3,
6096 1,
6097 0,
6098 gtior::Oadf,
6099 gtior::Oadf,
6100 Gtior_SPEC,
6101 crate::common::RW,
6102 > {
6103 crate::common::RegisterField::<
6104 9,
6105 0x3,
6106 1,
6107 0,
6108 gtior::Oadf,
6109 gtior::Oadf,
6110 Gtior_SPEC,
6111 crate::common::RW,
6112 >::from_register(self, 0)
6113 }
6114
6115 #[doc = "Noise Filter A Enable"]
6116 #[inline(always)]
6117 pub fn nfaen(
6118 self,
6119 ) -> crate::common::RegisterField<
6120 13,
6121 0x1,
6122 1,
6123 0,
6124 gtior::Nfaen,
6125 gtior::Nfaen,
6126 Gtior_SPEC,
6127 crate::common::RW,
6128 > {
6129 crate::common::RegisterField::<
6130 13,
6131 0x1,
6132 1,
6133 0,
6134 gtior::Nfaen,
6135 gtior::Nfaen,
6136 Gtior_SPEC,
6137 crate::common::RW,
6138 >::from_register(self, 0)
6139 }
6140
6141 #[doc = "Noise Filter A Sampling Clock Select"]
6142 #[inline(always)]
6143 pub fn nfcsa(
6144 self,
6145 ) -> crate::common::RegisterField<
6146 14,
6147 0x3,
6148 1,
6149 0,
6150 gtior::Nfcsa,
6151 gtior::Nfcsa,
6152 Gtior_SPEC,
6153 crate::common::RW,
6154 > {
6155 crate::common::RegisterField::<
6156 14,
6157 0x3,
6158 1,
6159 0,
6160 gtior::Nfcsa,
6161 gtior::Nfcsa,
6162 Gtior_SPEC,
6163 crate::common::RW,
6164 >::from_register(self, 0)
6165 }
6166
6167 #[doc = "GTIOCnB Pin Function Select"]
6168 #[inline(always)]
6169 pub fn gtiob(
6170 self,
6171 ) -> crate::common::RegisterField<16, 0x1f, 1, 0, u8, u8, Gtior_SPEC, crate::common::RW> {
6172 crate::common::RegisterField::<16,0x1f,1,0,u8,u8,Gtior_SPEC,crate::common::RW>::from_register(self,0)
6173 }
6174
6175 #[doc = "GTIOCnB Pin Output Value Setting at the Count Stop"]
6176 #[inline(always)]
6177 pub fn obdflt(
6178 self,
6179 ) -> crate::common::RegisterField<
6180 22,
6181 0x1,
6182 1,
6183 0,
6184 gtior::Obdflt,
6185 gtior::Obdflt,
6186 Gtior_SPEC,
6187 crate::common::RW,
6188 > {
6189 crate::common::RegisterField::<
6190 22,
6191 0x1,
6192 1,
6193 0,
6194 gtior::Obdflt,
6195 gtior::Obdflt,
6196 Gtior_SPEC,
6197 crate::common::RW,
6198 >::from_register(self, 0)
6199 }
6200
6201 #[doc = "GTIOCnB Pin Output Setting at the Start/Stop Count"]
6202 #[inline(always)]
6203 pub fn obhld(
6204 self,
6205 ) -> crate::common::RegisterField<
6206 23,
6207 0x1,
6208 1,
6209 0,
6210 gtior::Obhld,
6211 gtior::Obhld,
6212 Gtior_SPEC,
6213 crate::common::RW,
6214 > {
6215 crate::common::RegisterField::<
6216 23,
6217 0x1,
6218 1,
6219 0,
6220 gtior::Obhld,
6221 gtior::Obhld,
6222 Gtior_SPEC,
6223 crate::common::RW,
6224 >::from_register(self, 0)
6225 }
6226
6227 #[doc = "GTIOCnB Pin Output Enable"]
6228 #[inline(always)]
6229 pub fn obe(
6230 self,
6231 ) -> crate::common::RegisterField<
6232 24,
6233 0x1,
6234 1,
6235 0,
6236 gtior::Obe,
6237 gtior::Obe,
6238 Gtior_SPEC,
6239 crate::common::RW,
6240 > {
6241 crate::common::RegisterField::<
6242 24,
6243 0x1,
6244 1,
6245 0,
6246 gtior::Obe,
6247 gtior::Obe,
6248 Gtior_SPEC,
6249 crate::common::RW,
6250 >::from_register(self, 0)
6251 }
6252
6253 #[doc = "GTIOCnB Pin Disable Value Setting"]
6254 #[inline(always)]
6255 pub fn obdf(
6256 self,
6257 ) -> crate::common::RegisterField<
6258 25,
6259 0x3,
6260 1,
6261 0,
6262 gtior::Obdf,
6263 gtior::Obdf,
6264 Gtior_SPEC,
6265 crate::common::RW,
6266 > {
6267 crate::common::RegisterField::<
6268 25,
6269 0x3,
6270 1,
6271 0,
6272 gtior::Obdf,
6273 gtior::Obdf,
6274 Gtior_SPEC,
6275 crate::common::RW,
6276 >::from_register(self, 0)
6277 }
6278
6279 #[doc = "Noise Filter B Enable"]
6280 #[inline(always)]
6281 pub fn nfben(
6282 self,
6283 ) -> crate::common::RegisterField<
6284 29,
6285 0x1,
6286 1,
6287 0,
6288 gtior::Nfben,
6289 gtior::Nfben,
6290 Gtior_SPEC,
6291 crate::common::RW,
6292 > {
6293 crate::common::RegisterField::<
6294 29,
6295 0x1,
6296 1,
6297 0,
6298 gtior::Nfben,
6299 gtior::Nfben,
6300 Gtior_SPEC,
6301 crate::common::RW,
6302 >::from_register(self, 0)
6303 }
6304
6305 #[doc = "Noise Filter B Sampling Clock Select"]
6306 #[inline(always)]
6307 pub fn nfcsb(
6308 self,
6309 ) -> crate::common::RegisterField<
6310 30,
6311 0x3,
6312 1,
6313 0,
6314 gtior::Nfcsb,
6315 gtior::Nfcsb,
6316 Gtior_SPEC,
6317 crate::common::RW,
6318 > {
6319 crate::common::RegisterField::<
6320 30,
6321 0x3,
6322 1,
6323 0,
6324 gtior::Nfcsb,
6325 gtior::Nfcsb,
6326 Gtior_SPEC,
6327 crate::common::RW,
6328 >::from_register(self, 0)
6329 }
6330}
6331impl ::core::default::Default for Gtior {
6332 #[inline(always)]
6333 fn default() -> Gtior {
6334 <crate::RegValueT<Gtior_SPEC> as RegisterValue<_>>::new(0)
6335 }
6336}
6337pub mod gtior {
6338
6339 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6340 pub struct Oadflt_SPEC;
6341 pub type Oadflt = crate::EnumBitfieldStruct<u8, Oadflt_SPEC>;
6342 impl Oadflt {
6343 #[doc = "The GTIOCnA pin outputs low when counting stops"]
6344 pub const _0: Self = Self::new(0);
6345
6346 #[doc = "The GTIOCnA pin outputs high when counting stops"]
6347 pub const _1: Self = Self::new(1);
6348 }
6349 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6350 pub struct Oahld_SPEC;
6351 pub type Oahld = crate::EnumBitfieldStruct<u8, Oahld_SPEC>;
6352 impl Oahld {
6353 #[doc = "The GTIOCnA pin output level at the start or stop of counting depends on the register setting"]
6354 pub const _0: Self = Self::new(0);
6355
6356 #[doc = "The GTIOCnA pin output level is retained at the start or stop of counting"]
6357 pub const _1: Self = Self::new(1);
6358 }
6359 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6360 pub struct Oae_SPEC;
6361 pub type Oae = crate::EnumBitfieldStruct<u8, Oae_SPEC>;
6362 impl Oae {
6363 #[doc = "Output is disabled"]
6364 pub const _0: Self = Self::new(0);
6365
6366 #[doc = "Output is enabled"]
6367 pub const _1: Self = Self::new(1);
6368 }
6369 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6370 pub struct Oadf_SPEC;
6371 pub type Oadf = crate::EnumBitfieldStruct<u8, Oadf_SPEC>;
6372 impl Oadf {
6373 #[doc = "None of the below options are specified"]
6374 pub const _00: Self = Self::new(0);
6375
6376 #[doc = "GTIOCnA pin is set to Hi-Z in response to controlling the output negation"]
6377 pub const _01: Self = Self::new(1);
6378
6379 #[doc = "GTIOCnA pin is set to 0 in response to controlling the output negation"]
6380 pub const _10: Self = Self::new(2);
6381
6382 #[doc = "GTIOCnA pin is set to 1 in response to controlling the output negation"]
6383 pub const _11: Self = Self::new(3);
6384 }
6385 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6386 pub struct Nfaen_SPEC;
6387 pub type Nfaen = crate::EnumBitfieldStruct<u8, Nfaen_SPEC>;
6388 impl Nfaen {
6389 #[doc = "The noise filter for the GTIOCnA pin is disabled"]
6390 pub const _0: Self = Self::new(0);
6391
6392 #[doc = "The noise filter for the GTIOCnA pin is enabled"]
6393 pub const _1: Self = Self::new(1);
6394 }
6395 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6396 pub struct Nfcsa_SPEC;
6397 pub type Nfcsa = crate::EnumBitfieldStruct<u8, Nfcsa_SPEC>;
6398 impl Nfcsa {
6399 #[doc = "PCLKD/1"]
6400 pub const _00: Self = Self::new(0);
6401
6402 #[doc = "PCLKD/4"]
6403 pub const _01: Self = Self::new(1);
6404
6405 #[doc = "PCLKD/16"]
6406 pub const _10: Self = Self::new(2);
6407
6408 #[doc = "PCLKD/64"]
6409 pub const _11: Self = Self::new(3);
6410 }
6411 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6412 pub struct Obdflt_SPEC;
6413 pub type Obdflt = crate::EnumBitfieldStruct<u8, Obdflt_SPEC>;
6414 impl Obdflt {
6415 #[doc = "The GTIOCnB pin outputs low when counting stops"]
6416 pub const _0: Self = Self::new(0);
6417
6418 #[doc = "The GTIOCnB pin outputs high when counting stops"]
6419 pub const _1: Self = Self::new(1);
6420 }
6421 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6422 pub struct Obhld_SPEC;
6423 pub type Obhld = crate::EnumBitfieldStruct<u8, Obhld_SPEC>;
6424 impl Obhld {
6425 #[doc = "The GTIOCnB pin output level at the start/stop of counting depends on the register setting"]
6426 pub const _0: Self = Self::new(0);
6427
6428 #[doc = "The GTIOCnB pin output level is retained at the start/stop of counting"]
6429 pub const _1: Self = Self::new(1);
6430 }
6431 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6432 pub struct Obe_SPEC;
6433 pub type Obe = crate::EnumBitfieldStruct<u8, Obe_SPEC>;
6434 impl Obe {
6435 #[doc = "Output is disabled"]
6436 pub const _0: Self = Self::new(0);
6437
6438 #[doc = "Output is enabled"]
6439 pub const _1: Self = Self::new(1);
6440 }
6441 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6442 pub struct Obdf_SPEC;
6443 pub type Obdf = crate::EnumBitfieldStruct<u8, Obdf_SPEC>;
6444 impl Obdf {
6445 #[doc = "None of the below options are specified"]
6446 pub const _00: Self = Self::new(0);
6447
6448 #[doc = "GTIOCnB pin is set to Hi-Z in response to controlling the output negation"]
6449 pub const _01: Self = Self::new(1);
6450
6451 #[doc = "GTIOCnB pin is set to 0 in response to controlling the output negation"]
6452 pub const _10: Self = Self::new(2);
6453
6454 #[doc = "GTIOCnB pin is set to 1 in response to controlling the output negation"]
6455 pub const _11: Self = Self::new(3);
6456 }
6457 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6458 pub struct Nfben_SPEC;
6459 pub type Nfben = crate::EnumBitfieldStruct<u8, Nfben_SPEC>;
6460 impl Nfben {
6461 #[doc = "The noise filter for the GTIOCnB pin is disabled"]
6462 pub const _0: Self = Self::new(0);
6463
6464 #[doc = "The noise filter for the GTIOCnB pin is enabled"]
6465 pub const _1: Self = Self::new(1);
6466 }
6467 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6468 pub struct Nfcsb_SPEC;
6469 pub type Nfcsb = crate::EnumBitfieldStruct<u8, Nfcsb_SPEC>;
6470 impl Nfcsb {
6471 #[doc = "PCLKD/1"]
6472 pub const _00: Self = Self::new(0);
6473
6474 #[doc = "PCLKD/4"]
6475 pub const _01: Self = Self::new(1);
6476
6477 #[doc = "PCLKD/16"]
6478 pub const _10: Self = Self::new(2);
6479
6480 #[doc = "PCLKD/64"]
6481 pub const _11: Self = Self::new(3);
6482 }
6483}
6484#[doc(hidden)]
6485#[derive(Copy, Clone, Eq, PartialEq)]
6486pub struct Gtintad_SPEC;
6487impl crate::sealed::RegSpec for Gtintad_SPEC {
6488 type DataType = u32;
6489}
6490
6491#[doc = "General PWM Timer Interrupt Output Setting Register"]
6492pub type Gtintad = crate::RegValueT<Gtintad_SPEC>;
6493
6494impl Gtintad {
6495 #[doc = "Output Disable Source Select"]
6496 #[inline(always)]
6497 pub fn grp(
6498 self,
6499 ) -> crate::common::RegisterField<
6500 24,
6501 0x3,
6502 1,
6503 0,
6504 gtintad::Grp,
6505 gtintad::Grp,
6506 Gtintad_SPEC,
6507 crate::common::RW,
6508 > {
6509 crate::common::RegisterField::<
6510 24,
6511 0x3,
6512 1,
6513 0,
6514 gtintad::Grp,
6515 gtintad::Grp,
6516 Gtintad_SPEC,
6517 crate::common::RW,
6518 >::from_register(self, 0)
6519 }
6520
6521 #[doc = "Same Time Output Level High Disable Request Enable"]
6522 #[inline(always)]
6523 pub fn grpabh(
6524 self,
6525 ) -> crate::common::RegisterField<
6526 29,
6527 0x1,
6528 1,
6529 0,
6530 gtintad::Grpabh,
6531 gtintad::Grpabh,
6532 Gtintad_SPEC,
6533 crate::common::RW,
6534 > {
6535 crate::common::RegisterField::<
6536 29,
6537 0x1,
6538 1,
6539 0,
6540 gtintad::Grpabh,
6541 gtintad::Grpabh,
6542 Gtintad_SPEC,
6543 crate::common::RW,
6544 >::from_register(self, 0)
6545 }
6546
6547 #[doc = "Same Time Output Level Low Disable Request Enable"]
6548 #[inline(always)]
6549 pub fn grpabl(
6550 self,
6551 ) -> crate::common::RegisterField<
6552 30,
6553 0x1,
6554 1,
6555 0,
6556 gtintad::Grpabl,
6557 gtintad::Grpabl,
6558 Gtintad_SPEC,
6559 crate::common::RW,
6560 > {
6561 crate::common::RegisterField::<
6562 30,
6563 0x1,
6564 1,
6565 0,
6566 gtintad::Grpabl,
6567 gtintad::Grpabl,
6568 Gtintad_SPEC,
6569 crate::common::RW,
6570 >::from_register(self, 0)
6571 }
6572}
6573impl ::core::default::Default for Gtintad {
6574 #[inline(always)]
6575 fn default() -> Gtintad {
6576 <crate::RegValueT<Gtintad_SPEC> as RegisterValue<_>>::new(0)
6577 }
6578}
6579pub mod gtintad {
6580
6581 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6582 pub struct Grp_SPEC;
6583 pub type Grp = crate::EnumBitfieldStruct<u8, Grp_SPEC>;
6584 impl Grp {
6585 #[doc = "Group A output disable source is selected Group B output disable source is selected Setting prohibited"]
6586 pub const _00: Self = Self::new(0);
6587 }
6588 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6589 pub struct Grpabh_SPEC;
6590 pub type Grpabh = crate::EnumBitfieldStruct<u8, Grpabh_SPEC>;
6591 impl Grpabh {
6592 #[doc = "Same time output level high disable request disabled"]
6593 pub const _0: Self = Self::new(0);
6594
6595 #[doc = "Same time output level high disable request enabled"]
6596 pub const _1: Self = Self::new(1);
6597 }
6598 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6599 pub struct Grpabl_SPEC;
6600 pub type Grpabl = crate::EnumBitfieldStruct<u8, Grpabl_SPEC>;
6601 impl Grpabl {
6602 #[doc = "Same time output level low disable request disabled"]
6603 pub const _0: Self = Self::new(0);
6604
6605 #[doc = "Same time output level low disable request enabled"]
6606 pub const _1: Self = Self::new(1);
6607 }
6608}
6609#[doc(hidden)]
6610#[derive(Copy, Clone, Eq, PartialEq)]
6611pub struct Gtst_SPEC;
6612impl crate::sealed::RegSpec for Gtst_SPEC {
6613 type DataType = u32;
6614}
6615
6616#[doc = "General PWM Timer Status Register"]
6617pub type Gtst = crate::RegValueT<Gtst_SPEC>;
6618
6619impl Gtst {
6620 #[doc = "Input Capture/Compare Match Flag A"]
6621 #[inline(always)]
6622 pub fn tcfa(
6623 self,
6624 ) -> crate::common::RegisterField<
6625 0,
6626 0x1,
6627 1,
6628 0,
6629 gtst::Tcfa,
6630 gtst::Tcfa,
6631 Gtst_SPEC,
6632 crate::common::RW,
6633 > {
6634 crate::common::RegisterField::<
6635 0,
6636 0x1,
6637 1,
6638 0,
6639 gtst::Tcfa,
6640 gtst::Tcfa,
6641 Gtst_SPEC,
6642 crate::common::RW,
6643 >::from_register(self, 0)
6644 }
6645
6646 #[doc = "Input Capture/Compare Match Flag B"]
6647 #[inline(always)]
6648 pub fn tcfb(
6649 self,
6650 ) -> crate::common::RegisterField<
6651 1,
6652 0x1,
6653 1,
6654 0,
6655 gtst::Tcfb,
6656 gtst::Tcfb,
6657 Gtst_SPEC,
6658 crate::common::RW,
6659 > {
6660 crate::common::RegisterField::<
6661 1,
6662 0x1,
6663 1,
6664 0,
6665 gtst::Tcfb,
6666 gtst::Tcfb,
6667 Gtst_SPEC,
6668 crate::common::RW,
6669 >::from_register(self, 0)
6670 }
6671
6672 #[doc = "Input Compare Match Flag C"]
6673 #[inline(always)]
6674 pub fn tcfc(
6675 self,
6676 ) -> crate::common::RegisterField<
6677 2,
6678 0x1,
6679 1,
6680 0,
6681 gtst::Tcfc,
6682 gtst::Tcfc,
6683 Gtst_SPEC,
6684 crate::common::RW,
6685 > {
6686 crate::common::RegisterField::<
6687 2,
6688 0x1,
6689 1,
6690 0,
6691 gtst::Tcfc,
6692 gtst::Tcfc,
6693 Gtst_SPEC,
6694 crate::common::RW,
6695 >::from_register(self, 0)
6696 }
6697
6698 #[doc = "Input Compare Match Flag D"]
6699 #[inline(always)]
6700 pub fn tcfd(
6701 self,
6702 ) -> crate::common::RegisterField<
6703 3,
6704 0x1,
6705 1,
6706 0,
6707 gtst::Tcfd,
6708 gtst::Tcfd,
6709 Gtst_SPEC,
6710 crate::common::RW,
6711 > {
6712 crate::common::RegisterField::<
6713 3,
6714 0x1,
6715 1,
6716 0,
6717 gtst::Tcfd,
6718 gtst::Tcfd,
6719 Gtst_SPEC,
6720 crate::common::RW,
6721 >::from_register(self, 0)
6722 }
6723
6724 #[doc = "Input Compare Match Flag E"]
6725 #[inline(always)]
6726 pub fn tcfe(
6727 self,
6728 ) -> crate::common::RegisterField<
6729 4,
6730 0x1,
6731 1,
6732 0,
6733 gtst::Tcfe,
6734 gtst::Tcfe,
6735 Gtst_SPEC,
6736 crate::common::RW,
6737 > {
6738 crate::common::RegisterField::<
6739 4,
6740 0x1,
6741 1,
6742 0,
6743 gtst::Tcfe,
6744 gtst::Tcfe,
6745 Gtst_SPEC,
6746 crate::common::RW,
6747 >::from_register(self, 0)
6748 }
6749
6750 #[doc = "Input Compare Match Flag F"]
6751 #[inline(always)]
6752 pub fn tcff(
6753 self,
6754 ) -> crate::common::RegisterField<
6755 5,
6756 0x1,
6757 1,
6758 0,
6759 gtst::Tcff,
6760 gtst::Tcff,
6761 Gtst_SPEC,
6762 crate::common::RW,
6763 > {
6764 crate::common::RegisterField::<
6765 5,
6766 0x1,
6767 1,
6768 0,
6769 gtst::Tcff,
6770 gtst::Tcff,
6771 Gtst_SPEC,
6772 crate::common::RW,
6773 >::from_register(self, 0)
6774 }
6775
6776 #[doc = "Overflow Flag"]
6777 #[inline(always)]
6778 pub fn tcfpo(
6779 self,
6780 ) -> crate::common::RegisterField<
6781 6,
6782 0x1,
6783 1,
6784 0,
6785 gtst::Tcfpo,
6786 gtst::Tcfpo,
6787 Gtst_SPEC,
6788 crate::common::RW,
6789 > {
6790 crate::common::RegisterField::<
6791 6,
6792 0x1,
6793 1,
6794 0,
6795 gtst::Tcfpo,
6796 gtst::Tcfpo,
6797 Gtst_SPEC,
6798 crate::common::RW,
6799 >::from_register(self, 0)
6800 }
6801
6802 #[doc = "Underflow Flag"]
6803 #[inline(always)]
6804 pub fn tcfpu(
6805 self,
6806 ) -> crate::common::RegisterField<
6807 7,
6808 0x1,
6809 1,
6810 0,
6811 gtst::Tcfpu,
6812 gtst::Tcfpu,
6813 Gtst_SPEC,
6814 crate::common::RW,
6815 > {
6816 crate::common::RegisterField::<
6817 7,
6818 0x1,
6819 1,
6820 0,
6821 gtst::Tcfpu,
6822 gtst::Tcfpu,
6823 Gtst_SPEC,
6824 crate::common::RW,
6825 >::from_register(self, 0)
6826 }
6827
6828 #[doc = "Count Direction Flag"]
6829 #[inline(always)]
6830 pub fn tucf(
6831 self,
6832 ) -> crate::common::RegisterField<
6833 15,
6834 0x1,
6835 1,
6836 0,
6837 gtst::Tucf,
6838 gtst::Tucf,
6839 Gtst_SPEC,
6840 crate::common::R,
6841 > {
6842 crate::common::RegisterField::<
6843 15,
6844 0x1,
6845 1,
6846 0,
6847 gtst::Tucf,
6848 gtst::Tucf,
6849 Gtst_SPEC,
6850 crate::common::R,
6851 >::from_register(self, 0)
6852 }
6853
6854 #[doc = "Output Disable Flag"]
6855 #[inline(always)]
6856 pub fn odf(
6857 self,
6858 ) -> crate::common::RegisterField<
6859 24,
6860 0x1,
6861 1,
6862 0,
6863 gtst::Odf,
6864 gtst::Odf,
6865 Gtst_SPEC,
6866 crate::common::R,
6867 > {
6868 crate::common::RegisterField::<
6869 24,
6870 0x1,
6871 1,
6872 0,
6873 gtst::Odf,
6874 gtst::Odf,
6875 Gtst_SPEC,
6876 crate::common::R,
6877 >::from_register(self, 0)
6878 }
6879
6880 #[doc = "Same Time Output Level High Flag"]
6881 #[inline(always)]
6882 pub fn oabhf(
6883 self,
6884 ) -> crate::common::RegisterField<
6885 29,
6886 0x1,
6887 1,
6888 0,
6889 gtst::Oabhf,
6890 gtst::Oabhf,
6891 Gtst_SPEC,
6892 crate::common::R,
6893 > {
6894 crate::common::RegisterField::<
6895 29,
6896 0x1,
6897 1,
6898 0,
6899 gtst::Oabhf,
6900 gtst::Oabhf,
6901 Gtst_SPEC,
6902 crate::common::R,
6903 >::from_register(self, 0)
6904 }
6905
6906 #[doc = "Same Time Output Level Low Flag"]
6907 #[inline(always)]
6908 pub fn oablf(
6909 self,
6910 ) -> crate::common::RegisterField<
6911 30,
6912 0x1,
6913 1,
6914 0,
6915 gtst::Oablf,
6916 gtst::Oablf,
6917 Gtst_SPEC,
6918 crate::common::R,
6919 > {
6920 crate::common::RegisterField::<
6921 30,
6922 0x1,
6923 1,
6924 0,
6925 gtst::Oablf,
6926 gtst::Oablf,
6927 Gtst_SPEC,
6928 crate::common::R,
6929 >::from_register(self, 0)
6930 }
6931}
6932impl ::core::default::Default for Gtst {
6933 #[inline(always)]
6934 fn default() -> Gtst {
6935 <crate::RegValueT<Gtst_SPEC> as RegisterValue<_>>::new(32768)
6936 }
6937}
6938pub mod gtst {
6939
6940 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6941 pub struct Tcfa_SPEC;
6942 pub type Tcfa = crate::EnumBitfieldStruct<u8, Tcfa_SPEC>;
6943 impl Tcfa {
6944 #[doc = "No input capture/compare match of GTCCRA is generated"]
6945 pub const _0: Self = Self::new(0);
6946
6947 #[doc = "An input capture/compare match of GTCCRA is generated"]
6948 pub const _1: Self = Self::new(1);
6949 }
6950 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6951 pub struct Tcfb_SPEC;
6952 pub type Tcfb = crate::EnumBitfieldStruct<u8, Tcfb_SPEC>;
6953 impl Tcfb {
6954 #[doc = "No input capture/compare match of GTCCRB is generated"]
6955 pub const _0: Self = Self::new(0);
6956
6957 #[doc = "An input capture/compare match of GTCCRB is generated"]
6958 pub const _1: Self = Self::new(1);
6959 }
6960 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6961 pub struct Tcfc_SPEC;
6962 pub type Tcfc = crate::EnumBitfieldStruct<u8, Tcfc_SPEC>;
6963 impl Tcfc {
6964 #[doc = "No compare match of GTCCRC is generated"]
6965 pub const _0: Self = Self::new(0);
6966
6967 #[doc = "A compare match of GTCCRC is generated"]
6968 pub const _1: Self = Self::new(1);
6969 }
6970 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6971 pub struct Tcfd_SPEC;
6972 pub type Tcfd = crate::EnumBitfieldStruct<u8, Tcfd_SPEC>;
6973 impl Tcfd {
6974 #[doc = "No compare match of GTCCRD is generated"]
6975 pub const _0: Self = Self::new(0);
6976
6977 #[doc = "A compare match of GTCCRD is generated"]
6978 pub const _1: Self = Self::new(1);
6979 }
6980 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6981 pub struct Tcfe_SPEC;
6982 pub type Tcfe = crate::EnumBitfieldStruct<u8, Tcfe_SPEC>;
6983 impl Tcfe {
6984 #[doc = "No compare match of GTCCRE is generated"]
6985 pub const _0: Self = Self::new(0);
6986
6987 #[doc = "A compare match of GTCCRE is generated"]
6988 pub const _1: Self = Self::new(1);
6989 }
6990 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6991 pub struct Tcff_SPEC;
6992 pub type Tcff = crate::EnumBitfieldStruct<u8, Tcff_SPEC>;
6993 impl Tcff {
6994 #[doc = "No compare match of GTCCRF is generated"]
6995 pub const _0: Self = Self::new(0);
6996
6997 #[doc = "A compare match of GTCCRF is generated"]
6998 pub const _1: Self = Self::new(1);
6999 }
7000 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7001 pub struct Tcfpo_SPEC;
7002 pub type Tcfpo = crate::EnumBitfieldStruct<u8, Tcfpo_SPEC>;
7003 impl Tcfpo {
7004 #[doc = "No overflow (crest) occurred"]
7005 pub const _0: Self = Self::new(0);
7006
7007 #[doc = "An overflow (crest) occurred"]
7008 pub const _1: Self = Self::new(1);
7009 }
7010 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7011 pub struct Tcfpu_SPEC;
7012 pub type Tcfpu = crate::EnumBitfieldStruct<u8, Tcfpu_SPEC>;
7013 impl Tcfpu {
7014 #[doc = "No underflow (trough) occurred"]
7015 pub const _0: Self = Self::new(0);
7016
7017 #[doc = "An underflow (trough) occurred"]
7018 pub const _1: Self = Self::new(1);
7019 }
7020 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7021 pub struct Tucf_SPEC;
7022 pub type Tucf = crate::EnumBitfieldStruct<u8, Tucf_SPEC>;
7023 impl Tucf {
7024 #[doc = "GTCNT counter counts downward"]
7025 pub const _0: Self = Self::new(0);
7026
7027 #[doc = "GTCNT counter counts upward"]
7028 pub const _1: Self = Self::new(1);
7029 }
7030 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7031 pub struct Odf_SPEC;
7032 pub type Odf = crate::EnumBitfieldStruct<u8, Odf_SPEC>;
7033 impl Odf {
7034 #[doc = "No output disable request is generated"]
7035 pub const _0: Self = Self::new(0);
7036
7037 #[doc = "An output disable request is generated"]
7038 pub const _1: Self = Self::new(1);
7039 }
7040 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7041 pub struct Oabhf_SPEC;
7042 pub type Oabhf = crate::EnumBitfieldStruct<u8, Oabhf_SPEC>;
7043 impl Oabhf {
7044 #[doc = "No simultaneous generation of 1 both for the GTIOCnA and GTIOCnB pins has occurred."]
7045 pub const _0: Self = Self::new(0);
7046
7047 #[doc = "A simultaneous generation of 1 both for the GTIOCnA and GTIOCnB pins has occurred."]
7048 pub const _1: Self = Self::new(1);
7049 }
7050 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7051 pub struct Oablf_SPEC;
7052 pub type Oablf = crate::EnumBitfieldStruct<u8, Oablf_SPEC>;
7053 impl Oablf {
7054 #[doc = "No simultaneous generation of 0 both for the GTIOCnA and GTIOCnB pins has occurred."]
7055 pub const _0: Self = Self::new(0);
7056
7057 #[doc = "A simultaneous generation of 0 both for the GTIOCnA and GTIOCnB pins has occurred."]
7058 pub const _1: Self = Self::new(1);
7059 }
7060}
7061#[doc(hidden)]
7062#[derive(Copy, Clone, Eq, PartialEq)]
7063pub struct Gtber_SPEC;
7064impl crate::sealed::RegSpec for Gtber_SPEC {
7065 type DataType = u32;
7066}
7067
7068#[doc = "General PWM Timer Buffer Enable Register"]
7069pub type Gtber = crate::RegValueT<Gtber_SPEC>;
7070
7071impl Gtber {
7072 #[doc = "GTCCR Buffer Operation Disable"]
7073 #[inline(always)]
7074 pub fn bd0(
7075 self,
7076 ) -> crate::common::RegisterField<
7077 0,
7078 0x1,
7079 1,
7080 0,
7081 gtber::Bd0,
7082 gtber::Bd0,
7083 Gtber_SPEC,
7084 crate::common::RW,
7085 > {
7086 crate::common::RegisterField::<
7087 0,
7088 0x1,
7089 1,
7090 0,
7091 gtber::Bd0,
7092 gtber::Bd0,
7093 Gtber_SPEC,
7094 crate::common::RW,
7095 >::from_register(self, 0)
7096 }
7097
7098 #[doc = "GTPR Buffer Operation Disable"]
7099 #[inline(always)]
7100 pub fn bd1(
7101 self,
7102 ) -> crate::common::RegisterField<
7103 1,
7104 0x1,
7105 1,
7106 0,
7107 gtber::Bd1,
7108 gtber::Bd1,
7109 Gtber_SPEC,
7110 crate::common::RW,
7111 > {
7112 crate::common::RegisterField::<
7113 1,
7114 0x1,
7115 1,
7116 0,
7117 gtber::Bd1,
7118 gtber::Bd1,
7119 Gtber_SPEC,
7120 crate::common::RW,
7121 >::from_register(self, 0)
7122 }
7123
7124 #[doc = "GTCCRA Buffer Operation"]
7125 #[inline(always)]
7126 pub fn ccra(
7127 self,
7128 ) -> crate::common::RegisterField<
7129 16,
7130 0x3,
7131 1,
7132 0,
7133 gtber::Ccra,
7134 gtber::Ccra,
7135 Gtber_SPEC,
7136 crate::common::RW,
7137 > {
7138 crate::common::RegisterField::<
7139 16,
7140 0x3,
7141 1,
7142 0,
7143 gtber::Ccra,
7144 gtber::Ccra,
7145 Gtber_SPEC,
7146 crate::common::RW,
7147 >::from_register(self, 0)
7148 }
7149
7150 #[doc = "GTCCRB Buffer Operation"]
7151 #[inline(always)]
7152 pub fn ccrb(
7153 self,
7154 ) -> crate::common::RegisterField<
7155 18,
7156 0x3,
7157 1,
7158 0,
7159 gtber::Ccrb,
7160 gtber::Ccrb,
7161 Gtber_SPEC,
7162 crate::common::RW,
7163 > {
7164 crate::common::RegisterField::<
7165 18,
7166 0x3,
7167 1,
7168 0,
7169 gtber::Ccrb,
7170 gtber::Ccrb,
7171 Gtber_SPEC,
7172 crate::common::RW,
7173 >::from_register(self, 0)
7174 }
7175
7176 #[doc = "GTPR Buffer Operation"]
7177 #[inline(always)]
7178 pub fn pr(
7179 self,
7180 ) -> crate::common::RegisterField<
7181 20,
7182 0x3,
7183 1,
7184 0,
7185 gtber::Pr,
7186 gtber::Pr,
7187 Gtber_SPEC,
7188 crate::common::RW,
7189 > {
7190 crate::common::RegisterField::<
7191 20,
7192 0x3,
7193 1,
7194 0,
7195 gtber::Pr,
7196 gtber::Pr,
7197 Gtber_SPEC,
7198 crate::common::RW,
7199 >::from_register(self, 0)
7200 }
7201
7202 #[doc = "GTCCRA and GTCCRB Forcible Buffer Operation"]
7203 #[inline(always)]
7204 pub fn ccrswt(
7205 self,
7206 ) -> crate::common::RegisterFieldBool<22, 1, 0, Gtber_SPEC, crate::common::W> {
7207 crate::common::RegisterFieldBool::<22, 1, 0, Gtber_SPEC, crate::common::W>::from_register(
7208 self, 0,
7209 )
7210 }
7211}
7212impl ::core::default::Default for Gtber {
7213 #[inline(always)]
7214 fn default() -> Gtber {
7215 <crate::RegValueT<Gtber_SPEC> as RegisterValue<_>>::new(0)
7216 }
7217}
7218pub mod gtber {
7219
7220 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7221 pub struct Bd0_SPEC;
7222 pub type Bd0 = crate::EnumBitfieldStruct<u8, Bd0_SPEC>;
7223 impl Bd0 {
7224 #[doc = "Buffer operation is enabled"]
7225 pub const _0: Self = Self::new(0);
7226
7227 #[doc = "Buffer operation is disabled"]
7228 pub const _1: Self = Self::new(1);
7229 }
7230 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7231 pub struct Bd1_SPEC;
7232 pub type Bd1 = crate::EnumBitfieldStruct<u8, Bd1_SPEC>;
7233 impl Bd1 {
7234 #[doc = "Buffer operation is enabled"]
7235 pub const _0: Self = Self::new(0);
7236
7237 #[doc = "Buffer operation is disabled"]
7238 pub const _1: Self = Self::new(1);
7239 }
7240 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7241 pub struct Ccra_SPEC;
7242 pub type Ccra = crate::EnumBitfieldStruct<u8, Ccra_SPEC>;
7243 impl Ccra {
7244 #[doc = "No buffer operation"]
7245 pub const _00: Self = Self::new(0);
7246
7247 #[doc = "Single buffer operation (GTCCRA <---->GTCCRC)"]
7248 pub const _01: Self = Self::new(1);
7249 }
7250 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7251 pub struct Ccrb_SPEC;
7252 pub type Ccrb = crate::EnumBitfieldStruct<u8, Ccrb_SPEC>;
7253 impl Ccrb {
7254 #[doc = "No buffer operation"]
7255 pub const _00: Self = Self::new(0);
7256
7257 #[doc = "Single buffer operation (GTCCRB <----> GTCCRE)"]
7258 pub const _01: Self = Self::new(1);
7259 }
7260 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7261 pub struct Pr_SPEC;
7262 pub type Pr = crate::EnumBitfieldStruct<u8, Pr_SPEC>;
7263 impl Pr {
7264 #[doc = "No buffer operation"]
7265 pub const _00: Self = Self::new(0);
7266
7267 #[doc = "Single buffer operation (GTPBR --> GTPR)"]
7268 pub const _01: Self = Self::new(1);
7269 }
7270}
7271#[doc(hidden)]
7272#[derive(Copy, Clone, Eq, PartialEq)]
7273pub struct Gtcnt_SPEC;
7274impl crate::sealed::RegSpec for Gtcnt_SPEC {
7275 type DataType = u32;
7276}
7277
7278#[doc = "General PWM Timer Counter"]
7279pub type Gtcnt = crate::RegValueT<Gtcnt_SPEC>;
7280
7281impl NoBitfieldReg<Gtcnt_SPEC> for Gtcnt {}
7282impl ::core::default::Default for Gtcnt {
7283 #[inline(always)]
7284 fn default() -> Gtcnt {
7285 <crate::RegValueT<Gtcnt_SPEC> as RegisterValue<_>>::new(0)
7286 }
7287}
7288
7289#[doc(hidden)]
7290#[derive(Copy, Clone, Eq, PartialEq)]
7291pub struct Gtccra_SPEC;
7292impl crate::sealed::RegSpec for Gtccra_SPEC {
7293 type DataType = u32;
7294}
7295
7296#[doc = "General PWM Timer Compare Capture Register A"]
7297pub type Gtccra = crate::RegValueT<Gtccra_SPEC>;
7298
7299impl NoBitfieldReg<Gtccra_SPEC> for Gtccra {}
7300impl ::core::default::Default for Gtccra {
7301 #[inline(always)]
7302 fn default() -> Gtccra {
7303 <crate::RegValueT<Gtccra_SPEC> as RegisterValue<_>>::new(65535)
7304 }
7305}
7306
7307#[doc(hidden)]
7308#[derive(Copy, Clone, Eq, PartialEq)]
7309pub struct Gtccrb_SPEC;
7310impl crate::sealed::RegSpec for Gtccrb_SPEC {
7311 type DataType = u32;
7312}
7313
7314#[doc = "General PWM Timer Compare Capture Register B"]
7315pub type Gtccrb = crate::RegValueT<Gtccrb_SPEC>;
7316
7317impl NoBitfieldReg<Gtccrb_SPEC> for Gtccrb {}
7318impl ::core::default::Default for Gtccrb {
7319 #[inline(always)]
7320 fn default() -> Gtccrb {
7321 <crate::RegValueT<Gtccrb_SPEC> as RegisterValue<_>>::new(65535)
7322 }
7323}
7324
7325#[doc(hidden)]
7326#[derive(Copy, Clone, Eq, PartialEq)]
7327pub struct Gtccrc_SPEC;
7328impl crate::sealed::RegSpec for Gtccrc_SPEC {
7329 type DataType = u32;
7330}
7331
7332#[doc = "General PWM Timer Compare Capture Register C"]
7333pub type Gtccrc = crate::RegValueT<Gtccrc_SPEC>;
7334
7335impl NoBitfieldReg<Gtccrc_SPEC> for Gtccrc {}
7336impl ::core::default::Default for Gtccrc {
7337 #[inline(always)]
7338 fn default() -> Gtccrc {
7339 <crate::RegValueT<Gtccrc_SPEC> as RegisterValue<_>>::new(65535)
7340 }
7341}
7342
7343#[doc(hidden)]
7344#[derive(Copy, Clone, Eq, PartialEq)]
7345pub struct Gtccre_SPEC;
7346impl crate::sealed::RegSpec for Gtccre_SPEC {
7347 type DataType = u32;
7348}
7349
7350#[doc = "General PWM Timer Compare Capture Register E"]
7351pub type Gtccre = crate::RegValueT<Gtccre_SPEC>;
7352
7353impl NoBitfieldReg<Gtccre_SPEC> for Gtccre {}
7354impl ::core::default::Default for Gtccre {
7355 #[inline(always)]
7356 fn default() -> Gtccre {
7357 <crate::RegValueT<Gtccre_SPEC> as RegisterValue<_>>::new(65535)
7358 }
7359}
7360
7361#[doc(hidden)]
7362#[derive(Copy, Clone, Eq, PartialEq)]
7363pub struct Gtccrd_SPEC;
7364impl crate::sealed::RegSpec for Gtccrd_SPEC {
7365 type DataType = u32;
7366}
7367
7368#[doc = "General PWM Timer Compare Capture Register D"]
7369pub type Gtccrd = crate::RegValueT<Gtccrd_SPEC>;
7370
7371impl NoBitfieldReg<Gtccrd_SPEC> for Gtccrd {}
7372impl ::core::default::Default for Gtccrd {
7373 #[inline(always)]
7374 fn default() -> Gtccrd {
7375 <crate::RegValueT<Gtccrd_SPEC> as RegisterValue<_>>::new(65535)
7376 }
7377}
7378
7379#[doc(hidden)]
7380#[derive(Copy, Clone, Eq, PartialEq)]
7381pub struct Gtccrf_SPEC;
7382impl crate::sealed::RegSpec for Gtccrf_SPEC {
7383 type DataType = u32;
7384}
7385
7386#[doc = "General PWM Timer Compare Capture Register F"]
7387pub type Gtccrf = crate::RegValueT<Gtccrf_SPEC>;
7388
7389impl NoBitfieldReg<Gtccrf_SPEC> for Gtccrf {}
7390impl ::core::default::Default for Gtccrf {
7391 #[inline(always)]
7392 fn default() -> Gtccrf {
7393 <crate::RegValueT<Gtccrf_SPEC> as RegisterValue<_>>::new(65535)
7394 }
7395}
7396
7397#[doc(hidden)]
7398#[derive(Copy, Clone, Eq, PartialEq)]
7399pub struct Gtpr_SPEC;
7400impl crate::sealed::RegSpec for Gtpr_SPEC {
7401 type DataType = u32;
7402}
7403
7404#[doc = "General PWM Timer Cycle Setting Register"]
7405pub type Gtpr = crate::RegValueT<Gtpr_SPEC>;
7406
7407impl NoBitfieldReg<Gtpr_SPEC> for Gtpr {}
7408impl ::core::default::Default for Gtpr {
7409 #[inline(always)]
7410 fn default() -> Gtpr {
7411 <crate::RegValueT<Gtpr_SPEC> as RegisterValue<_>>::new(65535)
7412 }
7413}
7414
7415#[doc(hidden)]
7416#[derive(Copy, Clone, Eq, PartialEq)]
7417pub struct Gtpbr_SPEC;
7418impl crate::sealed::RegSpec for Gtpbr_SPEC {
7419 type DataType = u32;
7420}
7421
7422#[doc = "General PWM Timer Cycle Setting Buffer Register"]
7423pub type Gtpbr = crate::RegValueT<Gtpbr_SPEC>;
7424
7425impl NoBitfieldReg<Gtpbr_SPEC> for Gtpbr {}
7426impl ::core::default::Default for Gtpbr {
7427 #[inline(always)]
7428 fn default() -> Gtpbr {
7429 <crate::RegValueT<Gtpbr_SPEC> as RegisterValue<_>>::new(65535)
7430 }
7431}
7432
7433#[doc(hidden)]
7434#[derive(Copy, Clone, Eq, PartialEq)]
7435pub struct Gtdtcr_SPEC;
7436impl crate::sealed::RegSpec for Gtdtcr_SPEC {
7437 type DataType = u32;
7438}
7439
7440#[doc = "General PWM Timer Dead Time Control Register"]
7441pub type Gtdtcr = crate::RegValueT<Gtdtcr_SPEC>;
7442
7443impl Gtdtcr {
7444 #[doc = "Negative-Phase Waveform Setting"]
7445 #[inline(always)]
7446 pub fn tde(
7447 self,
7448 ) -> crate::common::RegisterField<
7449 0,
7450 0x1,
7451 1,
7452 0,
7453 gtdtcr::Tde,
7454 gtdtcr::Tde,
7455 Gtdtcr_SPEC,
7456 crate::common::RW,
7457 > {
7458 crate::common::RegisterField::<
7459 0,
7460 0x1,
7461 1,
7462 0,
7463 gtdtcr::Tde,
7464 gtdtcr::Tde,
7465 Gtdtcr_SPEC,
7466 crate::common::RW,
7467 >::from_register(self, 0)
7468 }
7469}
7470impl ::core::default::Default for Gtdtcr {
7471 #[inline(always)]
7472 fn default() -> Gtdtcr {
7473 <crate::RegValueT<Gtdtcr_SPEC> as RegisterValue<_>>::new(0)
7474 }
7475}
7476pub mod gtdtcr {
7477
7478 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7479 pub struct Tde_SPEC;
7480 pub type Tde = crate::EnumBitfieldStruct<u8, Tde_SPEC>;
7481 impl Tde {
7482 #[doc = "GTCCRB is set without using GTDVU"]
7483 pub const _0: Self = Self::new(0);
7484
7485 #[doc = "GTDVU is used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB"]
7486 pub const _1: Self = Self::new(1);
7487 }
7488}
7489#[doc(hidden)]
7490#[derive(Copy, Clone, Eq, PartialEq)]
7491pub struct Gtdvu_SPEC;
7492impl crate::sealed::RegSpec for Gtdvu_SPEC {
7493 type DataType = u32;
7494}
7495
7496#[doc = "General PWM Timer Dead Time Value Register U"]
7497pub type Gtdvu = crate::RegValueT<Gtdvu_SPEC>;
7498
7499impl NoBitfieldReg<Gtdvu_SPEC> for Gtdvu {}
7500impl ::core::default::Default for Gtdvu {
7501 #[inline(always)]
7502 fn default() -> Gtdvu {
7503 <crate::RegValueT<Gtdvu_SPEC> as RegisterValue<_>>::new(65535)
7504 }
7505}