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ra2a1_pac/
icu.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.1, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:31 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Interrupt Controller"]
28unsafe impl ::core::marker::Send for super::Icu {}
29unsafe impl ::core::marker::Sync for super::Icu {}
30impl super::Icu {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "IRQ Control Register %s"]
38    #[inline(always)]
39    pub const fn irqcr(
40        &self,
41    ) -> &'static crate::common::ClusterRegisterArray<
42        crate::common::Reg<self::Irqcr_SPEC, crate::common::RW>,
43        8,
44        0x1,
45    > {
46        unsafe {
47            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
48        }
49    }
50    #[inline(always)]
51    pub const fn irqcr0(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
52        unsafe {
53            crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
54                self._svd2pac_as_ptr().add(0x0usize),
55            )
56        }
57    }
58    #[inline(always)]
59    pub const fn irqcr1(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(0x1usize),
63            )
64        }
65    }
66    #[inline(always)]
67    pub const fn irqcr2(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
68        unsafe {
69            crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
70                self._svd2pac_as_ptr().add(0x2usize),
71            )
72        }
73    }
74    #[inline(always)]
75    pub const fn irqcr3(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
76        unsafe {
77            crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
78                self._svd2pac_as_ptr().add(0x3usize),
79            )
80        }
81    }
82    #[inline(always)]
83    pub const fn irqcr4(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
84        unsafe {
85            crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
86                self._svd2pac_as_ptr().add(0x4usize),
87            )
88        }
89    }
90    #[inline(always)]
91    pub const fn irqcr5(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
92        unsafe {
93            crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
94                self._svd2pac_as_ptr().add(0x5usize),
95            )
96        }
97    }
98    #[inline(always)]
99    pub const fn irqcr6(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(0x6usize),
103            )
104        }
105    }
106    #[inline(always)]
107    pub const fn irqcr7(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
108        unsafe {
109            crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
110                self._svd2pac_as_ptr().add(0x7usize),
111            )
112        }
113    }
114
115    #[doc = "Non-Maskable Interrupt Status Register"]
116    #[inline(always)]
117    pub const fn nmisr(&self) -> &'static crate::common::Reg<self::Nmisr_SPEC, crate::common::R> {
118        unsafe {
119            crate::common::Reg::<self::Nmisr_SPEC, crate::common::R>::from_ptr(
120                self._svd2pac_as_ptr().add(320usize),
121            )
122        }
123    }
124
125    #[doc = "Non-Maskable Interrupt Enable Register"]
126    #[inline(always)]
127    pub const fn nmier(&self) -> &'static crate::common::Reg<self::Nmier_SPEC, crate::common::RW> {
128        unsafe {
129            crate::common::Reg::<self::Nmier_SPEC, crate::common::RW>::from_ptr(
130                self._svd2pac_as_ptr().add(288usize),
131            )
132        }
133    }
134
135    #[doc = "Non-Maskable Interrupt Status Clear Register"]
136    #[inline(always)]
137    pub const fn nmiclr(
138        &self,
139    ) -> &'static crate::common::Reg<self::Nmiclr_SPEC, crate::common::RW> {
140        unsafe {
141            crate::common::Reg::<self::Nmiclr_SPEC, crate::common::RW>::from_ptr(
142                self._svd2pac_as_ptr().add(304usize),
143            )
144        }
145    }
146
147    #[doc = "NMI Pin Interrupt Control Register"]
148    #[inline(always)]
149    pub const fn nmicr(&self) -> &'static crate::common::Reg<self::Nmicr_SPEC, crate::common::RW> {
150        unsafe {
151            crate::common::Reg::<self::Nmicr_SPEC, crate::common::RW>::from_ptr(
152                self._svd2pac_as_ptr().add(256usize),
153            )
154        }
155    }
156
157    #[doc = "Wake Up Interrupt Enable Register"]
158    #[inline(always)]
159    pub const fn wupen(&self) -> &'static crate::common::Reg<self::Wupen_SPEC, crate::common::RW> {
160        unsafe {
161            crate::common::Reg::<self::Wupen_SPEC, crate::common::RW>::from_ptr(
162                self._svd2pac_as_ptr().add(416usize),
163            )
164        }
165    }
166
167    #[doc = "SYS Event Link Setting Register"]
168    #[inline(always)]
169    pub const fn selsr0(
170        &self,
171    ) -> &'static crate::common::Reg<self::Selsr0_SPEC, crate::common::RW> {
172        unsafe {
173            crate::common::Reg::<self::Selsr0_SPEC, crate::common::RW>::from_ptr(
174                self._svd2pac_as_ptr().add(512usize),
175            )
176        }
177    }
178
179    #[doc = "ICU Event Link Setting Register %s"]
180    #[inline(always)]
181    pub const fn ielsr(
182        &self,
183    ) -> &'static crate::common::ClusterRegisterArray<
184        crate::common::Reg<self::Ielsr_SPEC, crate::common::RW>,
185        32,
186        0x4,
187    > {
188        unsafe {
189            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x300usize))
190        }
191    }
192    #[inline(always)]
193    pub const fn ielsr0(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
194        unsafe {
195            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
196                self._svd2pac_as_ptr().add(0x300usize),
197            )
198        }
199    }
200    #[inline(always)]
201    pub const fn ielsr1(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
202        unsafe {
203            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
204                self._svd2pac_as_ptr().add(0x304usize),
205            )
206        }
207    }
208    #[inline(always)]
209    pub const fn ielsr2(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
210        unsafe {
211            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
212                self._svd2pac_as_ptr().add(0x308usize),
213            )
214        }
215    }
216    #[inline(always)]
217    pub const fn ielsr3(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
218        unsafe {
219            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
220                self._svd2pac_as_ptr().add(0x30cusize),
221            )
222        }
223    }
224    #[inline(always)]
225    pub const fn ielsr4(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
226        unsafe {
227            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
228                self._svd2pac_as_ptr().add(0x310usize),
229            )
230        }
231    }
232    #[inline(always)]
233    pub const fn ielsr5(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
234        unsafe {
235            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
236                self._svd2pac_as_ptr().add(0x314usize),
237            )
238        }
239    }
240    #[inline(always)]
241    pub const fn ielsr6(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
242        unsafe {
243            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
244                self._svd2pac_as_ptr().add(0x318usize),
245            )
246        }
247    }
248    #[inline(always)]
249    pub const fn ielsr7(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
250        unsafe {
251            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
252                self._svd2pac_as_ptr().add(0x31cusize),
253            )
254        }
255    }
256    #[inline(always)]
257    pub const fn ielsr8(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
258        unsafe {
259            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
260                self._svd2pac_as_ptr().add(0x320usize),
261            )
262        }
263    }
264    #[inline(always)]
265    pub const fn ielsr9(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
266        unsafe {
267            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
268                self._svd2pac_as_ptr().add(0x324usize),
269            )
270        }
271    }
272    #[inline(always)]
273    pub const fn ielsr10(
274        &self,
275    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
276        unsafe {
277            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
278                self._svd2pac_as_ptr().add(0x328usize),
279            )
280        }
281    }
282    #[inline(always)]
283    pub const fn ielsr11(
284        &self,
285    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
286        unsafe {
287            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
288                self._svd2pac_as_ptr().add(0x32cusize),
289            )
290        }
291    }
292    #[inline(always)]
293    pub const fn ielsr12(
294        &self,
295    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
296        unsafe {
297            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
298                self._svd2pac_as_ptr().add(0x330usize),
299            )
300        }
301    }
302    #[inline(always)]
303    pub const fn ielsr13(
304        &self,
305    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
306        unsafe {
307            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
308                self._svd2pac_as_ptr().add(0x334usize),
309            )
310        }
311    }
312    #[inline(always)]
313    pub const fn ielsr14(
314        &self,
315    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
316        unsafe {
317            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
318                self._svd2pac_as_ptr().add(0x338usize),
319            )
320        }
321    }
322    #[inline(always)]
323    pub const fn ielsr15(
324        &self,
325    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
326        unsafe {
327            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
328                self._svd2pac_as_ptr().add(0x33cusize),
329            )
330        }
331    }
332    #[inline(always)]
333    pub const fn ielsr16(
334        &self,
335    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
336        unsafe {
337            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
338                self._svd2pac_as_ptr().add(0x340usize),
339            )
340        }
341    }
342    #[inline(always)]
343    pub const fn ielsr17(
344        &self,
345    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
346        unsafe {
347            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
348                self._svd2pac_as_ptr().add(0x344usize),
349            )
350        }
351    }
352    #[inline(always)]
353    pub const fn ielsr18(
354        &self,
355    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
356        unsafe {
357            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
358                self._svd2pac_as_ptr().add(0x348usize),
359            )
360        }
361    }
362    #[inline(always)]
363    pub const fn ielsr19(
364        &self,
365    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
366        unsafe {
367            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
368                self._svd2pac_as_ptr().add(0x34cusize),
369            )
370        }
371    }
372    #[inline(always)]
373    pub const fn ielsr20(
374        &self,
375    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
376        unsafe {
377            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
378                self._svd2pac_as_ptr().add(0x350usize),
379            )
380        }
381    }
382    #[inline(always)]
383    pub const fn ielsr21(
384        &self,
385    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
386        unsafe {
387            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
388                self._svd2pac_as_ptr().add(0x354usize),
389            )
390        }
391    }
392    #[inline(always)]
393    pub const fn ielsr22(
394        &self,
395    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
396        unsafe {
397            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
398                self._svd2pac_as_ptr().add(0x358usize),
399            )
400        }
401    }
402    #[inline(always)]
403    pub const fn ielsr23(
404        &self,
405    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
406        unsafe {
407            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
408                self._svd2pac_as_ptr().add(0x35cusize),
409            )
410        }
411    }
412    #[inline(always)]
413    pub const fn ielsr24(
414        &self,
415    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
416        unsafe {
417            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
418                self._svd2pac_as_ptr().add(0x360usize),
419            )
420        }
421    }
422    #[inline(always)]
423    pub const fn ielsr25(
424        &self,
425    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
426        unsafe {
427            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
428                self._svd2pac_as_ptr().add(0x364usize),
429            )
430        }
431    }
432    #[inline(always)]
433    pub const fn ielsr26(
434        &self,
435    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
436        unsafe {
437            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
438                self._svd2pac_as_ptr().add(0x368usize),
439            )
440        }
441    }
442    #[inline(always)]
443    pub const fn ielsr27(
444        &self,
445    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
446        unsafe {
447            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
448                self._svd2pac_as_ptr().add(0x36cusize),
449            )
450        }
451    }
452    #[inline(always)]
453    pub const fn ielsr28(
454        &self,
455    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
456        unsafe {
457            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
458                self._svd2pac_as_ptr().add(0x370usize),
459            )
460        }
461    }
462    #[inline(always)]
463    pub const fn ielsr29(
464        &self,
465    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
466        unsafe {
467            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
468                self._svd2pac_as_ptr().add(0x374usize),
469            )
470        }
471    }
472    #[inline(always)]
473    pub const fn ielsr30(
474        &self,
475    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
476        unsafe {
477            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
478                self._svd2pac_as_ptr().add(0x378usize),
479            )
480        }
481    }
482    #[inline(always)]
483    pub const fn ielsr31(
484        &self,
485    ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
486        unsafe {
487            crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
488                self._svd2pac_as_ptr().add(0x37cusize),
489            )
490        }
491    }
492}
493#[doc(hidden)]
494#[derive(Copy, Clone, Eq, PartialEq)]
495pub struct Irqcr_SPEC;
496impl crate::sealed::RegSpec for Irqcr_SPEC {
497    type DataType = u8;
498}
499
500#[doc = "IRQ Control Register %s"]
501pub type Irqcr = crate::RegValueT<Irqcr_SPEC>;
502
503impl Irqcr {
504    #[doc = "IRQ Digital Filter Enable"]
505    #[inline(always)]
506    pub fn flten(
507        self,
508    ) -> crate::common::RegisterField<
509        7,
510        0x1,
511        1,
512        0,
513        irqcr::Flten,
514        irqcr::Flten,
515        Irqcr_SPEC,
516        crate::common::RW,
517    > {
518        crate::common::RegisterField::<
519            7,
520            0x1,
521            1,
522            0,
523            irqcr::Flten,
524            irqcr::Flten,
525            Irqcr_SPEC,
526            crate::common::RW,
527        >::from_register(self, 0)
528    }
529
530    #[doc = "IRQi Digital Filter Sampling Clock Select"]
531    #[inline(always)]
532    pub fn fclksel(
533        self,
534    ) -> crate::common::RegisterField<
535        4,
536        0x3,
537        1,
538        0,
539        irqcr::Fclksel,
540        irqcr::Fclksel,
541        Irqcr_SPEC,
542        crate::common::RW,
543    > {
544        crate::common::RegisterField::<
545            4,
546            0x3,
547            1,
548            0,
549            irqcr::Fclksel,
550            irqcr::Fclksel,
551            Irqcr_SPEC,
552            crate::common::RW,
553        >::from_register(self, 0)
554    }
555
556    #[doc = "These bits are read as 00. The write value should be 00."]
557    #[inline(always)]
558    pub fn reserved(
559        self,
560    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, Irqcr_SPEC, crate::common::RW> {
561        crate::common::RegisterField::<2,0x3,1,0,u8,u8,Irqcr_SPEC,crate::common::RW>::from_register(self,0)
562    }
563
564    #[doc = "IRQ Detection Sense Select"]
565    #[inline(always)]
566    pub fn irqmd(
567        self,
568    ) -> crate::common::RegisterField<
569        0,
570        0x3,
571        1,
572        0,
573        irqcr::Irqmd,
574        irqcr::Irqmd,
575        Irqcr_SPEC,
576        crate::common::RW,
577    > {
578        crate::common::RegisterField::<
579            0,
580            0x3,
581            1,
582            0,
583            irqcr::Irqmd,
584            irqcr::Irqmd,
585            Irqcr_SPEC,
586            crate::common::RW,
587        >::from_register(self, 0)
588    }
589}
590impl ::core::default::Default for Irqcr {
591    #[inline(always)]
592    fn default() -> Irqcr {
593        <crate::RegValueT<Irqcr_SPEC> as RegisterValue<_>>::new(0)
594    }
595}
596pub mod irqcr {
597
598    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
599    pub struct Flten_SPEC;
600    pub type Flten = crate::EnumBitfieldStruct<u8, Flten_SPEC>;
601    impl Flten {
602        #[doc = "Digital filter is disabled."]
603        pub const _0: Self = Self::new(0);
604
605        #[doc = "Digital filter is enabled."]
606        pub const _1: Self = Self::new(1);
607    }
608    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
609    pub struct Fclksel_SPEC;
610    pub type Fclksel = crate::EnumBitfieldStruct<u8, Fclksel_SPEC>;
611    impl Fclksel {
612        #[doc = "PCLKB"]
613        pub const _00: Self = Self::new(0);
614
615        #[doc = "PCLKB/8"]
616        pub const _01: Self = Self::new(1);
617
618        #[doc = "PCLKB/32"]
619        pub const _10: Self = Self::new(2);
620
621        #[doc = "PCLKB/64"]
622        pub const _11: Self = Self::new(3);
623    }
624    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
625    pub struct Irqmd_SPEC;
626    pub type Irqmd = crate::EnumBitfieldStruct<u8, Irqmd_SPEC>;
627    impl Irqmd {
628        #[doc = "Falling edge"]
629        pub const _00: Self = Self::new(0);
630
631        #[doc = "Rising edge"]
632        pub const _01: Self = Self::new(1);
633
634        #[doc = "Rising and falling edges"]
635        pub const _10: Self = Self::new(2);
636
637        #[doc = "Low level"]
638        pub const _11: Self = Self::new(3);
639    }
640}
641#[doc(hidden)]
642#[derive(Copy, Clone, Eq, PartialEq)]
643pub struct Nmisr_SPEC;
644impl crate::sealed::RegSpec for Nmisr_SPEC {
645    type DataType = u16;
646}
647
648#[doc = "Non-Maskable Interrupt Status Register"]
649pub type Nmisr = crate::RegValueT<Nmisr_SPEC>;
650
651impl Nmisr {
652    #[doc = "CPU Stack Pointer Monitor Interrupt Status Flag"]
653    #[inline(always)]
654    pub fn spest(
655        self,
656    ) -> crate::common::RegisterField<
657        12,
658        0x1,
659        1,
660        0,
661        nmisr::Spest,
662        nmisr::Spest,
663        Nmisr_SPEC,
664        crate::common::R,
665    > {
666        crate::common::RegisterField::<
667            12,
668            0x1,
669            1,
670            0,
671            nmisr::Spest,
672            nmisr::Spest,
673            Nmisr_SPEC,
674            crate::common::R,
675        >::from_register(self, 0)
676    }
677
678    #[doc = "MPU Bus Master Error Interrupt Status Flag"]
679    #[inline(always)]
680    pub fn busmst(
681        self,
682    ) -> crate::common::RegisterField<
683        11,
684        0x1,
685        1,
686        0,
687        nmisr::Busmst,
688        nmisr::Busmst,
689        Nmisr_SPEC,
690        crate::common::R,
691    > {
692        crate::common::RegisterField::<
693            11,
694            0x1,
695            1,
696            0,
697            nmisr::Busmst,
698            nmisr::Busmst,
699            Nmisr_SPEC,
700            crate::common::R,
701        >::from_register(self, 0)
702    }
703
704    #[doc = "MPU Bus Slave Error Interrupt Status Flag"]
705    #[inline(always)]
706    pub fn bussst(
707        self,
708    ) -> crate::common::RegisterField<
709        10,
710        0x1,
711        1,
712        0,
713        nmisr::Bussst,
714        nmisr::Bussst,
715        Nmisr_SPEC,
716        crate::common::R,
717    > {
718        crate::common::RegisterField::<
719            10,
720            0x1,
721            1,
722            0,
723            nmisr::Bussst,
724            nmisr::Bussst,
725            Nmisr_SPEC,
726            crate::common::R,
727        >::from_register(self, 0)
728    }
729
730    #[doc = "SRAM ECC Error Interrupt Status Flag"]
731    #[inline(always)]
732    pub fn reccst(
733        self,
734    ) -> crate::common::RegisterField<
735        9,
736        0x1,
737        1,
738        0,
739        nmisr::Reccst,
740        nmisr::Reccst,
741        Nmisr_SPEC,
742        crate::common::R,
743    > {
744        crate::common::RegisterField::<
745            9,
746            0x1,
747            1,
748            0,
749            nmisr::Reccst,
750            nmisr::Reccst,
751            Nmisr_SPEC,
752            crate::common::R,
753        >::from_register(self, 0)
754    }
755
756    #[doc = "RAM Parity Error Interrupt Status Flag"]
757    #[inline(always)]
758    pub fn rpest(
759        self,
760    ) -> crate::common::RegisterField<
761        8,
762        0x1,
763        1,
764        0,
765        nmisr::Rpest,
766        nmisr::Rpest,
767        Nmisr_SPEC,
768        crate::common::R,
769    > {
770        crate::common::RegisterField::<
771            8,
772            0x1,
773            1,
774            0,
775            nmisr::Rpest,
776            nmisr::Rpest,
777            Nmisr_SPEC,
778            crate::common::R,
779        >::from_register(self, 0)
780    }
781
782    #[doc = "NMI Status Flag"]
783    #[inline(always)]
784    pub fn nmist(
785        self,
786    ) -> crate::common::RegisterField<
787        7,
788        0x1,
789        1,
790        0,
791        nmisr::Nmist,
792        nmisr::Nmist,
793        Nmisr_SPEC,
794        crate::common::R,
795    > {
796        crate::common::RegisterField::<
797            7,
798            0x1,
799            1,
800            0,
801            nmisr::Nmist,
802            nmisr::Nmist,
803            Nmisr_SPEC,
804            crate::common::R,
805        >::from_register(self, 0)
806    }
807
808    #[doc = "Oscillation Stop Detection Interrupt Status Flag"]
809    #[inline(always)]
810    pub fn ostst(
811        self,
812    ) -> crate::common::RegisterField<
813        6,
814        0x1,
815        1,
816        0,
817        nmisr::Ostst,
818        nmisr::Ostst,
819        Nmisr_SPEC,
820        crate::common::R,
821    > {
822        crate::common::RegisterField::<
823            6,
824            0x1,
825            1,
826            0,
827            nmisr::Ostst,
828            nmisr::Ostst,
829            Nmisr_SPEC,
830            crate::common::R,
831        >::from_register(self, 0)
832    }
833
834    #[doc = "These bits are read as 00."]
835    #[inline(always)]
836    pub fn reserved(
837        self,
838    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, Nmisr_SPEC, crate::common::R> {
839        crate::common::RegisterField::<4,0x3,1,0,u8,u8,Nmisr_SPEC,crate::common::R>::from_register(self,0)
840    }
841
842    #[doc = "Voltage-Monitoring 2 Interrupt Status Flag"]
843    #[inline(always)]
844    pub fn lvd2st(
845        self,
846    ) -> crate::common::RegisterField<
847        3,
848        0x1,
849        1,
850        0,
851        nmisr::Lvd2St,
852        nmisr::Lvd2St,
853        Nmisr_SPEC,
854        crate::common::R,
855    > {
856        crate::common::RegisterField::<
857            3,
858            0x1,
859            1,
860            0,
861            nmisr::Lvd2St,
862            nmisr::Lvd2St,
863            Nmisr_SPEC,
864            crate::common::R,
865        >::from_register(self, 0)
866    }
867
868    #[doc = "Voltage-Monitoring 1 Interrupt Status Flag"]
869    #[inline(always)]
870    pub fn lvd1st(
871        self,
872    ) -> crate::common::RegisterField<
873        2,
874        0x1,
875        1,
876        0,
877        nmisr::Lvd1St,
878        nmisr::Lvd1St,
879        Nmisr_SPEC,
880        crate::common::R,
881    > {
882        crate::common::RegisterField::<
883            2,
884            0x1,
885            1,
886            0,
887            nmisr::Lvd1St,
888            nmisr::Lvd1St,
889            Nmisr_SPEC,
890            crate::common::R,
891        >::from_register(self, 0)
892    }
893
894    #[doc = "WDT Underflow/Refresh Error Status Flag"]
895    #[inline(always)]
896    pub fn wdtst(
897        self,
898    ) -> crate::common::RegisterField<
899        1,
900        0x1,
901        1,
902        0,
903        nmisr::Wdtst,
904        nmisr::Wdtst,
905        Nmisr_SPEC,
906        crate::common::R,
907    > {
908        crate::common::RegisterField::<
909            1,
910            0x1,
911            1,
912            0,
913            nmisr::Wdtst,
914            nmisr::Wdtst,
915            Nmisr_SPEC,
916            crate::common::R,
917        >::from_register(self, 0)
918    }
919
920    #[doc = "IWDT Underflow/Refresh Error Status Flag"]
921    #[inline(always)]
922    pub fn iwdtst(
923        self,
924    ) -> crate::common::RegisterField<
925        0,
926        0x1,
927        1,
928        0,
929        nmisr::Iwdtst,
930        nmisr::Iwdtst,
931        Nmisr_SPEC,
932        crate::common::R,
933    > {
934        crate::common::RegisterField::<
935            0,
936            0x1,
937            1,
938            0,
939            nmisr::Iwdtst,
940            nmisr::Iwdtst,
941            Nmisr_SPEC,
942            crate::common::R,
943        >::from_register(self, 0)
944    }
945}
946impl ::core::default::Default for Nmisr {
947    #[inline(always)]
948    fn default() -> Nmisr {
949        <crate::RegValueT<Nmisr_SPEC> as RegisterValue<_>>::new(0)
950    }
951}
952pub mod nmisr {
953
954    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
955    pub struct Spest_SPEC;
956    pub type Spest = crate::EnumBitfieldStruct<u8, Spest_SPEC>;
957    impl Spest {
958        #[doc = "Interrupt not requested"]
959        pub const _0: Self = Self::new(0);
960
961        #[doc = "Interrupt requested."]
962        pub const _1: Self = Self::new(1);
963    }
964    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
965    pub struct Busmst_SPEC;
966    pub type Busmst = crate::EnumBitfieldStruct<u8, Busmst_SPEC>;
967    impl Busmst {
968        #[doc = "Interrupt not requested"]
969        pub const _0: Self = Self::new(0);
970
971        #[doc = "Interrupt requested."]
972        pub const _1: Self = Self::new(1);
973    }
974    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
975    pub struct Bussst_SPEC;
976    pub type Bussst = crate::EnumBitfieldStruct<u8, Bussst_SPEC>;
977    impl Bussst {
978        #[doc = "Interrupt not requested"]
979        pub const _0: Self = Self::new(0);
980
981        #[doc = "Interrupt requested."]
982        pub const _1: Self = Self::new(1);
983    }
984    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
985    pub struct Reccst_SPEC;
986    pub type Reccst = crate::EnumBitfieldStruct<u8, Reccst_SPEC>;
987    impl Reccst {
988        #[doc = "Interrupt not requested"]
989        pub const _0: Self = Self::new(0);
990
991        #[doc = "Interrupt requested."]
992        pub const _1: Self = Self::new(1);
993    }
994    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
995    pub struct Rpest_SPEC;
996    pub type Rpest = crate::EnumBitfieldStruct<u8, Rpest_SPEC>;
997    impl Rpest {
998        #[doc = "RAM Parity Error interrupt is not requested."]
999        pub const _0: Self = Self::new(0);
1000
1001        #[doc = "RAM Parity Error interrupt is requested."]
1002        pub const _1: Self = Self::new(1);
1003    }
1004    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1005    pub struct Nmist_SPEC;
1006    pub type Nmist = crate::EnumBitfieldStruct<u8, Nmist_SPEC>;
1007    impl Nmist {
1008        #[doc = "NMI pin interrupt is not requested."]
1009        pub const _0: Self = Self::new(0);
1010
1011        #[doc = "NMI pin interrupt is requested."]
1012        pub const _1: Self = Self::new(1);
1013    }
1014    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1015    pub struct Ostst_SPEC;
1016    pub type Ostst = crate::EnumBitfieldStruct<u8, Ostst_SPEC>;
1017    impl Ostst {
1018        #[doc = "Main Oscillation stop detection interrupt is not requested."]
1019        pub const _0: Self = Self::new(0);
1020
1021        #[doc = "Main Oscillation stop detection interrupt is requested."]
1022        pub const _1: Self = Self::new(1);
1023    }
1024    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1025    pub struct Lvd2St_SPEC;
1026    pub type Lvd2St = crate::EnumBitfieldStruct<u8, Lvd2St_SPEC>;
1027    impl Lvd2St {
1028        #[doc = "Voltage-monitoring 2 interrupt is not requested."]
1029        pub const _0: Self = Self::new(0);
1030
1031        #[doc = "Voltage-monitoring 2 interrupt is requested."]
1032        pub const _1: Self = Self::new(1);
1033    }
1034    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1035    pub struct Lvd1St_SPEC;
1036    pub type Lvd1St = crate::EnumBitfieldStruct<u8, Lvd1St_SPEC>;
1037    impl Lvd1St {
1038        #[doc = "Voltage-monitoring 1 interrupt is not requested."]
1039        pub const _0: Self = Self::new(0);
1040
1041        #[doc = "Voltage-monitoring 1 interrupt is requested."]
1042        pub const _1: Self = Self::new(1);
1043    }
1044    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1045    pub struct Wdtst_SPEC;
1046    pub type Wdtst = crate::EnumBitfieldStruct<u8, Wdtst_SPEC>;
1047    impl Wdtst {
1048        #[doc = "WDT underflow/refresh error interrupt is not requested."]
1049        pub const _0: Self = Self::new(0);
1050
1051        #[doc = "WDT underflow/refresh error interrupt is requested."]
1052        pub const _1: Self = Self::new(1);
1053    }
1054    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1055    pub struct Iwdtst_SPEC;
1056    pub type Iwdtst = crate::EnumBitfieldStruct<u8, Iwdtst_SPEC>;
1057    impl Iwdtst {
1058        #[doc = "IWDT underflow/refresh error interrupt is not requested."]
1059        pub const _0: Self = Self::new(0);
1060
1061        #[doc = "IWDT underflow/refresh error interrupt is requested."]
1062        pub const _1: Self = Self::new(1);
1063    }
1064}
1065#[doc(hidden)]
1066#[derive(Copy, Clone, Eq, PartialEq)]
1067pub struct Nmier_SPEC;
1068impl crate::sealed::RegSpec for Nmier_SPEC {
1069    type DataType = u16;
1070}
1071
1072#[doc = "Non-Maskable Interrupt Enable Register"]
1073pub type Nmier = crate::RegValueT<Nmier_SPEC>;
1074
1075impl Nmier {
1076    #[doc = "CPU Stack Pointer Monitor Interrupt Enable"]
1077    #[inline(always)]
1078    pub fn speen(
1079        self,
1080    ) -> crate::common::RegisterField<
1081        12,
1082        0x1,
1083        1,
1084        0,
1085        nmier::Speen,
1086        nmier::Speen,
1087        Nmier_SPEC,
1088        crate::common::RW,
1089    > {
1090        crate::common::RegisterField::<
1091            12,
1092            0x1,
1093            1,
1094            0,
1095            nmier::Speen,
1096            nmier::Speen,
1097            Nmier_SPEC,
1098            crate::common::RW,
1099        >::from_register(self, 0)
1100    }
1101
1102    #[doc = "MPU Bus Master Error Interrupt Enable"]
1103    #[inline(always)]
1104    pub fn busmen(
1105        self,
1106    ) -> crate::common::RegisterField<
1107        11,
1108        0x1,
1109        1,
1110        0,
1111        nmier::Busmen,
1112        nmier::Busmen,
1113        Nmier_SPEC,
1114        crate::common::RW,
1115    > {
1116        crate::common::RegisterField::<
1117            11,
1118            0x1,
1119            1,
1120            0,
1121            nmier::Busmen,
1122            nmier::Busmen,
1123            Nmier_SPEC,
1124            crate::common::RW,
1125        >::from_register(self, 0)
1126    }
1127
1128    #[doc = "MPU Bus Slave Error Interrupt Enable"]
1129    #[inline(always)]
1130    pub fn bussen(
1131        self,
1132    ) -> crate::common::RegisterField<
1133        10,
1134        0x1,
1135        1,
1136        0,
1137        nmier::Bussen,
1138        nmier::Bussen,
1139        Nmier_SPEC,
1140        crate::common::RW,
1141    > {
1142        crate::common::RegisterField::<
1143            10,
1144            0x1,
1145            1,
1146            0,
1147            nmier::Bussen,
1148            nmier::Bussen,
1149            Nmier_SPEC,
1150            crate::common::RW,
1151        >::from_register(self, 0)
1152    }
1153
1154    #[doc = "SRAM ECC Error Interrupt Enable"]
1155    #[inline(always)]
1156    pub fn reccen(
1157        self,
1158    ) -> crate::common::RegisterField<
1159        9,
1160        0x1,
1161        1,
1162        0,
1163        nmier::Reccen,
1164        nmier::Reccen,
1165        Nmier_SPEC,
1166        crate::common::RW,
1167    > {
1168        crate::common::RegisterField::<
1169            9,
1170            0x1,
1171            1,
1172            0,
1173            nmier::Reccen,
1174            nmier::Reccen,
1175            Nmier_SPEC,
1176            crate::common::RW,
1177        >::from_register(self, 0)
1178    }
1179
1180    #[doc = "RAM Parity Error Interrupt Enable"]
1181    #[inline(always)]
1182    pub fn rpeen(
1183        self,
1184    ) -> crate::common::RegisterField<
1185        8,
1186        0x1,
1187        1,
1188        0,
1189        nmier::Rpeen,
1190        nmier::Rpeen,
1191        Nmier_SPEC,
1192        crate::common::RW,
1193    > {
1194        crate::common::RegisterField::<
1195            8,
1196            0x1,
1197            1,
1198            0,
1199            nmier::Rpeen,
1200            nmier::Rpeen,
1201            Nmier_SPEC,
1202            crate::common::RW,
1203        >::from_register(self, 0)
1204    }
1205
1206    #[doc = "NMI Pin Interrupt Enable"]
1207    #[inline(always)]
1208    pub fn nmien(
1209        self,
1210    ) -> crate::common::RegisterField<
1211        7,
1212        0x1,
1213        1,
1214        0,
1215        nmier::Nmien,
1216        nmier::Nmien,
1217        Nmier_SPEC,
1218        crate::common::RW,
1219    > {
1220        crate::common::RegisterField::<
1221            7,
1222            0x1,
1223            1,
1224            0,
1225            nmier::Nmien,
1226            nmier::Nmien,
1227            Nmier_SPEC,
1228            crate::common::RW,
1229        >::from_register(self, 0)
1230    }
1231
1232    #[doc = "Oscillation Stop Detection Interrupt Enable"]
1233    #[inline(always)]
1234    pub fn osten(
1235        self,
1236    ) -> crate::common::RegisterField<
1237        6,
1238        0x1,
1239        1,
1240        0,
1241        nmier::Osten,
1242        nmier::Osten,
1243        Nmier_SPEC,
1244        crate::common::RW,
1245    > {
1246        crate::common::RegisterField::<
1247            6,
1248            0x1,
1249            1,
1250            0,
1251            nmier::Osten,
1252            nmier::Osten,
1253            Nmier_SPEC,
1254            crate::common::RW,
1255        >::from_register(self, 0)
1256    }
1257
1258    #[doc = "These bits are read as 00. The write value should be 00."]
1259    #[inline(always)]
1260    pub fn reserved(
1261        self,
1262    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, Nmier_SPEC, crate::common::RW> {
1263        crate::common::RegisterField::<4,0x3,1,0,u8,u8,Nmier_SPEC,crate::common::RW>::from_register(self,0)
1264    }
1265
1266    #[doc = "Voltage-Monitoring 2 Interrupt Enable"]
1267    #[inline(always)]
1268    pub fn lvd2en(
1269        self,
1270    ) -> crate::common::RegisterField<
1271        3,
1272        0x1,
1273        1,
1274        0,
1275        nmier::Lvd2En,
1276        nmier::Lvd2En,
1277        Nmier_SPEC,
1278        crate::common::RW,
1279    > {
1280        crate::common::RegisterField::<
1281            3,
1282            0x1,
1283            1,
1284            0,
1285            nmier::Lvd2En,
1286            nmier::Lvd2En,
1287            Nmier_SPEC,
1288            crate::common::RW,
1289        >::from_register(self, 0)
1290    }
1291
1292    #[doc = "Voltage-Monitoring 1 Interrupt Enable"]
1293    #[inline(always)]
1294    pub fn lvd1en(
1295        self,
1296    ) -> crate::common::RegisterField<
1297        2,
1298        0x1,
1299        1,
1300        0,
1301        nmier::Lvd1En,
1302        nmier::Lvd1En,
1303        Nmier_SPEC,
1304        crate::common::RW,
1305    > {
1306        crate::common::RegisterField::<
1307            2,
1308            0x1,
1309            1,
1310            0,
1311            nmier::Lvd1En,
1312            nmier::Lvd1En,
1313            Nmier_SPEC,
1314            crate::common::RW,
1315        >::from_register(self, 0)
1316    }
1317
1318    #[doc = "WDT Underflow/Refresh Error Interrupt Enable"]
1319    #[inline(always)]
1320    pub fn wdten(
1321        self,
1322    ) -> crate::common::RegisterField<
1323        1,
1324        0x1,
1325        1,
1326        0,
1327        nmier::Wdten,
1328        nmier::Wdten,
1329        Nmier_SPEC,
1330        crate::common::RW,
1331    > {
1332        crate::common::RegisterField::<
1333            1,
1334            0x1,
1335            1,
1336            0,
1337            nmier::Wdten,
1338            nmier::Wdten,
1339            Nmier_SPEC,
1340            crate::common::RW,
1341        >::from_register(self, 0)
1342    }
1343
1344    #[doc = "IWDT Underflow/Refresh Error Interrupt Enable"]
1345    #[inline(always)]
1346    pub fn iwdten(
1347        self,
1348    ) -> crate::common::RegisterField<
1349        0,
1350        0x1,
1351        1,
1352        0,
1353        nmier::Iwdten,
1354        nmier::Iwdten,
1355        Nmier_SPEC,
1356        crate::common::RW,
1357    > {
1358        crate::common::RegisterField::<
1359            0,
1360            0x1,
1361            1,
1362            0,
1363            nmier::Iwdten,
1364            nmier::Iwdten,
1365            Nmier_SPEC,
1366            crate::common::RW,
1367        >::from_register(self, 0)
1368    }
1369}
1370impl ::core::default::Default for Nmier {
1371    #[inline(always)]
1372    fn default() -> Nmier {
1373        <crate::RegValueT<Nmier_SPEC> as RegisterValue<_>>::new(0)
1374    }
1375}
1376pub mod nmier {
1377
1378    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1379    pub struct Speen_SPEC;
1380    pub type Speen = crate::EnumBitfieldStruct<u8, Speen_SPEC>;
1381    impl Speen {
1382        #[doc = "CPU Stack Pointer Monitor interrupt is disabled."]
1383        pub const _0: Self = Self::new(0);
1384
1385        #[doc = "CPU Stack Pointer Monitor interrupt is enabled."]
1386        pub const _1: Self = Self::new(1);
1387    }
1388    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1389    pub struct Busmen_SPEC;
1390    pub type Busmen = crate::EnumBitfieldStruct<u8, Busmen_SPEC>;
1391    impl Busmen {
1392        #[doc = "MPU Bus Master Error interrupt is disabled."]
1393        pub const _0: Self = Self::new(0);
1394
1395        #[doc = "MPU Bus Master Error interrupt is enabled."]
1396        pub const _1: Self = Self::new(1);
1397    }
1398    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1399    pub struct Bussen_SPEC;
1400    pub type Bussen = crate::EnumBitfieldStruct<u8, Bussen_SPEC>;
1401    impl Bussen {
1402        #[doc = "MPU Bus Slave Error interrupt is disabled."]
1403        pub const _0: Self = Self::new(0);
1404
1405        #[doc = "MPU Bus Slave Error interrupt is enabled."]
1406        pub const _1: Self = Self::new(1);
1407    }
1408    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1409    pub struct Reccen_SPEC;
1410    pub type Reccen = crate::EnumBitfieldStruct<u8, Reccen_SPEC>;
1411    impl Reccen {
1412        #[doc = "SRAM ECC Error interrupt is disabled."]
1413        pub const _0: Self = Self::new(0);
1414
1415        #[doc = "SRAM ECC Error interrupt is enabled."]
1416        pub const _1: Self = Self::new(1);
1417    }
1418    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1419    pub struct Rpeen_SPEC;
1420    pub type Rpeen = crate::EnumBitfieldStruct<u8, Rpeen_SPEC>;
1421    impl Rpeen {
1422        #[doc = "SRAM Parity Error interrupt is disabled."]
1423        pub const _0: Self = Self::new(0);
1424
1425        #[doc = "SRAM Parity Error interrupt is enabled."]
1426        pub const _1: Self = Self::new(1);
1427    }
1428    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1429    pub struct Nmien_SPEC;
1430    pub type Nmien = crate::EnumBitfieldStruct<u8, Nmien_SPEC>;
1431    impl Nmien {
1432        #[doc = "NMI pin interrupt is disabled."]
1433        pub const _0: Self = Self::new(0);
1434
1435        #[doc = "NMI pin interrupt is enabled."]
1436        pub const _1: Self = Self::new(1);
1437    }
1438    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1439    pub struct Osten_SPEC;
1440    pub type Osten = crate::EnumBitfieldStruct<u8, Osten_SPEC>;
1441    impl Osten {
1442        #[doc = "Main Oscillation stop detection interrupt is disabled."]
1443        pub const _0: Self = Self::new(0);
1444
1445        #[doc = "Main Oscillation stop detection interrupt is enabled."]
1446        pub const _1: Self = Self::new(1);
1447    }
1448    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1449    pub struct Lvd2En_SPEC;
1450    pub type Lvd2En = crate::EnumBitfieldStruct<u8, Lvd2En_SPEC>;
1451    impl Lvd2En {
1452        #[doc = "Voltage-monitoring 2 interrupt is disabled."]
1453        pub const _0: Self = Self::new(0);
1454
1455        #[doc = "Voltage-monitoring 2 interrupt is enabled."]
1456        pub const _1: Self = Self::new(1);
1457    }
1458    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1459    pub struct Lvd1En_SPEC;
1460    pub type Lvd1En = crate::EnumBitfieldStruct<u8, Lvd1En_SPEC>;
1461    impl Lvd1En {
1462        #[doc = "Voltage-monitoring 1 interrupt is disabled."]
1463        pub const _0: Self = Self::new(0);
1464
1465        #[doc = "Voltage-monitoring 1 interrupt is enabled."]
1466        pub const _1: Self = Self::new(1);
1467    }
1468    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1469    pub struct Wdten_SPEC;
1470    pub type Wdten = crate::EnumBitfieldStruct<u8, Wdten_SPEC>;
1471    impl Wdten {
1472        #[doc = "WDT underflow/refresh error interrupt is disabled."]
1473        pub const _0: Self = Self::new(0);
1474
1475        #[doc = "WDT underflow/refresh error interrupt is enabled."]
1476        pub const _1: Self = Self::new(1);
1477    }
1478    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1479    pub struct Iwdten_SPEC;
1480    pub type Iwdten = crate::EnumBitfieldStruct<u8, Iwdten_SPEC>;
1481    impl Iwdten {
1482        #[doc = "IWDT underflow/refresh error interrupt is disabled."]
1483        pub const _0: Self = Self::new(0);
1484
1485        #[doc = "IWDT underflow/refresh error interrupt is enabled."]
1486        pub const _1: Self = Self::new(1);
1487    }
1488}
1489#[doc(hidden)]
1490#[derive(Copy, Clone, Eq, PartialEq)]
1491pub struct Nmiclr_SPEC;
1492impl crate::sealed::RegSpec for Nmiclr_SPEC {
1493    type DataType = u16;
1494}
1495
1496#[doc = "Non-Maskable Interrupt Status Clear Register"]
1497pub type Nmiclr = crate::RegValueT<Nmiclr_SPEC>;
1498
1499impl Nmiclr {
1500    #[doc = "CPU Stack Pointer Monitor Interrupt Clear"]
1501    #[inline(always)]
1502    pub fn speclr(
1503        self,
1504    ) -> crate::common::RegisterField<
1505        12,
1506        0x1,
1507        1,
1508        0,
1509        nmiclr::Speclr,
1510        nmiclr::Speclr,
1511        Nmiclr_SPEC,
1512        crate::common::W,
1513    > {
1514        crate::common::RegisterField::<
1515            12,
1516            0x1,
1517            1,
1518            0,
1519            nmiclr::Speclr,
1520            nmiclr::Speclr,
1521            Nmiclr_SPEC,
1522            crate::common::W,
1523        >::from_register(self, 0)
1524    }
1525
1526    #[doc = "MPU Bus Master Error Interrupt Clear"]
1527    #[inline(always)]
1528    pub fn busmclr(
1529        self,
1530    ) -> crate::common::RegisterField<
1531        11,
1532        0x1,
1533        1,
1534        0,
1535        nmiclr::Busmclr,
1536        nmiclr::Busmclr,
1537        Nmiclr_SPEC,
1538        crate::common::W,
1539    > {
1540        crate::common::RegisterField::<
1541            11,
1542            0x1,
1543            1,
1544            0,
1545            nmiclr::Busmclr,
1546            nmiclr::Busmclr,
1547            Nmiclr_SPEC,
1548            crate::common::W,
1549        >::from_register(self, 0)
1550    }
1551
1552    #[doc = "MPU Bus Slave Error Interrupt Clear"]
1553    #[inline(always)]
1554    pub fn bussclr(
1555        self,
1556    ) -> crate::common::RegisterField<
1557        10,
1558        0x1,
1559        1,
1560        0,
1561        nmiclr::Bussclr,
1562        nmiclr::Bussclr,
1563        Nmiclr_SPEC,
1564        crate::common::W,
1565    > {
1566        crate::common::RegisterField::<
1567            10,
1568            0x1,
1569            1,
1570            0,
1571            nmiclr::Bussclr,
1572            nmiclr::Bussclr,
1573            Nmiclr_SPEC,
1574            crate::common::W,
1575        >::from_register(self, 0)
1576    }
1577
1578    #[doc = "SRAM ECC Error Interrupt Clear"]
1579    #[inline(always)]
1580    pub fn reccclr(
1581        self,
1582    ) -> crate::common::RegisterField<
1583        9,
1584        0x1,
1585        1,
1586        0,
1587        nmiclr::Reccclr,
1588        nmiclr::Reccclr,
1589        Nmiclr_SPEC,
1590        crate::common::W,
1591    > {
1592        crate::common::RegisterField::<
1593            9,
1594            0x1,
1595            1,
1596            0,
1597            nmiclr::Reccclr,
1598            nmiclr::Reccclr,
1599            Nmiclr_SPEC,
1600            crate::common::W,
1601        >::from_register(self, 0)
1602    }
1603
1604    #[doc = "SRAM Parity Error Clear"]
1605    #[inline(always)]
1606    pub fn rpeclr(
1607        self,
1608    ) -> crate::common::RegisterField<
1609        8,
1610        0x1,
1611        1,
1612        0,
1613        nmiclr::Rpeclr,
1614        nmiclr::Rpeclr,
1615        Nmiclr_SPEC,
1616        crate::common::W,
1617    > {
1618        crate::common::RegisterField::<
1619            8,
1620            0x1,
1621            1,
1622            0,
1623            nmiclr::Rpeclr,
1624            nmiclr::Rpeclr,
1625            Nmiclr_SPEC,
1626            crate::common::W,
1627        >::from_register(self, 0)
1628    }
1629
1630    #[doc = "NMIST Clear"]
1631    #[inline(always)]
1632    pub fn nmiclr(
1633        self,
1634    ) -> crate::common::RegisterField<
1635        7,
1636        0x1,
1637        1,
1638        0,
1639        nmiclr::Nmiclr,
1640        nmiclr::Nmiclr,
1641        Nmiclr_SPEC,
1642        crate::common::W,
1643    > {
1644        crate::common::RegisterField::<
1645            7,
1646            0x1,
1647            1,
1648            0,
1649            nmiclr::Nmiclr,
1650            nmiclr::Nmiclr,
1651            Nmiclr_SPEC,
1652            crate::common::W,
1653        >::from_register(self, 0)
1654    }
1655
1656    #[doc = "OSTST Clear"]
1657    #[inline(always)]
1658    pub fn ostclr(
1659        self,
1660    ) -> crate::common::RegisterField<
1661        6,
1662        0x1,
1663        1,
1664        0,
1665        nmiclr::Ostclr,
1666        nmiclr::Ostclr,
1667        Nmiclr_SPEC,
1668        crate::common::W,
1669    > {
1670        crate::common::RegisterField::<
1671            6,
1672            0x1,
1673            1,
1674            0,
1675            nmiclr::Ostclr,
1676            nmiclr::Ostclr,
1677            Nmiclr_SPEC,
1678            crate::common::W,
1679        >::from_register(self, 0)
1680    }
1681
1682    #[doc = "These bits are read as 00. The write value should be 00."]
1683    #[inline(always)]
1684    pub fn reserved(
1685        self,
1686    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, Nmiclr_SPEC, crate::common::RW> {
1687        crate::common::RegisterField::<4,0x3,1,0,u8,u8,Nmiclr_SPEC,crate::common::RW>::from_register(self,0)
1688    }
1689
1690    #[doc = "LVD2ST Clear"]
1691    #[inline(always)]
1692    pub fn lvd2clr(
1693        self,
1694    ) -> crate::common::RegisterField<
1695        3,
1696        0x1,
1697        1,
1698        0,
1699        nmiclr::Lvd2Clr,
1700        nmiclr::Lvd2Clr,
1701        Nmiclr_SPEC,
1702        crate::common::W,
1703    > {
1704        crate::common::RegisterField::<
1705            3,
1706            0x1,
1707            1,
1708            0,
1709            nmiclr::Lvd2Clr,
1710            nmiclr::Lvd2Clr,
1711            Nmiclr_SPEC,
1712            crate::common::W,
1713        >::from_register(self, 0)
1714    }
1715
1716    #[doc = "LVD1ST Clear"]
1717    #[inline(always)]
1718    pub fn lvd1clr(
1719        self,
1720    ) -> crate::common::RegisterField<
1721        2,
1722        0x1,
1723        1,
1724        0,
1725        nmiclr::Lvd1Clr,
1726        nmiclr::Lvd1Clr,
1727        Nmiclr_SPEC,
1728        crate::common::W,
1729    > {
1730        crate::common::RegisterField::<
1731            2,
1732            0x1,
1733            1,
1734            0,
1735            nmiclr::Lvd1Clr,
1736            nmiclr::Lvd1Clr,
1737            Nmiclr_SPEC,
1738            crate::common::W,
1739        >::from_register(self, 0)
1740    }
1741
1742    #[doc = "WDTST Clear"]
1743    #[inline(always)]
1744    pub fn wdtclr(
1745        self,
1746    ) -> crate::common::RegisterField<
1747        1,
1748        0x1,
1749        1,
1750        0,
1751        nmiclr::Wdtclr,
1752        nmiclr::Wdtclr,
1753        Nmiclr_SPEC,
1754        crate::common::W,
1755    > {
1756        crate::common::RegisterField::<
1757            1,
1758            0x1,
1759            1,
1760            0,
1761            nmiclr::Wdtclr,
1762            nmiclr::Wdtclr,
1763            Nmiclr_SPEC,
1764            crate::common::W,
1765        >::from_register(self, 0)
1766    }
1767
1768    #[doc = "IWDTST Clear"]
1769    #[inline(always)]
1770    pub fn iwdtclr(
1771        self,
1772    ) -> crate::common::RegisterField<
1773        0,
1774        0x1,
1775        1,
1776        0,
1777        nmiclr::Iwdtclr,
1778        nmiclr::Iwdtclr,
1779        Nmiclr_SPEC,
1780        crate::common::W,
1781    > {
1782        crate::common::RegisterField::<
1783            0,
1784            0x1,
1785            1,
1786            0,
1787            nmiclr::Iwdtclr,
1788            nmiclr::Iwdtclr,
1789            Nmiclr_SPEC,
1790            crate::common::W,
1791        >::from_register(self, 0)
1792    }
1793}
1794impl ::core::default::Default for Nmiclr {
1795    #[inline(always)]
1796    fn default() -> Nmiclr {
1797        <crate::RegValueT<Nmiclr_SPEC> as RegisterValue<_>>::new(0)
1798    }
1799}
1800pub mod nmiclr {
1801
1802    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1803    pub struct Speclr_SPEC;
1804    pub type Speclr = crate::EnumBitfieldStruct<u8, Speclr_SPEC>;
1805    impl Speclr {
1806        #[doc = "No effect."]
1807        pub const _0: Self = Self::new(0);
1808
1809        #[doc = "Clear the NMISR.SPEST flag."]
1810        pub const _1: Self = Self::new(1);
1811    }
1812    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1813    pub struct Busmclr_SPEC;
1814    pub type Busmclr = crate::EnumBitfieldStruct<u8, Busmclr_SPEC>;
1815    impl Busmclr {
1816        #[doc = "No effect."]
1817        pub const _0: Self = Self::new(0);
1818
1819        #[doc = "Clear the NMISR.BUSMST flag."]
1820        pub const _1: Self = Self::new(1);
1821    }
1822    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1823    pub struct Bussclr_SPEC;
1824    pub type Bussclr = crate::EnumBitfieldStruct<u8, Bussclr_SPEC>;
1825    impl Bussclr {
1826        #[doc = "No effect."]
1827        pub const _0: Self = Self::new(0);
1828
1829        #[doc = "Clear the NMISR.BUSSST flag."]
1830        pub const _1: Self = Self::new(1);
1831    }
1832    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1833    pub struct Reccclr_SPEC;
1834    pub type Reccclr = crate::EnumBitfieldStruct<u8, Reccclr_SPEC>;
1835    impl Reccclr {
1836        #[doc = "No effect."]
1837        pub const _0: Self = Self::new(0);
1838
1839        #[doc = "Clear the NMISR.RECCST flag."]
1840        pub const _1: Self = Self::new(1);
1841    }
1842    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1843    pub struct Rpeclr_SPEC;
1844    pub type Rpeclr = crate::EnumBitfieldStruct<u8, Rpeclr_SPEC>;
1845    impl Rpeclr {
1846        #[doc = "No effect."]
1847        pub const _0: Self = Self::new(0);
1848
1849        #[doc = "Clear the NMISR.RPEST flag."]
1850        pub const _1: Self = Self::new(1);
1851    }
1852    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1853    pub struct Nmiclr_SPEC;
1854    pub type Nmiclr = crate::EnumBitfieldStruct<u8, Nmiclr_SPEC>;
1855    impl Nmiclr {
1856        #[doc = "No effect."]
1857        pub const _0: Self = Self::new(0);
1858
1859        #[doc = "Clear the NMISR.NMIST flag."]
1860        pub const _1: Self = Self::new(1);
1861    }
1862    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1863    pub struct Ostclr_SPEC;
1864    pub type Ostclr = crate::EnumBitfieldStruct<u8, Ostclr_SPEC>;
1865    impl Ostclr {
1866        #[doc = "No effect."]
1867        pub const _0: Self = Self::new(0);
1868
1869        #[doc = "Clear the NMISR.OSTST flag."]
1870        pub const _1: Self = Self::new(1);
1871    }
1872    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1873    pub struct Lvd2Clr_SPEC;
1874    pub type Lvd2Clr = crate::EnumBitfieldStruct<u8, Lvd2Clr_SPEC>;
1875    impl Lvd2Clr {
1876        #[doc = "No effect."]
1877        pub const _0: Self = Self::new(0);
1878
1879        #[doc = "Clear the NMISR.LVD2ST flag."]
1880        pub const _1: Self = Self::new(1);
1881    }
1882    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1883    pub struct Lvd1Clr_SPEC;
1884    pub type Lvd1Clr = crate::EnumBitfieldStruct<u8, Lvd1Clr_SPEC>;
1885    impl Lvd1Clr {
1886        #[doc = "No effect."]
1887        pub const _0: Self = Self::new(0);
1888
1889        #[doc = "Clear the NMISR.LVD1ST flag."]
1890        pub const _1: Self = Self::new(1);
1891    }
1892    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1893    pub struct Wdtclr_SPEC;
1894    pub type Wdtclr = crate::EnumBitfieldStruct<u8, Wdtclr_SPEC>;
1895    impl Wdtclr {
1896        #[doc = "No effect."]
1897        pub const _0: Self = Self::new(0);
1898
1899        #[doc = "Clear the NMISR.WDTST flag."]
1900        pub const _1: Self = Self::new(1);
1901    }
1902    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1903    pub struct Iwdtclr_SPEC;
1904    pub type Iwdtclr = crate::EnumBitfieldStruct<u8, Iwdtclr_SPEC>;
1905    impl Iwdtclr {
1906        #[doc = "No effect."]
1907        pub const _0: Self = Self::new(0);
1908
1909        #[doc = "Clear the NMISR.IWDTST flag."]
1910        pub const _1: Self = Self::new(1);
1911    }
1912}
1913#[doc(hidden)]
1914#[derive(Copy, Clone, Eq, PartialEq)]
1915pub struct Nmicr_SPEC;
1916impl crate::sealed::RegSpec for Nmicr_SPEC {
1917    type DataType = u8;
1918}
1919
1920#[doc = "NMI Pin Interrupt Control Register"]
1921pub type Nmicr = crate::RegValueT<Nmicr_SPEC>;
1922
1923impl Nmicr {
1924    #[doc = "NMI Digital Filter Enable"]
1925    #[inline(always)]
1926    pub fn nflten(
1927        self,
1928    ) -> crate::common::RegisterField<
1929        7,
1930        0x1,
1931        1,
1932        0,
1933        nmicr::Nflten,
1934        nmicr::Nflten,
1935        Nmicr_SPEC,
1936        crate::common::RW,
1937    > {
1938        crate::common::RegisterField::<
1939            7,
1940            0x1,
1941            1,
1942            0,
1943            nmicr::Nflten,
1944            nmicr::Nflten,
1945            Nmicr_SPEC,
1946            crate::common::RW,
1947        >::from_register(self, 0)
1948    }
1949
1950    #[doc = "NMI Digital Filter Sampling Clock Select"]
1951    #[inline(always)]
1952    pub fn nfclksel(
1953        self,
1954    ) -> crate::common::RegisterField<
1955        4,
1956        0x3,
1957        1,
1958        0,
1959        nmicr::Nfclksel,
1960        nmicr::Nfclksel,
1961        Nmicr_SPEC,
1962        crate::common::RW,
1963    > {
1964        crate::common::RegisterField::<
1965            4,
1966            0x3,
1967            1,
1968            0,
1969            nmicr::Nfclksel,
1970            nmicr::Nfclksel,
1971            Nmicr_SPEC,
1972            crate::common::RW,
1973        >::from_register(self, 0)
1974    }
1975
1976    #[doc = "These bits are read as 000. The write value should be 000."]
1977    #[inline(always)]
1978    pub fn reserved(
1979        self,
1980    ) -> crate::common::RegisterField<1, 0x7, 1, 0, u8, u8, Nmicr_SPEC, crate::common::RW> {
1981        crate::common::RegisterField::<1,0x7,1,0,u8,u8,Nmicr_SPEC,crate::common::RW>::from_register(self,0)
1982    }
1983
1984    #[doc = "NMI Detection Set"]
1985    #[inline(always)]
1986    pub fn nmimd(
1987        self,
1988    ) -> crate::common::RegisterField<
1989        0,
1990        0x1,
1991        1,
1992        0,
1993        nmicr::Nmimd,
1994        nmicr::Nmimd,
1995        Nmicr_SPEC,
1996        crate::common::RW,
1997    > {
1998        crate::common::RegisterField::<
1999            0,
2000            0x1,
2001            1,
2002            0,
2003            nmicr::Nmimd,
2004            nmicr::Nmimd,
2005            Nmicr_SPEC,
2006            crate::common::RW,
2007        >::from_register(self, 0)
2008    }
2009}
2010impl ::core::default::Default for Nmicr {
2011    #[inline(always)]
2012    fn default() -> Nmicr {
2013        <crate::RegValueT<Nmicr_SPEC> as RegisterValue<_>>::new(0)
2014    }
2015}
2016pub mod nmicr {
2017
2018    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2019    pub struct Nflten_SPEC;
2020    pub type Nflten = crate::EnumBitfieldStruct<u8, Nflten_SPEC>;
2021    impl Nflten {
2022        #[doc = "Digital filter is disabled."]
2023        pub const _0: Self = Self::new(0);
2024
2025        #[doc = "Digital filter is enabled."]
2026        pub const _1: Self = Self::new(1);
2027    }
2028    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2029    pub struct Nfclksel_SPEC;
2030    pub type Nfclksel = crate::EnumBitfieldStruct<u8, Nfclksel_SPEC>;
2031    impl Nfclksel {
2032        #[doc = "PCLKB"]
2033        pub const _00: Self = Self::new(0);
2034
2035        #[doc = "PCLKB/8"]
2036        pub const _01: Self = Self::new(1);
2037
2038        #[doc = "PCLKB/32"]
2039        pub const _10: Self = Self::new(2);
2040
2041        #[doc = "PCLKB/64"]
2042        pub const _11: Self = Self::new(3);
2043    }
2044    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2045    pub struct Nmimd_SPEC;
2046    pub type Nmimd = crate::EnumBitfieldStruct<u8, Nmimd_SPEC>;
2047    impl Nmimd {
2048        #[doc = "Falling edge"]
2049        pub const _0: Self = Self::new(0);
2050
2051        #[doc = "Rising edge"]
2052        pub const _1: Self = Self::new(1);
2053    }
2054}
2055#[doc(hidden)]
2056#[derive(Copy, Clone, Eq, PartialEq)]
2057pub struct Wupen_SPEC;
2058impl crate::sealed::RegSpec for Wupen_SPEC {
2059    type DataType = u32;
2060}
2061
2062#[doc = "Wake Up Interrupt Enable Register"]
2063pub type Wupen = crate::RegValueT<Wupen_SPEC>;
2064
2065impl Wupen {
2066    #[doc = "IIC0 address match interrupt S/W standby returns enable bit"]
2067    #[inline(always)]
2068    pub fn iic0wupen(
2069        self,
2070    ) -> crate::common::RegisterField<
2071        31,
2072        0x1,
2073        1,
2074        0,
2075        wupen::Iic0Wupen,
2076        wupen::Iic0Wupen,
2077        Wupen_SPEC,
2078        crate::common::RW,
2079    > {
2080        crate::common::RegisterField::<
2081            31,
2082            0x1,
2083            1,
2084            0,
2085            wupen::Iic0Wupen,
2086            wupen::Iic0Wupen,
2087            Wupen_SPEC,
2088            crate::common::RW,
2089        >::from_register(self, 0)
2090    }
2091
2092    #[doc = "AGT1 compare match B interrupt S/W standby returns enable bit"]
2093    #[inline(always)]
2094    pub fn agt1cbwupen(
2095        self,
2096    ) -> crate::common::RegisterField<
2097        30,
2098        0x1,
2099        1,
2100        0,
2101        wupen::Agt1Cbwupen,
2102        wupen::Agt1Cbwupen,
2103        Wupen_SPEC,
2104        crate::common::RW,
2105    > {
2106        crate::common::RegisterField::<
2107            30,
2108            0x1,
2109            1,
2110            0,
2111            wupen::Agt1Cbwupen,
2112            wupen::Agt1Cbwupen,
2113            Wupen_SPEC,
2114            crate::common::RW,
2115        >::from_register(self, 0)
2116    }
2117
2118    #[doc = "AGT1 compare match A interrupt S/W standby returns enable bit"]
2119    #[inline(always)]
2120    pub fn agt1cawupen(
2121        self,
2122    ) -> crate::common::RegisterField<
2123        29,
2124        0x1,
2125        1,
2126        0,
2127        wupen::Agt1Cawupen,
2128        wupen::Agt1Cawupen,
2129        Wupen_SPEC,
2130        crate::common::RW,
2131    > {
2132        crate::common::RegisterField::<
2133            29,
2134            0x1,
2135            1,
2136            0,
2137            wupen::Agt1Cawupen,
2138            wupen::Agt1Cawupen,
2139            Wupen_SPEC,
2140            crate::common::RW,
2141        >::from_register(self, 0)
2142    }
2143
2144    #[doc = "AGT1 underflow interrupt S/W standby returns enable bit"]
2145    #[inline(always)]
2146    pub fn agt1udwupen(
2147        self,
2148    ) -> crate::common::RegisterField<
2149        28,
2150        0x1,
2151        1,
2152        0,
2153        wupen::Agt1Udwupen,
2154        wupen::Agt1Udwupen,
2155        Wupen_SPEC,
2156        crate::common::RW,
2157    > {
2158        crate::common::RegisterField::<
2159            28,
2160            0x1,
2161            1,
2162            0,
2163            wupen::Agt1Udwupen,
2164            wupen::Agt1Udwupen,
2165            Wupen_SPEC,
2166            crate::common::RW,
2167        >::from_register(self, 0)
2168    }
2169
2170    #[doc = "USBFS interrupt S/W standby returns enable bit"]
2171    #[inline(always)]
2172    pub fn usbfswupen(
2173        self,
2174    ) -> crate::common::RegisterField<
2175        27,
2176        0x1,
2177        1,
2178        0,
2179        wupen::Usbfswupen,
2180        wupen::Usbfswupen,
2181        Wupen_SPEC,
2182        crate::common::RW,
2183    > {
2184        crate::common::RegisterField::<
2185            27,
2186            0x1,
2187            1,
2188            0,
2189            wupen::Usbfswupen,
2190            wupen::Usbfswupen,
2191            Wupen_SPEC,
2192            crate::common::RW,
2193        >::from_register(self, 0)
2194    }
2195
2196    #[doc = "RCT period interrupt S/W standby returns enable bit"]
2197    #[inline(always)]
2198    pub fn rtcprdwupen(
2199        self,
2200    ) -> crate::common::RegisterField<
2201        25,
2202        0x1,
2203        1,
2204        0,
2205        wupen::Rtcprdwupen,
2206        wupen::Rtcprdwupen,
2207        Wupen_SPEC,
2208        crate::common::RW,
2209    > {
2210        crate::common::RegisterField::<
2211            25,
2212            0x1,
2213            1,
2214            0,
2215            wupen::Rtcprdwupen,
2216            wupen::Rtcprdwupen,
2217            Wupen_SPEC,
2218            crate::common::RW,
2219        >::from_register(self, 0)
2220    }
2221
2222    #[doc = "RTC alarm interrupt S/W standby returns enable bit"]
2223    #[inline(always)]
2224    pub fn rtcalmwupen(
2225        self,
2226    ) -> crate::common::RegisterField<
2227        24,
2228        0x1,
2229        1,
2230        0,
2231        wupen::Rtcalmwupen,
2232        wupen::Rtcalmwupen,
2233        Wupen_SPEC,
2234        crate::common::RW,
2235    > {
2236        crate::common::RegisterField::<
2237            24,
2238            0x1,
2239            1,
2240            0,
2241            wupen::Rtcalmwupen,
2242            wupen::Rtcalmwupen,
2243            Wupen_SPEC,
2244            crate::common::RW,
2245        >::from_register(self, 0)
2246    }
2247
2248    #[doc = "ACMPLP0 interrupt S/W standby returns enable bit"]
2249    #[inline(always)]
2250    pub fn acmplp0wupen(
2251        self,
2252    ) -> crate::common::RegisterField<
2253        23,
2254        0x1,
2255        1,
2256        0,
2257        wupen::Acmplp0Wupen,
2258        wupen::Acmplp0Wupen,
2259        Wupen_SPEC,
2260        crate::common::RW,
2261    > {
2262        crate::common::RegisterField::<
2263            23,
2264            0x1,
2265            1,
2266            0,
2267            wupen::Acmplp0Wupen,
2268            wupen::Acmplp0Wupen,
2269            Wupen_SPEC,
2270            crate::common::RW,
2271        >::from_register(self, 0)
2272    }
2273
2274    #[doc = "LVD2 interrupt S/W standby returns enable bit"]
2275    #[inline(always)]
2276    pub fn lvd2wupen(
2277        self,
2278    ) -> crate::common::RegisterField<
2279        19,
2280        0x1,
2281        1,
2282        0,
2283        wupen::Lvd2Wupen,
2284        wupen::Lvd2Wupen,
2285        Wupen_SPEC,
2286        crate::common::RW,
2287    > {
2288        crate::common::RegisterField::<
2289            19,
2290            0x1,
2291            1,
2292            0,
2293            wupen::Lvd2Wupen,
2294            wupen::Lvd2Wupen,
2295            Wupen_SPEC,
2296            crate::common::RW,
2297        >::from_register(self, 0)
2298    }
2299
2300    #[doc = "LVD1 interrupt S/W standby returns enable bit"]
2301    #[inline(always)]
2302    pub fn lvd1wupen(
2303        self,
2304    ) -> crate::common::RegisterField<
2305        18,
2306        0x1,
2307        1,
2308        0,
2309        wupen::Lvd1Wupen,
2310        wupen::Lvd1Wupen,
2311        Wupen_SPEC,
2312        crate::common::RW,
2313    > {
2314        crate::common::RegisterField::<
2315            18,
2316            0x1,
2317            1,
2318            0,
2319            wupen::Lvd1Wupen,
2320            wupen::Lvd1Wupen,
2321            Wupen_SPEC,
2322            crate::common::RW,
2323        >::from_register(self, 0)
2324    }
2325
2326    #[doc = "Key interrupt S/W standby returns enable bit"]
2327    #[inline(always)]
2328    pub fn keywupen(
2329        self,
2330    ) -> crate::common::RegisterField<
2331        17,
2332        0x1,
2333        1,
2334        0,
2335        wupen::Keywupen,
2336        wupen::Keywupen,
2337        Wupen_SPEC,
2338        crate::common::RW,
2339    > {
2340        crate::common::RegisterField::<
2341            17,
2342            0x1,
2343            1,
2344            0,
2345            wupen::Keywupen,
2346            wupen::Keywupen,
2347            Wupen_SPEC,
2348            crate::common::RW,
2349        >::from_register(self, 0)
2350    }
2351
2352    #[doc = "IWDT interrupt S/W standby returns enable bit"]
2353    #[inline(always)]
2354    pub fn iwdtwupen(
2355        self,
2356    ) -> crate::common::RegisterField<
2357        16,
2358        0x1,
2359        1,
2360        0,
2361        wupen::Iwdtwupen,
2362        wupen::Iwdtwupen,
2363        Wupen_SPEC,
2364        crate::common::RW,
2365    > {
2366        crate::common::RegisterField::<
2367            16,
2368            0x1,
2369            1,
2370            0,
2371            wupen::Iwdtwupen,
2372            wupen::Iwdtwupen,
2373            Wupen_SPEC,
2374            crate::common::RW,
2375        >::from_register(self, 0)
2376    }
2377
2378    #[doc = "These bits are read as 00000000. The write value should be 00000000."]
2379    #[inline(always)]
2380    pub fn reserved(
2381        self,
2382    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Wupen_SPEC, crate::common::RW> {
2383        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Wupen_SPEC,crate::common::RW>::from_register(self,0)
2384    }
2385
2386    #[doc = "IRQ7 interrupt S/W standby returns enable bit"]
2387    #[inline(always)]
2388    pub fn irqwupen7(
2389        self,
2390    ) -> crate::common::RegisterField<
2391        7,
2392        0x1,
2393        1,
2394        0,
2395        wupen::Irqwupen7,
2396        wupen::Irqwupen7,
2397        Wupen_SPEC,
2398        crate::common::RW,
2399    > {
2400        crate::common::RegisterField::<
2401            7,
2402            0x1,
2403            1,
2404            0,
2405            wupen::Irqwupen7,
2406            wupen::Irqwupen7,
2407            Wupen_SPEC,
2408            crate::common::RW,
2409        >::from_register(self, 0)
2410    }
2411
2412    #[doc = "IRQ6 interrupt S/W standby returns enable bit"]
2413    #[inline(always)]
2414    pub fn irqwupen6(
2415        self,
2416    ) -> crate::common::RegisterField<
2417        6,
2418        0x1,
2419        1,
2420        0,
2421        wupen::Irqwupen6,
2422        wupen::Irqwupen6,
2423        Wupen_SPEC,
2424        crate::common::RW,
2425    > {
2426        crate::common::RegisterField::<
2427            6,
2428            0x1,
2429            1,
2430            0,
2431            wupen::Irqwupen6,
2432            wupen::Irqwupen6,
2433            Wupen_SPEC,
2434            crate::common::RW,
2435        >::from_register(self, 0)
2436    }
2437
2438    #[doc = "IRQ5 interrupt S/W standby returns enable bit"]
2439    #[inline(always)]
2440    pub fn irqwupen5(
2441        self,
2442    ) -> crate::common::RegisterField<
2443        5,
2444        0x1,
2445        1,
2446        0,
2447        wupen::Irqwupen5,
2448        wupen::Irqwupen5,
2449        Wupen_SPEC,
2450        crate::common::RW,
2451    > {
2452        crate::common::RegisterField::<
2453            5,
2454            0x1,
2455            1,
2456            0,
2457            wupen::Irqwupen5,
2458            wupen::Irqwupen5,
2459            Wupen_SPEC,
2460            crate::common::RW,
2461        >::from_register(self, 0)
2462    }
2463
2464    #[doc = "IRQ4 interrupt S/W standby returns enable bit"]
2465    #[inline(always)]
2466    pub fn irqwupen4(
2467        self,
2468    ) -> crate::common::RegisterField<
2469        4,
2470        0x1,
2471        1,
2472        0,
2473        wupen::Irqwupen4,
2474        wupen::Irqwupen4,
2475        Wupen_SPEC,
2476        crate::common::RW,
2477    > {
2478        crate::common::RegisterField::<
2479            4,
2480            0x1,
2481            1,
2482            0,
2483            wupen::Irqwupen4,
2484            wupen::Irqwupen4,
2485            Wupen_SPEC,
2486            crate::common::RW,
2487        >::from_register(self, 0)
2488    }
2489
2490    #[doc = "IRQ3 interrupt S/W standby returns enable bit"]
2491    #[inline(always)]
2492    pub fn irqwupen3(
2493        self,
2494    ) -> crate::common::RegisterField<
2495        3,
2496        0x1,
2497        1,
2498        0,
2499        wupen::Irqwupen3,
2500        wupen::Irqwupen3,
2501        Wupen_SPEC,
2502        crate::common::RW,
2503    > {
2504        crate::common::RegisterField::<
2505            3,
2506            0x1,
2507            1,
2508            0,
2509            wupen::Irqwupen3,
2510            wupen::Irqwupen3,
2511            Wupen_SPEC,
2512            crate::common::RW,
2513        >::from_register(self, 0)
2514    }
2515
2516    #[doc = "IRQ2 interrupt S/W standby returns enable bit"]
2517    #[inline(always)]
2518    pub fn irqwupen2(
2519        self,
2520    ) -> crate::common::RegisterField<
2521        2,
2522        0x1,
2523        1,
2524        0,
2525        wupen::Irqwupen2,
2526        wupen::Irqwupen2,
2527        Wupen_SPEC,
2528        crate::common::RW,
2529    > {
2530        crate::common::RegisterField::<
2531            2,
2532            0x1,
2533            1,
2534            0,
2535            wupen::Irqwupen2,
2536            wupen::Irqwupen2,
2537            Wupen_SPEC,
2538            crate::common::RW,
2539        >::from_register(self, 0)
2540    }
2541
2542    #[doc = "IRQ1 interrupt S/W standby returns enable bit"]
2543    #[inline(always)]
2544    pub fn irqwupen1(
2545        self,
2546    ) -> crate::common::RegisterField<
2547        1,
2548        0x1,
2549        1,
2550        0,
2551        wupen::Irqwupen1,
2552        wupen::Irqwupen1,
2553        Wupen_SPEC,
2554        crate::common::RW,
2555    > {
2556        crate::common::RegisterField::<
2557            1,
2558            0x1,
2559            1,
2560            0,
2561            wupen::Irqwupen1,
2562            wupen::Irqwupen1,
2563            Wupen_SPEC,
2564            crate::common::RW,
2565        >::from_register(self, 0)
2566    }
2567
2568    #[doc = "IRQ0 interrupt S/W standby returns enable bit"]
2569    #[inline(always)]
2570    pub fn irqwupen0(
2571        self,
2572    ) -> crate::common::RegisterField<
2573        0,
2574        0x1,
2575        1,
2576        0,
2577        wupen::Irqwupen0,
2578        wupen::Irqwupen0,
2579        Wupen_SPEC,
2580        crate::common::RW,
2581    > {
2582        crate::common::RegisterField::<
2583            0,
2584            0x1,
2585            1,
2586            0,
2587            wupen::Irqwupen0,
2588            wupen::Irqwupen0,
2589            Wupen_SPEC,
2590            crate::common::RW,
2591        >::from_register(self, 0)
2592    }
2593}
2594impl ::core::default::Default for Wupen {
2595    #[inline(always)]
2596    fn default() -> Wupen {
2597        <crate::RegValueT<Wupen_SPEC> as RegisterValue<_>>::new(0)
2598    }
2599}
2600pub mod wupen {
2601
2602    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2603    pub struct Iic0Wupen_SPEC;
2604    pub type Iic0Wupen = crate::EnumBitfieldStruct<u8, Iic0Wupen_SPEC>;
2605    impl Iic0Wupen {
2606        #[doc = "S/W standby returns by IIC0 address match interrupt is disabled"]
2607        pub const _0: Self = Self::new(0);
2608
2609        #[doc = "S/W standby returns by IIC0 address match interrupt is enabled"]
2610        pub const _1: Self = Self::new(1);
2611    }
2612    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2613    pub struct Agt1Cbwupen_SPEC;
2614    pub type Agt1Cbwupen = crate::EnumBitfieldStruct<u8, Agt1Cbwupen_SPEC>;
2615    impl Agt1Cbwupen {
2616        #[doc = "S/W standby returns by AGT1 compare match B interrupt is disabled"]
2617        pub const _0: Self = Self::new(0);
2618
2619        #[doc = "S/W standby returns by AGT1 compare match B interrupt is enabled"]
2620        pub const _1: Self = Self::new(1);
2621    }
2622    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2623    pub struct Agt1Cawupen_SPEC;
2624    pub type Agt1Cawupen = crate::EnumBitfieldStruct<u8, Agt1Cawupen_SPEC>;
2625    impl Agt1Cawupen {
2626        #[doc = "S/W standby returns by AGT1 compare match A interrupt is disabled"]
2627        pub const _0: Self = Self::new(0);
2628
2629        #[doc = "S/W standby returns by AGT1 compare match A interrupt is enabled"]
2630        pub const _1: Self = Self::new(1);
2631    }
2632    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2633    pub struct Agt1Udwupen_SPEC;
2634    pub type Agt1Udwupen = crate::EnumBitfieldStruct<u8, Agt1Udwupen_SPEC>;
2635    impl Agt1Udwupen {
2636        #[doc = "S/W standby returns by AGT1 underflow interrupt is disabled"]
2637        pub const _0: Self = Self::new(0);
2638
2639        #[doc = "S/W standby returns by AGT1 underflow interrupt is enabled"]
2640        pub const _1: Self = Self::new(1);
2641    }
2642    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2643    pub struct Usbfswupen_SPEC;
2644    pub type Usbfswupen = crate::EnumBitfieldStruct<u8, Usbfswupen_SPEC>;
2645    impl Usbfswupen {
2646        #[doc = "S/W standby returns by USBFS interrupt is disabled"]
2647        pub const _0: Self = Self::new(0);
2648
2649        #[doc = "S/W standby returns by USBFS interrupt is enabled"]
2650        pub const _1: Self = Self::new(1);
2651    }
2652    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2653    pub struct Rtcprdwupen_SPEC;
2654    pub type Rtcprdwupen = crate::EnumBitfieldStruct<u8, Rtcprdwupen_SPEC>;
2655    impl Rtcprdwupen {
2656        #[doc = "S/W standby returns by RTC period interrupt is disabled"]
2657        pub const _0: Self = Self::new(0);
2658
2659        #[doc = "S/W standby returns by RTC period interrupt is enabled"]
2660        pub const _1: Self = Self::new(1);
2661    }
2662    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2663    pub struct Rtcalmwupen_SPEC;
2664    pub type Rtcalmwupen = crate::EnumBitfieldStruct<u8, Rtcalmwupen_SPEC>;
2665    impl Rtcalmwupen {
2666        #[doc = "S/W standby returns by RTC alarm interrupt is disabled"]
2667        pub const _0: Self = Self::new(0);
2668
2669        #[doc = "S/W standby returns by RTC alarm interrupt is enabled"]
2670        pub const _1: Self = Self::new(1);
2671    }
2672    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2673    pub struct Acmplp0Wupen_SPEC;
2674    pub type Acmplp0Wupen = crate::EnumBitfieldStruct<u8, Acmplp0Wupen_SPEC>;
2675    impl Acmplp0Wupen {
2676        #[doc = "S/W standby returns by ACMPLP0 interrupt is disabled"]
2677        pub const _0: Self = Self::new(0);
2678
2679        #[doc = "S/W standby returns by ACMPLP0 interrupt is enabled"]
2680        pub const _1: Self = Self::new(1);
2681    }
2682    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2683    pub struct Lvd2Wupen_SPEC;
2684    pub type Lvd2Wupen = crate::EnumBitfieldStruct<u8, Lvd2Wupen_SPEC>;
2685    impl Lvd2Wupen {
2686        #[doc = "S/W standby returns by LVD2 interrupt is disabled"]
2687        pub const _0: Self = Self::new(0);
2688
2689        #[doc = "S/W standby returns by LVD2 interrupt is enabled"]
2690        pub const _1: Self = Self::new(1);
2691    }
2692    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2693    pub struct Lvd1Wupen_SPEC;
2694    pub type Lvd1Wupen = crate::EnumBitfieldStruct<u8, Lvd1Wupen_SPEC>;
2695    impl Lvd1Wupen {
2696        #[doc = "S/W standby returns by LVD1 interrupt is disabled"]
2697        pub const _0: Self = Self::new(0);
2698
2699        #[doc = "S/W standby returns by LVD1 interrupt is enabled"]
2700        pub const _1: Self = Self::new(1);
2701    }
2702    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2703    pub struct Keywupen_SPEC;
2704    pub type Keywupen = crate::EnumBitfieldStruct<u8, Keywupen_SPEC>;
2705    impl Keywupen {
2706        #[doc = "S/W standby returns by KEY interrupt is disabled"]
2707        pub const _0: Self = Self::new(0);
2708
2709        #[doc = "S/W standby returns by KEY interrupt is enabled"]
2710        pub const _1: Self = Self::new(1);
2711    }
2712    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2713    pub struct Iwdtwupen_SPEC;
2714    pub type Iwdtwupen = crate::EnumBitfieldStruct<u8, Iwdtwupen_SPEC>;
2715    impl Iwdtwupen {
2716        #[doc = "S/W standby returns by IWDT interrupt is disabled"]
2717        pub const _0: Self = Self::new(0);
2718
2719        #[doc = "S/W standby returns by IWDT interrupt is enabled"]
2720        pub const _1: Self = Self::new(1);
2721    }
2722    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2723    pub struct Irqwupen7_SPEC;
2724    pub type Irqwupen7 = crate::EnumBitfieldStruct<u8, Irqwupen7_SPEC>;
2725    impl Irqwupen7 {
2726        #[doc = "S/W standby returns by IRQ7 interrupt is disabled"]
2727        pub const _0: Self = Self::new(0);
2728
2729        #[doc = "S/W standby returns by IRQ7 interrupt is enabled"]
2730        pub const _1: Self = Self::new(1);
2731    }
2732    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2733    pub struct Irqwupen6_SPEC;
2734    pub type Irqwupen6 = crate::EnumBitfieldStruct<u8, Irqwupen6_SPEC>;
2735    impl Irqwupen6 {
2736        #[doc = "S/W standby returns by IRQ6 interrupt is disabled"]
2737        pub const _0: Self = Self::new(0);
2738
2739        #[doc = "S/W standby returns by IRQ6 interrupt is enabled"]
2740        pub const _1: Self = Self::new(1);
2741    }
2742    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2743    pub struct Irqwupen5_SPEC;
2744    pub type Irqwupen5 = crate::EnumBitfieldStruct<u8, Irqwupen5_SPEC>;
2745    impl Irqwupen5 {
2746        #[doc = "S/W standby returns by IRQ5 interrupt is disabled"]
2747        pub const _0: Self = Self::new(0);
2748
2749        #[doc = "S/W standby returns by IRQ5 interrupt is enabled"]
2750        pub const _1: Self = Self::new(1);
2751    }
2752    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2753    pub struct Irqwupen4_SPEC;
2754    pub type Irqwupen4 = crate::EnumBitfieldStruct<u8, Irqwupen4_SPEC>;
2755    impl Irqwupen4 {
2756        #[doc = "S/W standby returns by IRQ4 interrupt is disabled"]
2757        pub const _0: Self = Self::new(0);
2758
2759        #[doc = "S/W standby returns by IRQ4 interrupt is enabled"]
2760        pub const _1: Self = Self::new(1);
2761    }
2762    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2763    pub struct Irqwupen3_SPEC;
2764    pub type Irqwupen3 = crate::EnumBitfieldStruct<u8, Irqwupen3_SPEC>;
2765    impl Irqwupen3 {
2766        #[doc = "S/W standby returns by IRQ3 interrupt is disabled"]
2767        pub const _0: Self = Self::new(0);
2768
2769        #[doc = "S/W standby returns by IRQ3 interrupt is enabled"]
2770        pub const _1: Self = Self::new(1);
2771    }
2772    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2773    pub struct Irqwupen2_SPEC;
2774    pub type Irqwupen2 = crate::EnumBitfieldStruct<u8, Irqwupen2_SPEC>;
2775    impl Irqwupen2 {
2776        #[doc = "S/W standby returns by IRQ2 interrupt is disabled"]
2777        pub const _0: Self = Self::new(0);
2778
2779        #[doc = "S/W standby returns by IRQ2 interrupt is enabled"]
2780        pub const _1: Self = Self::new(1);
2781    }
2782    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2783    pub struct Irqwupen1_SPEC;
2784    pub type Irqwupen1 = crate::EnumBitfieldStruct<u8, Irqwupen1_SPEC>;
2785    impl Irqwupen1 {
2786        #[doc = "S/W standby returns by IRQ1 interrupt is disabled"]
2787        pub const _0: Self = Self::new(0);
2788
2789        #[doc = "S/W standby returns by IRQ1 interrupt is enabled"]
2790        pub const _1: Self = Self::new(1);
2791    }
2792    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2793    pub struct Irqwupen0_SPEC;
2794    pub type Irqwupen0 = crate::EnumBitfieldStruct<u8, Irqwupen0_SPEC>;
2795    impl Irqwupen0 {
2796        #[doc = "S/W standby returns by IRQ0 interrupt is disabled"]
2797        pub const _0: Self = Self::new(0);
2798
2799        #[doc = "S/W standby returns by IRQ0 interrupt is enabled"]
2800        pub const _1: Self = Self::new(1);
2801    }
2802}
2803#[doc(hidden)]
2804#[derive(Copy, Clone, Eq, PartialEq)]
2805pub struct Selsr0_SPEC;
2806impl crate::sealed::RegSpec for Selsr0_SPEC {
2807    type DataType = u16;
2808}
2809
2810#[doc = "SYS Event Link Setting Register"]
2811pub type Selsr0 = crate::RegValueT<Selsr0_SPEC>;
2812
2813impl Selsr0 {
2814    #[doc = "These bits are read as 00000000. The write value should be 00000000."]
2815    #[inline(always)]
2816    pub fn reserved(
2817        self,
2818    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Selsr0_SPEC, crate::common::RW> {
2819        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Selsr0_SPEC,crate::common::RW>::from_register(self,0)
2820    }
2821
2822    #[doc = "SYS Event Link Select"]
2823    #[inline(always)]
2824    pub fn sels(
2825        self,
2826    ) -> crate::common::RegisterField<
2827        0,
2828        0xff,
2829        1,
2830        0,
2831        selsr0::Sels,
2832        selsr0::Sels,
2833        Selsr0_SPEC,
2834        crate::common::RW,
2835    > {
2836        crate::common::RegisterField::<
2837            0,
2838            0xff,
2839            1,
2840            0,
2841            selsr0::Sels,
2842            selsr0::Sels,
2843            Selsr0_SPEC,
2844            crate::common::RW,
2845        >::from_register(self, 0)
2846    }
2847}
2848impl ::core::default::Default for Selsr0 {
2849    #[inline(always)]
2850    fn default() -> Selsr0 {
2851        <crate::RegValueT<Selsr0_SPEC> as RegisterValue<_>>::new(0)
2852    }
2853}
2854pub mod selsr0 {
2855
2856    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2857    pub struct Sels_SPEC;
2858    pub type Sels = crate::EnumBitfieldStruct<u8, Sels_SPEC>;
2859    impl Sels {
2860        #[doc = "Disable event output to the associated low-power mode module"]
2861        pub const _0_X_00: Self = Self::new(0);
2862    }
2863}
2864#[doc(hidden)]
2865#[derive(Copy, Clone, Eq, PartialEq)]
2866pub struct Ielsr_SPEC;
2867impl crate::sealed::RegSpec for Ielsr_SPEC {
2868    type DataType = u32;
2869}
2870
2871#[doc = "ICU Event Link Setting Register %s"]
2872pub type Ielsr = crate::RegValueT<Ielsr_SPEC>;
2873
2874impl Ielsr {
2875    #[doc = "DTC Activation Enable"]
2876    #[inline(always)]
2877    pub fn dtce(
2878        self,
2879    ) -> crate::common::RegisterField<
2880        24,
2881        0x1,
2882        1,
2883        0,
2884        ielsr::Dtce,
2885        ielsr::Dtce,
2886        Ielsr_SPEC,
2887        crate::common::RW,
2888    > {
2889        crate::common::RegisterField::<
2890            24,
2891            0x1,
2892            1,
2893            0,
2894            ielsr::Dtce,
2895            ielsr::Dtce,
2896            Ielsr_SPEC,
2897            crate::common::RW,
2898        >::from_register(self, 0)
2899    }
2900
2901    #[doc = "Interrupt Status Flag"]
2902    #[inline(always)]
2903    pub fn ir(
2904        self,
2905    ) -> crate::common::RegisterField<
2906        16,
2907        0x1,
2908        1,
2909        0,
2910        ielsr::Ir,
2911        ielsr::Ir,
2912        Ielsr_SPEC,
2913        crate::common::RW,
2914    > {
2915        crate::common::RegisterField::<
2916            16,
2917            0x1,
2918            1,
2919            0,
2920            ielsr::Ir,
2921            ielsr::Ir,
2922            Ielsr_SPEC,
2923            crate::common::RW,
2924        >::from_register(self, 0)
2925    }
2926
2927    #[doc = "These bits are read as 00000000. The write value should be 00000000."]
2928    #[inline(always)]
2929    pub fn reserved(
2930        self,
2931    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Ielsr_SPEC, crate::common::RW> {
2932        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Ielsr_SPEC,crate::common::RW>::from_register(self,0)
2933    }
2934
2935    #[doc = "ICU Event selection to NVICSet the number for the event signal to be linked ."]
2936    #[inline(always)]
2937    pub fn iels(
2938        self,
2939    ) -> crate::common::RegisterField<
2940        0,
2941        0xff,
2942        1,
2943        0,
2944        ielsr::Iels,
2945        ielsr::Iels,
2946        Ielsr_SPEC,
2947        crate::common::RW,
2948    > {
2949        crate::common::RegisterField::<
2950            0,
2951            0xff,
2952            1,
2953            0,
2954            ielsr::Iels,
2955            ielsr::Iels,
2956            Ielsr_SPEC,
2957            crate::common::RW,
2958        >::from_register(self, 0)
2959    }
2960}
2961impl ::core::default::Default for Ielsr {
2962    #[inline(always)]
2963    fn default() -> Ielsr {
2964        <crate::RegValueT<Ielsr_SPEC> as RegisterValue<_>>::new(0)
2965    }
2966}
2967pub mod ielsr {
2968
2969    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2970    pub struct Dtce_SPEC;
2971    pub type Dtce = crate::EnumBitfieldStruct<u8, Dtce_SPEC>;
2972    impl Dtce {
2973        #[doc = "DTC activation is disabled"]
2974        pub const _0: Self = Self::new(0);
2975
2976        #[doc = "DTC activation is enabled"]
2977        pub const _1: Self = Self::new(1);
2978    }
2979    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2980    pub struct Ir_SPEC;
2981    pub type Ir = crate::EnumBitfieldStruct<u8, Ir_SPEC>;
2982    impl Ir {
2983        #[doc = "No interrupt request is generated"]
2984        pub const _0: Self = Self::new(0);
2985
2986        #[doc = "An interrupt request is generated ( \"1\" write to the IR bit is prohibited. )"]
2987        pub const _1: Self = Self::new(1);
2988    }
2989    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2990    pub struct Iels_SPEC;
2991    pub type Iels = crate::EnumBitfieldStruct<u8, Iels_SPEC>;
2992    impl Iels {
2993        #[doc = "Nothing is selected"]
2994        pub const _0_X_000: Self = Self::new(0);
2995    }
2996}