1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"12-bit D/A converter"]
28unsafe impl ::core::marker::Send for super::Dac12 {}
29unsafe impl ::core::marker::Sync for super::Dac12 {}
30impl super::Dac12 {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "D/A Data Register 0"]
38 #[inline(always)]
39 pub const fn dadr0(&self) -> &'static crate::common::Reg<self::Dadr0_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Dadr0_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(0usize),
43 )
44 }
45 }
46
47 #[doc = "D/A Control Register"]
48 #[inline(always)]
49 pub const fn dacr(&self) -> &'static crate::common::Reg<self::Dacr_SPEC, crate::common::RW> {
50 unsafe {
51 crate::common::Reg::<self::Dacr_SPEC, crate::common::RW>::from_ptr(
52 self._svd2pac_as_ptr().add(4usize),
53 )
54 }
55 }
56
57 #[doc = "DADR0 Format Select Register"]
58 #[inline(always)]
59 pub const fn dadpr(&self) -> &'static crate::common::Reg<self::Dadpr_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Dadpr_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(5usize),
63 )
64 }
65 }
66
67 #[doc = "D/A-A/D Synchronous Start Control Register"]
68 #[inline(always)]
69 pub const fn daadscr(
70 &self,
71 ) -> &'static crate::common::Reg<self::Daadscr_SPEC, crate::common::RW> {
72 unsafe {
73 crate::common::Reg::<self::Daadscr_SPEC, crate::common::RW>::from_ptr(
74 self._svd2pac_as_ptr().add(6usize),
75 )
76 }
77 }
78
79 #[doc = "D/A VREF Control Register"]
80 #[inline(always)]
81 pub const fn davrefcr(
82 &self,
83 ) -> &'static crate::common::Reg<self::Davrefcr_SPEC, crate::common::RW> {
84 unsafe {
85 crate::common::Reg::<self::Davrefcr_SPEC, crate::common::RW>::from_ptr(
86 self._svd2pac_as_ptr().add(7usize),
87 )
88 }
89 }
90
91 #[doc = "D/A Switch Charge Pump Control Register"]
92 #[inline(always)]
93 pub const fn dapc(&self) -> &'static crate::common::Reg<self::Dapc_SPEC, crate::common::RW> {
94 unsafe {
95 crate::common::Reg::<self::Dapc_SPEC, crate::common::RW>::from_ptr(
96 self._svd2pac_as_ptr().add(9usize),
97 )
98 }
99 }
100}
101#[doc(hidden)]
102#[derive(Copy, Clone, Eq, PartialEq)]
103pub struct Dadr0_SPEC;
104impl crate::sealed::RegSpec for Dadr0_SPEC {
105 type DataType = u16;
106}
107
108#[doc = "D/A Data Register 0"]
109pub type Dadr0 = crate::RegValueT<Dadr0_SPEC>;
110
111impl Dadr0 {
112 #[doc = "D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format."]
113 #[inline(always)]
114 pub fn dadr(
115 self,
116 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Dadr0_SPEC, crate::common::RW>
117 {
118 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Dadr0_SPEC,crate::common::RW>::from_register(self,0)
119 }
120}
121impl ::core::default::Default for Dadr0 {
122 #[inline(always)]
123 fn default() -> Dadr0 {
124 <crate::RegValueT<Dadr0_SPEC> as RegisterValue<_>>::new(0)
125 }
126}
127
128#[doc(hidden)]
129#[derive(Copy, Clone, Eq, PartialEq)]
130pub struct Dacr_SPEC;
131impl crate::sealed::RegSpec for Dacr_SPEC {
132 type DataType = u8;
133}
134
135#[doc = "D/A Control Register"]
136pub type Dacr = crate::RegValueT<Dacr_SPEC>;
137
138impl Dacr {
139 #[doc = "D/A Output Enable 0"]
140 #[inline(always)]
141 pub fn daoe0(
142 self,
143 ) -> crate::common::RegisterField<
144 6,
145 0x1,
146 1,
147 0,
148 dacr::Daoe0,
149 dacr::Daoe0,
150 Dacr_SPEC,
151 crate::common::RW,
152 > {
153 crate::common::RegisterField::<
154 6,
155 0x1,
156 1,
157 0,
158 dacr::Daoe0,
159 dacr::Daoe0,
160 Dacr_SPEC,
161 crate::common::RW,
162 >::from_register(self, 0)
163 }
164
165 #[doc = "These bits are read as 11111. The write value should be 11111."]
166 #[inline(always)]
167 pub fn reserved(
168 self,
169 ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Dacr_SPEC, crate::common::RW> {
170 crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Dacr_SPEC,crate::common::RW>::from_register(self,0)
171 }
172}
173impl ::core::default::Default for Dacr {
174 #[inline(always)]
175 fn default() -> Dacr {
176 <crate::RegValueT<Dacr_SPEC> as RegisterValue<_>>::new(31)
177 }
178}
179pub mod dacr {
180
181 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
182 pub struct Daoe0_SPEC;
183 pub type Daoe0 = crate::EnumBitfieldStruct<u8, Daoe0_SPEC>;
184 impl Daoe0 {
185 #[doc = "Analog output of channel 0 (DA0) is disabled."]
186 pub const _0: Self = Self::new(0);
187
188 #[doc = "D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled."]
189 pub const _1: Self = Self::new(1);
190 }
191}
192#[doc(hidden)]
193#[derive(Copy, Clone, Eq, PartialEq)]
194pub struct Dadpr_SPEC;
195impl crate::sealed::RegSpec for Dadpr_SPEC {
196 type DataType = u8;
197}
198
199#[doc = "DADR0 Format Select Register"]
200pub type Dadpr = crate::RegValueT<Dadpr_SPEC>;
201
202impl Dadpr {
203 #[doc = "DADRm Format Select"]
204 #[inline(always)]
205 pub fn dpsel(
206 self,
207 ) -> crate::common::RegisterField<
208 7,
209 0x1,
210 1,
211 0,
212 dadpr::Dpsel,
213 dadpr::Dpsel,
214 Dadpr_SPEC,
215 crate::common::RW,
216 > {
217 crate::common::RegisterField::<
218 7,
219 0x1,
220 1,
221 0,
222 dadpr::Dpsel,
223 dadpr::Dpsel,
224 Dadpr_SPEC,
225 crate::common::RW,
226 >::from_register(self, 0)
227 }
228
229 #[doc = "These bits are read as 0000000. The write value should be 0000000."]
230 #[inline(always)]
231 pub fn reserved(
232 self,
233 ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Dadpr_SPEC, crate::common::RW> {
234 crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Dadpr_SPEC,crate::common::RW>::from_register(self,0)
235 }
236}
237impl ::core::default::Default for Dadpr {
238 #[inline(always)]
239 fn default() -> Dadpr {
240 <crate::RegValueT<Dadpr_SPEC> as RegisterValue<_>>::new(0)
241 }
242}
243pub mod dadpr {
244
245 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
246 pub struct Dpsel_SPEC;
247 pub type Dpsel = crate::EnumBitfieldStruct<u8, Dpsel_SPEC>;
248 impl Dpsel {
249 #[doc = "Right justified format."]
250 pub const _0: Self = Self::new(0);
251
252 #[doc = "Left justified format."]
253 pub const _1: Self = Self::new(1);
254 }
255}
256#[doc(hidden)]
257#[derive(Copy, Clone, Eq, PartialEq)]
258pub struct Daadscr_SPEC;
259impl crate::sealed::RegSpec for Daadscr_SPEC {
260 type DataType = u8;
261}
262
263#[doc = "D/A-A/D Synchronous Start Control Register"]
264pub type Daadscr = crate::RegValueT<Daadscr_SPEC>;
265
266impl Daadscr {
267 #[doc = "D/A-A/D Synchronous Conversion"]
268 #[inline(always)]
269 pub fn daadst(
270 self,
271 ) -> crate::common::RegisterField<
272 7,
273 0x1,
274 1,
275 0,
276 daadscr::Daadst,
277 daadscr::Daadst,
278 Daadscr_SPEC,
279 crate::common::RW,
280 > {
281 crate::common::RegisterField::<
282 7,
283 0x1,
284 1,
285 0,
286 daadscr::Daadst,
287 daadscr::Daadst,
288 Daadscr_SPEC,
289 crate::common::RW,
290 >::from_register(self, 0)
291 }
292
293 #[doc = "These bits are read as 0000000. The write value should be 0000000."]
294 #[inline(always)]
295 pub fn reserved(
296 self,
297 ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Daadscr_SPEC, crate::common::RW> {
298 crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Daadscr_SPEC,crate::common::RW>::from_register(self,0)
299 }
300}
301impl ::core::default::Default for Daadscr {
302 #[inline(always)]
303 fn default() -> Daadscr {
304 <crate::RegValueT<Daadscr_SPEC> as RegisterValue<_>>::new(0)
305 }
306}
307pub mod daadscr {
308
309 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
310 pub struct Daadst_SPEC;
311 pub type Daadst = crate::EnumBitfieldStruct<u8, Daadst_SPEC>;
312 impl Daadst {
313 #[doc = "D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled)."]
314 pub const _0: Self = Self::new(0);
315
316 #[doc = "D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled)."]
317 pub const _1: Self = Self::new(1);
318 }
319}
320#[doc(hidden)]
321#[derive(Copy, Clone, Eq, PartialEq)]
322pub struct Davrefcr_SPEC;
323impl crate::sealed::RegSpec for Davrefcr_SPEC {
324 type DataType = u8;
325}
326
327#[doc = "D/A VREF Control Register"]
328pub type Davrefcr = crate::RegValueT<Davrefcr_SPEC>;
329
330impl Davrefcr {
331 #[doc = "These bits are read as 00000. The write value should be 00000."]
332 #[inline(always)]
333 pub fn reserved(
334 self,
335 ) -> crate::common::RegisterField<3, 0x1f, 1, 0, u8, u8, Davrefcr_SPEC, crate::common::RW> {
336 crate::common::RegisterField::<3,0x1f,1,0,u8,u8,Davrefcr_SPEC,crate::common::RW>::from_register(self,0)
337 }
338
339 #[doc = "D/A Reference Voltage Select"]
340 #[inline(always)]
341 pub fn r#ref(
342 self,
343 ) -> crate::common::RegisterField<
344 0,
345 0x7,
346 1,
347 0,
348 davrefcr::Ref,
349 davrefcr::Ref,
350 Davrefcr_SPEC,
351 crate::common::RW,
352 > {
353 crate::common::RegisterField::<
354 0,
355 0x7,
356 1,
357 0,
358 davrefcr::Ref,
359 davrefcr::Ref,
360 Davrefcr_SPEC,
361 crate::common::RW,
362 >::from_register(self, 0)
363 }
364}
365impl ::core::default::Default for Davrefcr {
366 #[inline(always)]
367 fn default() -> Davrefcr {
368 <crate::RegValueT<Davrefcr_SPEC> as RegisterValue<_>>::new(0)
369 }
370}
371pub mod davrefcr {
372
373 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
374 pub struct Ref_SPEC;
375 pub type Ref = crate::EnumBitfieldStruct<u8, Ref_SPEC>;
376 impl Ref {
377 #[doc = "Not selected"]
378 pub const _000: Self = Self::new(0);
379
380 #[doc = "AVCC0/AVSS0"]
381 pub const _001: Self = Self::new(1);
382
383 #[doc = "Internal reference voltage/AVSS0"]
384 pub const _011: Self = Self::new(3);
385
386 #[doc = "VREFH/VREFL"]
387 pub const _110: Self = Self::new(6);
388 }
389}
390#[doc(hidden)]
391#[derive(Copy, Clone, Eq, PartialEq)]
392pub struct Dapc_SPEC;
393impl crate::sealed::RegSpec for Dapc_SPEC {
394 type DataType = u8;
395}
396
397#[doc = "D/A Switch Charge Pump Control Register"]
398pub type Dapc = crate::RegValueT<Dapc_SPEC>;
399
400impl Dapc {
401 #[doc = "These bits are read as 0000000. The write value should be 0000000."]
402 #[inline(always)]
403 pub fn reserved(
404 self,
405 ) -> crate::common::RegisterField<1, 0x7f, 1, 0, u8, u8, Dapc_SPEC, crate::common::RW> {
406 crate::common::RegisterField::<1,0x7f,1,0,u8,u8,Dapc_SPEC,crate::common::RW>::from_register(self,0)
407 }
408
409 #[doc = "Charge Pump Enable"]
410 #[inline(always)]
411 pub fn pumpen(
412 self,
413 ) -> crate::common::RegisterField<
414 0,
415 0x1,
416 1,
417 0,
418 dapc::Pumpen,
419 dapc::Pumpen,
420 Dapc_SPEC,
421 crate::common::RW,
422 > {
423 crate::common::RegisterField::<
424 0,
425 0x1,
426 1,
427 0,
428 dapc::Pumpen,
429 dapc::Pumpen,
430 Dapc_SPEC,
431 crate::common::RW,
432 >::from_register(self, 0)
433 }
434}
435impl ::core::default::Default for Dapc {
436 #[inline(always)]
437 fn default() -> Dapc {
438 <crate::RegValueT<Dapc_SPEC> as RegisterValue<_>>::new(0)
439 }
440}
441pub mod dapc {
442
443 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
444 pub struct Pumpen_SPEC;
445 pub type Pumpen = crate::EnumBitfieldStruct<u8, Pumpen_SPEC>;
446 impl Pumpen {
447 #[doc = "Charge pump disabled"]
448 pub const _0: Self = Self::new(0);
449
450 #[doc = "Charge pump enabled"]
451 pub const _1: Self = Self::new(1);
452 }
453}