ra2a1_pac/
iic0.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.1, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:31 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Inter-Integrated Circuit 0"]
28unsafe impl ::core::marker::Send for super::Iic0 {}
29unsafe impl ::core::marker::Sync for super::Iic0 {}
30impl super::Iic0 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "I2C Bus Control Register 1"]
38    #[inline(always)]
39    pub const fn iccr1(&self) -> &'static crate::common::Reg<self::Iccr1_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Iccr1_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "I2C Bus Control Register 2"]
48    #[inline(always)]
49    pub const fn iccr2(&self) -> &'static crate::common::Reg<self::Iccr2_SPEC, crate::common::RW> {
50        unsafe {
51            crate::common::Reg::<self::Iccr2_SPEC, crate::common::RW>::from_ptr(
52                self._svd2pac_as_ptr().add(1usize),
53            )
54        }
55    }
56
57    #[doc = "I2C Bus Mode Register 1"]
58    #[inline(always)]
59    pub const fn icmr1(&self) -> &'static crate::common::Reg<self::Icmr1_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Icmr1_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(2usize),
63            )
64        }
65    }
66
67    #[doc = "I2C Bus Mode Register 2"]
68    #[inline(always)]
69    pub const fn icmr2(&self) -> &'static crate::common::Reg<self::Icmr2_SPEC, crate::common::RW> {
70        unsafe {
71            crate::common::Reg::<self::Icmr2_SPEC, crate::common::RW>::from_ptr(
72                self._svd2pac_as_ptr().add(3usize),
73            )
74        }
75    }
76
77    #[doc = "I2C Bus Mode Register 3"]
78    #[inline(always)]
79    pub const fn icmr3(&self) -> &'static crate::common::Reg<self::Icmr3_SPEC, crate::common::RW> {
80        unsafe {
81            crate::common::Reg::<self::Icmr3_SPEC, crate::common::RW>::from_ptr(
82                self._svd2pac_as_ptr().add(4usize),
83            )
84        }
85    }
86
87    #[doc = "I2C Bus Function Enable Register"]
88    #[inline(always)]
89    pub const fn icfer(&self) -> &'static crate::common::Reg<self::Icfer_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::Icfer_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(5usize),
93            )
94        }
95    }
96
97    #[doc = "I2C Bus Status Enable Register"]
98    #[inline(always)]
99    pub const fn icser(&self) -> &'static crate::common::Reg<self::Icser_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::Icser_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(6usize),
103            )
104        }
105    }
106
107    #[doc = "I2C Bus Interrupt Enable Register"]
108    #[inline(always)]
109    pub const fn icier(&self) -> &'static crate::common::Reg<self::Icier_SPEC, crate::common::RW> {
110        unsafe {
111            crate::common::Reg::<self::Icier_SPEC, crate::common::RW>::from_ptr(
112                self._svd2pac_as_ptr().add(7usize),
113            )
114        }
115    }
116
117    #[doc = "I2C Bus Status Register 1"]
118    #[inline(always)]
119    pub const fn icsr1(&self) -> &'static crate::common::Reg<self::Icsr1_SPEC, crate::common::RW> {
120        unsafe {
121            crate::common::Reg::<self::Icsr1_SPEC, crate::common::RW>::from_ptr(
122                self._svd2pac_as_ptr().add(8usize),
123            )
124        }
125    }
126
127    #[doc = "I2C Bus Status Register 2"]
128    #[inline(always)]
129    pub const fn icsr2(&self) -> &'static crate::common::Reg<self::Icsr2_SPEC, crate::common::RW> {
130        unsafe {
131            crate::common::Reg::<self::Icsr2_SPEC, crate::common::RW>::from_ptr(
132                self._svd2pac_as_ptr().add(9usize),
133            )
134        }
135    }
136
137    #[doc = "Slave Address Register L%s"]
138    #[inline(always)]
139    pub const fn sarl(
140        &self,
141    ) -> &'static crate::common::ClusterRegisterArray<
142        crate::common::Reg<self::Sarl_SPEC, crate::common::RW>,
143        3,
144        0x2,
145    > {
146        unsafe {
147            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xausize))
148        }
149    }
150    #[inline(always)]
151    pub const fn sarl0(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
152        unsafe {
153            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
154                self._svd2pac_as_ptr().add(0xausize),
155            )
156        }
157    }
158    #[inline(always)]
159    pub const fn sarl1(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
160        unsafe {
161            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
162                self._svd2pac_as_ptr().add(0xcusize),
163            )
164        }
165    }
166    #[inline(always)]
167    pub const fn sarl2(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
168        unsafe {
169            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
170                self._svd2pac_as_ptr().add(0xeusize),
171            )
172        }
173    }
174
175    #[doc = "Slave Address Register U%s"]
176    #[inline(always)]
177    pub const fn saru(
178        &self,
179    ) -> &'static crate::common::ClusterRegisterArray<
180        crate::common::Reg<self::Saru_SPEC, crate::common::RW>,
181        3,
182        0x2,
183    > {
184        unsafe {
185            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xbusize))
186        }
187    }
188    #[inline(always)]
189    pub const fn saru0(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
190        unsafe {
191            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
192                self._svd2pac_as_ptr().add(0xbusize),
193            )
194        }
195    }
196    #[inline(always)]
197    pub const fn saru1(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
198        unsafe {
199            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
200                self._svd2pac_as_ptr().add(0xdusize),
201            )
202        }
203    }
204    #[inline(always)]
205    pub const fn saru2(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
206        unsafe {
207            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
208                self._svd2pac_as_ptr().add(0xfusize),
209            )
210        }
211    }
212
213    #[doc = "I2C Bus Bit Rate Low-Level Register"]
214    #[inline(always)]
215    pub const fn icbrl(&self) -> &'static crate::common::Reg<self::Icbrl_SPEC, crate::common::RW> {
216        unsafe {
217            crate::common::Reg::<self::Icbrl_SPEC, crate::common::RW>::from_ptr(
218                self._svd2pac_as_ptr().add(16usize),
219            )
220        }
221    }
222
223    #[doc = "I2C Bus Bit Rate High-Level Register"]
224    #[inline(always)]
225    pub const fn icbrh(&self) -> &'static crate::common::Reg<self::Icbrh_SPEC, crate::common::RW> {
226        unsafe {
227            crate::common::Reg::<self::Icbrh_SPEC, crate::common::RW>::from_ptr(
228                self._svd2pac_as_ptr().add(17usize),
229            )
230        }
231    }
232
233    #[doc = "I2C Bus Transmit Data Register"]
234    #[inline(always)]
235    pub const fn icdrt(&self) -> &'static crate::common::Reg<self::Icdrt_SPEC, crate::common::RW> {
236        unsafe {
237            crate::common::Reg::<self::Icdrt_SPEC, crate::common::RW>::from_ptr(
238                self._svd2pac_as_ptr().add(18usize),
239            )
240        }
241    }
242
243    #[doc = "I2C Bus Receive Data Register"]
244    #[inline(always)]
245    pub const fn icdrr(&self) -> &'static crate::common::Reg<self::Icdrr_SPEC, crate::common::R> {
246        unsafe {
247            crate::common::Reg::<self::Icdrr_SPEC, crate::common::R>::from_ptr(
248                self._svd2pac_as_ptr().add(19usize),
249            )
250        }
251    }
252
253    #[doc = "I2C Bus Wake Up Unit Register"]
254    #[inline(always)]
255    pub const fn icwur(&self) -> &'static crate::common::Reg<self::Icwur_SPEC, crate::common::RW> {
256        unsafe {
257            crate::common::Reg::<self::Icwur_SPEC, crate::common::RW>::from_ptr(
258                self._svd2pac_as_ptr().add(22usize),
259            )
260        }
261    }
262
263    #[doc = "Reserved"]
264    #[inline(always)]
265    pub const fn icwur2(
266        &self,
267    ) -> &'static crate::common::Reg<self::Icwur2_SPEC, crate::common::RW> {
268        unsafe {
269            crate::common::Reg::<self::Icwur2_SPEC, crate::common::RW>::from_ptr(
270                self._svd2pac_as_ptr().add(23usize),
271            )
272        }
273    }
274}
275#[doc(hidden)]
276#[derive(Copy, Clone, Eq, PartialEq)]
277pub struct Iccr1_SPEC;
278impl crate::sealed::RegSpec for Iccr1_SPEC {
279    type DataType = u8;
280}
281
282#[doc = "I2C Bus Control Register 1"]
283pub type Iccr1 = crate::RegValueT<Iccr1_SPEC>;
284
285impl Iccr1 {
286    #[doc = "I2C Bus Interface Enable"]
287    #[inline(always)]
288    pub fn ice(
289        self,
290    ) -> crate::common::RegisterField<
291        7,
292        0x1,
293        1,
294        0,
295        iccr1::Ice,
296        iccr1::Ice,
297        Iccr1_SPEC,
298        crate::common::RW,
299    > {
300        crate::common::RegisterField::<
301            7,
302            0x1,
303            1,
304            0,
305            iccr1::Ice,
306            iccr1::Ice,
307            Iccr1_SPEC,
308            crate::common::RW,
309        >::from_register(self, 0)
310    }
311
312    #[doc = "I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information)."]
313    #[inline(always)]
314    pub fn iicrst(
315        self,
316    ) -> crate::common::RegisterField<
317        6,
318        0x1,
319        1,
320        0,
321        iccr1::Iicrst,
322        iccr1::Iicrst,
323        Iccr1_SPEC,
324        crate::common::RW,
325    > {
326        crate::common::RegisterField::<
327            6,
328            0x1,
329            1,
330            0,
331            iccr1::Iicrst,
332            iccr1::Iicrst,
333            Iccr1_SPEC,
334            crate::common::RW,
335        >::from_register(self, 0)
336    }
337
338    #[doc = "Extra SCL Clock Cycle Output"]
339    #[inline(always)]
340    pub fn clo(
341        self,
342    ) -> crate::common::RegisterField<
343        5,
344        0x1,
345        1,
346        0,
347        iccr1::Clo,
348        iccr1::Clo,
349        Iccr1_SPEC,
350        crate::common::RW,
351    > {
352        crate::common::RegisterField::<
353            5,
354            0x1,
355            1,
356            0,
357            iccr1::Clo,
358            iccr1::Clo,
359            Iccr1_SPEC,
360            crate::common::RW,
361        >::from_register(self, 0)
362    }
363
364    #[doc = "SCLO/SDAO Write Protect"]
365    #[inline(always)]
366    pub fn sowp(
367        self,
368    ) -> crate::common::RegisterField<
369        4,
370        0x1,
371        1,
372        0,
373        iccr1::Sowp,
374        iccr1::Sowp,
375        Iccr1_SPEC,
376        crate::common::W,
377    > {
378        crate::common::RegisterField::<
379            4,
380            0x1,
381            1,
382            0,
383            iccr1::Sowp,
384            iccr1::Sowp,
385            Iccr1_SPEC,
386            crate::common::W,
387        >::from_register(self, 0)
388    }
389
390    #[doc = "SCL Output Control/Monitor"]
391    #[inline(always)]
392    pub fn sclo(
393        self,
394    ) -> crate::common::RegisterField<
395        3,
396        0x1,
397        1,
398        0,
399        iccr1::Sclo,
400        iccr1::Sclo,
401        Iccr1_SPEC,
402        crate::common::RW,
403    > {
404        crate::common::RegisterField::<
405            3,
406            0x1,
407            1,
408            0,
409            iccr1::Sclo,
410            iccr1::Sclo,
411            Iccr1_SPEC,
412            crate::common::RW,
413        >::from_register(self, 0)
414    }
415
416    #[doc = "SDA Output Control/Monitor"]
417    #[inline(always)]
418    pub fn sdao(
419        self,
420    ) -> crate::common::RegisterField<
421        2,
422        0x1,
423        1,
424        0,
425        iccr1::Sdao,
426        iccr1::Sdao,
427        Iccr1_SPEC,
428        crate::common::RW,
429    > {
430        crate::common::RegisterField::<
431            2,
432            0x1,
433            1,
434            0,
435            iccr1::Sdao,
436            iccr1::Sdao,
437            Iccr1_SPEC,
438            crate::common::RW,
439        >::from_register(self, 0)
440    }
441
442    #[doc = "SCL Line Monitor"]
443    #[inline(always)]
444    pub fn scli(
445        self,
446    ) -> crate::common::RegisterField<
447        1,
448        0x1,
449        1,
450        0,
451        iccr1::Scli,
452        iccr1::Scli,
453        Iccr1_SPEC,
454        crate::common::R,
455    > {
456        crate::common::RegisterField::<
457            1,
458            0x1,
459            1,
460            0,
461            iccr1::Scli,
462            iccr1::Scli,
463            Iccr1_SPEC,
464            crate::common::R,
465        >::from_register(self, 0)
466    }
467
468    #[doc = "SDA Line Monitor"]
469    #[inline(always)]
470    pub fn sdai(
471        self,
472    ) -> crate::common::RegisterField<
473        0,
474        0x1,
475        1,
476        0,
477        iccr1::Sdai,
478        iccr1::Sdai,
479        Iccr1_SPEC,
480        crate::common::R,
481    > {
482        crate::common::RegisterField::<
483            0,
484            0x1,
485            1,
486            0,
487            iccr1::Sdai,
488            iccr1::Sdai,
489            Iccr1_SPEC,
490            crate::common::R,
491        >::from_register(self, 0)
492    }
493}
494impl ::core::default::Default for Iccr1 {
495    #[inline(always)]
496    fn default() -> Iccr1 {
497        <crate::RegValueT<Iccr1_SPEC> as RegisterValue<_>>::new(31)
498    }
499}
500pub mod iccr1 {
501
502    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
503    pub struct Ice_SPEC;
504    pub type Ice = crate::EnumBitfieldStruct<u8, Ice_SPEC>;
505    impl Ice {
506        #[doc = "Disable (SCLn and SDAn pins in inactive state)"]
507        pub const _0: Self = Self::new(0);
508
509        #[doc = "Enable (SCLn and SDAn pins in active state)"]
510        pub const _1: Self = Self::new(1);
511    }
512    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
513    pub struct Iicrst_SPEC;
514    pub type Iicrst = crate::EnumBitfieldStruct<u8, Iicrst_SPEC>;
515    impl Iicrst {
516        #[doc = "Releases the RIIC reset or internal reset."]
517        pub const _0: Self = Self::new(0);
518
519        #[doc = "Initiates the RIIC reset or internal reset."]
520        pub const _1: Self = Self::new(1);
521    }
522    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
523    pub struct Clo_SPEC;
524    pub type Clo = crate::EnumBitfieldStruct<u8, Clo_SPEC>;
525    impl Clo {
526        #[doc = "Does not output an extra SCL clock cycle."]
527        pub const _0: Self = Self::new(0);
528
529        #[doc = "Outputs an extra SCL clock cycle."]
530        pub const _1: Self = Self::new(1);
531    }
532    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
533    pub struct Sowp_SPEC;
534    pub type Sowp = crate::EnumBitfieldStruct<u8, Sowp_SPEC>;
535    impl Sowp {
536        #[doc = "Bits SCLO and SDAO can be written."]
537        pub const _0: Self = Self::new(0);
538
539        #[doc = "Bits SCLO and SDAO are protected."]
540        pub const _1: Self = Self::new(1);
541    }
542    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
543    pub struct Sclo_SPEC;
544    pub type Sclo = crate::EnumBitfieldStruct<u8, Sclo_SPEC>;
545    impl Sclo {
546        #[doc = "(Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low."]
547        pub const _0: Self = Self::new(0);
548
549        #[doc = "(Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin."]
550        pub const _1: Self = Self::new(1);
551    }
552    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
553    pub struct Sdao_SPEC;
554    pub type Sdao = crate::EnumBitfieldStruct<u8, Sdao_SPEC>;
555    impl Sdao {
556        #[doc = "(Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low."]
557        pub const _0: Self = Self::new(0);
558
559        #[doc = "(Read)The RIIC has released the SDAn pin./  (Write)The RIIC releases the SDAn pin."]
560        pub const _1: Self = Self::new(1);
561    }
562    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
563    pub struct Scli_SPEC;
564    pub type Scli = crate::EnumBitfieldStruct<u8, Scli_SPEC>;
565    impl Scli {
566        #[doc = "SCLn line is low."]
567        pub const _0: Self = Self::new(0);
568
569        #[doc = "SCLn line is high."]
570        pub const _1: Self = Self::new(1);
571    }
572    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
573    pub struct Sdai_SPEC;
574    pub type Sdai = crate::EnumBitfieldStruct<u8, Sdai_SPEC>;
575    impl Sdai {
576        #[doc = "SDAn line is low."]
577        pub const _0: Self = Self::new(0);
578
579        #[doc = "SDAn line is high."]
580        pub const _1: Self = Self::new(1);
581    }
582}
583#[doc(hidden)]
584#[derive(Copy, Clone, Eq, PartialEq)]
585pub struct Iccr2_SPEC;
586impl crate::sealed::RegSpec for Iccr2_SPEC {
587    type DataType = u8;
588}
589
590#[doc = "I2C Bus Control Register 2"]
591pub type Iccr2 = crate::RegValueT<Iccr2_SPEC>;
592
593impl Iccr2 {
594    #[doc = "Bus Busy Detection Flag"]
595    #[inline(always)]
596    pub fn bbsy(
597        self,
598    ) -> crate::common::RegisterField<
599        7,
600        0x1,
601        1,
602        0,
603        iccr2::Bbsy,
604        iccr2::Bbsy,
605        Iccr2_SPEC,
606        crate::common::R,
607    > {
608        crate::common::RegisterField::<
609            7,
610            0x1,
611            1,
612            0,
613            iccr2::Bbsy,
614            iccr2::Bbsy,
615            Iccr2_SPEC,
616            crate::common::R,
617        >::from_register(self, 0)
618    }
619
620    #[doc = "Master/Slave Mode"]
621    #[inline(always)]
622    pub fn mst(
623        self,
624    ) -> crate::common::RegisterField<
625        6,
626        0x1,
627        1,
628        0,
629        iccr2::Mst,
630        iccr2::Mst,
631        Iccr2_SPEC,
632        crate::common::RW,
633    > {
634        crate::common::RegisterField::<
635            6,
636            0x1,
637            1,
638            0,
639            iccr2::Mst,
640            iccr2::Mst,
641            Iccr2_SPEC,
642            crate::common::RW,
643        >::from_register(self, 0)
644    }
645
646    #[doc = "Transmit/Receive Mode"]
647    #[inline(always)]
648    pub fn trs(
649        self,
650    ) -> crate::common::RegisterField<
651        5,
652        0x1,
653        1,
654        0,
655        iccr2::Trs,
656        iccr2::Trs,
657        Iccr2_SPEC,
658        crate::common::RW,
659    > {
660        crate::common::RegisterField::<
661            5,
662            0x1,
663            1,
664            0,
665            iccr2::Trs,
666            iccr2::Trs,
667            Iccr2_SPEC,
668            crate::common::RW,
669        >::from_register(self, 0)
670    }
671
672    #[doc = "Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued."]
673    #[inline(always)]
674    pub fn sp(
675        self,
676    ) -> crate::common::RegisterField<
677        3,
678        0x1,
679        1,
680        0,
681        iccr2::Sp,
682        iccr2::Sp,
683        Iccr2_SPEC,
684        crate::common::RW,
685    > {
686        crate::common::RegisterField::<
687            3,
688            0x1,
689            1,
690            0,
691            iccr2::Sp,
692            iccr2::Sp,
693            Iccr2_SPEC,
694            crate::common::RW,
695        >::from_register(self, 0)
696    }
697
698    #[doc = "Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition."]
699    #[inline(always)]
700    pub fn rs(
701        self,
702    ) -> crate::common::RegisterField<
703        2,
704        0x1,
705        1,
706        0,
707        iccr2::Rs,
708        iccr2::Rs,
709        Iccr2_SPEC,
710        crate::common::RW,
711    > {
712        crate::common::RegisterField::<
713            2,
714            0x1,
715            1,
716            0,
717            iccr2::Rs,
718            iccr2::Rs,
719            Iccr2_SPEC,
720            crate::common::RW,
721        >::from_register(self, 0)
722    }
723
724    #[doc = "Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state)."]
725    #[inline(always)]
726    pub fn st(
727        self,
728    ) -> crate::common::RegisterField<
729        1,
730        0x1,
731        1,
732        0,
733        iccr2::St,
734        iccr2::St,
735        Iccr2_SPEC,
736        crate::common::RW,
737    > {
738        crate::common::RegisterField::<
739            1,
740            0x1,
741            1,
742            0,
743            iccr2::St,
744            iccr2::St,
745            Iccr2_SPEC,
746            crate::common::RW,
747        >::from_register(self, 0)
748    }
749
750    #[doc = "This bit is read as 0. The write value should be 0."]
751    #[inline(always)]
752    pub fn reserved(
753        self,
754    ) -> crate::common::RegisterFieldBool<0, 1, 0, Iccr2_SPEC, crate::common::RW> {
755        crate::common::RegisterFieldBool::<0, 1, 0, Iccr2_SPEC, crate::common::RW>::from_register(
756            self, 0,
757        )
758    }
759}
760impl ::core::default::Default for Iccr2 {
761    #[inline(always)]
762    fn default() -> Iccr2 {
763        <crate::RegValueT<Iccr2_SPEC> as RegisterValue<_>>::new(0)
764    }
765}
766pub mod iccr2 {
767
768    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
769    pub struct Bbsy_SPEC;
770    pub type Bbsy = crate::EnumBitfieldStruct<u8, Bbsy_SPEC>;
771    impl Bbsy {
772        #[doc = "The I2C bus is released (bus free state)."]
773        pub const _0: Self = Self::new(0);
774
775        #[doc = "The I2C bus is occupied (bus busy state)."]
776        pub const _1: Self = Self::new(1);
777    }
778    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
779    pub struct Mst_SPEC;
780    pub type Mst = crate::EnumBitfieldStruct<u8, Mst_SPEC>;
781    impl Mst {
782        #[doc = "Slave mode"]
783        pub const _0: Self = Self::new(0);
784
785        #[doc = "Master mode"]
786        pub const _1: Self = Self::new(1);
787    }
788    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
789    pub struct Trs_SPEC;
790    pub type Trs = crate::EnumBitfieldStruct<u8, Trs_SPEC>;
791    impl Trs {
792        #[doc = "Receive mode"]
793        pub const _0: Self = Self::new(0);
794
795        #[doc = "Transmit mode"]
796        pub const _1: Self = Self::new(1);
797    }
798    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
799    pub struct Sp_SPEC;
800    pub type Sp = crate::EnumBitfieldStruct<u8, Sp_SPEC>;
801    impl Sp {
802        #[doc = "Does not request to issue a stop condition."]
803        pub const _0: Self = Self::new(0);
804
805        #[doc = "Requests to issue a stop condition."]
806        pub const _1: Self = Self::new(1);
807    }
808    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
809    pub struct Rs_SPEC;
810    pub type Rs = crate::EnumBitfieldStruct<u8, Rs_SPEC>;
811    impl Rs {
812        #[doc = "Does not request to issue a restart condition."]
813        pub const _0: Self = Self::new(0);
814
815        #[doc = "Requests to issue a restart condition."]
816        pub const _1: Self = Self::new(1);
817    }
818    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
819    pub struct St_SPEC;
820    pub type St = crate::EnumBitfieldStruct<u8, St_SPEC>;
821    impl St {
822        #[doc = "Does not request to issue a start condition."]
823        pub const _0: Self = Self::new(0);
824
825        #[doc = "Requests to issue a start condition."]
826        pub const _1: Self = Self::new(1);
827    }
828}
829#[doc(hidden)]
830#[derive(Copy, Clone, Eq, PartialEq)]
831pub struct Icmr1_SPEC;
832impl crate::sealed::RegSpec for Icmr1_SPEC {
833    type DataType = u8;
834}
835
836#[doc = "I2C Bus Mode Register 1"]
837pub type Icmr1 = crate::RegValueT<Icmr1_SPEC>;
838
839impl Icmr1 {
840    #[doc = "MST/TRS Write Protect"]
841    #[inline(always)]
842    pub fn mtwp(
843        self,
844    ) -> crate::common::RegisterField<
845        7,
846        0x1,
847        1,
848        0,
849        icmr1::Mtwp,
850        icmr1::Mtwp,
851        Icmr1_SPEC,
852        crate::common::RW,
853    > {
854        crate::common::RegisterField::<
855            7,
856            0x1,
857            1,
858            0,
859            icmr1::Mtwp,
860            icmr1::Mtwp,
861            Icmr1_SPEC,
862            crate::common::RW,
863        >::from_register(self, 0)
864    }
865
866    #[doc = "Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS )"]
867    #[inline(always)]
868    pub fn cks(
869        self,
870    ) -> crate::common::RegisterField<
871        4,
872        0x7,
873        1,
874        0,
875        icmr1::Cks,
876        icmr1::Cks,
877        Icmr1_SPEC,
878        crate::common::RW,
879    > {
880        crate::common::RegisterField::<
881            4,
882            0x7,
883            1,
884            0,
885            icmr1::Cks,
886            icmr1::Cks,
887            Icmr1_SPEC,
888            crate::common::RW,
889        >::from_register(self, 0)
890    }
891
892    #[doc = "BC Write Protect(This bit is read as 1.)"]
893    #[inline(always)]
894    pub fn bcwp(
895        self,
896    ) -> crate::common::RegisterField<
897        3,
898        0x1,
899        1,
900        0,
901        icmr1::Bcwp,
902        icmr1::Bcwp,
903        Icmr1_SPEC,
904        crate::common::W,
905    > {
906        crate::common::RegisterField::<
907            3,
908            0x1,
909            1,
910            0,
911            icmr1::Bcwp,
912            icmr1::Bcwp,
913            Icmr1_SPEC,
914            crate::common::W,
915        >::from_register(self, 0)
916    }
917
918    #[doc = "Bit Counter"]
919    #[inline(always)]
920    pub fn bc(
921        self,
922    ) -> crate::common::RegisterField<
923        0,
924        0x7,
925        1,
926        0,
927        icmr1::Bc,
928        icmr1::Bc,
929        Icmr1_SPEC,
930        crate::common::RW,
931    > {
932        crate::common::RegisterField::<
933            0,
934            0x7,
935            1,
936            0,
937            icmr1::Bc,
938            icmr1::Bc,
939            Icmr1_SPEC,
940            crate::common::RW,
941        >::from_register(self, 0)
942    }
943}
944impl ::core::default::Default for Icmr1 {
945    #[inline(always)]
946    fn default() -> Icmr1 {
947        <crate::RegValueT<Icmr1_SPEC> as RegisterValue<_>>::new(8)
948    }
949}
950pub mod icmr1 {
951
952    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
953    pub struct Mtwp_SPEC;
954    pub type Mtwp = crate::EnumBitfieldStruct<u8, Mtwp_SPEC>;
955    impl Mtwp {
956        #[doc = "Disables writing to the MST and TRS bits in ICCR2."]
957        pub const _0: Self = Self::new(0);
958
959        #[doc = "Enables writing to the MST and TRS bits in ICCR2."]
960        pub const _1: Self = Self::new(1);
961    }
962    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
963    pub struct Cks_SPEC;
964    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
965    impl Cks {
966        #[doc = "PCLKB/1 clock"]
967        pub const _000: Self = Self::new(0);
968
969        #[doc = "PCLKB/2 clock"]
970        pub const _001: Self = Self::new(1);
971
972        #[doc = "PCLKB/4 clock"]
973        pub const _010: Self = Self::new(2);
974
975        #[doc = "PCLKB/8 clock"]
976        pub const _011: Self = Self::new(3);
977
978        #[doc = "PCLKB/16 clock"]
979        pub const _100: Self = Self::new(4);
980
981        #[doc = "PCLKB/32 clock"]
982        pub const _101: Self = Self::new(5);
983
984        #[doc = "PCLKB/64 clock"]
985        pub const _110: Self = Self::new(6);
986
987        #[doc = "PCLKB/128 clock"]
988        pub const _111: Self = Self::new(7);
989    }
990    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
991    pub struct Bcwp_SPEC;
992    pub type Bcwp = crate::EnumBitfieldStruct<u8, Bcwp_SPEC>;
993    impl Bcwp {
994        #[doc = "Enables a value to be written in the BC\\[2:0\\] bits."]
995        pub const _0: Self = Self::new(0);
996
997        #[doc = "Disables a value to be written in the BC\\[2:0\\] bits."]
998        pub const _1: Self = Self::new(1);
999    }
1000    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1001    pub struct Bc_SPEC;
1002    pub type Bc = crate::EnumBitfieldStruct<u8, Bc_SPEC>;
1003    impl Bc {
1004        #[doc = "9 bits"]
1005        pub const _000: Self = Self::new(0);
1006
1007        #[doc = "2 bits"]
1008        pub const _001: Self = Self::new(1);
1009
1010        #[doc = "3 bits"]
1011        pub const _010: Self = Self::new(2);
1012
1013        #[doc = "4 bits"]
1014        pub const _011: Self = Self::new(3);
1015
1016        #[doc = "5 bits"]
1017        pub const _100: Self = Self::new(4);
1018
1019        #[doc = "6 bits"]
1020        pub const _101: Self = Self::new(5);
1021
1022        #[doc = "7 bits"]
1023        pub const _110: Self = Self::new(6);
1024
1025        #[doc = "8 bits"]
1026        pub const _111: Self = Self::new(7);
1027    }
1028}
1029#[doc(hidden)]
1030#[derive(Copy, Clone, Eq, PartialEq)]
1031pub struct Icmr2_SPEC;
1032impl crate::sealed::RegSpec for Icmr2_SPEC {
1033    type DataType = u8;
1034}
1035
1036#[doc = "I2C Bus Mode Register 2"]
1037pub type Icmr2 = crate::RegValueT<Icmr2_SPEC>;
1038
1039impl Icmr2 {
1040    #[doc = "SDA Output Delay Clock Source Selection"]
1041    #[inline(always)]
1042    pub fn dlcs(
1043        self,
1044    ) -> crate::common::RegisterField<
1045        7,
1046        0x1,
1047        1,
1048        0,
1049        icmr2::Dlcs,
1050        icmr2::Dlcs,
1051        Icmr2_SPEC,
1052        crate::common::RW,
1053    > {
1054        crate::common::RegisterField::<
1055            7,
1056            0x1,
1057            1,
1058            0,
1059            icmr2::Dlcs,
1060            icmr2::Dlcs,
1061            Icmr2_SPEC,
1062            crate::common::RW,
1063        >::from_register(self, 0)
1064    }
1065
1066    #[doc = "SDA Output Delay Counter"]
1067    #[inline(always)]
1068    pub fn sddl(
1069        self,
1070    ) -> crate::common::RegisterField<
1071        4,
1072        0x7,
1073        1,
1074        0,
1075        icmr2::Sddl,
1076        icmr2::Sddl,
1077        Icmr2_SPEC,
1078        crate::common::RW,
1079    > {
1080        crate::common::RegisterField::<
1081            4,
1082            0x7,
1083            1,
1084            0,
1085            icmr2::Sddl,
1086            icmr2::Sddl,
1087            Icmr2_SPEC,
1088            crate::common::RW,
1089        >::from_register(self, 0)
1090    }
1091
1092    #[doc = "This bit is read as 0. The write value should be 0."]
1093    #[inline(always)]
1094    pub fn reserved(
1095        self,
1096    ) -> crate::common::RegisterFieldBool<3, 1, 0, Icmr2_SPEC, crate::common::RW> {
1097        crate::common::RegisterFieldBool::<3, 1, 0, Icmr2_SPEC, crate::common::RW>::from_register(
1098            self, 0,
1099        )
1100    }
1101
1102    #[doc = "Timeout H Count Control"]
1103    #[inline(always)]
1104    pub fn tmoh(
1105        self,
1106    ) -> crate::common::RegisterField<
1107        2,
1108        0x1,
1109        1,
1110        0,
1111        icmr2::Tmoh,
1112        icmr2::Tmoh,
1113        Icmr2_SPEC,
1114        crate::common::RW,
1115    > {
1116        crate::common::RegisterField::<
1117            2,
1118            0x1,
1119            1,
1120            0,
1121            icmr2::Tmoh,
1122            icmr2::Tmoh,
1123            Icmr2_SPEC,
1124            crate::common::RW,
1125        >::from_register(self, 0)
1126    }
1127
1128    #[doc = "Timeout L Count Control"]
1129    #[inline(always)]
1130    pub fn tmol(
1131        self,
1132    ) -> crate::common::RegisterField<
1133        1,
1134        0x1,
1135        1,
1136        0,
1137        icmr2::Tmol,
1138        icmr2::Tmol,
1139        Icmr2_SPEC,
1140        crate::common::RW,
1141    > {
1142        crate::common::RegisterField::<
1143            1,
1144            0x1,
1145            1,
1146            0,
1147            icmr2::Tmol,
1148            icmr2::Tmol,
1149            Icmr2_SPEC,
1150            crate::common::RW,
1151        >::from_register(self, 0)
1152    }
1153
1154    #[doc = "Timeout Detection Time Selection"]
1155    #[inline(always)]
1156    pub fn tmos(
1157        self,
1158    ) -> crate::common::RegisterField<
1159        0,
1160        0x1,
1161        1,
1162        0,
1163        icmr2::Tmos,
1164        icmr2::Tmos,
1165        Icmr2_SPEC,
1166        crate::common::RW,
1167    > {
1168        crate::common::RegisterField::<
1169            0,
1170            0x1,
1171            1,
1172            0,
1173            icmr2::Tmos,
1174            icmr2::Tmos,
1175            Icmr2_SPEC,
1176            crate::common::RW,
1177        >::from_register(self, 0)
1178    }
1179}
1180impl ::core::default::Default for Icmr2 {
1181    #[inline(always)]
1182    fn default() -> Icmr2 {
1183        <crate::RegValueT<Icmr2_SPEC> as RegisterValue<_>>::new(6)
1184    }
1185}
1186pub mod icmr2 {
1187
1188    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1189    pub struct Dlcs_SPEC;
1190    pub type Dlcs = crate::EnumBitfieldStruct<u8, Dlcs_SPEC>;
1191    impl Dlcs {
1192        #[doc = "The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter."]
1193        pub const _0: Self = Self::new(0);
1194
1195        #[doc = "The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter."]
1196        pub const _1: Self = Self::new(1);
1197    }
1198    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1199    pub struct Sddl_SPEC;
1200    pub type Sddl = crate::EnumBitfieldStruct<u8, Sddl_SPEC>;
1201    impl Sddl {
1202        #[doc = "No output delay"]
1203        pub const _000: Self = Self::new(0);
1204
1205        #[doc = "1 fIIC cycle  (ICMR2.DLCS=0) / 1  or 2 fIIC cycles (ICMR2.DLCS=1)"]
1206        pub const _001: Self = Self::new(1);
1207
1208        #[doc = "2 fIIC cycles (ICMR2.DLCS=0) /  3 or 4 fIIC cycles (ICMR2.DLCS=1)"]
1209        pub const _010: Self = Self::new(2);
1210
1211        #[doc = "3 fIIC cycles (ICMR2.DLCS=0) /  5 or 6 fIIC cycles (ICMR2.DLCS=1)"]
1212        pub const _011: Self = Self::new(3);
1213
1214        #[doc = "4 fIIC cycles (ICMR2.DLCS=0) /  7 or 8 fIIC cycles (ICMR2.DLCS=1)"]
1215        pub const _100: Self = Self::new(4);
1216
1217        #[doc = "5 fIIC cycles (ICMR2.DLCS=0) /  9 or 10 fIIC cycles (ICMR2.DLCS=1)"]
1218        pub const _101: Self = Self::new(5);
1219
1220        #[doc = "6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1)"]
1221        pub const _110: Self = Self::new(6);
1222
1223        #[doc = "7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1)"]
1224        pub const _111: Self = Self::new(7);
1225    }
1226    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1227    pub struct Tmoh_SPEC;
1228    pub type Tmoh = crate::EnumBitfieldStruct<u8, Tmoh_SPEC>;
1229    impl Tmoh {
1230        #[doc = "Count is disabled while the SCLn line is at a high level."]
1231        pub const _0: Self = Self::new(0);
1232
1233        #[doc = "Count is enabled while the SCLn line is at a high level."]
1234        pub const _1: Self = Self::new(1);
1235    }
1236    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1237    pub struct Tmol_SPEC;
1238    pub type Tmol = crate::EnumBitfieldStruct<u8, Tmol_SPEC>;
1239    impl Tmol {
1240        #[doc = "Count is disabled while the SCLn line is at a low level."]
1241        pub const _0: Self = Self::new(0);
1242
1243        #[doc = "Count is enabled while the SCLn line is at a low level."]
1244        pub const _1: Self = Self::new(1);
1245    }
1246    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1247    pub struct Tmos_SPEC;
1248    pub type Tmos = crate::EnumBitfieldStruct<u8, Tmos_SPEC>;
1249    impl Tmos {
1250        #[doc = "Long mode is selected."]
1251        pub const _0: Self = Self::new(0);
1252
1253        #[doc = "Short mode is selected."]
1254        pub const _1: Self = Self::new(1);
1255    }
1256}
1257#[doc(hidden)]
1258#[derive(Copy, Clone, Eq, PartialEq)]
1259pub struct Icmr3_SPEC;
1260impl crate::sealed::RegSpec for Icmr3_SPEC {
1261    type DataType = u8;
1262}
1263
1264#[doc = "I2C Bus Mode Register 3"]
1265pub type Icmr3 = crate::RegValueT<Icmr3_SPEC>;
1266
1267impl Icmr3 {
1268    #[doc = "SMBus/I2C Bus Selection"]
1269    #[inline(always)]
1270    pub fn smbs(
1271        self,
1272    ) -> crate::common::RegisterField<
1273        7,
1274        0x1,
1275        1,
1276        0,
1277        icmr3::Smbs,
1278        icmr3::Smbs,
1279        Icmr3_SPEC,
1280        crate::common::RW,
1281    > {
1282        crate::common::RegisterField::<
1283            7,
1284            0x1,
1285            1,
1286            0,
1287            icmr3::Smbs,
1288            icmr3::Smbs,
1289            Icmr3_SPEC,
1290            crate::common::RW,
1291        >::from_register(self, 0)
1292    }
1293
1294    #[doc = "WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand."]
1295    #[inline(always)]
1296    pub fn wait(
1297        self,
1298    ) -> crate::common::RegisterField<
1299        6,
1300        0x1,
1301        1,
1302        0,
1303        icmr3::Wait,
1304        icmr3::Wait,
1305        Icmr3_SPEC,
1306        crate::common::RW,
1307    > {
1308        crate::common::RegisterField::<
1309            6,
1310            0x1,
1311            1,
1312            0,
1313            icmr3::Wait,
1314            icmr3::Wait,
1315            Icmr3_SPEC,
1316            crate::common::RW,
1317        >::from_register(self, 0)
1318    }
1319
1320    #[doc = "RDRF Flag Set Timing Selection"]
1321    #[inline(always)]
1322    pub fn rdrfs(
1323        self,
1324    ) -> crate::common::RegisterField<
1325        5,
1326        0x1,
1327        1,
1328        0,
1329        icmr3::Rdrfs,
1330        icmr3::Rdrfs,
1331        Icmr3_SPEC,
1332        crate::common::RW,
1333    > {
1334        crate::common::RegisterField::<
1335            5,
1336            0x1,
1337            1,
1338            0,
1339            icmr3::Rdrfs,
1340            icmr3::Rdrfs,
1341            Icmr3_SPEC,
1342            crate::common::RW,
1343        >::from_register(self, 0)
1344    }
1345
1346    #[doc = "ACKBT Write Protect"]
1347    #[inline(always)]
1348    pub fn ackwp(
1349        self,
1350    ) -> crate::common::RegisterField<
1351        4,
1352        0x1,
1353        1,
1354        0,
1355        icmr3::Ackwp,
1356        icmr3::Ackwp,
1357        Icmr3_SPEC,
1358        crate::common::RW,
1359    > {
1360        crate::common::RegisterField::<
1361            4,
1362            0x1,
1363            1,
1364            0,
1365            icmr3::Ackwp,
1366            icmr3::Ackwp,
1367            Icmr3_SPEC,
1368            crate::common::RW,
1369        >::from_register(self, 0)
1370    }
1371
1372    #[doc = "Transmit Acknowledge"]
1373    #[inline(always)]
1374    pub fn ackbt(
1375        self,
1376    ) -> crate::common::RegisterField<
1377        3,
1378        0x1,
1379        1,
1380        0,
1381        icmr3::Ackbt,
1382        icmr3::Ackbt,
1383        Icmr3_SPEC,
1384        crate::common::RW,
1385    > {
1386        crate::common::RegisterField::<
1387            3,
1388            0x1,
1389            1,
1390            0,
1391            icmr3::Ackbt,
1392            icmr3::Ackbt,
1393            Icmr3_SPEC,
1394            crate::common::RW,
1395        >::from_register(self, 0)
1396    }
1397
1398    #[doc = "Receive Acknowledge"]
1399    #[inline(always)]
1400    pub fn ackbr(
1401        self,
1402    ) -> crate::common::RegisterField<
1403        2,
1404        0x1,
1405        1,
1406        0,
1407        icmr3::Ackbr,
1408        icmr3::Ackbr,
1409        Icmr3_SPEC,
1410        crate::common::R,
1411    > {
1412        crate::common::RegisterField::<
1413            2,
1414            0x1,
1415            1,
1416            0,
1417            icmr3::Ackbr,
1418            icmr3::Ackbr,
1419            Icmr3_SPEC,
1420            crate::common::R,
1421        >::from_register(self, 0)
1422    }
1423
1424    #[doc = "Noise Filter Stage Selection"]
1425    #[inline(always)]
1426    pub fn nf(
1427        self,
1428    ) -> crate::common::RegisterField<
1429        0,
1430        0x3,
1431        1,
1432        0,
1433        icmr3::Nf,
1434        icmr3::Nf,
1435        Icmr3_SPEC,
1436        crate::common::RW,
1437    > {
1438        crate::common::RegisterField::<
1439            0,
1440            0x3,
1441            1,
1442            0,
1443            icmr3::Nf,
1444            icmr3::Nf,
1445            Icmr3_SPEC,
1446            crate::common::RW,
1447        >::from_register(self, 0)
1448    }
1449}
1450impl ::core::default::Default for Icmr3 {
1451    #[inline(always)]
1452    fn default() -> Icmr3 {
1453        <crate::RegValueT<Icmr3_SPEC> as RegisterValue<_>>::new(0)
1454    }
1455}
1456pub mod icmr3 {
1457
1458    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1459    pub struct Smbs_SPEC;
1460    pub type Smbs = crate::EnumBitfieldStruct<u8, Smbs_SPEC>;
1461    impl Smbs {
1462        #[doc = "The I2C bus is selected."]
1463        pub const _0: Self = Self::new(0);
1464
1465        #[doc = "The SMBus is selected."]
1466        pub const _1: Self = Self::new(1);
1467    }
1468    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1469    pub struct Wait_SPEC;
1470    pub type Wait = crate::EnumBitfieldStruct<u8, Wait_SPEC>;
1471    impl Wait {
1472        #[doc = "No WAIT (The period between ninth clock cycle and first clock cycle is not held low.)"]
1473        pub const _0: Self = Self::new(0);
1474
1475        #[doc = "WAIT (The period between ninth clock cycle and first clock cycle is held low.)"]
1476        pub const _1: Self = Self::new(1);
1477    }
1478    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1479    pub struct Rdrfs_SPEC;
1480    pub type Rdrfs = crate::EnumBitfieldStruct<u8, Rdrfs_SPEC>;
1481    impl Rdrfs {
1482        #[doc = "The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.)"]
1483        pub const _0: Self = Self::new(0);
1484
1485        #[doc = "The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.)"]
1486        pub const _1: Self = Self::new(1);
1487    }
1488    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1489    pub struct Ackwp_SPEC;
1490    pub type Ackwp = crate::EnumBitfieldStruct<u8, Ackwp_SPEC>;
1491    impl Ackwp {
1492        #[doc = "Modification of the ACKBT bit is disabled."]
1493        pub const _0: Self = Self::new(0);
1494
1495        #[doc = "Modification of the ACKBT bit is enabled."]
1496        pub const _1: Self = Self::new(1);
1497    }
1498    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1499    pub struct Ackbt_SPEC;
1500    pub type Ackbt = crate::EnumBitfieldStruct<u8, Ackbt_SPEC>;
1501    impl Ackbt {
1502        #[doc = "A 0 is sent as the acknowledge bit (ACK transmission)."]
1503        pub const _0: Self = Self::new(0);
1504
1505        #[doc = "A 1 is sent as the acknowledge bit (NACK transmission)."]
1506        pub const _1: Self = Self::new(1);
1507    }
1508    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1509    pub struct Ackbr_SPEC;
1510    pub type Ackbr = crate::EnumBitfieldStruct<u8, Ackbr_SPEC>;
1511    impl Ackbr {
1512        #[doc = "A 0 is received as the acknowledge bit (ACK reception)."]
1513        pub const _0: Self = Self::new(0);
1514
1515        #[doc = "A 1 is received as the acknowledge bit (NACK reception)."]
1516        pub const _1: Self = Self::new(1);
1517    }
1518    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1519    pub struct Nf_SPEC;
1520    pub type Nf = crate::EnumBitfieldStruct<u8, Nf_SPEC>;
1521    impl Nf {
1522        #[doc = "Noise of up to one IIC cycle is filtered out (single-stage filter)."]
1523        pub const _00: Self = Self::new(0);
1524
1525        #[doc = "Noise of up to two IIC cycles is filtered out (2-stage filter)."]
1526        pub const _01: Self = Self::new(1);
1527
1528        #[doc = "Noise of up to three IIC cycles is filtered out (3-stage filter)."]
1529        pub const _10: Self = Self::new(2);
1530
1531        #[doc = "Noise of up to four IIC cycles is filtered out (4-stage filter)"]
1532        pub const _11: Self = Self::new(3);
1533    }
1534}
1535#[doc(hidden)]
1536#[derive(Copy, Clone, Eq, PartialEq)]
1537pub struct Icfer_SPEC;
1538impl crate::sealed::RegSpec for Icfer_SPEC {
1539    type DataType = u8;
1540}
1541
1542#[doc = "I2C Bus Function Enable Register"]
1543pub type Icfer = crate::RegValueT<Icfer_SPEC>;
1544
1545impl Icfer {
1546    #[doc = "This bit is read as 0. The write value should be 0."]
1547    #[inline(always)]
1548    pub fn reserved(
1549        self,
1550    ) -> crate::common::RegisterFieldBool<7, 1, 0, Icfer_SPEC, crate::common::RW> {
1551        crate::common::RegisterFieldBool::<7, 1, 0, Icfer_SPEC, crate::common::RW>::from_register(
1552            self, 0,
1553        )
1554    }
1555
1556    #[doc = "SCL Synchronous Circuit Enable"]
1557    #[inline(always)]
1558    pub fn scle(
1559        self,
1560    ) -> crate::common::RegisterField<
1561        6,
1562        0x1,
1563        1,
1564        0,
1565        icfer::Scle,
1566        icfer::Scle,
1567        Icfer_SPEC,
1568        crate::common::RW,
1569    > {
1570        crate::common::RegisterField::<
1571            6,
1572            0x1,
1573            1,
1574            0,
1575            icfer::Scle,
1576            icfer::Scle,
1577            Icfer_SPEC,
1578            crate::common::RW,
1579        >::from_register(self, 0)
1580    }
1581
1582    #[doc = "Digital Noise Filter Circuit Enable"]
1583    #[inline(always)]
1584    pub fn nfe(
1585        self,
1586    ) -> crate::common::RegisterField<
1587        5,
1588        0x1,
1589        1,
1590        0,
1591        icfer::Nfe,
1592        icfer::Nfe,
1593        Icfer_SPEC,
1594        crate::common::RW,
1595    > {
1596        crate::common::RegisterField::<
1597            5,
1598            0x1,
1599            1,
1600            0,
1601            icfer::Nfe,
1602            icfer::Nfe,
1603            Icfer_SPEC,
1604            crate::common::RW,
1605        >::from_register(self, 0)
1606    }
1607
1608    #[doc = "NACK Reception Transfer Suspension Enable"]
1609    #[inline(always)]
1610    pub fn nacke(
1611        self,
1612    ) -> crate::common::RegisterField<
1613        4,
1614        0x1,
1615        1,
1616        0,
1617        icfer::Nacke,
1618        icfer::Nacke,
1619        Icfer_SPEC,
1620        crate::common::RW,
1621    > {
1622        crate::common::RegisterField::<
1623            4,
1624            0x1,
1625            1,
1626            0,
1627            icfer::Nacke,
1628            icfer::Nacke,
1629            Icfer_SPEC,
1630            crate::common::RW,
1631        >::from_register(self, 0)
1632    }
1633
1634    #[doc = "Slave Arbitration-Lost Detection Enable"]
1635    #[inline(always)]
1636    pub fn sale(
1637        self,
1638    ) -> crate::common::RegisterField<
1639        3,
1640        0x1,
1641        1,
1642        0,
1643        icfer::Sale,
1644        icfer::Sale,
1645        Icfer_SPEC,
1646        crate::common::RW,
1647    > {
1648        crate::common::RegisterField::<
1649            3,
1650            0x1,
1651            1,
1652            0,
1653            icfer::Sale,
1654            icfer::Sale,
1655            Icfer_SPEC,
1656            crate::common::RW,
1657        >::from_register(self, 0)
1658    }
1659
1660    #[doc = "NACK Transmission Arbitration-Lost Detection Enable"]
1661    #[inline(always)]
1662    pub fn nale(
1663        self,
1664    ) -> crate::common::RegisterField<
1665        2,
1666        0x1,
1667        1,
1668        0,
1669        icfer::Nale,
1670        icfer::Nale,
1671        Icfer_SPEC,
1672        crate::common::RW,
1673    > {
1674        crate::common::RegisterField::<
1675            2,
1676            0x1,
1677            1,
1678            0,
1679            icfer::Nale,
1680            icfer::Nale,
1681            Icfer_SPEC,
1682            crate::common::RW,
1683        >::from_register(self, 0)
1684    }
1685
1686    #[doc = "Master Arbitration-Lost Detection Enable"]
1687    #[inline(always)]
1688    pub fn male(
1689        self,
1690    ) -> crate::common::RegisterField<
1691        1,
1692        0x1,
1693        1,
1694        0,
1695        icfer::Male,
1696        icfer::Male,
1697        Icfer_SPEC,
1698        crate::common::RW,
1699    > {
1700        crate::common::RegisterField::<
1701            1,
1702            0x1,
1703            1,
1704            0,
1705            icfer::Male,
1706            icfer::Male,
1707            Icfer_SPEC,
1708            crate::common::RW,
1709        >::from_register(self, 0)
1710    }
1711
1712    #[doc = "Timeout Function Enable"]
1713    #[inline(always)]
1714    pub fn tmoe(
1715        self,
1716    ) -> crate::common::RegisterField<
1717        0,
1718        0x1,
1719        1,
1720        0,
1721        icfer::Tmoe,
1722        icfer::Tmoe,
1723        Icfer_SPEC,
1724        crate::common::RW,
1725    > {
1726        crate::common::RegisterField::<
1727            0,
1728            0x1,
1729            1,
1730            0,
1731            icfer::Tmoe,
1732            icfer::Tmoe,
1733            Icfer_SPEC,
1734            crate::common::RW,
1735        >::from_register(self, 0)
1736    }
1737}
1738impl ::core::default::Default for Icfer {
1739    #[inline(always)]
1740    fn default() -> Icfer {
1741        <crate::RegValueT<Icfer_SPEC> as RegisterValue<_>>::new(114)
1742    }
1743}
1744pub mod icfer {
1745
1746    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1747    pub struct Scle_SPEC;
1748    pub type Scle = crate::EnumBitfieldStruct<u8, Scle_SPEC>;
1749    impl Scle {
1750        #[doc = "No SCL synchronous circuit is used."]
1751        pub const _0: Self = Self::new(0);
1752
1753        #[doc = "An SCL synchronous circuit is used."]
1754        pub const _1: Self = Self::new(1);
1755    }
1756    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1757    pub struct Nfe_SPEC;
1758    pub type Nfe = crate::EnumBitfieldStruct<u8, Nfe_SPEC>;
1759    impl Nfe {
1760        #[doc = "No digital noise filter circuit is used."]
1761        pub const _0: Self = Self::new(0);
1762
1763        #[doc = "A digital noise filter circuit is used."]
1764        pub const _1: Self = Self::new(1);
1765    }
1766    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1767    pub struct Nacke_SPEC;
1768    pub type Nacke = crate::EnumBitfieldStruct<u8, Nacke_SPEC>;
1769    impl Nacke {
1770        #[doc = "Transfer operation is not suspended during NACK reception (transfer suspension disabled)."]
1771        pub const _0: Self = Self::new(0);
1772
1773        #[doc = "Transfer operation is suspended during NACK reception (transfer suspension enabled)."]
1774        pub const _1: Self = Self::new(1);
1775    }
1776    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1777    pub struct Sale_SPEC;
1778    pub type Sale = crate::EnumBitfieldStruct<u8, Sale_SPEC>;
1779    impl Sale {
1780        #[doc = "Slave arbitration-lost detection is disabled."]
1781        pub const _0: Self = Self::new(0);
1782
1783        #[doc = "Slave arbitration-lost detection is enabled."]
1784        pub const _1: Self = Self::new(1);
1785    }
1786    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1787    pub struct Nale_SPEC;
1788    pub type Nale = crate::EnumBitfieldStruct<u8, Nale_SPEC>;
1789    impl Nale {
1790        #[doc = "NACK transmission arbitration-lost detection is disabled."]
1791        pub const _0: Self = Self::new(0);
1792
1793        #[doc = "NACK transmission arbitration-lost detection is enabled."]
1794        pub const _1: Self = Self::new(1);
1795    }
1796    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1797    pub struct Male_SPEC;
1798    pub type Male = crate::EnumBitfieldStruct<u8, Male_SPEC>;
1799    impl Male {
1800        #[doc = "Master arbitration-lost detection is disabled."]
1801        pub const _0: Self = Self::new(0);
1802
1803        #[doc = "Master arbitration-lost detection is enabled."]
1804        pub const _1: Self = Self::new(1);
1805    }
1806    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1807    pub struct Tmoe_SPEC;
1808    pub type Tmoe = crate::EnumBitfieldStruct<u8, Tmoe_SPEC>;
1809    impl Tmoe {
1810        #[doc = "The timeout function is disabled."]
1811        pub const _0: Self = Self::new(0);
1812
1813        #[doc = "The timeout function is enabled."]
1814        pub const _1: Self = Self::new(1);
1815    }
1816}
1817#[doc(hidden)]
1818#[derive(Copy, Clone, Eq, PartialEq)]
1819pub struct Icser_SPEC;
1820impl crate::sealed::RegSpec for Icser_SPEC {
1821    type DataType = u8;
1822}
1823
1824#[doc = "I2C Bus Status Enable Register"]
1825pub type Icser = crate::RegValueT<Icser_SPEC>;
1826
1827impl Icser {
1828    #[doc = "Host Address Enable"]
1829    #[inline(always)]
1830    pub fn hoae(
1831        self,
1832    ) -> crate::common::RegisterField<
1833        7,
1834        0x1,
1835        1,
1836        0,
1837        icser::Hoae,
1838        icser::Hoae,
1839        Icser_SPEC,
1840        crate::common::RW,
1841    > {
1842        crate::common::RegisterField::<
1843            7,
1844            0x1,
1845            1,
1846            0,
1847            icser::Hoae,
1848            icser::Hoae,
1849            Icser_SPEC,
1850            crate::common::RW,
1851        >::from_register(self, 0)
1852    }
1853
1854    #[doc = "Device-ID Address Detection Enable"]
1855    #[inline(always)]
1856    pub fn dide(
1857        self,
1858    ) -> crate::common::RegisterField<
1859        5,
1860        0x1,
1861        1,
1862        0,
1863        icser::Dide,
1864        icser::Dide,
1865        Icser_SPEC,
1866        crate::common::RW,
1867    > {
1868        crate::common::RegisterField::<
1869            5,
1870            0x1,
1871            1,
1872            0,
1873            icser::Dide,
1874            icser::Dide,
1875            Icser_SPEC,
1876            crate::common::RW,
1877        >::from_register(self, 0)
1878    }
1879
1880    #[doc = "This bit is read as 0. The write value should be 0."]
1881    #[inline(always)]
1882    pub fn reserved(
1883        self,
1884    ) -> crate::common::RegisterFieldBool<4, 1, 0, Icser_SPEC, crate::common::RW> {
1885        crate::common::RegisterFieldBool::<4, 1, 0, Icser_SPEC, crate::common::RW>::from_register(
1886            self, 0,
1887        )
1888    }
1889
1890    #[doc = "General Call Address Enable"]
1891    #[inline(always)]
1892    pub fn gcae(
1893        self,
1894    ) -> crate::common::RegisterField<
1895        3,
1896        0x1,
1897        1,
1898        0,
1899        icser::Gcae,
1900        icser::Gcae,
1901        Icser_SPEC,
1902        crate::common::RW,
1903    > {
1904        crate::common::RegisterField::<
1905            3,
1906            0x1,
1907            1,
1908            0,
1909            icser::Gcae,
1910            icser::Gcae,
1911            Icser_SPEC,
1912            crate::common::RW,
1913        >::from_register(self, 0)
1914    }
1915
1916    #[doc = "Slave Address Register 2 Enable"]
1917    #[inline(always)]
1918    pub fn sar2e(
1919        self,
1920    ) -> crate::common::RegisterField<
1921        2,
1922        0x1,
1923        1,
1924        0,
1925        icser::Sar2E,
1926        icser::Sar2E,
1927        Icser_SPEC,
1928        crate::common::RW,
1929    > {
1930        crate::common::RegisterField::<
1931            2,
1932            0x1,
1933            1,
1934            0,
1935            icser::Sar2E,
1936            icser::Sar2E,
1937            Icser_SPEC,
1938            crate::common::RW,
1939        >::from_register(self, 0)
1940    }
1941
1942    #[doc = "Slave Address Register 1 Enable"]
1943    #[inline(always)]
1944    pub fn sar1e(
1945        self,
1946    ) -> crate::common::RegisterField<
1947        1,
1948        0x1,
1949        1,
1950        0,
1951        icser::Sar1E,
1952        icser::Sar1E,
1953        Icser_SPEC,
1954        crate::common::RW,
1955    > {
1956        crate::common::RegisterField::<
1957            1,
1958            0x1,
1959            1,
1960            0,
1961            icser::Sar1E,
1962            icser::Sar1E,
1963            Icser_SPEC,
1964            crate::common::RW,
1965        >::from_register(self, 0)
1966    }
1967
1968    #[doc = "Slave Address Register 0 Enable"]
1969    #[inline(always)]
1970    pub fn sar0e(
1971        self,
1972    ) -> crate::common::RegisterField<
1973        0,
1974        0x1,
1975        1,
1976        0,
1977        icser::Sar0E,
1978        icser::Sar0E,
1979        Icser_SPEC,
1980        crate::common::RW,
1981    > {
1982        crate::common::RegisterField::<
1983            0,
1984            0x1,
1985            1,
1986            0,
1987            icser::Sar0E,
1988            icser::Sar0E,
1989            Icser_SPEC,
1990            crate::common::RW,
1991        >::from_register(self, 0)
1992    }
1993}
1994impl ::core::default::Default for Icser {
1995    #[inline(always)]
1996    fn default() -> Icser {
1997        <crate::RegValueT<Icser_SPEC> as RegisterValue<_>>::new(9)
1998    }
1999}
2000pub mod icser {
2001
2002    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2003    pub struct Hoae_SPEC;
2004    pub type Hoae = crate::EnumBitfieldStruct<u8, Hoae_SPEC>;
2005    impl Hoae {
2006        #[doc = "Host address detection is disabled."]
2007        pub const _0: Self = Self::new(0);
2008
2009        #[doc = "Host address detection is enabled."]
2010        pub const _1: Self = Self::new(1);
2011    }
2012    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2013    pub struct Dide_SPEC;
2014    pub type Dide = crate::EnumBitfieldStruct<u8, Dide_SPEC>;
2015    impl Dide {
2016        #[doc = "Device-ID address detection is disabled."]
2017        pub const _0: Self = Self::new(0);
2018
2019        #[doc = "Device-ID address detection is enabled."]
2020        pub const _1: Self = Self::new(1);
2021    }
2022    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2023    pub struct Gcae_SPEC;
2024    pub type Gcae = crate::EnumBitfieldStruct<u8, Gcae_SPEC>;
2025    impl Gcae {
2026        #[doc = "General call address detection is disabled."]
2027        pub const _0: Self = Self::new(0);
2028
2029        #[doc = "General call address detection is enabled."]
2030        pub const _1: Self = Self::new(1);
2031    }
2032    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2033    pub struct Sar2E_SPEC;
2034    pub type Sar2E = crate::EnumBitfieldStruct<u8, Sar2E_SPEC>;
2035    impl Sar2E {
2036        #[doc = "Slave address in SARL2 and SARU2 is disabled."]
2037        pub const _0: Self = Self::new(0);
2038
2039        #[doc = "Slave address in SARL2 and SARU2 is enabled"]
2040        pub const _1: Self = Self::new(1);
2041    }
2042    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2043    pub struct Sar1E_SPEC;
2044    pub type Sar1E = crate::EnumBitfieldStruct<u8, Sar1E_SPEC>;
2045    impl Sar1E {
2046        #[doc = "Slave address in SARL1 and SARU1 is disabled."]
2047        pub const _0: Self = Self::new(0);
2048
2049        #[doc = "Slave address in SARL1 and SARU1 is enabled."]
2050        pub const _1: Self = Self::new(1);
2051    }
2052    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2053    pub struct Sar0E_SPEC;
2054    pub type Sar0E = crate::EnumBitfieldStruct<u8, Sar0E_SPEC>;
2055    impl Sar0E {
2056        #[doc = "Slave address in SARL0 and SARU0 is disabled."]
2057        pub const _0: Self = Self::new(0);
2058
2059        #[doc = "Slave address in SARL0 and SARU0 is enabled."]
2060        pub const _1: Self = Self::new(1);
2061    }
2062}
2063#[doc(hidden)]
2064#[derive(Copy, Clone, Eq, PartialEq)]
2065pub struct Icier_SPEC;
2066impl crate::sealed::RegSpec for Icier_SPEC {
2067    type DataType = u8;
2068}
2069
2070#[doc = "I2C Bus Interrupt Enable Register"]
2071pub type Icier = crate::RegValueT<Icier_SPEC>;
2072
2073impl Icier {
2074    #[doc = "Transmit Data Empty Interrupt Request Enable"]
2075    #[inline(always)]
2076    pub fn tie(
2077        self,
2078    ) -> crate::common::RegisterField<
2079        7,
2080        0x1,
2081        1,
2082        0,
2083        icier::Tie,
2084        icier::Tie,
2085        Icier_SPEC,
2086        crate::common::RW,
2087    > {
2088        crate::common::RegisterField::<
2089            7,
2090            0x1,
2091            1,
2092            0,
2093            icier::Tie,
2094            icier::Tie,
2095            Icier_SPEC,
2096            crate::common::RW,
2097        >::from_register(self, 0)
2098    }
2099
2100    #[doc = "Transmit End Interrupt Request  Enable"]
2101    #[inline(always)]
2102    pub fn teie(
2103        self,
2104    ) -> crate::common::RegisterField<
2105        6,
2106        0x1,
2107        1,
2108        0,
2109        icier::Teie,
2110        icier::Teie,
2111        Icier_SPEC,
2112        crate::common::RW,
2113    > {
2114        crate::common::RegisterField::<
2115            6,
2116            0x1,
2117            1,
2118            0,
2119            icier::Teie,
2120            icier::Teie,
2121            Icier_SPEC,
2122            crate::common::RW,
2123        >::from_register(self, 0)
2124    }
2125
2126    #[doc = "Receive Data Full Interrupt Request Enable"]
2127    #[inline(always)]
2128    pub fn rie(
2129        self,
2130    ) -> crate::common::RegisterField<
2131        5,
2132        0x1,
2133        1,
2134        0,
2135        icier::Rie,
2136        icier::Rie,
2137        Icier_SPEC,
2138        crate::common::RW,
2139    > {
2140        crate::common::RegisterField::<
2141            5,
2142            0x1,
2143            1,
2144            0,
2145            icier::Rie,
2146            icier::Rie,
2147            Icier_SPEC,
2148            crate::common::RW,
2149        >::from_register(self, 0)
2150    }
2151
2152    #[doc = "NACK Reception Interrupt Request Enable"]
2153    #[inline(always)]
2154    pub fn nakie(
2155        self,
2156    ) -> crate::common::RegisterField<
2157        4,
2158        0x1,
2159        1,
2160        0,
2161        icier::Nakie,
2162        icier::Nakie,
2163        Icier_SPEC,
2164        crate::common::RW,
2165    > {
2166        crate::common::RegisterField::<
2167            4,
2168            0x1,
2169            1,
2170            0,
2171            icier::Nakie,
2172            icier::Nakie,
2173            Icier_SPEC,
2174            crate::common::RW,
2175        >::from_register(self, 0)
2176    }
2177
2178    #[doc = "Stop Condition Detection Interrupt Request Enable"]
2179    #[inline(always)]
2180    pub fn spie(
2181        self,
2182    ) -> crate::common::RegisterField<
2183        3,
2184        0x1,
2185        1,
2186        0,
2187        icier::Spie,
2188        icier::Spie,
2189        Icier_SPEC,
2190        crate::common::RW,
2191    > {
2192        crate::common::RegisterField::<
2193            3,
2194            0x1,
2195            1,
2196            0,
2197            icier::Spie,
2198            icier::Spie,
2199            Icier_SPEC,
2200            crate::common::RW,
2201        >::from_register(self, 0)
2202    }
2203
2204    #[doc = "Start Condition Detection Interrupt Request Enable"]
2205    #[inline(always)]
2206    pub fn stie(
2207        self,
2208    ) -> crate::common::RegisterField<
2209        2,
2210        0x1,
2211        1,
2212        0,
2213        icier::Stie,
2214        icier::Stie,
2215        Icier_SPEC,
2216        crate::common::RW,
2217    > {
2218        crate::common::RegisterField::<
2219            2,
2220            0x1,
2221            1,
2222            0,
2223            icier::Stie,
2224            icier::Stie,
2225            Icier_SPEC,
2226            crate::common::RW,
2227        >::from_register(self, 0)
2228    }
2229
2230    #[doc = "Arbitration-Lost Interrupt Request Enable"]
2231    #[inline(always)]
2232    pub fn alie(
2233        self,
2234    ) -> crate::common::RegisterField<
2235        1,
2236        0x1,
2237        1,
2238        0,
2239        icier::Alie,
2240        icier::Alie,
2241        Icier_SPEC,
2242        crate::common::RW,
2243    > {
2244        crate::common::RegisterField::<
2245            1,
2246            0x1,
2247            1,
2248            0,
2249            icier::Alie,
2250            icier::Alie,
2251            Icier_SPEC,
2252            crate::common::RW,
2253        >::from_register(self, 0)
2254    }
2255
2256    #[doc = "Timeout Interrupt Request Enable"]
2257    #[inline(always)]
2258    pub fn tmoie(
2259        self,
2260    ) -> crate::common::RegisterField<
2261        0,
2262        0x1,
2263        1,
2264        0,
2265        icier::Tmoie,
2266        icier::Tmoie,
2267        Icier_SPEC,
2268        crate::common::RW,
2269    > {
2270        crate::common::RegisterField::<
2271            0,
2272            0x1,
2273            1,
2274            0,
2275            icier::Tmoie,
2276            icier::Tmoie,
2277            Icier_SPEC,
2278            crate::common::RW,
2279        >::from_register(self, 0)
2280    }
2281}
2282impl ::core::default::Default for Icier {
2283    #[inline(always)]
2284    fn default() -> Icier {
2285        <crate::RegValueT<Icier_SPEC> as RegisterValue<_>>::new(0)
2286    }
2287}
2288pub mod icier {
2289
2290    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2291    pub struct Tie_SPEC;
2292    pub type Tie = crate::EnumBitfieldStruct<u8, Tie_SPEC>;
2293    impl Tie {
2294        #[doc = "Transmit data empty interrupt request (IICn_TXI) is disabled."]
2295        pub const _0: Self = Self::new(0);
2296
2297        #[doc = "Transmit data empty interrupt request (IICn_TXI) is enabled."]
2298        pub const _1: Self = Self::new(1);
2299    }
2300    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2301    pub struct Teie_SPEC;
2302    pub type Teie = crate::EnumBitfieldStruct<u8, Teie_SPEC>;
2303    impl Teie {
2304        #[doc = "Transmit end interrupt request (IICn_TEI) is disabled."]
2305        pub const _0: Self = Self::new(0);
2306
2307        #[doc = "Transmit end interrupt request (IICn_TEI) is enabled."]
2308        pub const _1: Self = Self::new(1);
2309    }
2310    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2311    pub struct Rie_SPEC;
2312    pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
2313    impl Rie {
2314        #[doc = "Receive data full interrupt request (IICn_RXI) is disabled."]
2315        pub const _0: Self = Self::new(0);
2316
2317        #[doc = "Receive data full interrupt request (IICn_RXI) is enabled."]
2318        pub const _1: Self = Self::new(1);
2319    }
2320    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2321    pub struct Nakie_SPEC;
2322    pub type Nakie = crate::EnumBitfieldStruct<u8, Nakie_SPEC>;
2323    impl Nakie {
2324        #[doc = "NACK reception interrupt request (NAKI) is disabled."]
2325        pub const _0: Self = Self::new(0);
2326
2327        #[doc = "NACK reception interrupt request (NAKI) is enabled."]
2328        pub const _1: Self = Self::new(1);
2329    }
2330    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2331    pub struct Spie_SPEC;
2332    pub type Spie = crate::EnumBitfieldStruct<u8, Spie_SPEC>;
2333    impl Spie {
2334        #[doc = "Stop condition detection interrupt request (SPI) is disabled."]
2335        pub const _0: Self = Self::new(0);
2336
2337        #[doc = "Stop condition detection interrupt request (SPI) is enabled."]
2338        pub const _1: Self = Self::new(1);
2339    }
2340    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2341    pub struct Stie_SPEC;
2342    pub type Stie = crate::EnumBitfieldStruct<u8, Stie_SPEC>;
2343    impl Stie {
2344        #[doc = "Start condition detection interrupt request (STI) is disabled."]
2345        pub const _0: Self = Self::new(0);
2346
2347        #[doc = "Start condition detection interrupt request (STI) is enabled."]
2348        pub const _1: Self = Self::new(1);
2349    }
2350    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2351    pub struct Alie_SPEC;
2352    pub type Alie = crate::EnumBitfieldStruct<u8, Alie_SPEC>;
2353    impl Alie {
2354        #[doc = "Arbitration-lost interrupt request (ALI) is disabled."]
2355        pub const _0: Self = Self::new(0);
2356
2357        #[doc = "Arbitration-lost interrupt request (ALI) is enabled."]
2358        pub const _1: Self = Self::new(1);
2359    }
2360    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2361    pub struct Tmoie_SPEC;
2362    pub type Tmoie = crate::EnumBitfieldStruct<u8, Tmoie_SPEC>;
2363    impl Tmoie {
2364        #[doc = "Timeout interrupt request (TMOI) is disabled."]
2365        pub const _0: Self = Self::new(0);
2366
2367        #[doc = "Timeout interrupt request (TMOI) is enabled."]
2368        pub const _1: Self = Self::new(1);
2369    }
2370}
2371#[doc(hidden)]
2372#[derive(Copy, Clone, Eq, PartialEq)]
2373pub struct Icsr1_SPEC;
2374impl crate::sealed::RegSpec for Icsr1_SPEC {
2375    type DataType = u8;
2376}
2377
2378#[doc = "I2C Bus Status Register 1"]
2379pub type Icsr1 = crate::RegValueT<Icsr1_SPEC>;
2380
2381impl Icsr1 {
2382    #[doc = "Host Address Detection Flag"]
2383    #[inline(always)]
2384    pub fn hoa(
2385        self,
2386    ) -> crate::common::RegisterField<
2387        7,
2388        0x1,
2389        1,
2390        0,
2391        icsr1::Hoa,
2392        icsr1::Hoa,
2393        Icsr1_SPEC,
2394        crate::common::RW,
2395    > {
2396        crate::common::RegisterField::<
2397            7,
2398            0x1,
2399            1,
2400            0,
2401            icsr1::Hoa,
2402            icsr1::Hoa,
2403            Icsr1_SPEC,
2404            crate::common::RW,
2405        >::from_register(self, 0)
2406    }
2407
2408    #[doc = "Device-ID Address Detection Flag"]
2409    #[inline(always)]
2410    pub fn did(
2411        self,
2412    ) -> crate::common::RegisterField<
2413        5,
2414        0x1,
2415        1,
2416        0,
2417        icsr1::Did,
2418        icsr1::Did,
2419        Icsr1_SPEC,
2420        crate::common::RW,
2421    > {
2422        crate::common::RegisterField::<
2423            5,
2424            0x1,
2425            1,
2426            0,
2427            icsr1::Did,
2428            icsr1::Did,
2429            Icsr1_SPEC,
2430            crate::common::RW,
2431        >::from_register(self, 0)
2432    }
2433
2434    #[doc = "This bit is read as 0. The write value should be 0."]
2435    #[inline(always)]
2436    pub fn reserved(
2437        self,
2438    ) -> crate::common::RegisterFieldBool<4, 1, 0, Icsr1_SPEC, crate::common::RW> {
2439        crate::common::RegisterFieldBool::<4, 1, 0, Icsr1_SPEC, crate::common::RW>::from_register(
2440            self, 0,
2441        )
2442    }
2443
2444    #[doc = "General Call Address Detection Flag"]
2445    #[inline(always)]
2446    pub fn gca(
2447        self,
2448    ) -> crate::common::RegisterField<
2449        3,
2450        0x1,
2451        1,
2452        0,
2453        icsr1::Gca,
2454        icsr1::Gca,
2455        Icsr1_SPEC,
2456        crate::common::RW,
2457    > {
2458        crate::common::RegisterField::<
2459            3,
2460            0x1,
2461            1,
2462            0,
2463            icsr1::Gca,
2464            icsr1::Gca,
2465            Icsr1_SPEC,
2466            crate::common::RW,
2467        >::from_register(self, 0)
2468    }
2469
2470    #[doc = "Slave Address 2 Detection Flag"]
2471    #[inline(always)]
2472    pub fn aas2(
2473        self,
2474    ) -> crate::common::RegisterField<
2475        2,
2476        0x1,
2477        1,
2478        0,
2479        icsr1::Aas2,
2480        icsr1::Aas2,
2481        Icsr1_SPEC,
2482        crate::common::RW,
2483    > {
2484        crate::common::RegisterField::<
2485            2,
2486            0x1,
2487            1,
2488            0,
2489            icsr1::Aas2,
2490            icsr1::Aas2,
2491            Icsr1_SPEC,
2492            crate::common::RW,
2493        >::from_register(self, 0)
2494    }
2495
2496    #[doc = "Slave Address 1 Detection Flag"]
2497    #[inline(always)]
2498    pub fn aas1(
2499        self,
2500    ) -> crate::common::RegisterField<
2501        1,
2502        0x1,
2503        1,
2504        0,
2505        icsr1::Aas1,
2506        icsr1::Aas1,
2507        Icsr1_SPEC,
2508        crate::common::RW,
2509    > {
2510        crate::common::RegisterField::<
2511            1,
2512            0x1,
2513            1,
2514            0,
2515            icsr1::Aas1,
2516            icsr1::Aas1,
2517            Icsr1_SPEC,
2518            crate::common::RW,
2519        >::from_register(self, 0)
2520    }
2521
2522    #[doc = "Slave Address 0 Detection Flag"]
2523    #[inline(always)]
2524    pub fn aas0(
2525        self,
2526    ) -> crate::common::RegisterField<
2527        0,
2528        0x1,
2529        1,
2530        0,
2531        icsr1::Aas0,
2532        icsr1::Aas0,
2533        Icsr1_SPEC,
2534        crate::common::RW,
2535    > {
2536        crate::common::RegisterField::<
2537            0,
2538            0x1,
2539            1,
2540            0,
2541            icsr1::Aas0,
2542            icsr1::Aas0,
2543            Icsr1_SPEC,
2544            crate::common::RW,
2545        >::from_register(self, 0)
2546    }
2547}
2548impl ::core::default::Default for Icsr1 {
2549    #[inline(always)]
2550    fn default() -> Icsr1 {
2551        <crate::RegValueT<Icsr1_SPEC> as RegisterValue<_>>::new(0)
2552    }
2553}
2554pub mod icsr1 {
2555
2556    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2557    pub struct Hoa_SPEC;
2558    pub type Hoa = crate::EnumBitfieldStruct<u8, Hoa_SPEC>;
2559    impl Hoa {
2560        #[doc = "Host address is not detected."]
2561        pub const _0: Self = Self::new(0);
2562
2563        #[doc = "Host address is detected."]
2564        pub const _1: Self = Self::new(1);
2565    }
2566    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2567    pub struct Did_SPEC;
2568    pub type Did = crate::EnumBitfieldStruct<u8, Did_SPEC>;
2569    impl Did {
2570        #[doc = "Device-ID command is not detected."]
2571        pub const _0: Self = Self::new(0);
2572
2573        #[doc = "Device-ID command is detected."]
2574        pub const _1: Self = Self::new(1);
2575    }
2576    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2577    pub struct Gca_SPEC;
2578    pub type Gca = crate::EnumBitfieldStruct<u8, Gca_SPEC>;
2579    impl Gca {
2580        #[doc = "General call address is not detected."]
2581        pub const _0: Self = Self::new(0);
2582
2583        #[doc = "General call address is detected."]
2584        pub const _1: Self = Self::new(1);
2585    }
2586    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2587    pub struct Aas2_SPEC;
2588    pub type Aas2 = crate::EnumBitfieldStruct<u8, Aas2_SPEC>;
2589    impl Aas2 {
2590        #[doc = "Slave address 2 is not detected."]
2591        pub const _0: Self = Self::new(0);
2592
2593        #[doc = "Slave address 2 is detected"]
2594        pub const _1: Self = Self::new(1);
2595    }
2596    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2597    pub struct Aas1_SPEC;
2598    pub type Aas1 = crate::EnumBitfieldStruct<u8, Aas1_SPEC>;
2599    impl Aas1 {
2600        #[doc = "Slave address 1 is not detected."]
2601        pub const _0: Self = Self::new(0);
2602
2603        #[doc = "Slave address 1 is detected."]
2604        pub const _1: Self = Self::new(1);
2605    }
2606    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2607    pub struct Aas0_SPEC;
2608    pub type Aas0 = crate::EnumBitfieldStruct<u8, Aas0_SPEC>;
2609    impl Aas0 {
2610        #[doc = "Slave address 0 is not detected."]
2611        pub const _0: Self = Self::new(0);
2612
2613        #[doc = "Slave address 0 is detected."]
2614        pub const _1: Self = Self::new(1);
2615    }
2616}
2617#[doc(hidden)]
2618#[derive(Copy, Clone, Eq, PartialEq)]
2619pub struct Icsr2_SPEC;
2620impl crate::sealed::RegSpec for Icsr2_SPEC {
2621    type DataType = u8;
2622}
2623
2624#[doc = "I2C Bus Status Register 2"]
2625pub type Icsr2 = crate::RegValueT<Icsr2_SPEC>;
2626
2627impl Icsr2 {
2628    #[doc = "Transmit Data Empty Flag"]
2629    #[inline(always)]
2630    pub fn tdre(
2631        self,
2632    ) -> crate::common::RegisterField<
2633        7,
2634        0x1,
2635        1,
2636        0,
2637        icsr2::Tdre,
2638        icsr2::Tdre,
2639        Icsr2_SPEC,
2640        crate::common::R,
2641    > {
2642        crate::common::RegisterField::<
2643            7,
2644            0x1,
2645            1,
2646            0,
2647            icsr2::Tdre,
2648            icsr2::Tdre,
2649            Icsr2_SPEC,
2650            crate::common::R,
2651        >::from_register(self, 0)
2652    }
2653
2654    #[doc = "Transmit End Flag"]
2655    #[inline(always)]
2656    pub fn tend(
2657        self,
2658    ) -> crate::common::RegisterField<
2659        6,
2660        0x1,
2661        1,
2662        0,
2663        icsr2::Tend,
2664        icsr2::Tend,
2665        Icsr2_SPEC,
2666        crate::common::RW,
2667    > {
2668        crate::common::RegisterField::<
2669            6,
2670            0x1,
2671            1,
2672            0,
2673            icsr2::Tend,
2674            icsr2::Tend,
2675            Icsr2_SPEC,
2676            crate::common::RW,
2677        >::from_register(self, 0)
2678    }
2679
2680    #[doc = "Receive Data Full Flag"]
2681    #[inline(always)]
2682    pub fn rdrf(
2683        self,
2684    ) -> crate::common::RegisterField<
2685        5,
2686        0x1,
2687        1,
2688        0,
2689        icsr2::Rdrf,
2690        icsr2::Rdrf,
2691        Icsr2_SPEC,
2692        crate::common::RW,
2693    > {
2694        crate::common::RegisterField::<
2695            5,
2696            0x1,
2697            1,
2698            0,
2699            icsr2::Rdrf,
2700            icsr2::Rdrf,
2701            Icsr2_SPEC,
2702            crate::common::RW,
2703        >::from_register(self, 0)
2704    }
2705
2706    #[doc = "NACK Detection Flag"]
2707    #[inline(always)]
2708    pub fn nackf(
2709        self,
2710    ) -> crate::common::RegisterField<
2711        4,
2712        0x1,
2713        1,
2714        0,
2715        icsr2::Nackf,
2716        icsr2::Nackf,
2717        Icsr2_SPEC,
2718        crate::common::RW,
2719    > {
2720        crate::common::RegisterField::<
2721            4,
2722            0x1,
2723            1,
2724            0,
2725            icsr2::Nackf,
2726            icsr2::Nackf,
2727            Icsr2_SPEC,
2728            crate::common::RW,
2729        >::from_register(self, 0)
2730    }
2731
2732    #[doc = "Stop Condition Detection Flag"]
2733    #[inline(always)]
2734    pub fn stop(
2735        self,
2736    ) -> crate::common::RegisterField<
2737        3,
2738        0x1,
2739        1,
2740        0,
2741        icsr2::Stop,
2742        icsr2::Stop,
2743        Icsr2_SPEC,
2744        crate::common::RW,
2745    > {
2746        crate::common::RegisterField::<
2747            3,
2748            0x1,
2749            1,
2750            0,
2751            icsr2::Stop,
2752            icsr2::Stop,
2753            Icsr2_SPEC,
2754            crate::common::RW,
2755        >::from_register(self, 0)
2756    }
2757
2758    #[doc = "Start Condition Detection Flag"]
2759    #[inline(always)]
2760    pub fn start(
2761        self,
2762    ) -> crate::common::RegisterField<
2763        2,
2764        0x1,
2765        1,
2766        0,
2767        icsr2::Start,
2768        icsr2::Start,
2769        Icsr2_SPEC,
2770        crate::common::RW,
2771    > {
2772        crate::common::RegisterField::<
2773            2,
2774            0x1,
2775            1,
2776            0,
2777            icsr2::Start,
2778            icsr2::Start,
2779            Icsr2_SPEC,
2780            crate::common::RW,
2781        >::from_register(self, 0)
2782    }
2783
2784    #[doc = "Arbitration-Lost Flag"]
2785    #[inline(always)]
2786    pub fn al(
2787        self,
2788    ) -> crate::common::RegisterField<
2789        1,
2790        0x1,
2791        1,
2792        0,
2793        icsr2::Al,
2794        icsr2::Al,
2795        Icsr2_SPEC,
2796        crate::common::RW,
2797    > {
2798        crate::common::RegisterField::<
2799            1,
2800            0x1,
2801            1,
2802            0,
2803            icsr2::Al,
2804            icsr2::Al,
2805            Icsr2_SPEC,
2806            crate::common::RW,
2807        >::from_register(self, 0)
2808    }
2809
2810    #[doc = "Timeout Detection Flag"]
2811    #[inline(always)]
2812    pub fn tmof(
2813        self,
2814    ) -> crate::common::RegisterField<
2815        0,
2816        0x1,
2817        1,
2818        0,
2819        icsr2::Tmof,
2820        icsr2::Tmof,
2821        Icsr2_SPEC,
2822        crate::common::RW,
2823    > {
2824        crate::common::RegisterField::<
2825            0,
2826            0x1,
2827            1,
2828            0,
2829            icsr2::Tmof,
2830            icsr2::Tmof,
2831            Icsr2_SPEC,
2832            crate::common::RW,
2833        >::from_register(self, 0)
2834    }
2835}
2836impl ::core::default::Default for Icsr2 {
2837    #[inline(always)]
2838    fn default() -> Icsr2 {
2839        <crate::RegValueT<Icsr2_SPEC> as RegisterValue<_>>::new(0)
2840    }
2841}
2842pub mod icsr2 {
2843
2844    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2845    pub struct Tdre_SPEC;
2846    pub type Tdre = crate::EnumBitfieldStruct<u8, Tdre_SPEC>;
2847    impl Tdre {
2848        #[doc = "ICDRT contains transmit data."]
2849        pub const _0: Self = Self::new(0);
2850
2851        #[doc = "ICDRT contains no transmit data."]
2852        pub const _1: Self = Self::new(1);
2853    }
2854    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2855    pub struct Tend_SPEC;
2856    pub type Tend = crate::EnumBitfieldStruct<u8, Tend_SPEC>;
2857    impl Tend {
2858        #[doc = "Data is being transmitted."]
2859        pub const _0: Self = Self::new(0);
2860
2861        #[doc = "Data has been transmitted."]
2862        pub const _1: Self = Self::new(1);
2863    }
2864    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2865    pub struct Rdrf_SPEC;
2866    pub type Rdrf = crate::EnumBitfieldStruct<u8, Rdrf_SPEC>;
2867    impl Rdrf {
2868        #[doc = "ICDRR contains no receive data."]
2869        pub const _0: Self = Self::new(0);
2870
2871        #[doc = "ICDRR contains receive data."]
2872        pub const _1: Self = Self::new(1);
2873    }
2874    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2875    pub struct Nackf_SPEC;
2876    pub type Nackf = crate::EnumBitfieldStruct<u8, Nackf_SPEC>;
2877    impl Nackf {
2878        #[doc = "NACK is not detected."]
2879        pub const _0: Self = Self::new(0);
2880
2881        #[doc = "NACK is detected."]
2882        pub const _1: Self = Self::new(1);
2883    }
2884    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2885    pub struct Stop_SPEC;
2886    pub type Stop = crate::EnumBitfieldStruct<u8, Stop_SPEC>;
2887    impl Stop {
2888        #[doc = "Stop condition is not detected."]
2889        pub const _0: Self = Self::new(0);
2890
2891        #[doc = "Stop condition is detected."]
2892        pub const _1: Self = Self::new(1);
2893    }
2894    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2895    pub struct Start_SPEC;
2896    pub type Start = crate::EnumBitfieldStruct<u8, Start_SPEC>;
2897    impl Start {
2898        #[doc = "Start condition is not detected."]
2899        pub const _0: Self = Self::new(0);
2900
2901        #[doc = "Start condition is detected."]
2902        pub const _1: Self = Self::new(1);
2903    }
2904    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2905    pub struct Al_SPEC;
2906    pub type Al = crate::EnumBitfieldStruct<u8, Al_SPEC>;
2907    impl Al {
2908        #[doc = "Arbitration is not lost."]
2909        pub const _0: Self = Self::new(0);
2910
2911        #[doc = "Arbitration is lost."]
2912        pub const _1: Self = Self::new(1);
2913    }
2914    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2915    pub struct Tmof_SPEC;
2916    pub type Tmof = crate::EnumBitfieldStruct<u8, Tmof_SPEC>;
2917    impl Tmof {
2918        #[doc = "Timeout is not detected."]
2919        pub const _0: Self = Self::new(0);
2920
2921        #[doc = "Timeout is detected."]
2922        pub const _1: Self = Self::new(1);
2923    }
2924}
2925#[doc(hidden)]
2926#[derive(Copy, Clone, Eq, PartialEq)]
2927pub struct Sarl_SPEC;
2928impl crate::sealed::RegSpec for Sarl_SPEC {
2929    type DataType = u8;
2930}
2931
2932#[doc = "Slave Address Register L%s"]
2933pub type Sarl = crate::RegValueT<Sarl_SPEC>;
2934
2935impl Sarl {
2936    #[doc = "A slave address is set.7-Bit Address = SVA\\[7:1\\] 10-Bit Address = { SVA9,SVA8,SVA\\[7:0\\] }"]
2937    #[inline(always)]
2938    pub fn sva(
2939        self,
2940    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Sarl_SPEC, crate::common::RW> {
2941        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Sarl_SPEC,crate::common::RW>::from_register(self,0)
2942    }
2943}
2944impl ::core::default::Default for Sarl {
2945    #[inline(always)]
2946    fn default() -> Sarl {
2947        <crate::RegValueT<Sarl_SPEC> as RegisterValue<_>>::new(0)
2948    }
2949}
2950
2951#[doc(hidden)]
2952#[derive(Copy, Clone, Eq, PartialEq)]
2953pub struct Saru_SPEC;
2954impl crate::sealed::RegSpec for Saru_SPEC {
2955    type DataType = u8;
2956}
2957
2958#[doc = "Slave Address Register U%s"]
2959pub type Saru = crate::RegValueT<Saru_SPEC>;
2960
2961impl Saru {
2962    #[doc = "These bits are read as 00000. The write value should be 00000."]
2963    #[inline(always)]
2964    pub fn reserved(
2965        self,
2966    ) -> crate::common::RegisterField<3, 0x1f, 1, 0, u8, u8, Saru_SPEC, crate::common::RW> {
2967        crate::common::RegisterField::<3,0x1f,1,0,u8,u8,Saru_SPEC,crate::common::RW>::from_register(self,0)
2968    }
2969
2970    #[doc = "10-Bit Address(bit9)"]
2971    #[inline(always)]
2972    pub fn sva9(self) -> crate::common::RegisterFieldBool<2, 1, 0, Saru_SPEC, crate::common::RW> {
2973        crate::common::RegisterFieldBool::<2, 1, 0, Saru_SPEC, crate::common::RW>::from_register(
2974            self, 0,
2975        )
2976    }
2977
2978    #[doc = "10-Bit Address(bit8)"]
2979    #[inline(always)]
2980    pub fn sva8(self) -> crate::common::RegisterFieldBool<1, 1, 0, Saru_SPEC, crate::common::RW> {
2981        crate::common::RegisterFieldBool::<1, 1, 0, Saru_SPEC, crate::common::RW>::from_register(
2982            self, 0,
2983        )
2984    }
2985
2986    #[doc = "7-Bit/10-Bit Address Format Selection"]
2987    #[inline(always)]
2988    pub fn fs(
2989        self,
2990    ) -> crate::common::RegisterField<0, 0x1, 1, 0, saru::Fs, saru::Fs, Saru_SPEC, crate::common::RW>
2991    {
2992        crate::common::RegisterField::<0,0x1,1,0,saru::Fs,saru::Fs,Saru_SPEC,crate::common::RW>::from_register(self,0)
2993    }
2994}
2995impl ::core::default::Default for Saru {
2996    #[inline(always)]
2997    fn default() -> Saru {
2998        <crate::RegValueT<Saru_SPEC> as RegisterValue<_>>::new(0)
2999    }
3000}
3001pub mod saru {
3002
3003    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3004    pub struct Fs_SPEC;
3005    pub type Fs = crate::EnumBitfieldStruct<u8, Fs_SPEC>;
3006    impl Fs {
3007        #[doc = "The 7-bit address format is selected."]
3008        pub const _0: Self = Self::new(0);
3009
3010        #[doc = "The 10-bit address format is selected."]
3011        pub const _1: Self = Self::new(1);
3012    }
3013}
3014#[doc(hidden)]
3015#[derive(Copy, Clone, Eq, PartialEq)]
3016pub struct Icbrl_SPEC;
3017impl crate::sealed::RegSpec for Icbrl_SPEC {
3018    type DataType = u8;
3019}
3020
3021#[doc = "I2C Bus Bit Rate Low-Level Register"]
3022pub type Icbrl = crate::RegValueT<Icbrl_SPEC>;
3023
3024impl Icbrl {
3025    #[doc = "These bits are read as 111. The write value should be 111."]
3026    #[inline(always)]
3027    pub fn reserved(
3028        self,
3029    ) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, Icbrl_SPEC, crate::common::RW> {
3030        crate::common::RegisterField::<5,0x7,1,0,u8,u8,Icbrl_SPEC,crate::common::RW>::from_register(self,0)
3031    }
3032
3033    #[doc = "Bit Rate Low-Level Period(Low-level period of SCL clock)"]
3034    #[inline(always)]
3035    pub fn brl(
3036        self,
3037    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Icbrl_SPEC, crate::common::RW> {
3038        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Icbrl_SPEC,crate::common::RW>::from_register(self,0)
3039    }
3040}
3041impl ::core::default::Default for Icbrl {
3042    #[inline(always)]
3043    fn default() -> Icbrl {
3044        <crate::RegValueT<Icbrl_SPEC> as RegisterValue<_>>::new(255)
3045    }
3046}
3047
3048#[doc(hidden)]
3049#[derive(Copy, Clone, Eq, PartialEq)]
3050pub struct Icbrh_SPEC;
3051impl crate::sealed::RegSpec for Icbrh_SPEC {
3052    type DataType = u8;
3053}
3054
3055#[doc = "I2C Bus Bit Rate High-Level Register"]
3056pub type Icbrh = crate::RegValueT<Icbrh_SPEC>;
3057
3058impl Icbrh {
3059    #[doc = "These bits are read as 111. The write value should be 111."]
3060    #[inline(always)]
3061    pub fn reserved(
3062        self,
3063    ) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, Icbrh_SPEC, crate::common::RW> {
3064        crate::common::RegisterField::<5,0x7,1,0,u8,u8,Icbrh_SPEC,crate::common::RW>::from_register(self,0)
3065    }
3066
3067    #[doc = "Bit Rate High-Level Period(High-level period of SCL clock)"]
3068    #[inline(always)]
3069    pub fn brh(
3070        self,
3071    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Icbrh_SPEC, crate::common::RW> {
3072        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Icbrh_SPEC,crate::common::RW>::from_register(self,0)
3073    }
3074}
3075impl ::core::default::Default for Icbrh {
3076    #[inline(always)]
3077    fn default() -> Icbrh {
3078        <crate::RegValueT<Icbrh_SPEC> as RegisterValue<_>>::new(255)
3079    }
3080}
3081
3082#[doc(hidden)]
3083#[derive(Copy, Clone, Eq, PartialEq)]
3084pub struct Icdrt_SPEC;
3085impl crate::sealed::RegSpec for Icdrt_SPEC {
3086    type DataType = u8;
3087}
3088
3089#[doc = "I2C Bus Transmit Data Register"]
3090pub type Icdrt = crate::RegValueT<Icdrt_SPEC>;
3091
3092impl Icdrt {
3093    #[doc = "8-bit read-write register that stores transmit data."]
3094    #[inline(always)]
3095    pub fn icdrt(
3096        self,
3097    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Icdrt_SPEC, crate::common::RW> {
3098        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Icdrt_SPEC,crate::common::RW>::from_register(self,0)
3099    }
3100}
3101impl ::core::default::Default for Icdrt {
3102    #[inline(always)]
3103    fn default() -> Icdrt {
3104        <crate::RegValueT<Icdrt_SPEC> as RegisterValue<_>>::new(255)
3105    }
3106}
3107
3108#[doc(hidden)]
3109#[derive(Copy, Clone, Eq, PartialEq)]
3110pub struct Icdrr_SPEC;
3111impl crate::sealed::RegSpec for Icdrr_SPEC {
3112    type DataType = u8;
3113}
3114
3115#[doc = "I2C Bus Receive Data Register"]
3116pub type Icdrr = crate::RegValueT<Icdrr_SPEC>;
3117
3118impl Icdrr {
3119    #[doc = "8-bit register that stores the received data"]
3120    #[inline(always)]
3121    pub fn icdrr(
3122        self,
3123    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Icdrr_SPEC, crate::common::R> {
3124        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Icdrr_SPEC,crate::common::R>::from_register(self,0)
3125    }
3126}
3127impl ::core::default::Default for Icdrr {
3128    #[inline(always)]
3129    fn default() -> Icdrr {
3130        <crate::RegValueT<Icdrr_SPEC> as RegisterValue<_>>::new(0)
3131    }
3132}
3133
3134#[doc(hidden)]
3135#[derive(Copy, Clone, Eq, PartialEq)]
3136pub struct Icwur_SPEC;
3137impl crate::sealed::RegSpec for Icwur_SPEC {
3138    type DataType = u8;
3139}
3140
3141#[doc = "I2C Bus Wake Up Unit Register"]
3142pub type Icwur = crate::RegValueT<Icwur_SPEC>;
3143
3144impl Icwur {
3145    #[doc = "Wake Up function Enable"]
3146    #[inline(always)]
3147    pub fn wue(
3148        self,
3149    ) -> crate::common::RegisterField<
3150        7,
3151        0x1,
3152        1,
3153        0,
3154        icwur::Wue,
3155        icwur::Wue,
3156        Icwur_SPEC,
3157        crate::common::RW,
3158    > {
3159        crate::common::RegisterField::<
3160            7,
3161            0x1,
3162            1,
3163            0,
3164            icwur::Wue,
3165            icwur::Wue,
3166            Icwur_SPEC,
3167            crate::common::RW,
3168        >::from_register(self, 0)
3169    }
3170
3171    #[doc = "Wake Up Interrupt Request Enable"]
3172    #[inline(always)]
3173    pub fn wuie(
3174        self,
3175    ) -> crate::common::RegisterField<
3176        6,
3177        0x1,
3178        1,
3179        0,
3180        icwur::Wuie,
3181        icwur::Wuie,
3182        Icwur_SPEC,
3183        crate::common::RW,
3184    > {
3185        crate::common::RegisterField::<
3186            6,
3187            0x1,
3188            1,
3189            0,
3190            icwur::Wuie,
3191            icwur::Wuie,
3192            Icwur_SPEC,
3193            crate::common::RW,
3194        >::from_register(self, 0)
3195    }
3196
3197    #[doc = "Wake-Up Event Occurrence Flag"]
3198    #[inline(always)]
3199    pub fn wuf(
3200        self,
3201    ) -> crate::common::RegisterField<
3202        5,
3203        0x1,
3204        1,
3205        0,
3206        icwur::Wuf,
3207        icwur::Wuf,
3208        Icwur_SPEC,
3209        crate::common::RW,
3210    > {
3211        crate::common::RegisterField::<
3212            5,
3213            0x1,
3214            1,
3215            0,
3216            icwur::Wuf,
3217            icwur::Wuf,
3218            Icwur_SPEC,
3219            crate::common::RW,
3220        >::from_register(self, 0)
3221    }
3222
3223    #[doc = "Asynchronous/Synchronous Operation State Flag"]
3224    #[inline(always)]
3225    pub fn wuack(
3226        self,
3227    ) -> crate::common::RegisterField<
3228        4,
3229        0x1,
3230        1,
3231        0,
3232        icwur::Wuack,
3233        icwur::Wuack,
3234        Icwur_SPEC,
3235        crate::common::RW,
3236    > {
3237        crate::common::RegisterField::<
3238            4,
3239            0x1,
3240            1,
3241            0,
3242            icwur::Wuack,
3243            icwur::Wuack,
3244            Icwur_SPEC,
3245            crate::common::RW,
3246        >::from_register(self, 0)
3247    }
3248
3249    #[doc = "These bits are read as 000. The write value should be 000."]
3250    #[inline(always)]
3251    pub fn reserved(
3252        self,
3253    ) -> crate::common::RegisterField<1, 0x7, 1, 0, u8, u8, Icwur_SPEC, crate::common::RW> {
3254        crate::common::RegisterField::<1,0x7,1,0,u8,u8,Icwur_SPEC,crate::common::RW>::from_register(self,0)
3255    }
3256
3257    #[doc = "Wake-Up Analog Filter Additional Selection"]
3258    #[inline(always)]
3259    pub fn wuafa(
3260        self,
3261    ) -> crate::common::RegisterField<
3262        0,
3263        0x1,
3264        1,
3265        0,
3266        icwur::Wuafa,
3267        icwur::Wuafa,
3268        Icwur_SPEC,
3269        crate::common::RW,
3270    > {
3271        crate::common::RegisterField::<
3272            0,
3273            0x1,
3274            1,
3275            0,
3276            icwur::Wuafa,
3277            icwur::Wuafa,
3278            Icwur_SPEC,
3279            crate::common::RW,
3280        >::from_register(self, 0)
3281    }
3282}
3283impl ::core::default::Default for Icwur {
3284    #[inline(always)]
3285    fn default() -> Icwur {
3286        <crate::RegValueT<Icwur_SPEC> as RegisterValue<_>>::new(16)
3287    }
3288}
3289pub mod icwur {
3290
3291    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3292    pub struct Wue_SPEC;
3293    pub type Wue = crate::EnumBitfieldStruct<u8, Wue_SPEC>;
3294    impl Wue {
3295        #[doc = "Wake-up function is disabled"]
3296        pub const _0: Self = Self::new(0);
3297
3298        #[doc = "Wake-up function is enabled."]
3299        pub const _1: Self = Self::new(1);
3300    }
3301    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3302    pub struct Wuie_SPEC;
3303    pub type Wuie = crate::EnumBitfieldStruct<u8, Wuie_SPEC>;
3304    impl Wuie {
3305        #[doc = "Wake Up Interrupt Request (WUI) is disabled."]
3306        pub const _0: Self = Self::new(0);
3307
3308        #[doc = "Wake Up Interrupt Request (WUI) is enabled."]
3309        pub const _1: Self = Self::new(1);
3310    }
3311    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3312    pub struct Wuf_SPEC;
3313    pub type Wuf = crate::EnumBitfieldStruct<u8, Wuf_SPEC>;
3314    impl Wuf {
3315        #[doc = "Wake-Up event does not occur"]
3316        pub const _0: Self = Self::new(0);
3317
3318        #[doc = "Wake-Up event occur."]
3319        pub const _1: Self = Self::new(1);
3320    }
3321    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3322    pub struct Wuack_SPEC;
3323    pub type Wuack = crate::EnumBitfieldStruct<u8, Wuack_SPEC>;
3324    impl Wuack {
3325        #[doc = "State of synchronous operation"]
3326        pub const _0: Self = Self::new(0);
3327
3328        #[doc = "State of asynchronous operation"]
3329        pub const _1: Self = Self::new(1);
3330    }
3331    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3332    pub struct Wuafa_SPEC;
3333    pub type Wuafa = crate::EnumBitfieldStruct<u8, Wuafa_SPEC>;
3334    impl Wuafa {
3335        #[doc = "Do not add the Wake Up analog filter."]
3336        pub const _0: Self = Self::new(0);
3337
3338        #[doc = "Add the Wake Up analog filter."]
3339        pub const _1: Self = Self::new(1);
3340    }
3341}
3342#[doc(hidden)]
3343#[derive(Copy, Clone, Eq, PartialEq)]
3344pub struct Icwur2_SPEC;
3345impl crate::sealed::RegSpec for Icwur2_SPEC {
3346    type DataType = u8;
3347}
3348
3349#[doc = "Reserved"]
3350pub type Icwur2 = crate::RegValueT<Icwur2_SPEC>;
3351
3352impl Icwur2 {
3353    #[doc = "These bits are read as 11111. The write value should be 11111."]
3354    #[inline(always)]
3355    pub fn reserved(
3356        self,
3357    ) -> crate::common::RegisterField<3, 0x1f, 1, 0, u8, u8, Icwur2_SPEC, crate::common::RW> {
3358        crate::common::RegisterField::<3,0x1f,1,0,u8,u8,Icwur2_SPEC,crate::common::RW>::from_register(self,0)
3359    }
3360
3361    #[doc = "Wake-Up function Synchronous operation status Flag"]
3362    #[inline(always)]
3363    pub fn wusyf(
3364        self,
3365    ) -> crate::common::RegisterField<
3366        2,
3367        0x1,
3368        1,
3369        0,
3370        icwur2::Wusyf,
3371        icwur2::Wusyf,
3372        Icwur2_SPEC,
3373        crate::common::R,
3374    > {
3375        crate::common::RegisterField::<
3376            2,
3377            0x1,
3378            1,
3379            0,
3380            icwur2::Wusyf,
3381            icwur2::Wusyf,
3382            Icwur2_SPEC,
3383            crate::common::R,
3384        >::from_register(self, 0)
3385    }
3386
3387    #[doc = "Wake-Up function Asynchronous operation status Flag"]
3388    #[inline(always)]
3389    pub fn wuasyf(
3390        self,
3391    ) -> crate::common::RegisterField<
3392        1,
3393        0x1,
3394        1,
3395        0,
3396        icwur2::Wuasyf,
3397        icwur2::Wuasyf,
3398        Icwur2_SPEC,
3399        crate::common::R,
3400    > {
3401        crate::common::RegisterField::<
3402            1,
3403            0x1,
3404            1,
3405            0,
3406            icwur2::Wuasyf,
3407            icwur2::Wuasyf,
3408            Icwur2_SPEC,
3409            crate::common::R,
3410        >::from_register(self, 0)
3411    }
3412
3413    #[doc = "Wake-Up function Synchronous Enable"]
3414    #[inline(always)]
3415    pub fn wusen(
3416        self,
3417    ) -> crate::common::RegisterField<
3418        0,
3419        0x1,
3420        1,
3421        0,
3422        icwur2::Wusen,
3423        icwur2::Wusen,
3424        Icwur2_SPEC,
3425        crate::common::RW,
3426    > {
3427        crate::common::RegisterField::<
3428            0,
3429            0x1,
3430            1,
3431            0,
3432            icwur2::Wusen,
3433            icwur2::Wusen,
3434            Icwur2_SPEC,
3435            crate::common::RW,
3436        >::from_register(self, 0)
3437    }
3438}
3439impl ::core::default::Default for Icwur2 {
3440    #[inline(always)]
3441    fn default() -> Icwur2 {
3442        <crate::RegValueT<Icwur2_SPEC> as RegisterValue<_>>::new(253)
3443    }
3444}
3445pub mod icwur2 {
3446
3447    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3448    pub struct Wusyf_SPEC;
3449    pub type Wusyf = crate::EnumBitfieldStruct<u8, Wusyf_SPEC>;
3450    impl Wusyf {
3451        #[doc = "RIIC asynchronous circuit enable condition"]
3452        pub const _0: Self = Self::new(0);
3453
3454        #[doc = "RIIC synchronous circuit enable condition"]
3455        pub const _1: Self = Self::new(1);
3456    }
3457    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3458    pub struct Wuasyf_SPEC;
3459    pub type Wuasyf = crate::EnumBitfieldStruct<u8, Wuasyf_SPEC>;
3460    impl Wuasyf {
3461        #[doc = "RIIC synchronous circuit enable condition"]
3462        pub const _0: Self = Self::new(0);
3463
3464        #[doc = "RIIC asynchronous circuit enable condition"]
3465        pub const _1: Self = Self::new(1);
3466    }
3467    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3468    pub struct Wusen_SPEC;
3469    pub type Wusen = crate::EnumBitfieldStruct<u8, Wusen_SPEC>;
3470    impl Wusen {
3471        #[doc = "RIIC asynchronous circuit enable"]
3472        pub const _0: Self = Self::new(0);
3473
3474        #[doc = "RIIC synchronous circuit enable"]
3475        pub const _1: Self = Self::new(1);
3476    }
3477}
ra2a1_pac/iic0.rs

ra2a1_pac/
iic0.rs
