ra2a1_pac/
gpt_ops.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.1, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:31 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Output Phase Switching Controller"]
28unsafe impl ::core::marker::Send for super::GptOps {}
29unsafe impl ::core::marker::Sync for super::GptOps {}
30impl super::GptOps {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Output Phase Switching Control Register"]
38    #[inline(always)]
39    pub const fn opscr(&self) -> &'static crate::common::Reg<self::Opscr_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Opscr_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46}
47#[doc(hidden)]
48#[derive(Copy, Clone, Eq, PartialEq)]
49pub struct Opscr_SPEC;
50impl crate::sealed::RegSpec for Opscr_SPEC {
51    type DataType = u32;
52}
53
54#[doc = "Output Phase Switching Control Register"]
55pub type Opscr = crate::RegValueT<Opscr_SPEC>;
56
57impl Opscr {
58    #[doc = "External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input."]
59    #[inline(always)]
60    pub fn nfcs(
61        self,
62    ) -> crate::common::RegisterField<
63        30,
64        0x3,
65        1,
66        0,
67        opscr::Nfcs,
68        opscr::Nfcs,
69        Opscr_SPEC,
70        crate::common::RW,
71    > {
72        crate::common::RegisterField::<
73            30,
74            0x3,
75            1,
76            0,
77            opscr::Nfcs,
78            opscr::Nfcs,
79            Opscr_SPEC,
80            crate::common::RW,
81        >::from_register(self, 0)
82    }
83
84    #[doc = "External Input Noise Filter Enable"]
85    #[inline(always)]
86    pub fn nfen(
87        self,
88    ) -> crate::common::RegisterField<
89        29,
90        0x1,
91        1,
92        0,
93        opscr::Nfen,
94        opscr::Nfen,
95        Opscr_SPEC,
96        crate::common::RW,
97    > {
98        crate::common::RegisterField::<
99            29,
100            0x1,
101            1,
102            0,
103            opscr::Nfen,
104            opscr::Nfen,
105            Opscr_SPEC,
106            crate::common::RW,
107        >::from_register(self, 0)
108    }
109
110    #[doc = "Group output disable function"]
111    #[inline(always)]
112    pub fn godf(
113        self,
114    ) -> crate::common::RegisterField<
115        26,
116        0x1,
117        1,
118        0,
119        opscr::Godf,
120        opscr::Godf,
121        Opscr_SPEC,
122        crate::common::RW,
123    > {
124        crate::common::RegisterField::<
125            26,
126            0x1,
127            1,
128            0,
129            opscr::Godf,
130            opscr::Godf,
131            Opscr_SPEC,
132            crate::common::RW,
133        >::from_register(self, 0)
134    }
135
136    #[doc = "Output disabled source selection"]
137    #[inline(always)]
138    pub fn grp(
139        self,
140    ) -> crate::common::RegisterField<
141        24,
142        0x1,
143        1,
144        0,
145        opscr::Grp,
146        opscr::Grp,
147        Opscr_SPEC,
148        crate::common::RW,
149    > {
150        crate::common::RegisterField::<
151            24,
152            0x1,
153            1,
154            0,
155            opscr::Grp,
156            opscr::Grp,
157            Opscr_SPEC,
158            crate::common::RW,
159        >::from_register(self, 0)
160    }
161
162    #[doc = "Input phase alignment"]
163    #[inline(always)]
164    pub fn align(
165        self,
166    ) -> crate::common::RegisterField<
167        21,
168        0x1,
169        1,
170        0,
171        opscr::Align,
172        opscr::Align,
173        Opscr_SPEC,
174        crate::common::RW,
175    > {
176        crate::common::RegisterField::<
177            21,
178            0x1,
179            1,
180            0,
181            opscr::Align,
182            opscr::Align,
183            Opscr_SPEC,
184            crate::common::RW,
185        >::from_register(self, 0)
186    }
187
188    #[doc = "Output phase rotation direction reversal"]
189    #[inline(always)]
190    pub fn rv(
191        self,
192    ) -> crate::common::RegisterField<
193        20,
194        0x1,
195        1,
196        0,
197        opscr::Rv,
198        opscr::Rv,
199        Opscr_SPEC,
200        crate::common::RW,
201    > {
202        crate::common::RegisterField::<
203            20,
204            0x1,
205            1,
206            0,
207            opscr::Rv,
208            opscr::Rv,
209            Opscr_SPEC,
210            crate::common::RW,
211        >::from_register(self, 0)
212    }
213
214    #[doc = "Invert-Phase Output Control"]
215    #[inline(always)]
216    pub fn inv(
217        self,
218    ) -> crate::common::RegisterField<
219        19,
220        0x1,
221        1,
222        0,
223        opscr::Inv,
224        opscr::Inv,
225        Opscr_SPEC,
226        crate::common::RW,
227    > {
228        crate::common::RegisterField::<
229            19,
230            0x1,
231            1,
232            0,
233            opscr::Inv,
234            opscr::Inv,
235            Opscr_SPEC,
236            crate::common::RW,
237        >::from_register(self, 0)
238    }
239
240    #[doc = "Negative-Phase Output (N) Control"]
241    #[inline(always)]
242    pub fn n(
243        self,
244    ) -> crate::common::RegisterField<
245        18,
246        0x1,
247        1,
248        0,
249        opscr::N,
250        opscr::N,
251        Opscr_SPEC,
252        crate::common::RW,
253    > {
254        crate::common::RegisterField::<
255            18,
256            0x1,
257            1,
258            0,
259            opscr::N,
260            opscr::N,
261            Opscr_SPEC,
262            crate::common::RW,
263        >::from_register(self, 0)
264    }
265
266    #[doc = "Positive-Phase Output (P) Control"]
267    #[inline(always)]
268    pub fn p(
269        self,
270    ) -> crate::common::RegisterField<
271        17,
272        0x1,
273        1,
274        0,
275        opscr::P,
276        opscr::P,
277        Opscr_SPEC,
278        crate::common::RW,
279    > {
280        crate::common::RegisterField::<
281            17,
282            0x1,
283            1,
284            0,
285            opscr::P,
286            opscr::P,
287            Opscr_SPEC,
288            crate::common::RW,
289        >::from_register(self, 0)
290    }
291
292    #[doc = "External Feedback Signal EnableThis bit selects the input phase from the software settings and external input."]
293    #[inline(always)]
294    pub fn fb(
295        self,
296    ) -> crate::common::RegisterField<
297        16,
298        0x1,
299        1,
300        0,
301        opscr::Fb,
302        opscr::Fb,
303        Opscr_SPEC,
304        crate::common::RW,
305    > {
306        crate::common::RegisterField::<
307            16,
308            0x1,
309            1,
310            0,
311            opscr::Fb,
312            opscr::Fb,
313            Opscr_SPEC,
314            crate::common::RW,
315        >::from_register(self, 0)
316    }
317
318    #[doc = "Enable-Phase Output Control"]
319    #[inline(always)]
320    pub fn en(
321        self,
322    ) -> crate::common::RegisterField<
323        8,
324        0x1,
325        1,
326        0,
327        opscr::En,
328        opscr::En,
329        Opscr_SPEC,
330        crate::common::RW,
331    > {
332        crate::common::RegisterField::<
333            8,
334            0x1,
335            1,
336            0,
337            opscr::En,
338            opscr::En,
339            Opscr_SPEC,
340            crate::common::RW,
341        >::from_register(self, 0)
342    }
343
344    #[doc = "Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF)"]
345    #[inline(always)]
346    pub fn w(self) -> crate::common::RegisterFieldBool<6, 1, 0, Opscr_SPEC, crate::common::R> {
347        crate::common::RegisterFieldBool::<6, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
348            self, 0,
349        )
350    }
351
352    #[doc = "Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF)"]
353    #[inline(always)]
354    pub fn v(self) -> crate::common::RegisterFieldBool<5, 1, 0, Opscr_SPEC, crate::common::R> {
355        crate::common::RegisterFieldBool::<5, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
356            self, 0,
357        )
358    }
359
360    #[doc = "Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF)"]
361    #[inline(always)]
362    pub fn u(self) -> crate::common::RegisterFieldBool<4, 1, 0, Opscr_SPEC, crate::common::R> {
363        crate::common::RegisterFieldBool::<4, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
364            self, 0,
365        )
366    }
367
368    #[doc = "This bit is read as 0. The write value should be 0."]
369    #[inline(always)]
370    pub fn reserved(
371        self,
372    ) -> crate::common::RegisterFieldBool<3, 1, 0, Opscr_SPEC, crate::common::RW> {
373        crate::common::RegisterFieldBool::<3, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
374            self, 0,
375        )
376    }
377
378    #[doc = "Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1."]
379    #[inline(always)]
380    pub fn wf(self) -> crate::common::RegisterFieldBool<2, 1, 0, Opscr_SPEC, crate::common::RW> {
381        crate::common::RegisterFieldBool::<2, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
382            self, 0,
383        )
384    }
385
386    #[doc = "Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1."]
387    #[inline(always)]
388    pub fn vf(self) -> crate::common::RegisterFieldBool<1, 1, 0, Opscr_SPEC, crate::common::RW> {
389        crate::common::RegisterFieldBool::<1, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
390            self, 0,
391        )
392    }
393
394    #[doc = "Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1."]
395    #[inline(always)]
396    pub fn uf(self) -> crate::common::RegisterFieldBool<0, 1, 0, Opscr_SPEC, crate::common::RW> {
397        crate::common::RegisterFieldBool::<0, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
398            self, 0,
399        )
400    }
401}
402impl ::core::default::Default for Opscr {
403    #[inline(always)]
404    fn default() -> Opscr {
405        <crate::RegValueT<Opscr_SPEC> as RegisterValue<_>>::new(0)
406    }
407}
408pub mod opscr {
409
410    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
411    pub struct Nfcs_SPEC;
412    pub type Nfcs = crate::EnumBitfieldStruct<u8, Nfcs_SPEC>;
413    impl Nfcs {
414        #[doc = "PCLK/1"]
415        pub const _00: Self = Self::new(0);
416
417        #[doc = "PCLK/4"]
418        pub const _01: Self = Self::new(1);
419
420        #[doc = "PCLK/16"]
421        pub const _10: Self = Self::new(2);
422
423        #[doc = "PCLK/64"]
424        pub const _11: Self = Self::new(3);
425    }
426    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
427    pub struct Nfen_SPEC;
428    pub type Nfen = crate::EnumBitfieldStruct<u8, Nfen_SPEC>;
429    impl Nfen {
430        #[doc = "Do not use a noise filter to the external input."]
431        pub const _0: Self = Self::new(0);
432
433        #[doc = "Use a noise filter to the external input."]
434        pub const _1: Self = Self::new(1);
435    }
436    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
437    pub struct Godf_SPEC;
438    pub type Godf = crate::EnumBitfieldStruct<u8, Godf_SPEC>;
439    impl Godf {
440        #[doc = "This bit function is ignored."]
441        pub const _0: Self = Self::new(0);
442
443        #[doc = "Group disable will clear OPSCR.EN Bit."]
444        pub const _1: Self = Self::new(1);
445    }
446    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
447    pub struct Grp_SPEC;
448    pub type Grp = crate::EnumBitfieldStruct<u8, Grp_SPEC>;
449    impl Grp {
450        #[doc = "Select Group A output disable source"]
451        pub const _0: Self = Self::new(0);
452
453        #[doc = "Select Group B output disable source."]
454        pub const _1: Self = Self::new(1);
455    }
456    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
457    pub struct Align_SPEC;
458    pub type Align = crate::EnumBitfieldStruct<u8, Align_SPEC>;
459    impl Align {
460        #[doc = "Input phase is aligned to PCLK."]
461        pub const _0: Self = Self::new(0);
462
463        #[doc = "Input phase is aligned PWM."]
464        pub const _1: Self = Self::new(1);
465    }
466    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
467    pub struct Rv_SPEC;
468    pub type Rv = crate::EnumBitfieldStruct<u8, Rv_SPEC>;
469    impl Rv {
470        #[doc = "U/V/W-Phase output"]
471        pub const _0: Self = Self::new(0);
472
473        #[doc = "Output to reverse the V / W-phase"]
474        pub const _1: Self = Self::new(1);
475    }
476    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
477    pub struct Inv_SPEC;
478    pub type Inv = crate::EnumBitfieldStruct<u8, Inv_SPEC>;
479    impl Inv {
480        #[doc = "Positive Logic (Active High)output"]
481        pub const _0: Self = Self::new(0);
482
483        #[doc = "Negative Logic (Active Low)output"]
484        pub const _1: Self = Self::new(1);
485    }
486    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
487    pub struct N_SPEC;
488    pub type N = crate::EnumBitfieldStruct<u8, N_SPEC>;
489    impl N {
490        #[doc = "Level signal output"]
491        pub const _0: Self = Self::new(0);
492
493        #[doc = "PWM signal output (PWM of GPT0)"]
494        pub const _1: Self = Self::new(1);
495    }
496    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
497    pub struct P_SPEC;
498    pub type P = crate::EnumBitfieldStruct<u8, P_SPEC>;
499    impl P {
500        #[doc = "Level signal output"]
501        pub const _0: Self = Self::new(0);
502
503        #[doc = "PWM signal output (PWM of GPT0)"]
504        pub const _1: Self = Self::new(1);
505    }
506    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
507    pub struct Fb_SPEC;
508    pub type Fb = crate::EnumBitfieldStruct<u8, Fb_SPEC>;
509    impl Fb {
510        #[doc = "Select the external input."]
511        pub const _0: Self = Self::new(0);
512
513        #[doc = "Select the soft setting(OPSCR.UF, VF, WF)."]
514        pub const _1: Self = Self::new(1);
515    }
516    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
517    pub struct En_SPEC;
518    pub type En = crate::EnumBitfieldStruct<u8, En_SPEC>;
519    impl En {
520        #[doc = "Not Output(Hi-Z external terminals)."]
521        pub const _0: Self = Self::new(0);
522
523        #[doc = "Output"]
524        pub const _1: Self = Self::new(1);
525    }
526}
ra2a1_pac/gpt_ops.rs

ra2a1_pac/
gpt_ops.rs
