ra0e1_pac/
pclbuz.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.10.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:13 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Clock Output/Buzzer Output Controller"]
28unsafe impl ::core::marker::Send for super::Pclbuz {}
29unsafe impl ::core::marker::Sync for super::Pclbuz {}
30impl super::Pclbuz {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Clock Out Control Register 0"]
38    #[inline(always)]
39    pub const fn cks0(&self) -> &'static crate::common::Reg<self::Cks0_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Cks0_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(1usize),
43            )
44        }
45    }
46}
47#[doc(hidden)]
48#[derive(Copy, Clone, Eq, PartialEq)]
49pub struct Cks0_SPEC;
50impl crate::sealed::RegSpec for Cks0_SPEC {
51    type DataType = u8;
52}
53
54#[doc = "Clock Out Control Register 0"]
55pub type Cks0 = crate::RegValueT<Cks0_SPEC>;
56
57impl Cks0 {
58    #[doc = "Clock Out Divide Select"]
59    #[inline(always)]
60    pub fn ccs(
61        self,
62    ) -> crate::common::RegisterField<
63        0,
64        0x7,
65        1,
66        0,
67        cks0::Ccs,
68        cks0::Ccs,
69        Cks0_SPEC,
70        crate::common::RW,
71    > {
72        crate::common::RegisterField::<
73            0,
74            0x7,
75            1,
76            0,
77            cks0::Ccs,
78            cks0::Ccs,
79            Cks0_SPEC,
80            crate::common::RW,
81        >::from_register(self, 0)
82    }
83
84    #[doc = "Clock Out Select"]
85    #[inline(always)]
86    pub fn csel(
87        self,
88    ) -> crate::common::RegisterField<
89        3,
90        0x1,
91        1,
92        0,
93        cks0::Csel,
94        cks0::Csel,
95        Cks0_SPEC,
96        crate::common::RW,
97    > {
98        crate::common::RegisterField::<
99            3,
100            0x1,
101            1,
102            0,
103            cks0::Csel,
104            cks0::Csel,
105            Cks0_SPEC,
106            crate::common::RW,
107        >::from_register(self, 0)
108    }
109
110    #[doc = "Clock Out Enable"]
111    #[inline(always)]
112    pub fn pcloe(
113        self,
114    ) -> crate::common::RegisterField<
115        7,
116        0x1,
117        1,
118        0,
119        cks0::Pcloe,
120        cks0::Pcloe,
121        Cks0_SPEC,
122        crate::common::RW,
123    > {
124        crate::common::RegisterField::<
125            7,
126            0x1,
127            1,
128            0,
129            cks0::Pcloe,
130            cks0::Pcloe,
131            Cks0_SPEC,
132            crate::common::RW,
133        >::from_register(self, 0)
134    }
135}
136impl ::core::default::Default for Cks0 {
137    #[inline(always)]
138    fn default() -> Cks0 {
139        <crate::RegValueT<Cks0_SPEC> as RegisterValue<_>>::new(0)
140    }
141}
142pub mod cks0 {
143
144    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
145    pub struct Ccs_SPEC;
146    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
147    impl Ccs {
148        #[doc = "value after reset FMAIN (When CKS0.CSEL = 0) FSUB (When CKS0.CSEL = 1)"]
149        pub const _000: Self = Self::new(0);
150
151        #[doc = "FMAIN × 1/2 (When CKS0.CSEL = 0) FSUB × 1/2 (When CKS0.CSEL = 1)"]
152        pub const _001: Self = Self::new(1);
153
154        #[doc = "FMAIN × 1/22 (When CKS0.CSEL = 0) FSUB × 1/22 (When CKS0.CSEL = 1)"]
155        pub const _010: Self = Self::new(2);
156
157        #[doc = "FMAIN × 1/23 (When CKS0.CSEL = 0) FSUB × 1/23 (When CKS0.CSEL = 1)"]
158        pub const _011: Self = Self::new(3);
159
160        #[doc = "FMAIN × 1/24 (When CKS0.CSEL = 0) FSUB × 1/24 (When CKS0.CSEL = 1)"]
161        pub const _100: Self = Self::new(4);
162
163        #[doc = "FMAIN × 1/211 (When CKS0.CSEL = 0) FSUB × 1/25 (When CKS0.CSEL = 1)"]
164        pub const _101: Self = Self::new(5);
165
166        #[doc = "FMAIN 1/212 (When CKS0.CSEL = 0) FSUB × 1/26 (When CKS0.CSEL = 1)"]
167        pub const _110: Self = Self::new(6);
168
169        #[doc = "FMAIN × 1/213 (When CKS0.CSEL = 0) FSUB × 1/27 (When CKS0.CSEL = 1)"]
170        pub const _111: Self = Self::new(7);
171    }
172    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
173    pub struct Csel_SPEC;
174    pub type Csel = crate::EnumBitfieldStruct<u8, Csel_SPEC>;
175    impl Csel {
176        #[doc = "FMAIN"]
177        pub const _0: Self = Self::new(0);
178
179        #[doc = "FSUB"]
180        pub const _1: Self = Self::new(1);
181    }
182    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
183    pub struct Pcloe_SPEC;
184    pub type Pcloe = crate::EnumBitfieldStruct<u8, Pcloe_SPEC>;
185    impl Pcloe {
186        #[doc = "Disable clock out"]
187        pub const _0: Self = Self::new(0);
188
189        #[doc = "Enable clock out"]
190        pub const _1: Self = Self::new(1);
191    }
192}
ra0e1_pac/pclbuz.rs

ra0e1_pac/
pclbuz.rs
