1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x10],
5 #[doc = "0x10 - IOMMU Reset Register"]
6 pub iommu_reset_reg: crate::Reg<iommu_reset_reg::IOMMU_RESET_REG_SPEC>,
7 _reserved1: [u8; 0x0c],
8 #[doc = "0x20 - IOMMU Enable Register"]
9 pub iommu_enable_reg: crate::Reg<iommu_enable_reg::IOMMU_ENABLE_REG_SPEC>,
10 _reserved2: [u8; 0x0c],
11 #[doc = "0x30 - IOMMU Bypass Register"]
12 pub iommu_bypass_reg: crate::Reg<iommu_bypass_reg::IOMMU_BYPASS_REG_SPEC>,
13 _reserved3: [u8; 0x0c],
14 #[doc = "0x40 - IOMMU Auto Gating Register"]
15 pub iommu_auto_gating_reg: crate::Reg<iommu_auto_gating_reg::IOMMU_AUTO_GATING_REG_SPEC>,
16 #[doc = "0x44 - IOMMU Write Buffer Control Register"]
17 pub iommu_wbuf_ctrl_reg: crate::Reg<iommu_wbuf_ctrl_reg::IOMMU_WBUF_CTRL_REG_SPEC>,
18 #[doc = "0x48 - IOMMU Out of Order Control Register"]
19 pub iommu_ooo_ctrl_reg: crate::Reg<iommu_ooo_ctrl_reg::IOMMU_OOO_CTRL_REG_SPEC>,
20 #[doc = "0x4c - IOMMU 4KB Boundary Protect Control Register"]
21 pub iommu_4kb_bdy_prt_ctrl_reg:
22 crate::Reg<iommu_4kb_bdy_prt_ctrl_reg::IOMMU_4KB_BDY_PRT_CTRL_REG_SPEC>,
23 #[doc = "0x50 - IOMMU Translation Table Base Register"]
24 pub iommu_ttb_reg: crate::Reg<iommu_ttb_reg::IOMMU_TTB_REG_SPEC>,
25 _reserved8: [u8; 0x0c],
26 #[doc = "0x60 - IOMMU TLB Enable Register"]
27 pub iommu_tlb_enable_reg: crate::Reg<iommu_tlb_enable_reg::IOMMU_TLB_ENABLE_REG_SPEC>,
28 _reserved9: [u8; 0x0c],
29 #[doc = "0x70 - IOMMU TLB Prefetch Register"]
30 pub iommu_tlb_prefetch_reg: crate::Reg<iommu_tlb_prefetch_reg::IOMMU_TLB_PREFETCH_REG_SPEC>,
31 _reserved10: [u8; 0x0c],
32 #[doc = "0x80 - IOMMU TLB Flush Enable Register"]
33 pub iommu_tlb_flush_enable_reg:
34 crate::Reg<iommu_tlb_flush_enable_reg::IOMMU_TLB_FLUSH_ENABLE_REG_SPEC>,
35 #[doc = "0x84 - IOMMU TLB Invalidation Mode Select Register"]
36 pub iommu_tlb_ivld_mode_sel_reg:
37 crate::Reg<iommu_tlb_ivld_mode_sel_reg::IOMMU_TLB_IVLD_MODE_SEL_REG_SPEC>,
38 #[doc = "0x88 - IOMMU TLB Invalidation Start Address Register"]
39 pub iommu_tlb_ivld_sta_addr_reg:
40 crate::Reg<iommu_tlb_ivld_sta_addr_reg::IOMMU_TLB_IVLD_STA_ADDR_REG_SPEC>,
41 #[doc = "0x8c - IOMMU TLB Invalidation End Address Register"]
42 pub iommu_tlb_ivld_end_addr_reg:
43 crate::Reg<iommu_tlb_ivld_end_addr_reg::IOMMU_TLB_IVLD_END_ADDR_REG_SPEC>,
44 #[doc = "0x90 - IOMMU TLB Invalidation Address Register"]
45 pub iommu_tlb_ivld_addr_reg: crate::Reg<iommu_tlb_ivld_addr_reg::IOMMU_TLB_IVLD_ADDR_REG_SPEC>,
46 #[doc = "0x94 - IOMMU TLB Invalidation Address Mask Register"]
47 pub iommu_tlb_ivld_addr_mask_reg:
48 crate::Reg<iommu_tlb_ivld_addr_mask_reg::IOMMU_TLB_IVLD_ADDR_MASK_REG_SPEC>,
49 #[doc = "0x98 - IOMMU TLB Invalidation Enable Register"]
50 pub iommu_tlb_ivld_enable_reg:
51 crate::Reg<iommu_tlb_ivld_enable_reg::IOMMU_TLB_IVLD_ENABLE_REG_SPEC>,
52 #[doc = "0x9c - IOMMU PC Invalidation Mode Select Register"]
53 pub iommu_pc_ivld_mode_sel_reg:
54 crate::Reg<iommu_pc_ivld_mode_sel_reg::IOMMU_PC_IVLD_MODE_SEL_REG_SPEC>,
55 #[doc = "0xa0 - IOMMU PC Invalidation Address Register"]
56 pub iommu_pc_ivld_addr_reg: crate::Reg<iommu_pc_ivld_addr_reg::IOMMU_PC_IVLD_ADDR_REG_SPEC>,
57 #[doc = "0xa4 - IOMMU PC Invalidation Start Address Register"]
58 pub iommu_pc_ivld_sta_addr_reg:
59 crate::Reg<iommu_pc_ivld_sta_addr_reg::IOMMU_PC_IVLD_STA_ADDR_REG_SPEC>,
60 #[doc = "0xa8 - IOMMU PC Invalidation Enable Register"]
61 pub iommu_pc_ivld_enable_reg:
62 crate::Reg<iommu_pc_ivld_enable_reg::IOMMU_PC_IVLD_ENABLE_REG_SPEC>,
63 #[doc = "0xac - IOMMU PC Invalidation End Address Register"]
64 pub iommu_pc_ivld_end_addr_reg:
65 crate::Reg<iommu_pc_ivld_end_addr_reg::IOMMU_PC_IVLD_END_ADDR_REG_SPEC>,
66 #[doc = "0xb0 - IOMMU Domain Authority Control 0 Register"]
67 pub iommu_dm_aut_ctrl0_reg: crate::Reg<iommu_dm_aut_ctrl0_reg::IOMMU_DM_AUT_CTRL0_REG_SPEC>,
68 #[doc = "0xb4 - IOMMU Domain Authority Control 1 Register"]
69 pub iommu_dm_aut_ctrl1_reg: crate::Reg<iommu_dm_aut_ctrl1_reg::IOMMU_DM_AUT_CTRL1_REG_SPEC>,
70 #[doc = "0xb8 - IOMMU Domain Authority Control 2 Register"]
71 pub iommu_dm_aut_ctrl2_reg: crate::Reg<iommu_dm_aut_ctrl2_reg::IOMMU_DM_AUT_CTRL2_REG_SPEC>,
72 #[doc = "0xbc - IOMMU Domain Authority Control 3 Register"]
73 pub iommu_dm_aut_ctrl3_reg: crate::Reg<iommu_dm_aut_ctrl3_reg::IOMMU_DM_AUT_CTRL3_REG_SPEC>,
74 #[doc = "0xc0 - IOMMU Domain Authority Control 4 Register"]
75 pub iommu_dm_aut_ctrl4_reg: crate::Reg<iommu_dm_aut_ctrl4_reg::IOMMU_DM_AUT_CTRL4_REG_SPEC>,
76 #[doc = "0xc4 - IOMMU Domain Authority Control 5 Register"]
77 pub iommu_dm_aut_ctrl5_reg: crate::Reg<iommu_dm_aut_ctrl5_reg::IOMMU_DM_AUT_CTRL5_REG_SPEC>,
78 #[doc = "0xc8 - IOMMU Domain Authority Control 6 Register"]
79 pub iommu_dm_aut_ctrl6_reg: crate::Reg<iommu_dm_aut_ctrl6_reg::IOMMU_DM_AUT_CTRL6_REG_SPEC>,
80 #[doc = "0xcc - IOMMU Domain Authority Control 7 Register"]
81 pub iommu_dm_aut_ctrl7_reg: crate::Reg<iommu_dm_aut_ctrl7_reg::IOMMU_DM_AUT_CTRL7_REG_SPEC>,
82 #[doc = "0xd0 - IOMMU Domain Authority Overwrite Register"]
83 pub iommu_dm_aut_ovwt_reg: crate::Reg<iommu_dm_aut_ovwt_reg::IOMMU_DM_AUT_OVWT_REG_SPEC>,
84 _reserved31: [u8; 0x2c],
85 #[doc = "0x100 - IOMMU Interrupt Enable Register"]
86 pub iommu_int_enable_reg: crate::Reg<iommu_int_enable_reg::IOMMU_INT_ENABLE_REG_SPEC>,
87 #[doc = "0x104 - IOMMU Interrupt Clear Register"]
88 pub iommu_int_clr_reg: crate::Reg<iommu_int_clr_reg::IOMMU_INT_CLR_REG_SPEC>,
89 #[doc = "0x108 - IOMMU Interrupt Status Register"]
90 pub iommu_int_sta_reg: crate::Reg<iommu_int_sta_reg::IOMMU_INT_STA_REG_SPEC>,
91 _reserved34: [u8; 0x04],
92 #[doc = "0x110 - IOMMU Interrupt Error Address 0"]
93 pub iommu_int_err_addr0_reg: crate::Reg<iommu_int_err_addr0_reg::IOMMU_INT_ERR_ADDR0_REG_SPEC>,
94 #[doc = "0x114 - IOMMU Interrupt Error Address 1"]
95 pub iommu_int_err_addr1_reg: crate::Reg<iommu_int_err_addr1_reg::IOMMU_INT_ERR_ADDR1_REG_SPEC>,
96 #[doc = "0x118 - IOMMU Interrupt Error Address 2"]
97 pub iommu_int_err_addr2_reg: crate::Reg<iommu_int_err_addr2_reg::IOMMU_INT_ERR_ADDR2_REG_SPEC>,
98 #[doc = "0x11c - IOMMU Interrupt Error Address 3"]
99 pub iommu_int_err_addr3_reg: crate::Reg<iommu_int_err_addr3_reg::IOMMU_INT_ERR_ADDR3_REG_SPEC>,
100 #[doc = "0x120 - IOMMU Interrupt Error Address 4"]
101 pub iommu_int_err_addr4_reg: crate::Reg<iommu_int_err_addr4_reg::IOMMU_INT_ERR_ADDR4_REG_SPEC>,
102 #[doc = "0x124 - IOMMU Interrupt Error Address 5"]
103 pub iommu_int_err_addr5_reg: crate::Reg<iommu_int_err_addr5_reg::IOMMU_INT_ERR_ADDR5_REG_SPEC>,
104 #[doc = "0x128 - IOMMU Interrupt Error Address 6"]
105 pub iommu_int_err_addr6_reg: crate::Reg<iommu_int_err_addr6_reg::IOMMU_INT_ERR_ADDR6_REG_SPEC>,
106 _reserved41: [u8; 0x04],
107 #[doc = "0x130 - IOMMU Interrupt Error Address 7"]
108 pub iommu_int_err_addr7_reg: crate::Reg<iommu_int_err_addr7_reg::IOMMU_INT_ERR_ADDR7_REG_SPEC>,
109 #[doc = "0x134 - IOMMU Interrupt Error Address 8"]
110 pub iommu_int_err_addr8_reg: crate::Reg<iommu_int_err_addr8_reg::IOMMU_INT_ERR_ADDR8_REG_SPEC>,
111 _reserved43: [u8; 0x18],
112 #[doc = "0x150 - IOMMU Interrupt Error Data 0 Register"]
113 pub iommu_int_err_data0_reg: crate::Reg<iommu_int_err_data0_reg::IOMMU_INT_ERR_DATA0_REG_SPEC>,
114 #[doc = "0x154 - IOMMU Interrupt Error Data 1 Register"]
115 pub iommu_int_err_data1_reg: crate::Reg<iommu_int_err_data1_reg::IOMMU_INT_ERR_DATA1_REG_SPEC>,
116 #[doc = "0x158 - IOMMU Interrupt Error Data 2 Register"]
117 pub iommu_int_err_data2_reg: crate::Reg<iommu_int_err_data2_reg::IOMMU_INT_ERR_DATA2_REG_SPEC>,
118 #[doc = "0x15c - IOMMU Interrupt Error Data 3 Register"]
119 pub iommu_int_err_data3_reg: crate::Reg<iommu_int_err_data3_reg::IOMMU_INT_ERR_DATA3_REG_SPEC>,
120 #[doc = "0x160 - IOMMU Interrupt Error Data 4 Register"]
121 pub iommu_int_err_data4_reg: crate::Reg<iommu_int_err_data4_reg::IOMMU_INT_ERR_DATA4_REG_SPEC>,
122 #[doc = "0x164 - IOMMU Interrupt Error Data 5 Register"]
123 pub iommu_int_err_data5_reg: crate::Reg<iommu_int_err_data5_reg::IOMMU_INT_ERR_DATA5_REG_SPEC>,
124 #[doc = "0x168 - IOMMU Interrupt Error Data 6 Register"]
125 pub iommu_int_err_data6_reg: crate::Reg<iommu_int_err_data6_reg::IOMMU_INT_ERR_DATA6_REG_SPEC>,
126 _reserved50: [u8; 0x04],
127 #[doc = "0x170 - IOMMU Interrupt Error Data 7 Register"]
128 pub iommu_int_err_data7_reg: crate::Reg<iommu_int_err_data7_reg::IOMMU_INT_ERR_DATA7_REG_SPEC>,
129 #[doc = "0x174 - IOMMU Interrupt Error Data 8 Register"]
130 pub iommu_int_err_data8_reg: crate::Reg<iommu_int_err_data8_reg::IOMMU_INT_ERR_DATA8_REG_SPEC>,
131 _reserved52: [u8; 0x08],
132 #[doc = "0x180 - IOMMU L1 Page Table Interrupt Register"]
133 pub iommu_l1pg_int_reg: crate::Reg<iommu_l1pg_int_reg::IOMMU_L1PG_INT_REG_SPEC>,
134 #[doc = "0x184 - IOMMU L2 Page Table Interrupt Register"]
135 pub iommu_l2pg_int_reg: crate::Reg<iommu_l2pg_int_reg::IOMMU_L2PG_INT_REG_SPEC>,
136 _reserved54: [u8; 0x08],
137 #[doc = "0x190 - IOMMU Virtual Address Register"]
138 pub iommu_va_reg: crate::Reg<iommu_va_reg::IOMMU_VA_REG_SPEC>,
139 #[doc = "0x194 - IOMMU Virtual Address Data Register"]
140 pub iommu_va_data_reg: crate::Reg<iommu_va_data_reg::IOMMU_VA_DATA_REG_SPEC>,
141 #[doc = "0x198 - IOMMU Virtual Address Configuration Register"]
142 pub iommu_va_config_reg: crate::Reg<iommu_va_config_reg::IOMMU_VA_CONFIG_REG_SPEC>,
143 _reserved57: [u8; 0x64],
144 #[doc = "0x200 - IOMMU PMU Enable Register"]
145 pub iommu_pmu_enable_reg: crate::Reg<iommu_pmu_enable_reg::IOMMU_PMU_ENABLE_REG_SPEC>,
146 _reserved58: [u8; 0x0c],
147 #[doc = "0x210 - IOMMU PMU Clear Register"]
148 pub iommu_pmu_clr_reg: crate::Reg<iommu_pmu_clr_reg::IOMMU_PMU_CLR_REG_SPEC>,
149 _reserved59: [u8; 0x1c],
150 #[doc = "0x230 - IOMMU PMU Access Low 0 Register"]
151 pub iommu_pmu_access_low0_reg:
152 crate::Reg<iommu_pmu_access_low0_reg::IOMMU_PMU_ACCESS_LOW0_REG_SPEC>,
153 #[doc = "0x234 - IOMMU PMU Access High 0 Register"]
154 pub iommu_pmu_access_high0_reg:
155 crate::Reg<iommu_pmu_access_high0_reg::IOMMU_PMU_ACCESS_HIGH0_REG_SPEC>,
156 #[doc = "0x238 - IOMMU PMU Hit Low 0 Register"]
157 pub iommu_pmu_hit_low0_reg: crate::Reg<iommu_pmu_hit_low0_reg::IOMMU_PMU_HIT_LOW0_REG_SPEC>,
158 #[doc = "0x23c - IOMMU PMU Hit High 0 Register"]
159 pub iommu_pmu_hit_high0_reg: crate::Reg<iommu_pmu_hit_high0_reg::IOMMU_PMU_HIT_HIGH0_REG_SPEC>,
160 #[doc = "0x240 - IOMMU PMU Access Low 1 Register"]
161 pub iommu_pmu_access_low1_reg:
162 crate::Reg<iommu_pmu_access_low1_reg::IOMMU_PMU_ACCESS_LOW1_REG_SPEC>,
163 #[doc = "0x244 - IOMMU PMU Access High 1 Register"]
164 pub iommu_pmu_access_high1_reg:
165 crate::Reg<iommu_pmu_access_high1_reg::IOMMU_PMU_ACCESS_HIGH1_REG_SPEC>,
166 #[doc = "0x248 - IOMMU PMU Hit Low 1 Register"]
167 pub iommu_pmu_hit_low1_reg: crate::Reg<iommu_pmu_hit_low1_reg::IOMMU_PMU_HIT_LOW1_REG_SPEC>,
168 #[doc = "0x24c - IOMMU PMU Hit High 1 Register"]
169 pub iommu_pmu_hit_high1_reg: crate::Reg<iommu_pmu_hit_high1_reg::IOMMU_PMU_HIT_HIGH1_REG_SPEC>,
170 #[doc = "0x250 - IOMMU PMU Access Low 2 Register"]
171 pub iommu_pmu_access_low2_reg:
172 crate::Reg<iommu_pmu_access_low2_reg::IOMMU_PMU_ACCESS_LOW2_REG_SPEC>,
173 #[doc = "0x254 - IOMMU PMU Access High 2 Register"]
174 pub iommu_pmu_access_high2_reg:
175 crate::Reg<iommu_pmu_access_high2_reg::IOMMU_PMU_ACCESS_HIGH2_REG_SPEC>,
176 #[doc = "0x258 - IOMMU PMU Hit Low 2 Register"]
177 pub iommu_pmu_hit_low2_reg: crate::Reg<iommu_pmu_hit_low2_reg::IOMMU_PMU_HIT_LOW2_REG_SPEC>,
178 #[doc = "0x25c - IOMMU PMU Hit High 2 Register"]
179 pub iommu_pmu_hit_high2_reg: crate::Reg<iommu_pmu_hit_high2_reg::IOMMU_PMU_HIT_HIGH2_REG_SPEC>,
180 #[doc = "0x260 - IOMMU PMU Access Low 3 Register"]
181 pub iommu_pmu_access_low3_reg:
182 crate::Reg<iommu_pmu_access_low3_reg::IOMMU_PMU_ACCESS_LOW3_REG_SPEC>,
183 #[doc = "0x264 - IOMMU PMU Access High 3 Register"]
184 pub iommu_pmu_access_high3_reg:
185 crate::Reg<iommu_pmu_access_high3_reg::IOMMU_PMU_ACCESS_HIGH3_REG_SPEC>,
186 #[doc = "0x268 - IOMMU PMU Hit Low 3 Register"]
187 pub iommu_pmu_hit_low3_reg: crate::Reg<iommu_pmu_hit_low3_reg::IOMMU_PMU_HIT_LOW3_REG_SPEC>,
188 #[doc = "0x26c - IOMMU PMU Hit High 3 Register"]
189 pub iommu_pmu_hit_high3_reg: crate::Reg<iommu_pmu_hit_high3_reg::IOMMU_PMU_HIT_HIGH3_REG_SPEC>,
190 #[doc = "0x270 - IOMMU PMU Access Low 4 Register"]
191 pub iommu_pmu_access_low4_reg:
192 crate::Reg<iommu_pmu_access_low4_reg::IOMMU_PMU_ACCESS_LOW4_REG_SPEC>,
193 #[doc = "0x274 - IOMMU PMU Access High 4 Register"]
194 pub iommu_pmu_access_high4_reg:
195 crate::Reg<iommu_pmu_access_high4_reg::IOMMU_PMU_ACCESS_HIGH4_REG_SPEC>,
196 #[doc = "0x278 - IOMMU PMU Hit Low 4 Register"]
197 pub iommu_pmu_hit_low4_reg: crate::Reg<iommu_pmu_hit_low4_reg::IOMMU_PMU_HIT_LOW4_REG_SPEC>,
198 #[doc = "0x27c - IOMMU PMU Hit High 4 Register"]
199 pub iommu_pmu_hit_high4_reg: crate::Reg<iommu_pmu_hit_high4_reg::IOMMU_PMU_HIT_HIGH4_REG_SPEC>,
200 #[doc = "0x280 - IOMMU PMU Access Low 5 Register"]
201 pub iommu_pmu_access_low5_reg:
202 crate::Reg<iommu_pmu_access_low5_reg::IOMMU_PMU_ACCESS_LOW5_REG_SPEC>,
203 #[doc = "0x284 - IOMMU PMU Access High 5 Register"]
204 pub iommu_pmu_access_high5_reg:
205 crate::Reg<iommu_pmu_access_high5_reg::IOMMU_PMU_ACCESS_HIGH5_REG_SPEC>,
206 #[doc = "0x288 - IOMMU PMU Hit Low 5 Register"]
207 pub iommu_pmu_hit_low5_reg: crate::Reg<iommu_pmu_hit_low5_reg::IOMMU_PMU_HIT_LOW5_REG_SPEC>,
208 #[doc = "0x28c - IOMMU PMU Hit High 5 Register"]
209 pub iommu_pmu_hit_high5_reg: crate::Reg<iommu_pmu_hit_high5_reg::IOMMU_PMU_HIT_HIGH5_REG_SPEC>,
210 #[doc = "0x290 - IOMMU PMU Access Low 6 Register"]
211 pub iommu_pmu_access_low6_reg:
212 crate::Reg<iommu_pmu_access_low6_reg::IOMMU_PMU_ACCESS_LOW6_REG_SPEC>,
213 #[doc = "0x294 - IOMMU PMU Access High 6 Register"]
214 pub iommu_pmu_access_high6_reg:
215 crate::Reg<iommu_pmu_access_high6_reg::IOMMU_PMU_ACCESS_HIGH6_REG_SPEC>,
216 #[doc = "0x298 - IOMMU PMU Hit Low 6 Register"]
217 pub iommu_pmu_hit_low6_reg: crate::Reg<iommu_pmu_hit_low6_reg::IOMMU_PMU_HIT_LOW6_REG_SPEC>,
218 #[doc = "0x29c - IOMMU PMU Hit High 6 Register"]
219 pub iommu_pmu_hit_high6_reg: crate::Reg<iommu_pmu_hit_high6_reg::IOMMU_PMU_HIT_HIGH6_REG_SPEC>,
220 _reserved87: [u8; 0x30],
221 #[doc = "0x2d0 - IOMMU PMU Access Low 7 Register"]
222 pub iommu_pmu_access_low7_reg:
223 crate::Reg<iommu_pmu_access_low7_reg::IOMMU_PMU_ACCESS_LOW7_REG_SPEC>,
224 #[doc = "0x2d4 - IOMMU PMU Access High 7 Register"]
225 pub iommu_pmu_access_high7_reg:
226 crate::Reg<iommu_pmu_access_high7_reg::IOMMU_PMU_ACCESS_HIGH7_REG_SPEC>,
227 #[doc = "0x2d8 - IOMMU PMU Hit Low 7 Register"]
228 pub iommu_pmu_hit_low7_reg: crate::Reg<iommu_pmu_hit_low7_reg::IOMMU_PMU_HIT_LOW7_REG_SPEC>,
229 #[doc = "0x2dc - IOMMU PMU Hit High 7 Register"]
230 pub iommu_pmu_hit_high7_reg: crate::Reg<iommu_pmu_hit_high7_reg::IOMMU_PMU_HIT_HIGH7_REG_SPEC>,
231 #[doc = "0x2e0 - IOMMU PMU Access Low 8 Register"]
232 pub iommu_pmu_access_low8_reg:
233 crate::Reg<iommu_pmu_access_low8_reg::IOMMU_PMU_ACCESS_LOW8_REG_SPEC>,
234 #[doc = "0x2e4 - IOMMU PMU Access High 8 Register"]
235 pub iommu_pmu_access_high8_reg:
236 crate::Reg<iommu_pmu_access_high8_reg::IOMMU_PMU_ACCESS_HIGH8_REG_SPEC>,
237 #[doc = "0x2e8 - IOMMU PMU Hit Low 8 Register"]
238 pub iommu_pmu_hit_low8_reg: crate::Reg<iommu_pmu_hit_low8_reg::IOMMU_PMU_HIT_LOW8_REG_SPEC>,
239 #[doc = "0x2ec - IOMMU PMU Hit High 8 Register"]
240 pub iommu_pmu_hit_high8_reg: crate::Reg<iommu_pmu_hit_high8_reg::IOMMU_PMU_HIT_HIGH8_REG_SPEC>,
241 _reserved95: [u8; 0x10],
242 #[doc = "0x300 - IOMMU Total Latency Low 0 Register"]
243 pub iommu_pmu_tl_low0_reg: crate::Reg<iommu_pmu_tl_low0_reg::IOMMU_PMU_TL_LOW0_REG_SPEC>,
244 #[doc = "0x304 - IOMMU Total Latency High 0 Register"]
245 pub iommu_pmu_tl_high0_reg: crate::Reg<iommu_pmu_tl_high0_reg::IOMMU_PMU_TL_HIGH0_REG_SPEC>,
246 #[doc = "0x308 - IOMMU Max Latency 0 Register"]
247 pub iommu_pmu_ml0_reg: crate::Reg<iommu_pmu_ml0_reg::IOMMU_PMU_ML0_REG_SPEC>,
248 _reserved98: [u8; 0x04],
249 #[doc = "0x310 - IOMMU Total Latency Low 1 Register"]
250 pub iommu_pmu_tl_low1_reg: crate::Reg<iommu_pmu_tl_low1_reg::IOMMU_PMU_TL_LOW1_REG_SPEC>,
251 #[doc = "0x314 - IOMMU Total Latency High 1 Register"]
252 pub iommu_pmu_tl_high1_reg: crate::Reg<iommu_pmu_tl_high1_reg::IOMMU_PMU_TL_HIGH1_REG_SPEC>,
253 #[doc = "0x318 - IOMMU Max Latency 1 Register"]
254 pub iommu_pmu_ml1_reg: crate::Reg<iommu_pmu_ml1_reg::IOMMU_PMU_ML1_REG_SPEC>,
255 _reserved101: [u8; 0x04],
256 #[doc = "0x320 - IOMMU Total Latency Low 2 Register"]
257 pub iommu_pmu_tl_low2_reg: crate::Reg<iommu_pmu_tl_low2_reg::IOMMU_PMU_TL_LOW2_REG_SPEC>,
258 #[doc = "0x324 - IOMMU Total Latency High 2 Register"]
259 pub iommu_pmu_tl_high2_reg: crate::Reg<iommu_pmu_tl_high2_reg::IOMMU_PMU_TL_HIGH2_REG_SPEC>,
260 #[doc = "0x328 - IOMMU Max Latency 2 Register"]
261 pub iommu_pmu_ml2_reg: crate::Reg<iommu_pmu_ml2_reg::IOMMU_PMU_ML2_REG_SPEC>,
262 _reserved104: [u8; 0x04],
263 #[doc = "0x330 - IOMMU Total Latency Low 3 Register"]
264 pub iommu_pmu_tl_low3_reg: crate::Reg<iommu_pmu_tl_low3_reg::IOMMU_PMU_TL_LOW3_REG_SPEC>,
265 #[doc = "0x334 - IOMMU Total Latency High 3 Register"]
266 pub iommu_pmu_tl_high3_reg: crate::Reg<iommu_pmu_tl_high3_reg::IOMMU_PMU_TL_HIGH3_REG_SPEC>,
267 #[doc = "0x338 - IOMMU Max Latency 3 Register"]
268 pub iommu_pmu_ml3_reg: crate::Reg<iommu_pmu_ml3_reg::IOMMU_PMU_ML3_REG_SPEC>,
269 _reserved107: [u8; 0x04],
270 #[doc = "0x340 - IOMMU Total Latency Low 4 Register"]
271 pub iommu_pmu_tl_low4_reg: crate::Reg<iommu_pmu_tl_low4_reg::IOMMU_PMU_TL_LOW4_REG_SPEC>,
272 #[doc = "0x344 - IOMMU Total Latency High 4 Register"]
273 pub iommu_pmu_tl_high4_reg: crate::Reg<iommu_pmu_tl_high4_reg::IOMMU_PMU_TL_HIGH4_REG_SPEC>,
274 #[doc = "0x348 - IOMMU Max Latency 4 Register"]
275 pub iommu_pmu_ml4_reg: crate::Reg<iommu_pmu_ml4_reg::IOMMU_PMU_ML4_REG_SPEC>,
276 _reserved110: [u8; 0x04],
277 #[doc = "0x350 - IOMMU Total Latency Low 5 Register"]
278 pub iommu_pmu_tl_low5_reg: crate::Reg<iommu_pmu_tl_low5_reg::IOMMU_PMU_TL_LOW5_REG_SPEC>,
279 #[doc = "0x354 - IOMMU Total Latency High 5 Register"]
280 pub iommu_pmu_tl_high5_reg: crate::Reg<iommu_pmu_tl_high5_reg::IOMMU_PMU_TL_HIGH5_REG_SPEC>,
281 #[doc = "0x358 - IOMMU Max Latency 5 Register"]
282 pub iommu_pmu_ml5_reg: crate::Reg<iommu_pmu_ml5_reg::IOMMU_PMU_ML5_REG_SPEC>,
283 _reserved113: [u8; 0x04],
284 #[doc = "0x360 - IOMMU Total Latency Low 6 Register"]
285 pub iommu_pmu_tl_low6_reg: crate::Reg<iommu_pmu_tl_low6_reg::IOMMU_PMU_TL_LOW6_REG_SPEC>,
286 #[doc = "0x364 - IOMMU Total Latency High 6 Register"]
287 pub iommu_pmu_tl_high6_reg: crate::Reg<iommu_pmu_tl_high6_reg::IOMMU_PMU_TL_HIGH6_REG_SPEC>,
288 #[doc = "0x368 - IOMMU Max Latency 6 Register"]
289 pub iommu_pmu_ml6_reg: crate::Reg<iommu_pmu_ml6_reg::IOMMU_PMU_ML6_REG_SPEC>,
290}
291#[doc = "IOMMU_RESET_REG register accessor: an alias for `Reg<IOMMU_RESET_REG_SPEC>`"]
292pub type IOMMU_RESET_REG = crate::Reg<iommu_reset_reg::IOMMU_RESET_REG_SPEC>;
293#[doc = "IOMMU Reset Register"]
294pub mod iommu_reset_reg;
295#[doc = "IOMMU_ENABLE_REG register accessor: an alias for `Reg<IOMMU_ENABLE_REG_SPEC>`"]
296pub type IOMMU_ENABLE_REG = crate::Reg<iommu_enable_reg::IOMMU_ENABLE_REG_SPEC>;
297#[doc = "IOMMU Enable Register"]
298pub mod iommu_enable_reg;
299#[doc = "IOMMU_BYPASS_REG register accessor: an alias for `Reg<IOMMU_BYPASS_REG_SPEC>`"]
300pub type IOMMU_BYPASS_REG = crate::Reg<iommu_bypass_reg::IOMMU_BYPASS_REG_SPEC>;
301#[doc = "IOMMU Bypass Register"]
302pub mod iommu_bypass_reg;
303#[doc = "IOMMU_AUTO_GATING_REG register accessor: an alias for `Reg<IOMMU_AUTO_GATING_REG_SPEC>`"]
304pub type IOMMU_AUTO_GATING_REG = crate::Reg<iommu_auto_gating_reg::IOMMU_AUTO_GATING_REG_SPEC>;
305#[doc = "IOMMU Auto Gating Register"]
306pub mod iommu_auto_gating_reg;
307#[doc = "IOMMU_WBUF_CTRL_REG register accessor: an alias for `Reg<IOMMU_WBUF_CTRL_REG_SPEC>`"]
308pub type IOMMU_WBUF_CTRL_REG = crate::Reg<iommu_wbuf_ctrl_reg::IOMMU_WBUF_CTRL_REG_SPEC>;
309#[doc = "IOMMU Write Buffer Control Register"]
310pub mod iommu_wbuf_ctrl_reg;
311#[doc = "IOMMU_OOO_CTRL_REG register accessor: an alias for `Reg<IOMMU_OOO_CTRL_REG_SPEC>`"]
312pub type IOMMU_OOO_CTRL_REG = crate::Reg<iommu_ooo_ctrl_reg::IOMMU_OOO_CTRL_REG_SPEC>;
313#[doc = "IOMMU Out of Order Control Register"]
314pub mod iommu_ooo_ctrl_reg;
315#[doc = "IOMMU_4KB_BDY_PRT_CTRL_REG register accessor: an alias for `Reg<IOMMU_4KB_BDY_PRT_CTRL_REG_SPEC>`"]
316pub type IOMMU_4KB_BDY_PRT_CTRL_REG =
317 crate::Reg<iommu_4kb_bdy_prt_ctrl_reg::IOMMU_4KB_BDY_PRT_CTRL_REG_SPEC>;
318#[doc = "IOMMU 4KB Boundary Protect Control Register"]
319pub mod iommu_4kb_bdy_prt_ctrl_reg;
320#[doc = "IOMMU_TTB_REG register accessor: an alias for `Reg<IOMMU_TTB_REG_SPEC>`"]
321pub type IOMMU_TTB_REG = crate::Reg<iommu_ttb_reg::IOMMU_TTB_REG_SPEC>;
322#[doc = "IOMMU Translation Table Base Register"]
323pub mod iommu_ttb_reg;
324#[doc = "IOMMU_TLB_ENABLE_REG register accessor: an alias for `Reg<IOMMU_TLB_ENABLE_REG_SPEC>`"]
325pub type IOMMU_TLB_ENABLE_REG = crate::Reg<iommu_tlb_enable_reg::IOMMU_TLB_ENABLE_REG_SPEC>;
326#[doc = "IOMMU TLB Enable Register"]
327pub mod iommu_tlb_enable_reg;
328#[doc = "IOMMU_TLB_PREFETCH_REG register accessor: an alias for `Reg<IOMMU_TLB_PREFETCH_REG_SPEC>`"]
329pub type IOMMU_TLB_PREFETCH_REG = crate::Reg<iommu_tlb_prefetch_reg::IOMMU_TLB_PREFETCH_REG_SPEC>;
330#[doc = "IOMMU TLB Prefetch Register"]
331pub mod iommu_tlb_prefetch_reg;
332#[doc = "IOMMU_TLB_FLUSH_ENABLE_REG register accessor: an alias for `Reg<IOMMU_TLB_FLUSH_ENABLE_REG_SPEC>`"]
333pub type IOMMU_TLB_FLUSH_ENABLE_REG =
334 crate::Reg<iommu_tlb_flush_enable_reg::IOMMU_TLB_FLUSH_ENABLE_REG_SPEC>;
335#[doc = "IOMMU TLB Flush Enable Register"]
336pub mod iommu_tlb_flush_enable_reg;
337#[doc = "IOMMU_TLB_IVLD_MODE_SEL_REG register accessor: an alias for `Reg<IOMMU_TLB_IVLD_MODE_SEL_REG_SPEC>`"]
338pub type IOMMU_TLB_IVLD_MODE_SEL_REG =
339 crate::Reg<iommu_tlb_ivld_mode_sel_reg::IOMMU_TLB_IVLD_MODE_SEL_REG_SPEC>;
340#[doc = "IOMMU TLB Invalidation Mode Select Register"]
341pub mod iommu_tlb_ivld_mode_sel_reg;
342#[doc = "IOMMU_TLB_IVLD_STA_ADDR_REG register accessor: an alias for `Reg<IOMMU_TLB_IVLD_STA_ADDR_REG_SPEC>`"]
343pub type IOMMU_TLB_IVLD_STA_ADDR_REG =
344 crate::Reg<iommu_tlb_ivld_sta_addr_reg::IOMMU_TLB_IVLD_STA_ADDR_REG_SPEC>;
345#[doc = "IOMMU TLB Invalidation Start Address Register"]
346pub mod iommu_tlb_ivld_sta_addr_reg;
347#[doc = "IOMMU_TLB_IVLD_END_ADDR_REG register accessor: an alias for `Reg<IOMMU_TLB_IVLD_END_ADDR_REG_SPEC>`"]
348pub type IOMMU_TLB_IVLD_END_ADDR_REG =
349 crate::Reg<iommu_tlb_ivld_end_addr_reg::IOMMU_TLB_IVLD_END_ADDR_REG_SPEC>;
350#[doc = "IOMMU TLB Invalidation End Address Register"]
351pub mod iommu_tlb_ivld_end_addr_reg;
352#[doc = "IOMMU_TLB_IVLD_ADDR_REG register accessor: an alias for `Reg<IOMMU_TLB_IVLD_ADDR_REG_SPEC>`"]
353pub type IOMMU_TLB_IVLD_ADDR_REG =
354 crate::Reg<iommu_tlb_ivld_addr_reg::IOMMU_TLB_IVLD_ADDR_REG_SPEC>;
355#[doc = "IOMMU TLB Invalidation Address Register"]
356pub mod iommu_tlb_ivld_addr_reg;
357#[doc = "IOMMU_TLB_IVLD_ADDR_MASK_REG register accessor: an alias for `Reg<IOMMU_TLB_IVLD_ADDR_MASK_REG_SPEC>`"]
358pub type IOMMU_TLB_IVLD_ADDR_MASK_REG =
359 crate::Reg<iommu_tlb_ivld_addr_mask_reg::IOMMU_TLB_IVLD_ADDR_MASK_REG_SPEC>;
360#[doc = "IOMMU TLB Invalidation Address Mask Register"]
361pub mod iommu_tlb_ivld_addr_mask_reg;
362#[doc = "IOMMU_TLB_IVLD_ENABLE_REG register accessor: an alias for `Reg<IOMMU_TLB_IVLD_ENABLE_REG_SPEC>`"]
363pub type IOMMU_TLB_IVLD_ENABLE_REG =
364 crate::Reg<iommu_tlb_ivld_enable_reg::IOMMU_TLB_IVLD_ENABLE_REG_SPEC>;
365#[doc = "IOMMU TLB Invalidation Enable Register"]
366pub mod iommu_tlb_ivld_enable_reg;
367#[doc = "IOMMU_PC_IVLD_MODE_SEL_REG register accessor: an alias for `Reg<IOMMU_PC_IVLD_MODE_SEL_REG_SPEC>`"]
368pub type IOMMU_PC_IVLD_MODE_SEL_REG =
369 crate::Reg<iommu_pc_ivld_mode_sel_reg::IOMMU_PC_IVLD_MODE_SEL_REG_SPEC>;
370#[doc = "IOMMU PC Invalidation Mode Select Register"]
371pub mod iommu_pc_ivld_mode_sel_reg;
372#[doc = "IOMMU_PC_IVLD_ADDR_REG register accessor: an alias for `Reg<IOMMU_PC_IVLD_ADDR_REG_SPEC>`"]
373pub type IOMMU_PC_IVLD_ADDR_REG = crate::Reg<iommu_pc_ivld_addr_reg::IOMMU_PC_IVLD_ADDR_REG_SPEC>;
374#[doc = "IOMMU PC Invalidation Address Register"]
375pub mod iommu_pc_ivld_addr_reg;
376#[doc = "IOMMU_PC_IVLD_STA_ADDR_REG register accessor: an alias for `Reg<IOMMU_PC_IVLD_STA_ADDR_REG_SPEC>`"]
377pub type IOMMU_PC_IVLD_STA_ADDR_REG =
378 crate::Reg<iommu_pc_ivld_sta_addr_reg::IOMMU_PC_IVLD_STA_ADDR_REG_SPEC>;
379#[doc = "IOMMU PC Invalidation Start Address Register"]
380pub mod iommu_pc_ivld_sta_addr_reg;
381#[doc = "IOMMU_PC_IVLD_ENABLE_REG register accessor: an alias for `Reg<IOMMU_PC_IVLD_ENABLE_REG_SPEC>`"]
382pub type IOMMU_PC_IVLD_ENABLE_REG =
383 crate::Reg<iommu_pc_ivld_enable_reg::IOMMU_PC_IVLD_ENABLE_REG_SPEC>;
384#[doc = "IOMMU PC Invalidation Enable Register"]
385pub mod iommu_pc_ivld_enable_reg;
386#[doc = "IOMMU_PC_IVLD_END_ADDR_REG register accessor: an alias for `Reg<IOMMU_PC_IVLD_END_ADDR_REG_SPEC>`"]
387pub type IOMMU_PC_IVLD_END_ADDR_REG =
388 crate::Reg<iommu_pc_ivld_end_addr_reg::IOMMU_PC_IVLD_END_ADDR_REG_SPEC>;
389#[doc = "IOMMU PC Invalidation End Address Register"]
390pub mod iommu_pc_ivld_end_addr_reg;
391#[doc = "IOMMU_DM_AUT_CTRL0_REG register accessor: an alias for `Reg<IOMMU_DM_AUT_CTRL0_REG_SPEC>`"]
392pub type IOMMU_DM_AUT_CTRL0_REG = crate::Reg<iommu_dm_aut_ctrl0_reg::IOMMU_DM_AUT_CTRL0_REG_SPEC>;
393#[doc = "IOMMU Domain Authority Control 0 Register"]
394pub mod iommu_dm_aut_ctrl0_reg;
395#[doc = "IOMMU_DM_AUT_CTRL1_REG register accessor: an alias for `Reg<IOMMU_DM_AUT_CTRL1_REG_SPEC>`"]
396pub type IOMMU_DM_AUT_CTRL1_REG = crate::Reg<iommu_dm_aut_ctrl1_reg::IOMMU_DM_AUT_CTRL1_REG_SPEC>;
397#[doc = "IOMMU Domain Authority Control 1 Register"]
398pub mod iommu_dm_aut_ctrl1_reg;
399#[doc = "IOMMU_DM_AUT_CTRL2_REG register accessor: an alias for `Reg<IOMMU_DM_AUT_CTRL2_REG_SPEC>`"]
400pub type IOMMU_DM_AUT_CTRL2_REG = crate::Reg<iommu_dm_aut_ctrl2_reg::IOMMU_DM_AUT_CTRL2_REG_SPEC>;
401#[doc = "IOMMU Domain Authority Control 2 Register"]
402pub mod iommu_dm_aut_ctrl2_reg;
403#[doc = "IOMMU_DM_AUT_CTRL3_REG register accessor: an alias for `Reg<IOMMU_DM_AUT_CTRL3_REG_SPEC>`"]
404pub type IOMMU_DM_AUT_CTRL3_REG = crate::Reg<iommu_dm_aut_ctrl3_reg::IOMMU_DM_AUT_CTRL3_REG_SPEC>;
405#[doc = "IOMMU Domain Authority Control 3 Register"]
406pub mod iommu_dm_aut_ctrl3_reg;
407#[doc = "IOMMU_DM_AUT_CTRL4_REG register accessor: an alias for `Reg<IOMMU_DM_AUT_CTRL4_REG_SPEC>`"]
408pub type IOMMU_DM_AUT_CTRL4_REG = crate::Reg<iommu_dm_aut_ctrl4_reg::IOMMU_DM_AUT_CTRL4_REG_SPEC>;
409#[doc = "IOMMU Domain Authority Control 4 Register"]
410pub mod iommu_dm_aut_ctrl4_reg;
411#[doc = "IOMMU_DM_AUT_CTRL5_REG register accessor: an alias for `Reg<IOMMU_DM_AUT_CTRL5_REG_SPEC>`"]
412pub type IOMMU_DM_AUT_CTRL5_REG = crate::Reg<iommu_dm_aut_ctrl5_reg::IOMMU_DM_AUT_CTRL5_REG_SPEC>;
413#[doc = "IOMMU Domain Authority Control 5 Register"]
414pub mod iommu_dm_aut_ctrl5_reg;
415#[doc = "IOMMU_DM_AUT_CTRL6_REG register accessor: an alias for `Reg<IOMMU_DM_AUT_CTRL6_REG_SPEC>`"]
416pub type IOMMU_DM_AUT_CTRL6_REG = crate::Reg<iommu_dm_aut_ctrl6_reg::IOMMU_DM_AUT_CTRL6_REG_SPEC>;
417#[doc = "IOMMU Domain Authority Control 6 Register"]
418pub mod iommu_dm_aut_ctrl6_reg;
419#[doc = "IOMMU_DM_AUT_CTRL7_REG register accessor: an alias for `Reg<IOMMU_DM_AUT_CTRL7_REG_SPEC>`"]
420pub type IOMMU_DM_AUT_CTRL7_REG = crate::Reg<iommu_dm_aut_ctrl7_reg::IOMMU_DM_AUT_CTRL7_REG_SPEC>;
421#[doc = "IOMMU Domain Authority Control 7 Register"]
422pub mod iommu_dm_aut_ctrl7_reg;
423#[doc = "IOMMU_DM_AUT_OVWT_REG register accessor: an alias for `Reg<IOMMU_DM_AUT_OVWT_REG_SPEC>`"]
424pub type IOMMU_DM_AUT_OVWT_REG = crate::Reg<iommu_dm_aut_ovwt_reg::IOMMU_DM_AUT_OVWT_REG_SPEC>;
425#[doc = "IOMMU Domain Authority Overwrite Register"]
426pub mod iommu_dm_aut_ovwt_reg;
427#[doc = "IOMMU_INT_ENABLE_REG register accessor: an alias for `Reg<IOMMU_INT_ENABLE_REG_SPEC>`"]
428pub type IOMMU_INT_ENABLE_REG = crate::Reg<iommu_int_enable_reg::IOMMU_INT_ENABLE_REG_SPEC>;
429#[doc = "IOMMU Interrupt Enable Register"]
430pub mod iommu_int_enable_reg;
431#[doc = "IOMMU_INT_CLR_REG register accessor: an alias for `Reg<IOMMU_INT_CLR_REG_SPEC>`"]
432pub type IOMMU_INT_CLR_REG = crate::Reg<iommu_int_clr_reg::IOMMU_INT_CLR_REG_SPEC>;
433#[doc = "IOMMU Interrupt Clear Register"]
434pub mod iommu_int_clr_reg;
435#[doc = "IOMMU_INT_STA_REG register accessor: an alias for `Reg<IOMMU_INT_STA_REG_SPEC>`"]
436pub type IOMMU_INT_STA_REG = crate::Reg<iommu_int_sta_reg::IOMMU_INT_STA_REG_SPEC>;
437#[doc = "IOMMU Interrupt Status Register"]
438pub mod iommu_int_sta_reg;
439#[doc = "IOMMU_INT_ERR_ADDR0_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_ADDR0_REG_SPEC>`"]
440pub type IOMMU_INT_ERR_ADDR0_REG =
441 crate::Reg<iommu_int_err_addr0_reg::IOMMU_INT_ERR_ADDR0_REG_SPEC>;
442#[doc = "IOMMU Interrupt Error Address 0"]
443pub mod iommu_int_err_addr0_reg;
444#[doc = "IOMMU_INT_ERR_ADDR1_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_ADDR1_REG_SPEC>`"]
445pub type IOMMU_INT_ERR_ADDR1_REG =
446 crate::Reg<iommu_int_err_addr1_reg::IOMMU_INT_ERR_ADDR1_REG_SPEC>;
447#[doc = "IOMMU Interrupt Error Address 1"]
448pub mod iommu_int_err_addr1_reg;
449#[doc = "IOMMU_INT_ERR_ADDR2_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_ADDR2_REG_SPEC>`"]
450pub type IOMMU_INT_ERR_ADDR2_REG =
451 crate::Reg<iommu_int_err_addr2_reg::IOMMU_INT_ERR_ADDR2_REG_SPEC>;
452#[doc = "IOMMU Interrupt Error Address 2"]
453pub mod iommu_int_err_addr2_reg;
454#[doc = "IOMMU_INT_ERR_ADDR3_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_ADDR3_REG_SPEC>`"]
455pub type IOMMU_INT_ERR_ADDR3_REG =
456 crate::Reg<iommu_int_err_addr3_reg::IOMMU_INT_ERR_ADDR3_REG_SPEC>;
457#[doc = "IOMMU Interrupt Error Address 3"]
458pub mod iommu_int_err_addr3_reg;
459#[doc = "IOMMU_INT_ERR_ADDR4_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_ADDR4_REG_SPEC>`"]
460pub type IOMMU_INT_ERR_ADDR4_REG =
461 crate::Reg<iommu_int_err_addr4_reg::IOMMU_INT_ERR_ADDR4_REG_SPEC>;
462#[doc = "IOMMU Interrupt Error Address 4"]
463pub mod iommu_int_err_addr4_reg;
464#[doc = "IOMMU_INT_ERR_ADDR5_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_ADDR5_REG_SPEC>`"]
465pub type IOMMU_INT_ERR_ADDR5_REG =
466 crate::Reg<iommu_int_err_addr5_reg::IOMMU_INT_ERR_ADDR5_REG_SPEC>;
467#[doc = "IOMMU Interrupt Error Address 5"]
468pub mod iommu_int_err_addr5_reg;
469#[doc = "IOMMU_INT_ERR_ADDR6_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_ADDR6_REG_SPEC>`"]
470pub type IOMMU_INT_ERR_ADDR6_REG =
471 crate::Reg<iommu_int_err_addr6_reg::IOMMU_INT_ERR_ADDR6_REG_SPEC>;
472#[doc = "IOMMU Interrupt Error Address 6"]
473pub mod iommu_int_err_addr6_reg;
474#[doc = "IOMMU_INT_ERR_ADDR7_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_ADDR7_REG_SPEC>`"]
475pub type IOMMU_INT_ERR_ADDR7_REG =
476 crate::Reg<iommu_int_err_addr7_reg::IOMMU_INT_ERR_ADDR7_REG_SPEC>;
477#[doc = "IOMMU Interrupt Error Address 7"]
478pub mod iommu_int_err_addr7_reg;
479#[doc = "IOMMU_INT_ERR_ADDR8_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_ADDR8_REG_SPEC>`"]
480pub type IOMMU_INT_ERR_ADDR8_REG =
481 crate::Reg<iommu_int_err_addr8_reg::IOMMU_INT_ERR_ADDR8_REG_SPEC>;
482#[doc = "IOMMU Interrupt Error Address 8"]
483pub mod iommu_int_err_addr8_reg;
484#[doc = "IOMMU_INT_ERR_DATA0_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_DATA0_REG_SPEC>`"]
485pub type IOMMU_INT_ERR_DATA0_REG =
486 crate::Reg<iommu_int_err_data0_reg::IOMMU_INT_ERR_DATA0_REG_SPEC>;
487#[doc = "IOMMU Interrupt Error Data 0 Register"]
488pub mod iommu_int_err_data0_reg;
489#[doc = "IOMMU_INT_ERR_DATA1_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_DATA1_REG_SPEC>`"]
490pub type IOMMU_INT_ERR_DATA1_REG =
491 crate::Reg<iommu_int_err_data1_reg::IOMMU_INT_ERR_DATA1_REG_SPEC>;
492#[doc = "IOMMU Interrupt Error Data 1 Register"]
493pub mod iommu_int_err_data1_reg;
494#[doc = "IOMMU_INT_ERR_DATA2_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_DATA2_REG_SPEC>`"]
495pub type IOMMU_INT_ERR_DATA2_REG =
496 crate::Reg<iommu_int_err_data2_reg::IOMMU_INT_ERR_DATA2_REG_SPEC>;
497#[doc = "IOMMU Interrupt Error Data 2 Register"]
498pub mod iommu_int_err_data2_reg;
499#[doc = "IOMMU_INT_ERR_DATA3_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_DATA3_REG_SPEC>`"]
500pub type IOMMU_INT_ERR_DATA3_REG =
501 crate::Reg<iommu_int_err_data3_reg::IOMMU_INT_ERR_DATA3_REG_SPEC>;
502#[doc = "IOMMU Interrupt Error Data 3 Register"]
503pub mod iommu_int_err_data3_reg;
504#[doc = "IOMMU_INT_ERR_DATA4_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_DATA4_REG_SPEC>`"]
505pub type IOMMU_INT_ERR_DATA4_REG =
506 crate::Reg<iommu_int_err_data4_reg::IOMMU_INT_ERR_DATA4_REG_SPEC>;
507#[doc = "IOMMU Interrupt Error Data 4 Register"]
508pub mod iommu_int_err_data4_reg;
509#[doc = "IOMMU_INT_ERR_DATA5_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_DATA5_REG_SPEC>`"]
510pub type IOMMU_INT_ERR_DATA5_REG =
511 crate::Reg<iommu_int_err_data5_reg::IOMMU_INT_ERR_DATA5_REG_SPEC>;
512#[doc = "IOMMU Interrupt Error Data 5 Register"]
513pub mod iommu_int_err_data5_reg;
514#[doc = "IOMMU_INT_ERR_DATA6_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_DATA6_REG_SPEC>`"]
515pub type IOMMU_INT_ERR_DATA6_REG =
516 crate::Reg<iommu_int_err_data6_reg::IOMMU_INT_ERR_DATA6_REG_SPEC>;
517#[doc = "IOMMU Interrupt Error Data 6 Register"]
518pub mod iommu_int_err_data6_reg;
519#[doc = "IOMMU_INT_ERR_DATA7_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_DATA7_REG_SPEC>`"]
520pub type IOMMU_INT_ERR_DATA7_REG =
521 crate::Reg<iommu_int_err_data7_reg::IOMMU_INT_ERR_DATA7_REG_SPEC>;
522#[doc = "IOMMU Interrupt Error Data 7 Register"]
523pub mod iommu_int_err_data7_reg;
524#[doc = "IOMMU_INT_ERR_DATA8_REG register accessor: an alias for `Reg<IOMMU_INT_ERR_DATA8_REG_SPEC>`"]
525pub type IOMMU_INT_ERR_DATA8_REG =
526 crate::Reg<iommu_int_err_data8_reg::IOMMU_INT_ERR_DATA8_REG_SPEC>;
527#[doc = "IOMMU Interrupt Error Data 8 Register"]
528pub mod iommu_int_err_data8_reg;
529#[doc = "IOMMU_L1PG_INT_REG register accessor: an alias for `Reg<IOMMU_L1PG_INT_REG_SPEC>`"]
530pub type IOMMU_L1PG_INT_REG = crate::Reg<iommu_l1pg_int_reg::IOMMU_L1PG_INT_REG_SPEC>;
531#[doc = "IOMMU L1 Page Table Interrupt Register"]
532pub mod iommu_l1pg_int_reg;
533#[doc = "IOMMU_L2PG_INT_REG register accessor: an alias for `Reg<IOMMU_L2PG_INT_REG_SPEC>`"]
534pub type IOMMU_L2PG_INT_REG = crate::Reg<iommu_l2pg_int_reg::IOMMU_L2PG_INT_REG_SPEC>;
535#[doc = "IOMMU L2 Page Table Interrupt Register"]
536pub mod iommu_l2pg_int_reg;
537#[doc = "IOMMU_VA_REG register accessor: an alias for `Reg<IOMMU_VA_REG_SPEC>`"]
538pub type IOMMU_VA_REG = crate::Reg<iommu_va_reg::IOMMU_VA_REG_SPEC>;
539#[doc = "IOMMU Virtual Address Register"]
540pub mod iommu_va_reg;
541#[doc = "IOMMU_VA_DATA_REG register accessor: an alias for `Reg<IOMMU_VA_DATA_REG_SPEC>`"]
542pub type IOMMU_VA_DATA_REG = crate::Reg<iommu_va_data_reg::IOMMU_VA_DATA_REG_SPEC>;
543#[doc = "IOMMU Virtual Address Data Register"]
544pub mod iommu_va_data_reg;
545#[doc = "IOMMU_VA_CONFIG_REG register accessor: an alias for `Reg<IOMMU_VA_CONFIG_REG_SPEC>`"]
546pub type IOMMU_VA_CONFIG_REG = crate::Reg<iommu_va_config_reg::IOMMU_VA_CONFIG_REG_SPEC>;
547#[doc = "IOMMU Virtual Address Configuration Register"]
548pub mod iommu_va_config_reg;
549#[doc = "IOMMU_PMU_ENABLE_REG register accessor: an alias for `Reg<IOMMU_PMU_ENABLE_REG_SPEC>`"]
550pub type IOMMU_PMU_ENABLE_REG = crate::Reg<iommu_pmu_enable_reg::IOMMU_PMU_ENABLE_REG_SPEC>;
551#[doc = "IOMMU PMU Enable Register"]
552pub mod iommu_pmu_enable_reg;
553#[doc = "IOMMU_PMU_CLR_REG register accessor: an alias for `Reg<IOMMU_PMU_CLR_REG_SPEC>`"]
554pub type IOMMU_PMU_CLR_REG = crate::Reg<iommu_pmu_clr_reg::IOMMU_PMU_CLR_REG_SPEC>;
555#[doc = "IOMMU PMU Clear Register"]
556pub mod iommu_pmu_clr_reg;
557#[doc = "IOMMU_PMU_ACCESS_LOW0_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_LOW0_REG_SPEC>`"]
558pub type IOMMU_PMU_ACCESS_LOW0_REG =
559 crate::Reg<iommu_pmu_access_low0_reg::IOMMU_PMU_ACCESS_LOW0_REG_SPEC>;
560#[doc = "IOMMU PMU Access Low 0 Register"]
561pub mod iommu_pmu_access_low0_reg;
562#[doc = "IOMMU_PMU_ACCESS_HIGH0_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_HIGH0_REG_SPEC>`"]
563pub type IOMMU_PMU_ACCESS_HIGH0_REG =
564 crate::Reg<iommu_pmu_access_high0_reg::IOMMU_PMU_ACCESS_HIGH0_REG_SPEC>;
565#[doc = "IOMMU PMU Access High 0 Register"]
566pub mod iommu_pmu_access_high0_reg;
567#[doc = "IOMMU_PMU_HIT_LOW0_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_LOW0_REG_SPEC>`"]
568pub type IOMMU_PMU_HIT_LOW0_REG = crate::Reg<iommu_pmu_hit_low0_reg::IOMMU_PMU_HIT_LOW0_REG_SPEC>;
569#[doc = "IOMMU PMU Hit Low 0 Register"]
570pub mod iommu_pmu_hit_low0_reg;
571#[doc = "IOMMU_PMU_HIT_HIGH0_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_HIGH0_REG_SPEC>`"]
572pub type IOMMU_PMU_HIT_HIGH0_REG =
573 crate::Reg<iommu_pmu_hit_high0_reg::IOMMU_PMU_HIT_HIGH0_REG_SPEC>;
574#[doc = "IOMMU PMU Hit High 0 Register"]
575pub mod iommu_pmu_hit_high0_reg;
576#[doc = "IOMMU_PMU_ACCESS_LOW1_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_LOW1_REG_SPEC>`"]
577pub type IOMMU_PMU_ACCESS_LOW1_REG =
578 crate::Reg<iommu_pmu_access_low1_reg::IOMMU_PMU_ACCESS_LOW1_REG_SPEC>;
579#[doc = "IOMMU PMU Access Low 1 Register"]
580pub mod iommu_pmu_access_low1_reg;
581#[doc = "IOMMU_PMU_ACCESS_HIGH1_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_HIGH1_REG_SPEC>`"]
582pub type IOMMU_PMU_ACCESS_HIGH1_REG =
583 crate::Reg<iommu_pmu_access_high1_reg::IOMMU_PMU_ACCESS_HIGH1_REG_SPEC>;
584#[doc = "IOMMU PMU Access High 1 Register"]
585pub mod iommu_pmu_access_high1_reg;
586#[doc = "IOMMU_PMU_HIT_LOW1_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_LOW1_REG_SPEC>`"]
587pub type IOMMU_PMU_HIT_LOW1_REG = crate::Reg<iommu_pmu_hit_low1_reg::IOMMU_PMU_HIT_LOW1_REG_SPEC>;
588#[doc = "IOMMU PMU Hit Low 1 Register"]
589pub mod iommu_pmu_hit_low1_reg;
590#[doc = "IOMMU_PMU_HIT_HIGH1_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_HIGH1_REG_SPEC>`"]
591pub type IOMMU_PMU_HIT_HIGH1_REG =
592 crate::Reg<iommu_pmu_hit_high1_reg::IOMMU_PMU_HIT_HIGH1_REG_SPEC>;
593#[doc = "IOMMU PMU Hit High 1 Register"]
594pub mod iommu_pmu_hit_high1_reg;
595#[doc = "IOMMU_PMU_ACCESS_LOW2_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_LOW2_REG_SPEC>`"]
596pub type IOMMU_PMU_ACCESS_LOW2_REG =
597 crate::Reg<iommu_pmu_access_low2_reg::IOMMU_PMU_ACCESS_LOW2_REG_SPEC>;
598#[doc = "IOMMU PMU Access Low 2 Register"]
599pub mod iommu_pmu_access_low2_reg;
600#[doc = "IOMMU_PMU_ACCESS_HIGH2_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_HIGH2_REG_SPEC>`"]
601pub type IOMMU_PMU_ACCESS_HIGH2_REG =
602 crate::Reg<iommu_pmu_access_high2_reg::IOMMU_PMU_ACCESS_HIGH2_REG_SPEC>;
603#[doc = "IOMMU PMU Access High 2 Register"]
604pub mod iommu_pmu_access_high2_reg;
605#[doc = "IOMMU_PMU_HIT_LOW2_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_LOW2_REG_SPEC>`"]
606pub type IOMMU_PMU_HIT_LOW2_REG = crate::Reg<iommu_pmu_hit_low2_reg::IOMMU_PMU_HIT_LOW2_REG_SPEC>;
607#[doc = "IOMMU PMU Hit Low 2 Register"]
608pub mod iommu_pmu_hit_low2_reg;
609#[doc = "IOMMU_PMU_HIT_HIGH2_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_HIGH2_REG_SPEC>`"]
610pub type IOMMU_PMU_HIT_HIGH2_REG =
611 crate::Reg<iommu_pmu_hit_high2_reg::IOMMU_PMU_HIT_HIGH2_REG_SPEC>;
612#[doc = "IOMMU PMU Hit High 2 Register"]
613pub mod iommu_pmu_hit_high2_reg;
614#[doc = "IOMMU_PMU_ACCESS_LOW3_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_LOW3_REG_SPEC>`"]
615pub type IOMMU_PMU_ACCESS_LOW3_REG =
616 crate::Reg<iommu_pmu_access_low3_reg::IOMMU_PMU_ACCESS_LOW3_REG_SPEC>;
617#[doc = "IOMMU PMU Access Low 3 Register"]
618pub mod iommu_pmu_access_low3_reg;
619#[doc = "IOMMU_PMU_ACCESS_HIGH3_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_HIGH3_REG_SPEC>`"]
620pub type IOMMU_PMU_ACCESS_HIGH3_REG =
621 crate::Reg<iommu_pmu_access_high3_reg::IOMMU_PMU_ACCESS_HIGH3_REG_SPEC>;
622#[doc = "IOMMU PMU Access High 3 Register"]
623pub mod iommu_pmu_access_high3_reg;
624#[doc = "IOMMU_PMU_HIT_LOW3_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_LOW3_REG_SPEC>`"]
625pub type IOMMU_PMU_HIT_LOW3_REG = crate::Reg<iommu_pmu_hit_low3_reg::IOMMU_PMU_HIT_LOW3_REG_SPEC>;
626#[doc = "IOMMU PMU Hit Low 3 Register"]
627pub mod iommu_pmu_hit_low3_reg;
628#[doc = "IOMMU_PMU_HIT_HIGH3_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_HIGH3_REG_SPEC>`"]
629pub type IOMMU_PMU_HIT_HIGH3_REG =
630 crate::Reg<iommu_pmu_hit_high3_reg::IOMMU_PMU_HIT_HIGH3_REG_SPEC>;
631#[doc = "IOMMU PMU Hit High 3 Register"]
632pub mod iommu_pmu_hit_high3_reg;
633#[doc = "IOMMU_PMU_ACCESS_LOW4_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_LOW4_REG_SPEC>`"]
634pub type IOMMU_PMU_ACCESS_LOW4_REG =
635 crate::Reg<iommu_pmu_access_low4_reg::IOMMU_PMU_ACCESS_LOW4_REG_SPEC>;
636#[doc = "IOMMU PMU Access Low 4 Register"]
637pub mod iommu_pmu_access_low4_reg;
638#[doc = "IOMMU_PMU_ACCESS_HIGH4_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_HIGH4_REG_SPEC>`"]
639pub type IOMMU_PMU_ACCESS_HIGH4_REG =
640 crate::Reg<iommu_pmu_access_high4_reg::IOMMU_PMU_ACCESS_HIGH4_REG_SPEC>;
641#[doc = "IOMMU PMU Access High 4 Register"]
642pub mod iommu_pmu_access_high4_reg;
643#[doc = "IOMMU_PMU_HIT_LOW4_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_LOW4_REG_SPEC>`"]
644pub type IOMMU_PMU_HIT_LOW4_REG = crate::Reg<iommu_pmu_hit_low4_reg::IOMMU_PMU_HIT_LOW4_REG_SPEC>;
645#[doc = "IOMMU PMU Hit Low 4 Register"]
646pub mod iommu_pmu_hit_low4_reg;
647#[doc = "IOMMU_PMU_HIT_HIGH4_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_HIGH4_REG_SPEC>`"]
648pub type IOMMU_PMU_HIT_HIGH4_REG =
649 crate::Reg<iommu_pmu_hit_high4_reg::IOMMU_PMU_HIT_HIGH4_REG_SPEC>;
650#[doc = "IOMMU PMU Hit High 4 Register"]
651pub mod iommu_pmu_hit_high4_reg;
652#[doc = "IOMMU_PMU_ACCESS_LOW5_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_LOW5_REG_SPEC>`"]
653pub type IOMMU_PMU_ACCESS_LOW5_REG =
654 crate::Reg<iommu_pmu_access_low5_reg::IOMMU_PMU_ACCESS_LOW5_REG_SPEC>;
655#[doc = "IOMMU PMU Access Low 5 Register"]
656pub mod iommu_pmu_access_low5_reg;
657#[doc = "IOMMU_PMU_ACCESS_HIGH5_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_HIGH5_REG_SPEC>`"]
658pub type IOMMU_PMU_ACCESS_HIGH5_REG =
659 crate::Reg<iommu_pmu_access_high5_reg::IOMMU_PMU_ACCESS_HIGH5_REG_SPEC>;
660#[doc = "IOMMU PMU Access High 5 Register"]
661pub mod iommu_pmu_access_high5_reg;
662#[doc = "IOMMU_PMU_HIT_LOW5_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_LOW5_REG_SPEC>`"]
663pub type IOMMU_PMU_HIT_LOW5_REG = crate::Reg<iommu_pmu_hit_low5_reg::IOMMU_PMU_HIT_LOW5_REG_SPEC>;
664#[doc = "IOMMU PMU Hit Low 5 Register"]
665pub mod iommu_pmu_hit_low5_reg;
666#[doc = "IOMMU_PMU_HIT_HIGH5_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_HIGH5_REG_SPEC>`"]
667pub type IOMMU_PMU_HIT_HIGH5_REG =
668 crate::Reg<iommu_pmu_hit_high5_reg::IOMMU_PMU_HIT_HIGH5_REG_SPEC>;
669#[doc = "IOMMU PMU Hit High 5 Register"]
670pub mod iommu_pmu_hit_high5_reg;
671#[doc = "IOMMU_PMU_ACCESS_LOW6_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_LOW6_REG_SPEC>`"]
672pub type IOMMU_PMU_ACCESS_LOW6_REG =
673 crate::Reg<iommu_pmu_access_low6_reg::IOMMU_PMU_ACCESS_LOW6_REG_SPEC>;
674#[doc = "IOMMU PMU Access Low 6 Register"]
675pub mod iommu_pmu_access_low6_reg;
676#[doc = "IOMMU_PMU_ACCESS_HIGH6_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_HIGH6_REG_SPEC>`"]
677pub type IOMMU_PMU_ACCESS_HIGH6_REG =
678 crate::Reg<iommu_pmu_access_high6_reg::IOMMU_PMU_ACCESS_HIGH6_REG_SPEC>;
679#[doc = "IOMMU PMU Access High 6 Register"]
680pub mod iommu_pmu_access_high6_reg;
681#[doc = "IOMMU_PMU_HIT_LOW6_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_LOW6_REG_SPEC>`"]
682pub type IOMMU_PMU_HIT_LOW6_REG = crate::Reg<iommu_pmu_hit_low6_reg::IOMMU_PMU_HIT_LOW6_REG_SPEC>;
683#[doc = "IOMMU PMU Hit Low 6 Register"]
684pub mod iommu_pmu_hit_low6_reg;
685#[doc = "IOMMU_PMU_HIT_HIGH6_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_HIGH6_REG_SPEC>`"]
686pub type IOMMU_PMU_HIT_HIGH6_REG =
687 crate::Reg<iommu_pmu_hit_high6_reg::IOMMU_PMU_HIT_HIGH6_REG_SPEC>;
688#[doc = "IOMMU PMU Hit High 6 Register"]
689pub mod iommu_pmu_hit_high6_reg;
690#[doc = "IOMMU_PMU_ACCESS_LOW7_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_LOW7_REG_SPEC>`"]
691pub type IOMMU_PMU_ACCESS_LOW7_REG =
692 crate::Reg<iommu_pmu_access_low7_reg::IOMMU_PMU_ACCESS_LOW7_REG_SPEC>;
693#[doc = "IOMMU PMU Access Low 7 Register"]
694pub mod iommu_pmu_access_low7_reg;
695#[doc = "IOMMU_PMU_ACCESS_HIGH7_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_HIGH7_REG_SPEC>`"]
696pub type IOMMU_PMU_ACCESS_HIGH7_REG =
697 crate::Reg<iommu_pmu_access_high7_reg::IOMMU_PMU_ACCESS_HIGH7_REG_SPEC>;
698#[doc = "IOMMU PMU Access High 7 Register"]
699pub mod iommu_pmu_access_high7_reg;
700#[doc = "IOMMU_PMU_HIT_LOW7_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_LOW7_REG_SPEC>`"]
701pub type IOMMU_PMU_HIT_LOW7_REG = crate::Reg<iommu_pmu_hit_low7_reg::IOMMU_PMU_HIT_LOW7_REG_SPEC>;
702#[doc = "IOMMU PMU Hit Low 7 Register"]
703pub mod iommu_pmu_hit_low7_reg;
704#[doc = "IOMMU_PMU_HIT_HIGH7_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_HIGH7_REG_SPEC>`"]
705pub type IOMMU_PMU_HIT_HIGH7_REG =
706 crate::Reg<iommu_pmu_hit_high7_reg::IOMMU_PMU_HIT_HIGH7_REG_SPEC>;
707#[doc = "IOMMU PMU Hit High 7 Register"]
708pub mod iommu_pmu_hit_high7_reg;
709#[doc = "IOMMU_PMU_ACCESS_LOW8_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_LOW8_REG_SPEC>`"]
710pub type IOMMU_PMU_ACCESS_LOW8_REG =
711 crate::Reg<iommu_pmu_access_low8_reg::IOMMU_PMU_ACCESS_LOW8_REG_SPEC>;
712#[doc = "IOMMU PMU Access Low 8 Register"]
713pub mod iommu_pmu_access_low8_reg;
714#[doc = "IOMMU_PMU_ACCESS_HIGH8_REG register accessor: an alias for `Reg<IOMMU_PMU_ACCESS_HIGH8_REG_SPEC>`"]
715pub type IOMMU_PMU_ACCESS_HIGH8_REG =
716 crate::Reg<iommu_pmu_access_high8_reg::IOMMU_PMU_ACCESS_HIGH8_REG_SPEC>;
717#[doc = "IOMMU PMU Access High 8 Register"]
718pub mod iommu_pmu_access_high8_reg;
719#[doc = "IOMMU_PMU_HIT_LOW8_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_LOW8_REG_SPEC>`"]
720pub type IOMMU_PMU_HIT_LOW8_REG = crate::Reg<iommu_pmu_hit_low8_reg::IOMMU_PMU_HIT_LOW8_REG_SPEC>;
721#[doc = "IOMMU PMU Hit Low 8 Register"]
722pub mod iommu_pmu_hit_low8_reg;
723#[doc = "IOMMU_PMU_HIT_HIGH8_REG register accessor: an alias for `Reg<IOMMU_PMU_HIT_HIGH8_REG_SPEC>`"]
724pub type IOMMU_PMU_HIT_HIGH8_REG =
725 crate::Reg<iommu_pmu_hit_high8_reg::IOMMU_PMU_HIT_HIGH8_REG_SPEC>;
726#[doc = "IOMMU PMU Hit High 8 Register"]
727pub mod iommu_pmu_hit_high8_reg;
728#[doc = "IOMMU_PMU_TL_LOW0_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_LOW0_REG_SPEC>`"]
729pub type IOMMU_PMU_TL_LOW0_REG = crate::Reg<iommu_pmu_tl_low0_reg::IOMMU_PMU_TL_LOW0_REG_SPEC>;
730#[doc = "IOMMU Total Latency Low 0 Register"]
731pub mod iommu_pmu_tl_low0_reg;
732#[doc = "IOMMU_PMU_TL_HIGH0_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_HIGH0_REG_SPEC>`"]
733pub type IOMMU_PMU_TL_HIGH0_REG = crate::Reg<iommu_pmu_tl_high0_reg::IOMMU_PMU_TL_HIGH0_REG_SPEC>;
734#[doc = "IOMMU Total Latency High 0 Register"]
735pub mod iommu_pmu_tl_high0_reg;
736#[doc = "IOMMU_PMU_ML0_REG register accessor: an alias for `Reg<IOMMU_PMU_ML0_REG_SPEC>`"]
737pub type IOMMU_PMU_ML0_REG = crate::Reg<iommu_pmu_ml0_reg::IOMMU_PMU_ML0_REG_SPEC>;
738#[doc = "IOMMU Max Latency 0 Register"]
739pub mod iommu_pmu_ml0_reg;
740#[doc = "IOMMU_PMU_TL_LOW1_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_LOW1_REG_SPEC>`"]
741pub type IOMMU_PMU_TL_LOW1_REG = crate::Reg<iommu_pmu_tl_low1_reg::IOMMU_PMU_TL_LOW1_REG_SPEC>;
742#[doc = "IOMMU Total Latency Low 1 Register"]
743pub mod iommu_pmu_tl_low1_reg;
744#[doc = "IOMMU_PMU_TL_HIGH1_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_HIGH1_REG_SPEC>`"]
745pub type IOMMU_PMU_TL_HIGH1_REG = crate::Reg<iommu_pmu_tl_high1_reg::IOMMU_PMU_TL_HIGH1_REG_SPEC>;
746#[doc = "IOMMU Total Latency High 1 Register"]
747pub mod iommu_pmu_tl_high1_reg;
748#[doc = "IOMMU_PMU_ML1_REG register accessor: an alias for `Reg<IOMMU_PMU_ML1_REG_SPEC>`"]
749pub type IOMMU_PMU_ML1_REG = crate::Reg<iommu_pmu_ml1_reg::IOMMU_PMU_ML1_REG_SPEC>;
750#[doc = "IOMMU Max Latency 1 Register"]
751pub mod iommu_pmu_ml1_reg;
752#[doc = "IOMMU_PMU_TL_LOW2_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_LOW2_REG_SPEC>`"]
753pub type IOMMU_PMU_TL_LOW2_REG = crate::Reg<iommu_pmu_tl_low2_reg::IOMMU_PMU_TL_LOW2_REG_SPEC>;
754#[doc = "IOMMU Total Latency Low 2 Register"]
755pub mod iommu_pmu_tl_low2_reg;
756#[doc = "IOMMU_PMU_TL_HIGH2_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_HIGH2_REG_SPEC>`"]
757pub type IOMMU_PMU_TL_HIGH2_REG = crate::Reg<iommu_pmu_tl_high2_reg::IOMMU_PMU_TL_HIGH2_REG_SPEC>;
758#[doc = "IOMMU Total Latency High 2 Register"]
759pub mod iommu_pmu_tl_high2_reg;
760#[doc = "IOMMU_PMU_ML2_REG register accessor: an alias for `Reg<IOMMU_PMU_ML2_REG_SPEC>`"]
761pub type IOMMU_PMU_ML2_REG = crate::Reg<iommu_pmu_ml2_reg::IOMMU_PMU_ML2_REG_SPEC>;
762#[doc = "IOMMU Max Latency 2 Register"]
763pub mod iommu_pmu_ml2_reg;
764#[doc = "IOMMU_PMU_TL_LOW3_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_LOW3_REG_SPEC>`"]
765pub type IOMMU_PMU_TL_LOW3_REG = crate::Reg<iommu_pmu_tl_low3_reg::IOMMU_PMU_TL_LOW3_REG_SPEC>;
766#[doc = "IOMMU Total Latency Low 3 Register"]
767pub mod iommu_pmu_tl_low3_reg;
768#[doc = "IOMMU_PMU_TL_HIGH3_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_HIGH3_REG_SPEC>`"]
769pub type IOMMU_PMU_TL_HIGH3_REG = crate::Reg<iommu_pmu_tl_high3_reg::IOMMU_PMU_TL_HIGH3_REG_SPEC>;
770#[doc = "IOMMU Total Latency High 3 Register"]
771pub mod iommu_pmu_tl_high3_reg;
772#[doc = "IOMMU_PMU_ML3_REG register accessor: an alias for `Reg<IOMMU_PMU_ML3_REG_SPEC>`"]
773pub type IOMMU_PMU_ML3_REG = crate::Reg<iommu_pmu_ml3_reg::IOMMU_PMU_ML3_REG_SPEC>;
774#[doc = "IOMMU Max Latency 3 Register"]
775pub mod iommu_pmu_ml3_reg;
776#[doc = "IOMMU_PMU_TL_LOW4_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_LOW4_REG_SPEC>`"]
777pub type IOMMU_PMU_TL_LOW4_REG = crate::Reg<iommu_pmu_tl_low4_reg::IOMMU_PMU_TL_LOW4_REG_SPEC>;
778#[doc = "IOMMU Total Latency Low 4 Register"]
779pub mod iommu_pmu_tl_low4_reg;
780#[doc = "IOMMU_PMU_TL_HIGH4_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_HIGH4_REG_SPEC>`"]
781pub type IOMMU_PMU_TL_HIGH4_REG = crate::Reg<iommu_pmu_tl_high4_reg::IOMMU_PMU_TL_HIGH4_REG_SPEC>;
782#[doc = "IOMMU Total Latency High 4 Register"]
783pub mod iommu_pmu_tl_high4_reg;
784#[doc = "IOMMU_PMU_ML4_REG register accessor: an alias for `Reg<IOMMU_PMU_ML4_REG_SPEC>`"]
785pub type IOMMU_PMU_ML4_REG = crate::Reg<iommu_pmu_ml4_reg::IOMMU_PMU_ML4_REG_SPEC>;
786#[doc = "IOMMU Max Latency 4 Register"]
787pub mod iommu_pmu_ml4_reg;
788#[doc = "IOMMU_PMU_TL_LOW5_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_LOW5_REG_SPEC>`"]
789pub type IOMMU_PMU_TL_LOW5_REG = crate::Reg<iommu_pmu_tl_low5_reg::IOMMU_PMU_TL_LOW5_REG_SPEC>;
790#[doc = "IOMMU Total Latency Low 5 Register"]
791pub mod iommu_pmu_tl_low5_reg;
792#[doc = "IOMMU_PMU_TL_HIGH5_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_HIGH5_REG_SPEC>`"]
793pub type IOMMU_PMU_TL_HIGH5_REG = crate::Reg<iommu_pmu_tl_high5_reg::IOMMU_PMU_TL_HIGH5_REG_SPEC>;
794#[doc = "IOMMU Total Latency High 5 Register"]
795pub mod iommu_pmu_tl_high5_reg;
796#[doc = "IOMMU_PMU_ML5_REG register accessor: an alias for `Reg<IOMMU_PMU_ML5_REG_SPEC>`"]
797pub type IOMMU_PMU_ML5_REG = crate::Reg<iommu_pmu_ml5_reg::IOMMU_PMU_ML5_REG_SPEC>;
798#[doc = "IOMMU Max Latency 5 Register"]
799pub mod iommu_pmu_ml5_reg;
800#[doc = "IOMMU_PMU_TL_LOW6_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_LOW6_REG_SPEC>`"]
801pub type IOMMU_PMU_TL_LOW6_REG = crate::Reg<iommu_pmu_tl_low6_reg::IOMMU_PMU_TL_LOW6_REG_SPEC>;
802#[doc = "IOMMU Total Latency Low 6 Register"]
803pub mod iommu_pmu_tl_low6_reg;
804#[doc = "IOMMU_PMU_TL_HIGH6_REG register accessor: an alias for `Reg<IOMMU_PMU_TL_HIGH6_REG_SPEC>`"]
805pub type IOMMU_PMU_TL_HIGH6_REG = crate::Reg<iommu_pmu_tl_high6_reg::IOMMU_PMU_TL_HIGH6_REG_SPEC>;
806#[doc = "IOMMU Total Latency High 6 Register"]
807pub mod iommu_pmu_tl_high6_reg;
808#[doc = "IOMMU_PMU_ML6_REG register accessor: an alias for `Reg<IOMMU_PMU_ML6_REG_SPEC>`"]
809pub type IOMMU_PMU_ML6_REG = crate::Reg<iommu_pmu_ml6_reg::IOMMU_PMU_ML6_REG_SPEC>;
810#[doc = "IOMMU Max Latency 6 Register"]
811pub mod iommu_pmu_ml6_reg;