r528_pac/ccu/
pll_ve_pat0_ctrl.rs

1#[doc = "Register `PLL_VE_PAT0_CTRL` reader"]
2pub struct R(crate::R<PLL_VE_PAT0_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PLL_VE_PAT0_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PLL_VE_PAT0_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PLL_VE_PAT0_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PLL_VE_PAT0_CTRL` writer"]
17pub struct W(crate::W<PLL_VE_PAT0_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PLL_VE_PAT0_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PLL_VE_PAT0_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PLL_VE_PAT0_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIG_DELT_PAT_EN` reader - Sigma-Delta Pattern Enable"]
38pub type SIG_DELT_PAT_EN_R = crate::BitReader<bool>;
39#[doc = "Field `SIG_DELT_PAT_EN` writer - Sigma-Delta Pattern Enable"]
40pub type SIG_DELT_PAT_EN_W<'a> = crate::BitWriter<'a, u32, PLL_VE_PAT0_CTRL_SPEC, bool, 31>;
41#[doc = "Spread Frequency Mode\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SPR_FREQ_MODE_A {
45    #[doc = "0: `0`"]
46    DC0 = 0,
47    #[doc = "1: `1`"]
48    DC1 = 1,
49    #[doc = "2: `10`"]
50    TRIANGULAR_1 = 2,
51    #[doc = "3: `11`"]
52    TRIANGULAR_N = 3,
53}
54impl From<SPR_FREQ_MODE_A> for u8 {
55    #[inline(always)]
56    fn from(variant: SPR_FREQ_MODE_A) -> Self {
57        variant as _
58    }
59}
60#[doc = "Field `SPR_FREQ_MODE` reader - Spread Frequency Mode"]
61pub type SPR_FREQ_MODE_R = crate::FieldReader<u8, SPR_FREQ_MODE_A>;
62impl SPR_FREQ_MODE_R {
63    #[doc = "Get enumerated values variant"]
64    #[inline(always)]
65    pub fn variant(&self) -> SPR_FREQ_MODE_A {
66        match self.bits {
67            0 => SPR_FREQ_MODE_A::DC0,
68            1 => SPR_FREQ_MODE_A::DC1,
69            2 => SPR_FREQ_MODE_A::TRIANGULAR_1,
70            3 => SPR_FREQ_MODE_A::TRIANGULAR_N,
71            _ => unreachable!(),
72        }
73    }
74    #[doc = "Checks if the value of the field is `DC0`"]
75    #[inline(always)]
76    pub fn is_dc0(&self) -> bool {
77        *self == SPR_FREQ_MODE_A::DC0
78    }
79    #[doc = "Checks if the value of the field is `DC1`"]
80    #[inline(always)]
81    pub fn is_dc1(&self) -> bool {
82        *self == SPR_FREQ_MODE_A::DC1
83    }
84    #[doc = "Checks if the value of the field is `TRIANGULAR_1`"]
85    #[inline(always)]
86    pub fn is_triangular_1(&self) -> bool {
87        *self == SPR_FREQ_MODE_A::TRIANGULAR_1
88    }
89    #[doc = "Checks if the value of the field is `TRIANGULAR_N`"]
90    #[inline(always)]
91    pub fn is_triangular_n(&self) -> bool {
92        *self == SPR_FREQ_MODE_A::TRIANGULAR_N
93    }
94}
95#[doc = "Field `SPR_FREQ_MODE` writer - Spread Frequency Mode"]
96pub type SPR_FREQ_MODE_W<'a> =
97    crate::FieldWriterSafe<'a, u32, PLL_VE_PAT0_CTRL_SPEC, u8, SPR_FREQ_MODE_A, 2, 29>;
98impl<'a> SPR_FREQ_MODE_W<'a> {
99    #[doc = "`0`"]
100    #[inline(always)]
101    pub fn dc0(self) -> &'a mut W {
102        self.variant(SPR_FREQ_MODE_A::DC0)
103    }
104    #[doc = "`1`"]
105    #[inline(always)]
106    pub fn dc1(self) -> &'a mut W {
107        self.variant(SPR_FREQ_MODE_A::DC1)
108    }
109    #[doc = "`10`"]
110    #[inline(always)]
111    pub fn triangular_1(self) -> &'a mut W {
112        self.variant(SPR_FREQ_MODE_A::TRIANGULAR_1)
113    }
114    #[doc = "`11`"]
115    #[inline(always)]
116    pub fn triangular_n(self) -> &'a mut W {
117        self.variant(SPR_FREQ_MODE_A::TRIANGULAR_N)
118    }
119}
120#[doc = "Field `WAVE_STEP` reader - Wave Step"]
121pub type WAVE_STEP_R = crate::FieldReader<u16, u16>;
122#[doc = "Field `WAVE_STEP` writer - Wave Step"]
123pub type WAVE_STEP_W<'a> = crate::FieldWriter<'a, u32, PLL_VE_PAT0_CTRL_SPEC, u16, u16, 9, 20>;
124#[doc = "SDM Clock Select\n\nValue on reset: 0"]
125#[derive(Clone, Copy, Debug, PartialEq)]
126pub enum SDM_CLK_SEL_A {
127    #[doc = "0: `0`"]
128    F_24_M = 0,
129    #[doc = "1: `1`"]
130    F_12_M = 1,
131}
132impl From<SDM_CLK_SEL_A> for bool {
133    #[inline(always)]
134    fn from(variant: SDM_CLK_SEL_A) -> Self {
135        variant as u8 != 0
136    }
137}
138#[doc = "Field `SDM_CLK_SEL` reader - SDM Clock Select"]
139pub type SDM_CLK_SEL_R = crate::BitReader<SDM_CLK_SEL_A>;
140impl SDM_CLK_SEL_R {
141    #[doc = "Get enumerated values variant"]
142    #[inline(always)]
143    pub fn variant(&self) -> SDM_CLK_SEL_A {
144        match self.bits {
145            false => SDM_CLK_SEL_A::F_24_M,
146            true => SDM_CLK_SEL_A::F_12_M,
147        }
148    }
149    #[doc = "Checks if the value of the field is `F_24_M`"]
150    #[inline(always)]
151    pub fn is_f_24_m(&self) -> bool {
152        *self == SDM_CLK_SEL_A::F_24_M
153    }
154    #[doc = "Checks if the value of the field is `F_12_M`"]
155    #[inline(always)]
156    pub fn is_f_12_m(&self) -> bool {
157        *self == SDM_CLK_SEL_A::F_12_M
158    }
159}
160#[doc = "Field `SDM_CLK_SEL` writer - SDM Clock Select"]
161pub type SDM_CLK_SEL_W<'a> = crate::BitWriter<'a, u32, PLL_VE_PAT0_CTRL_SPEC, SDM_CLK_SEL_A, 19>;
162impl<'a> SDM_CLK_SEL_W<'a> {
163    #[doc = "`0`"]
164    #[inline(always)]
165    pub fn f_24_m(self) -> &'a mut W {
166        self.variant(SDM_CLK_SEL_A::F_24_M)
167    }
168    #[doc = "`1`"]
169    #[inline(always)]
170    pub fn f_12_m(self) -> &'a mut W {
171        self.variant(SDM_CLK_SEL_A::F_12_M)
172    }
173}
174#[doc = "Frequency\n\nValue on reset: 0"]
175#[derive(Clone, Copy, Debug, PartialEq)]
176#[repr(u8)]
177pub enum FREQ_A {
178    #[doc = "0: `0`"]
179    F_31_5_K = 0,
180    #[doc = "1: `1`"]
181    F_32_K = 1,
182    #[doc = "2: `10`"]
183    F_32_5_K = 2,
184    #[doc = "3: `11`"]
185    F_33_K = 3,
186}
187impl From<FREQ_A> for u8 {
188    #[inline(always)]
189    fn from(variant: FREQ_A) -> Self {
190        variant as _
191    }
192}
193#[doc = "Field `FREQ` reader - Frequency"]
194pub type FREQ_R = crate::FieldReader<u8, FREQ_A>;
195impl FREQ_R {
196    #[doc = "Get enumerated values variant"]
197    #[inline(always)]
198    pub fn variant(&self) -> FREQ_A {
199        match self.bits {
200            0 => FREQ_A::F_31_5_K,
201            1 => FREQ_A::F_32_K,
202            2 => FREQ_A::F_32_5_K,
203            3 => FREQ_A::F_33_K,
204            _ => unreachable!(),
205        }
206    }
207    #[doc = "Checks if the value of the field is `F_31_5_K`"]
208    #[inline(always)]
209    pub fn is_f_31_5_k(&self) -> bool {
210        *self == FREQ_A::F_31_5_K
211    }
212    #[doc = "Checks if the value of the field is `F_32_K`"]
213    #[inline(always)]
214    pub fn is_f_32_k(&self) -> bool {
215        *self == FREQ_A::F_32_K
216    }
217    #[doc = "Checks if the value of the field is `F_32_5_K`"]
218    #[inline(always)]
219    pub fn is_f_32_5_k(&self) -> bool {
220        *self == FREQ_A::F_32_5_K
221    }
222    #[doc = "Checks if the value of the field is `F_33_K`"]
223    #[inline(always)]
224    pub fn is_f_33_k(&self) -> bool {
225        *self == FREQ_A::F_33_K
226    }
227}
228#[doc = "Field `FREQ` writer - Frequency"]
229pub type FREQ_W<'a> = crate::FieldWriterSafe<'a, u32, PLL_VE_PAT0_CTRL_SPEC, u8, FREQ_A, 2, 17>;
230impl<'a> FREQ_W<'a> {
231    #[doc = "`0`"]
232    #[inline(always)]
233    pub fn f_31_5_k(self) -> &'a mut W {
234        self.variant(FREQ_A::F_31_5_K)
235    }
236    #[doc = "`1`"]
237    #[inline(always)]
238    pub fn f_32_k(self) -> &'a mut W {
239        self.variant(FREQ_A::F_32_K)
240    }
241    #[doc = "`10`"]
242    #[inline(always)]
243    pub fn f_32_5_k(self) -> &'a mut W {
244        self.variant(FREQ_A::F_32_5_K)
245    }
246    #[doc = "`11`"]
247    #[inline(always)]
248    pub fn f_33_k(self) -> &'a mut W {
249        self.variant(FREQ_A::F_33_K)
250    }
251}
252#[doc = "Field `WAVE_BOT` reader - Wave Bottom"]
253pub type WAVE_BOT_R = crate::FieldReader<u32, u32>;
254#[doc = "Field `WAVE_BOT` writer - Wave Bottom"]
255pub type WAVE_BOT_W<'a> = crate::FieldWriter<'a, u32, PLL_VE_PAT0_CTRL_SPEC, u32, u32, 17, 0>;
256impl R {
257    #[doc = "Bit 31 - Sigma-Delta Pattern Enable"]
258    #[inline(always)]
259    pub fn sig_delt_pat_en(&self) -> SIG_DELT_PAT_EN_R {
260        SIG_DELT_PAT_EN_R::new(((self.bits >> 31) & 1) != 0)
261    }
262    #[doc = "Bits 29:30 - Spread Frequency Mode"]
263    #[inline(always)]
264    pub fn spr_freq_mode(&self) -> SPR_FREQ_MODE_R {
265        SPR_FREQ_MODE_R::new(((self.bits >> 29) & 3) as u8)
266    }
267    #[doc = "Bits 20:28 - Wave Step"]
268    #[inline(always)]
269    pub fn wave_step(&self) -> WAVE_STEP_R {
270        WAVE_STEP_R::new(((self.bits >> 20) & 0x01ff) as u16)
271    }
272    #[doc = "Bit 19 - SDM Clock Select"]
273    #[inline(always)]
274    pub fn sdm_clk_sel(&self) -> SDM_CLK_SEL_R {
275        SDM_CLK_SEL_R::new(((self.bits >> 19) & 1) != 0)
276    }
277    #[doc = "Bits 17:18 - Frequency"]
278    #[inline(always)]
279    pub fn freq(&self) -> FREQ_R {
280        FREQ_R::new(((self.bits >> 17) & 3) as u8)
281    }
282    #[doc = "Bits 0:16 - Wave Bottom"]
283    #[inline(always)]
284    pub fn wave_bot(&self) -> WAVE_BOT_R {
285        WAVE_BOT_R::new((self.bits & 0x0001_ffff) as u32)
286    }
287}
288impl W {
289    #[doc = "Bit 31 - Sigma-Delta Pattern Enable"]
290    #[inline(always)]
291    pub fn sig_delt_pat_en(&mut self) -> SIG_DELT_PAT_EN_W {
292        SIG_DELT_PAT_EN_W::new(self)
293    }
294    #[doc = "Bits 29:30 - Spread Frequency Mode"]
295    #[inline(always)]
296    pub fn spr_freq_mode(&mut self) -> SPR_FREQ_MODE_W {
297        SPR_FREQ_MODE_W::new(self)
298    }
299    #[doc = "Bits 20:28 - Wave Step"]
300    #[inline(always)]
301    pub fn wave_step(&mut self) -> WAVE_STEP_W {
302        WAVE_STEP_W::new(self)
303    }
304    #[doc = "Bit 19 - SDM Clock Select"]
305    #[inline(always)]
306    pub fn sdm_clk_sel(&mut self) -> SDM_CLK_SEL_W {
307        SDM_CLK_SEL_W::new(self)
308    }
309    #[doc = "Bits 17:18 - Frequency"]
310    #[inline(always)]
311    pub fn freq(&mut self) -> FREQ_W {
312        FREQ_W::new(self)
313    }
314    #[doc = "Bits 0:16 - Wave Bottom"]
315    #[inline(always)]
316    pub fn wave_bot(&mut self) -> WAVE_BOT_W {
317        WAVE_BOT_W::new(self)
318    }
319    #[doc = "Writes raw bits to the register."]
320    #[inline(always)]
321    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
322        self.0.bits(bits);
323        self
324    }
325}
326#[doc = "PLL_VE Pattern0 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll_ve_pat0_ctrl](index.html) module"]
327pub struct PLL_VE_PAT0_CTRL_SPEC;
328impl crate::RegisterSpec for PLL_VE_PAT0_CTRL_SPEC {
329    type Ux = u32;
330}
331#[doc = "`read()` method returns [pll_ve_pat0_ctrl::R](R) reader structure"]
332impl crate::Readable for PLL_VE_PAT0_CTRL_SPEC {
333    type Reader = R;
334}
335#[doc = "`write(|w| ..)` method takes [pll_ve_pat0_ctrl::W](W) writer structure"]
336impl crate::Writable for PLL_VE_PAT0_CTRL_SPEC {
337    type Writer = W;
338}
339#[doc = "`reset()` method sets PLL_VE_PAT0_CTRL to value 0"]
340impl crate::Resettable for PLL_VE_PAT0_CTRL_SPEC {
341    #[inline(always)]
342    fn reset_value() -> Self::Ux {
343        0
344    }
345}
r528_pac/ccu/pll_ve_pat0_ctrl.rs

r528_pac/ccu/
pll_ve_pat0_ctrl.rs
