#![no_std]
#![allow(non_camel_case_types)]
#![allow(clippy::uninit_assumed_init)]
#![allow(internal_features)]
#![feature(core_intrinsics)]
#![allow(non_snake_case)]
#![feature(async_closure)]
use config::SysClockSource;
use mcu::Peripherals;
pub use PY32f030xx_pac as pac;
pub mod adc;
pub mod bit;
pub mod clock;
pub mod crc;
pub mod delay;
pub mod dma;
#[cfg(feature = "embassy")]
mod embassy;
pub mod exti;
pub mod flash;
pub mod gpio;
pub mod i2c;
#[cfg(not(feature = "embassy"))]
pub mod interrupt;
pub mod iwdg;
mod macro_def;
pub mod mcu;
pub(crate) mod pwr;
pub mod rtc;
pub mod spi;
pub mod syscfg;
pub mod timer;
pub mod usart;
pub mod config {
#[derive(Default)]
pub enum SysClockSource {
#[default]
HSI,
HSE,
PLL_HSI,
}
#[derive(Default)]
pub struct Config {
pub sys_clk: SysClockSource,
}
impl Config {
pub fn sys_clk(self, sys_clk: SysClockSource) -> Self {
Self { sys_clk }
}
}
}
pub fn init(config: config::Config) -> Peripherals {
let peripherals = Peripherals::take();
cortex_m::asm::delay(1000 * 1000 * 5);
match config.sys_clk {
SysClockSource::HSE => {
clock::SysClock::<clock::HSE>::config().unwrap();
}
SysClockSource::HSI => {
clock::SysClock::<clock::HSIDiv<1>>::config().unwrap();
}
SysClockSource::PLL_HSI => {
clock::SysClock::<clock::PLL<clock::HSI>>::config().unwrap();
}
}
#[cfg(feature = "embassy")]
embassy::init();
peripherals
}
pub mod mode {
trait Sealed {}
#[allow(private_bounds)]
pub trait Mode: Sealed {
fn is_async() -> bool;
}
pub struct Blocking;
pub struct Async;
impl Sealed for Blocking {}
impl Mode for Blocking {
fn is_async() -> bool {
false
}
}
impl Sealed for Async {}
impl Mode for Async {
fn is_async() -> bool {
true
}
}
}