py32f0 0.2.1

Device support crates for PY32F0 devices
Documentation
///Register block
#[repr(C)]
pub struct RegisterBlock {
    ///0x00 - desc SR
    pub sr: SR,
    _reserved_1_dr: [u8; 0x04],
    ///0x08 - desc BRR
    pub brr: BRR,
    ///0x0c - desc CR1
    pub cr1: CR1,
    ///0x10 - desc CR2
    pub cr2: CR2,
    ///0x14 - desc CR3
    pub cr3: CR3,
    ///0x18 - desc GTPR
    pub gtpr: GTPR,
}
impl RegisterBlock {
    ///0x04 - Direct 8-bit access to data register
    #[inline(always)]
    pub const fn dr8(&self) -> &DR8 {
        unsafe { &*(self as *const Self).cast::<u8>().add(4usize).cast() }
    }
    ///0x04 - desc DR
    #[inline(always)]
    pub const fn dr(&self) -> &DR {
        unsafe { &*(self as *const Self).cast::<u8>().add(4usize).cast() }
    }
}
///SR (rw) register accessor: an alias for `Reg<SR_SPEC>`
pub type SR = crate::Reg<sr::SR_SPEC>;
///desc SR
pub mod sr;
///DR (rw) register accessor: an alias for `Reg<DR_SPEC>`
pub type DR = crate::Reg<dr::DR_SPEC>;
///desc DR
pub mod dr;
///BRR (rw) register accessor: an alias for `Reg<BRR_SPEC>`
pub type BRR = crate::Reg<brr::BRR_SPEC>;
///desc BRR
pub mod brr;
///CR1 (rw) register accessor: an alias for `Reg<CR1_SPEC>`
pub type CR1 = crate::Reg<cr1::CR1_SPEC>;
///desc CR1
pub mod cr1;
///CR2 (rw) register accessor: an alias for `Reg<CR2_SPEC>`
pub type CR2 = crate::Reg<cr2::CR2_SPEC>;
///desc CR2
pub mod cr2;
///CR3 (rw) register accessor: an alias for `Reg<CR3_SPEC>`
pub type CR3 = crate::Reg<cr3::CR3_SPEC>;
///desc CR3
pub mod cr3;
///GTPR (rw) register accessor: an alias for `Reg<GTPR_SPEC>`
pub type GTPR = crate::Reg<gtpr::GTPR_SPEC>;
///desc GTPR
pub mod gtpr;
///DR8 (rw) register accessor: an alias for `Reg<DR8_SPEC>`
pub type DR8 = crate::Reg<dr8::DR8_SPEC>;
///Direct 8-bit access to data register
pub mod dr8;