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//! Per-chipset CPU hint intrinsics. This is the ONE place in the workspace that
//! expresses architecture hints, so a primitive that wants one depends on this.
//!
//! These use only the **stable `core::arch` intrinsics** — no inline `asm!`, no
//! unstable features. We write the intrinsic; the COMPILER emits the instruction
//! for whatever target it is building (the asm is build output, not source we
//! maintain). Every function is a HINT: correctness never depends on it, so a
//! target we cannot express lowers to a no-op — supporting it later is one line
//! here, never a portability gate.
//!
//! Coverage today: x86_64 has a stable prefetch intrinsic (`_mm_prefetch`).
//! aarch64's (`core::arch::aarch64::_prefetch`) is still unstable
//! (`stdarch_aarch64_prefetch`), so aarch64 is a no-op until it stabilises — at
//! which point it becomes one more `#[cfg]` arm here, still no asm.
/// Prefetch the cache line at `ptr` toward L1 for an upcoming WRITE, so a
/// latency-bound store stream (e.g. a batch drain into a caller buffer that
/// exceeds L1) does not stall on read-for-ownership.
///
/// Pure hint: `ptr` is never dereferenced, never faults, and any address is
/// legal. On a target without a stable intrinsic this compiles to nothing.
///
/// - x86_64: `_mm_prefetch::<_MM_HINT_T0>` — the compiler emits `prefetcht0`
/// (baseline SSE); the line lands in L1 and the subsequent store upgrades it.
/// - other targets (incl. aarch64 until its intrinsic stabilises): no-op.
let _ = ptr;
}