pub(crate) mod adi_v5_memory_interface;
pub mod romtable;
use crate::{memory::MemoryInterface, probe::DebugProbeError, CoreStatus};
use super::{
ap::memory_ap::MemoryAp,
communication_interface::{Initialized, SwdSequence},
ArmCommunicationInterface, ArmError,
};
pub use romtable::{Component, ComponentId, CoresightComponent, PeripheralType};
pub trait ArmMemoryInterface: SwdSequence + ArmMemoryInterfaceShim {
fn ap(&mut self) -> &mut MemoryAp;
fn base_address(&mut self) -> Result<u64, ArmError>;
fn get_arm_communication_interface(
&mut self,
) -> Result<&mut ArmCommunicationInterface<Initialized>, DebugProbeError>;
fn try_as_parts(
&mut self,
) -> Result<(&mut ArmCommunicationInterface<Initialized>, &mut MemoryAp), DebugProbeError>;
fn update_core_status(&mut self, state: CoreStatus) {
self.get_arm_communication_interface()
.map(|iface| iface.core_status_notification(state))
.ok();
}
}
pub trait ArmMemoryInterfaceShim: MemoryInterface<ArmError> {
fn as_memory_interface(&self) -> &dyn MemoryInterface<ArmError>;
fn as_memory_interface_mut(&mut self) -> &mut dyn MemoryInterface<ArmError>;
}
impl<T> ArmMemoryInterfaceShim for T
where
T: ArmMemoryInterface,
{
fn as_memory_interface(&self) -> &dyn MemoryInterface<ArmError> {
self
}
fn as_memory_interface_mut(&mut self) -> &mut dyn MemoryInterface<ArmError> {
self
}
}